[rpi] Add support for the second PWM channel
Add support for the second channel to bcm2835_pwm driver. Configurable parameters like mode, period, ratio are exposed as sysctls with postfix '2', e.g.: dev.pwm.N.mode2, dev.pwm.N.period2, dev.pwm.N.ratio2 Second channel can be enabled in DTB by configuring pwn-2chan overlay instead of pwm in config.txt. See [1] [1] https://github.com/raspberrypi/firmware/blob/master/boot/overlays/README Submitted by: Bob Frazier Differential Revision: https://reviews.freebsd.org/D15769
This commit is contained in:
Oleksandr Tymoshenko
parent
5f88cf68fc
commit
3f9b72b641
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=335855
@ -63,11 +63,13 @@ struct bcm_pwm_softc {
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device_t clkman;
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uint32_t freq;
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uint32_t period;
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uint32_t freq; /* shared between channels 1 and 2 */
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uint32_t period; /* channel 1 */
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uint32_t ratio;
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uint32_t mode;
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uint32_t period2; /* channel 2 */
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uint32_t ratio2;
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uint32_t mode2;
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};
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#define BCM_PWM_MEM_WRITE(_sc, _off, _val) \
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@ -87,11 +89,15 @@ struct bcm_pwm_softc {
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#define R_RNG(_sc) BCM_PWM_MEM_READ(_sc, 0x10)
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#define W_DAT(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x14, _val)
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#define R_DAT(_sc) BCM_PWM_MEM_READ(_sc, 0x14)
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#define W_RNG2(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x20, _val)
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#define R_RNG2(_sc) BCM_PWM_MEM_READ(_sc, 0x20)
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#define W_DAT2(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x24, _val)
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#define R_DAT2(_sc) BCM_PWM_MEM_READ(_sc, 0x24)
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static int
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bcm_pwm_reconf(struct bcm_pwm_softc *sc)
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{
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uint32_t u;
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uint32_t u, ctlr;
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/* Disable PWM */
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W_CTL(sc, 0);
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@ -99,25 +105,77 @@ bcm_pwm_reconf(struct bcm_pwm_softc *sc)
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/* Stop PWM clock */
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(void)bcm2835_clkman_set_frequency(sc->clkman, BCM_PWM_CLKSRC, 0);
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if (sc->mode == 0)
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return (0);
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ctlr = 0; /* pre-assign zero, enable bits, write to CTL at end */
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if (sc->mode == 0 && sc->mode2 == 0) /* both modes are zero */
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return 0; /* device is now off - return */
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/* set the PWM clock frequency */
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/* TODO: should I only do this if it changes and not stop it first? */
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u = bcm2835_clkman_set_frequency(sc->clkman, BCM_PWM_CLKSRC, sc->freq);
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if (u == 0)
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return (EINVAL);
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sc->freq = u;
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/* Config PWM */
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W_RNG(sc, sc->period);
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if (sc->ratio > sc->period)
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sc->ratio = sc->period;
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W_DAT(sc, sc->ratio);
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/* control register CTL bits:
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* (from BCM2835 ARM Peripherals manual, section 9.6)
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*
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* 15 MSEN2 chan 2 M/S enable; 0 for PWM algo, 1 for M/S transmission
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* 14 unused; always reads as 0
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* 13 USEF2 chan 2 use FIFO (0 uses data; 1 uses FIFO)
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* 12 POLA2 chan 2 invert polarity (0 normal, 1 inverted polarity)
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* 11 SBIT2 chan 2 'Silence' bit (when not transmitting data)
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* 10 RPTL2 chan 2 FIFO repeat last data (1 repeats, 0 interrupts)
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* 9 MODE2 chan 2 PWM/Serializer mode (0 PWM, 1 Serializer)
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* 8 PWEN2 chan 2 enable (0 disable, 1 enable)
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* 7 MSEN1 chan 1 M/S enable; 0 for PWM algo, 1 for M/S transmission
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* 6 CLRF1 chan 1 clear FIFO (set 1 to clear; always reads as 0)
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* 5 USEF1 chan 1 use FIFO (0 uses data; 1 uses FIFO)
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* 4 POLA1 chan 1 invert polarity (0 normal, 1 inverted polarity)
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* 3 SBIT1 chan 1 'Silence' bit (when not transmitting data)
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* 2 RTPL1 chan 1 FIFO repeat last data (1 repeats, 0 interrupts)
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* 1 MODE1 chan 1 PWM/Serializer mode (0 PWM, 1 Serializer)
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* 0 PWMEN1 chan 1 enable (0 disable, 1 enable)
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*
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* Notes on M/S enable: when this bit is '1', a simple M/S ratio is used. In short,
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* the value of 'ratio' is the number of 'on' bits, and the total length of the data is
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* defined by 'period'. So if 'ratio' is 2500 and 'period' is 10000, then the output
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* remains 'on' for 2500 clocks, and goes 'off' for the remaining 7500 clocks.
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* When the M/S enable is '0', a more complicated algorithm effectively 'dithers' the
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* pulses in order to obtain the desired ratio. For details, see section 9.3 of the
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* BCM2835 ARM Peripherals manual.
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*/
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/* Start PWM */
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if (sc->mode == 1)
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W_CTL(sc, 0x81);
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else
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W_CTL(sc, 0x1);
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if (sc->mode != 0) {
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/* Config PWM Channel 1 */
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W_RNG(sc, sc->period);
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if (sc->ratio > sc->period)
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sc->ratio = sc->period;
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W_DAT(sc, sc->ratio);
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/* Start PWM Channel 1 */
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if (sc->mode == 1)
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ctlr |= 0x81; /* chan 1 enable + chan 1 M/S enable */
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else
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ctlr |= 0x1; /* chan 1 enable */
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}
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if (sc->mode2 != 0) {
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/* Config PWM Channel 2 */
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W_RNG2(sc, sc->period2);
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if (sc->ratio2 > sc->period2)
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sc->ratio2 = sc->period2;
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W_DAT2(sc, sc->ratio2);
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/* Start PWM Channel 2 */
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if (sc->mode2 == 1)
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ctlr |= 0x8100; /* chan 2 enable + chan 2 M/S enable */
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else
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ctlr |= 0x100; /* chan 2 enable */
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}
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/* write CTL register with updated value */
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W_CTL(sc, ctlr);
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return (0);
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}
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@ -138,7 +196,6 @@ bcm_pwm_pwm_freq_proc(SYSCTL_HANDLER_ARGS)
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return (error);
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}
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static int
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bcm_pwm_mode_proc(SYSCTL_HANDLER_ARGS)
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{
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@ -203,7 +260,73 @@ bcm_pwm_ratio_proc(SYSCTL_HANDLER_ARGS)
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if (r > sc->period) // XXX >= ?
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return (EINVAL);
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sc->ratio = r;
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BCM_PWM_MEM_WRITE(sc, 0x14, sc->ratio);
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W_DAT(sc, sc->ratio);
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return (0);
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}
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static int
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bcm_pwm_pwm_freq2_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_pwm_softc *sc;
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uint32_t r;
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int error;
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sc = (struct bcm_pwm_softc *)arg1;
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if (sc->mode2 == 1)
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r = sc->freq / sc->period2;
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else
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r = 0;
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error = sysctl_handle_int(oidp, &r, sizeof(r), req);
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return (error);
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}
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static int
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bcm_pwm_mode2_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_pwm_softc *sc;
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uint32_t r;
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int error;
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sc = (struct bcm_pwm_softc *)arg1;
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r = sc->mode2;
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error = sysctl_handle_int(oidp, &r, sizeof(r), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (r > 2)
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return (EINVAL);
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sc->mode2 = r;
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return (bcm_pwm_reconf(sc));
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}
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static int
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bcm_pwm_period2_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_pwm_softc *sc;
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int error;
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sc = (struct bcm_pwm_softc *)arg1;
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error = sysctl_handle_int(oidp, &sc->period2, sizeof(sc->period2), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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return (bcm_pwm_reconf(sc));
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}
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static int
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bcm_pwm_ratio2_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_pwm_softc *sc;
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uint32_t r;
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int error;
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sc = (struct bcm_pwm_softc *)arg1;
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r = sc->ratio2;
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error = sysctl_handle_int(oidp, &r, sizeof(r), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (r > sc->period2) // XXX >= ?
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return (EINVAL);
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sc->ratio2 = r;
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W_DAT(sc, sc->ratio2);
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return (0);
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}
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@ -257,19 +380,31 @@ bcm_pwm_sysctl_init(struct bcm_pwm_softc *sc)
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "pwm_freq",
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CTLFLAG_RD | CTLTYPE_UINT, sc, 0,
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bcm_pwm_pwm_freq_proc, "IU", "PWM frequency (Hz)");
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bcm_pwm_pwm_freq_proc, "IU", "PWM frequency ch 1 (Hz)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "period",
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CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
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bcm_pwm_period_proc, "IU", "PWM period (#clocks)");
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bcm_pwm_period_proc, "IU", "PWM period ch 1 (#clocks)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "ratio",
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CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
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bcm_pwm_ratio_proc, "IU", "PWM ratio (0...period)");
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bcm_pwm_ratio_proc, "IU", "PWM ratio ch 1 (0...period)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "freq",
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CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
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bcm_pwm_freq_proc, "IU", "PWM clock (Hz)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "mode",
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CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
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bcm_pwm_mode_proc, "IU", "PWM mode (0=off, 1=pwm, 2=dither)");
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bcm_pwm_mode_proc, "IU", "PWM mode ch 1 (0=off, 1=pwm, 2=dither)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "pwm_freq2",
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CTLFLAG_RD | CTLTYPE_UINT, sc, 0,
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bcm_pwm_pwm_freq2_proc, "IU", "PWM frequency ch 2 (Hz)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "period2",
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CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
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bcm_pwm_period2_proc, "IU", "PWM period ch 2 (#clocks)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "ratio2",
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CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
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bcm_pwm_ratio2_proc, "IU", "PWM ratio ch 2 (0...period)");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "mode2",
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CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
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bcm_pwm_mode2_proc, "IU", "PWM mode ch 2 (0=off, 1=pwm, 2=dither)");
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}
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static int
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@ -321,10 +456,11 @@ bcm_pwm_attach(device_t dev)
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/* Add sysctl nodes. */
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bcm_pwm_sysctl_init(sc);
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sc->freq = 125000000;
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sc->period = 10000;
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sc->ratio = 2500;
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sc->freq = 125000000; /* 125 Mhz */
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sc->period = 10000; /* 12.5 khz */
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sc->ratio = 2500; /* 25% */
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sc->period2 = 10000; /* 12.5 khz */
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sc->ratio2 = 2500; /* 25% */
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return (bus_generic_attach(dev));
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}
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@ -338,6 +474,7 @@ bcm_pwm_detach(device_t dev)
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sc = device_get_softc(dev);
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sc->mode = 0;
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sc->mode2 = 0;
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(void)bcm_pwm_reconf(sc);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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