Add new identify data structures fields from NVMe 1.3a.
Some of them are already supported by existing hardware, so reporting them `nvmecontrol identify` can be useful.
This commit is contained in:
Alexander Motin
parent
82ce05526b
commit
3fa5467a06
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=330759
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@ -95,25 +95,35 @@ print_controller(struct nvme_controller_data *cdata)
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printf("Controller Capabilities/Features\n");
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printf("================================\n");
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printf("Vendor ID: %04x\n", cdata->vid);
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printf("Subsystem Vendor ID: %04x\n", cdata->ssvid);
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printf("Vendor ID: %04x\n", cdata->vid);
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printf("Subsystem Vendor ID: %04x\n", cdata->ssvid);
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nvme_strvis(str, cdata->sn, sizeof(str), NVME_SERIAL_NUMBER_LENGTH);
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printf("Serial Number: %s\n", str);
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printf("Serial Number: %s\n", str);
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nvme_strvis(str, cdata->mn, sizeof(str), NVME_MODEL_NUMBER_LENGTH);
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printf("Model Number: %s\n", str);
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printf("Model Number: %s\n", str);
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nvme_strvis(str, cdata->fr, sizeof(str), NVME_FIRMWARE_REVISION_LENGTH);
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printf("Firmware Version: %s\n", str);
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printf("Recommended Arb Burst: %d\n", cdata->rab);
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printf("IEEE OUI Identifier: %02x %02x %02x\n",
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printf("Firmware Version: %s\n", str);
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printf("Recommended Arb Burst: %d\n", cdata->rab);
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printf("IEEE OUI Identifier: %02x %02x %02x\n",
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cdata->ieee[0], cdata->ieee[1], cdata->ieee[2]);
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printf("Multi-Interface Cap: %02x\n", cdata->mic);
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printf("Multi-Path I/O Capabilities: %s%s%s%s\n",
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(cdata->mic == 0) ? "Not Supported" : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT) &
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NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "SR-IOV VF, " : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT) &
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NVME_CTRLR_DATA_MIC_MCTRLRS_MASK) ? "Multiple controllers, " : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_MPORTS_SHIFT) &
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NVME_CTRLR_DATA_MIC_MPORTS_MASK) ? "Multiple ports" : "");
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/* TODO: Use CAP.MPSMIN to determine true memory page size. */
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printf("Max Data Transfer Size: ");
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printf("Max Data Transfer Size: ");
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if (cdata->mdts == 0)
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printf("Unlimited\n");
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else
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printf("%d\n", PAGE_SIZE * (1 << cdata->mdts));
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printf("Controller ID: 0x%02x\n", cdata->ctrlr_id);
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printf("Controller ID: 0x%02x\n", cdata->ctrlr_id);
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printf("Version: %d.%d.%d\n",
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(cdata->ver >> 16) & 0xffff, (cdata->ver >> 8) & 0xff,
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cdata->ver & 0xff);
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printf("\n");
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printf("Admin Command Set Attributes\n");
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@ -126,6 +136,21 @@ print_controller(struct nvme_controller_data *cdata)
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fw ? "Supported" : "Not Supported");
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printf("Namespace Managment: %s\n",
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nsmgmt ? "Supported" : "Not Supported");
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printf("Device Self-test: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT) &
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NVME_CTRLR_DATA_OACS_SELFTEST_MASK) ? "" : "Not ");
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printf("Directives: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT) &
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NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK) ? "" : "Not ");
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printf("NVMe-MI Send/Receive: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT) &
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NVME_CTRLR_DATA_OACS_NVMEMI_MASK) ? "" : "Not ");
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printf("Virtualization Management: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_VM_SHIFT) &
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NVME_CTRLR_DATA_OACS_VM_MASK) ? "" : "Not ");
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printf("Doorbell Buffer Config %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT) &
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NVME_CTRLR_DATA_OACS_DBBUFFER_MASK) ? "" : "Not ");
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printf("Abort Command Limit: %d\n", cdata->acl+1);
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printf("Async Event Request Limit: %d\n", cdata->aerl+1);
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printf("Number of Firmware Slots: ");
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@ -159,6 +184,18 @@ print_controller(struct nvme_controller_data *cdata)
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write_unc ? "Supported" : "Not Supported");
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printf("Dataset Management Command: %s\n",
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dsm ? "Supported" : "Not Supported");
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printf("Write Zeroes Command: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT) &
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NVME_CTRLR_DATA_ONCS_WRZERO_MASK) ? "" : "Not ");
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printf("Save Features: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT) &
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NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK) ? "" : "Not ");
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printf("Reservations: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_RESERV_SHIFT) &
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NVME_CTRLR_DATA_ONCS_RESERV_MASK) ? "" : "Not ");
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printf("Timestamp feature: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT) &
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NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK) ? "" : "Not ");
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printf("Volatile Write Cache: %s\n",
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vwc_present ? "Present" : "Not Present");
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@ -177,8 +214,8 @@ static void
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print_namespace(struct nvme_namespace_data *nsdata)
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{
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uint32_t i;
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uint32_t lbaf, lbads, ms;
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uint8_t thin_prov;
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uint32_t lbaf, lbads, ms, rp;
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uint8_t thin_prov, ptype;
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uint8_t flbas_fmt;
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thin_prov = (nsdata->nsfeat >> NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT) &
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@ -200,14 +237,79 @@ print_namespace(struct nvme_namespace_data *nsdata)
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thin_prov ? "Supported" : "Not Supported");
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printf("Number of LBA Formats: %d\n", nsdata->nlbaf+1);
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printf("Current LBA Format: LBA Format #%02d\n", flbas_fmt);
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printf("Data Protection Caps: %s%s%s%s%s%s\n",
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(nsdata->dpc == 0) ? "Not Supported" : "",
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((nsdata->dpc >> NVME_NS_DATA_DPC_MD_END_SHIFT) &
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NVME_NS_DATA_DPC_MD_END_MASK) ? "Last Bytes, " : "",
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((nsdata->dpc >> NVME_NS_DATA_DPC_MD_START_SHIFT) &
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NVME_NS_DATA_DPC_MD_START_MASK) ? "First Bytes, " : "",
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((nsdata->dpc >> NVME_NS_DATA_DPC_PIT3_SHIFT) &
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NVME_NS_DATA_DPC_PIT3_MASK) ? "Type 3, " : "",
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((nsdata->dpc >> NVME_NS_DATA_DPC_PIT2_SHIFT) &
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NVME_NS_DATA_DPC_PIT2_MASK) ? "Type 2, " : "",
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((nsdata->dpc >> NVME_NS_DATA_DPC_PIT2_MASK) &
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NVME_NS_DATA_DPC_PIT1_MASK) ? "Type 1" : "");
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printf("Data Protection Settings: ");
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ptype = (nsdata->dps >> NVME_NS_DATA_DPS_PIT_SHIFT) &
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NVME_NS_DATA_DPS_PIT_MASK;
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if (ptype) {
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printf("Type %d, %s Bytes\n", ptype,
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((nsdata->dps >> NVME_NS_DATA_DPS_MD_START_SHIFT) &
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NVME_NS_DATA_DPS_MD_START_MASK) ? "First" : "Last");
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} else {
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printf("Not Enabled\n");
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}
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printf("Multi-Path I/O Capabilities: %s%s\n",
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(nsdata->nmic == 0) ? "Not Supported" : "",
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((nsdata->nmic >> NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT) &
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NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK) ? "May be shared" : "");
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printf("Reservation Capabilities: %s%s%s%s%s%s%s%s%s\n",
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(nsdata->rescap == 0) ? "Not Supported" : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_IEKEY13_SHIFT) &
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NVME_NS_DATA_RESCAP_IEKEY13_MASK) ? "IEKEY13, " : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT) &
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NVME_NS_DATA_RESCAP_EX_AC_AR_MASK) ? "EX_AC_AR, " : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT) &
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NVME_NS_DATA_RESCAP_WR_EX_AR_MASK) ? "WR_EX_AR, " : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT) &
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NVME_NS_DATA_RESCAP_EX_AC_RO_MASK) ? "EX_AC_RO, " : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT) &
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NVME_NS_DATA_RESCAP_WR_EX_RO_MASK) ? "WR_EX_RO, " : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_EX_AC_SHIFT) &
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NVME_NS_DATA_RESCAP_EX_AC_MASK) ? "EX_AC, " : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_WR_EX_SHIFT) &
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NVME_NS_DATA_RESCAP_WR_EX_MASK) ? "WR_EX, " : "",
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((nsdata->rescap >> NVME_NS_DATA_RESCAP_PTPL_SHIFT) &
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NVME_NS_DATA_RESCAP_PTPL_MASK) ? "PTPL" : "");
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printf("Format Progress Indicator: ");
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if ((nsdata->fpi >> NVME_NS_DATA_FPI_SUPP_SHIFT) &
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NVME_NS_DATA_FPI_SUPP_MASK) {
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printf("%u%% remains\n",
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(nsdata->fpi >> NVME_NS_DATA_FPI_PERC_SHIFT) &
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NVME_NS_DATA_FPI_PERC_MASK);
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} else
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printf("Not Supported\n");
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printf("Optimal I/O Boundary (LBAs): %u\n", nsdata->noiob);
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printf("Globally Unique Identifier: ");
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for (i = 0; i < sizeof(nsdata->nguid); i++)
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printf("%02x", nsdata->nguid[i]);
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printf("\n");
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printf("IEEE EUI64: ");
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for (i = 0; i < sizeof(nsdata->eui64); i++)
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printf("%02x", nsdata->eui64[i]);
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printf("\n");
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for (i = 0; i <= nsdata->nlbaf; i++) {
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lbaf = nsdata->lbaf[i];
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lbads = (lbaf >> NVME_NS_DATA_LBAF_LBADS_SHIFT) &
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NVME_NS_DATA_LBAF_LBADS_MASK;
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ms = (lbaf >> NVME_NS_DATA_LBAF_MS_SHIFT) &
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NVME_NS_DATA_LBAF_MS_MASK;
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printf("LBA Format #%02d: Data Size: %5d Metadata Size: %5d\n",
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i, 1 << lbads, ms);
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rp = (lbaf >> NVME_NS_DATA_LBAF_RP_SHIFT) &
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NVME_NS_DATA_LBAF_RP_MASK;
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printf("LBA Format #%02d: Data Size: %5d Metadata Size: %5d"
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" Performance: %s\n",
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i, 1 << lbads, ms, (rp == 0) ? "Best" :
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(rp == 1) ? "Better" : (rp == 2) ? "Good" : "Degraded");
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}
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}
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@ -252,7 +354,7 @@ identify_ctrlr(int argc, char *argv[])
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hexlength = sizeof(struct nvme_controller_data);
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else
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hexlength = offsetof(struct nvme_controller_data,
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reserved5);
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reserved8);
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print_hex(&cdata, hexlength);
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exit(0);
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}
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@ -153,6 +153,17 @@
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#define NVME_PWR_ST_APS_SHIFT (6)
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#define NVME_PWR_ST_APS_MASK (0x3)
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/** Controller Multi-path I/O and Namespace Sharing Capabilities */
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/* More then one port */
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#define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0)
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#define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1)
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/* More then one controller */
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#define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1)
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#define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1)
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/* SR-IOV Virtual Function */
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#define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
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#define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
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/** OACS - optional admin command support */
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/* supports security send/receive commands */
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#define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0)
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@ -166,6 +177,21 @@
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/* supports namespace management commands */
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#define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3)
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#define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1)
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/* supports Device Self-test command */
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#define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4)
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#define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1)
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/* supports Directives */
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#define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5)
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#define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1)
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/* supports NVMe-MI Send/Receive */
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#define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6)
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#define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1)
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/* supports Virtualization Management */
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#define NVME_CTRLR_DATA_OACS_VM_SHIFT (7)
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#define NVME_CTRLR_DATA_OACS_VM_MASK (0x1)
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/* supports Doorbell Buffer Config */
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#define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
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#define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
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/** firmware updates */
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/* first slot is read-only */
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@ -209,6 +235,14 @@
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#define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1)
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#define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2)
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#define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1)
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#define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3)
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#define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1)
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#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4)
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#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1)
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#define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5)
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#define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
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#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
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#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
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/** volatile write cache */
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#define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
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@ -218,6 +252,15 @@
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/* thin provisioning */
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#define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0)
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#define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1)
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/* NAWUN, NAWUPF, and NACWU fields are valid */
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#define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1)
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#define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1)
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/* Deallocated or Unwritten Logical Block errors supported */
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#define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2)
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#define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1)
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/* NGUID and EUI64 fields are not reusable */
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#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
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#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
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/** formatted lba size */
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#define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
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@ -259,6 +302,45 @@
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#define NVME_NS_DATA_DPS_MD_START_SHIFT (3)
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#define NVME_NS_DATA_DPS_MD_START_MASK (0x1)
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/** Namespace Multi-path I/O and Namespace Sharing Capabilities */
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/* the namespace may be attached to two or more controllers */
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#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0)
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#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1)
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/** Reservation Capabilities */
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/* Persist Through Power Loss */
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#define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0)
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#define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1)
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/* supports the Write Exclusive */
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#define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1)
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#define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1)
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/* supports the Exclusive Access */
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#define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2)
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#define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1)
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/* supports the Write Exclusive – Registrants Only */
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#define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3)
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#define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1)
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/* supports the Exclusive Access - Registrants Only */
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#define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4)
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#define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1)
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/* supports the Write Exclusive – All Registrants */
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#define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5)
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#define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1)
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/* supports the Exclusive Access - All Registrants */
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#define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6)
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#define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1)
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/* Ignore Existing Key is used as defined in revision 1.3 or later */
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#define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7)
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#define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1)
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/** Format Progress Indicator */
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/* percentage of the Format NVM command that remains to be completed */
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#define NVME_NS_DATA_FPI_PERC_SHIFT (0)
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#define NVME_NS_DATA_FPI_PERC_MASK (0x7f)
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/* namespace supports the Format Progress Indicator */
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#define NVME_NS_DATA_FPI_SUPP_SHIFT (7)
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#define NVME_NS_DATA_FPI_SUPP_MASK (0x1)
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/** lba format support */
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/* metadata size */
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#define NVME_NS_DATA_LBAF_MS_SHIFT (0)
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@ -719,11 +801,34 @@ struct nvme_controller_data {
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/** volatile write cache */
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uint8_t vwc;
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/* TODO: flesh out remaining nvm command set attributes */
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uint8_t reserved5[178];
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/** Atomic Write Unit Normal */
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uint16_t awun;
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/* bytes 704-2047: i/o command set attributes */
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uint8_t reserved6[1344];
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/** Atomic Write Unit Power Fail */
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uint16_t awupf;
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/** NVM Vendor Specific Command Configuration */
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uint8_t nvscc;
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uint8_t reserved5;
|
||||
|
||||
/** Atomic Compare & Write Unit */
|
||||
uint16_t acwu;
|
||||
uint16_t reserved6;
|
||||
|
||||
/** SGL Support */
|
||||
uint32_t sgls;
|
||||
|
||||
/* bytes 540-767: Reserved */
|
||||
uint8_t reserved7[228];
|
||||
|
||||
/** NVM Subsystem NVMe Qualified Name */
|
||||
uint8_t subnqn[256];
|
||||
|
||||
/* bytes 1024-1791: Reserved */
|
||||
uint8_t reserved8[768];
|
||||
|
||||
/* bytes 1792-2047: NVMe over Fabrics specification */
|
||||
uint8_t reserved9[256];
|
||||
|
||||
/* bytes 2048-3071: power state descriptors */
|
||||
struct nvme_power_state power_state[32];
|
||||
|
|
@ -763,7 +868,50 @@ struct nvme_namespace_data {
|
|||
/** end-to-end data protection type settings */
|
||||
uint8_t dps;
|
||||
|
||||
uint8_t reserved5[98];
|
||||
/** Namespace Multi-path I/O and Namespace Sharing Capabilities */
|
||||
uint8_t nmic;
|
||||
|
||||
/** Reservation Capabilities */
|
||||
uint8_t rescap;
|
||||
|
||||
/** Format Progress Indicator */
|
||||
uint8_t fpi;
|
||||
|
||||
/** Deallocate Logical Block Features */
|
||||
uint8_t dlfeat;
|
||||
|
||||
/** Namespace Atomic Write Unit Normal */
|
||||
uint16_t nawun;
|
||||
|
||||
/** Namespace Atomic Write Unit Power Fail */
|
||||
uint16_t nawupf;
|
||||
|
||||
/** Namespace Atomic Compare & Write Unit */
|
||||
uint16_t nacwu;
|
||||
|
||||
/** Namespace Atomic Boundary Size Normal */
|
||||
uint16_t nabsn;
|
||||
|
||||
/** Namespace Atomic Boundary Offset */
|
||||
uint16_t nabo;
|
||||
|
||||
/** Namespace Atomic Boundary Size Power Fail */
|
||||
uint16_t nabspf;
|
||||
|
||||
/** Namespace Optimal IO Boundary */
|
||||
uint16_t noiob;
|
||||
|
||||
/** NVM Capacity */
|
||||
uint8_t nvmcap[16];
|
||||
|
||||
/* bytes 64-103: Reserved */
|
||||
uint8_t reserved5[40];
|
||||
|
||||
/** Namespace Globally Unique Identifier */
|
||||
uint8_t nguid[16];
|
||||
|
||||
/** IEEE Extended Unique Identifier */
|
||||
uint8_t eui64[8];
|
||||
|
||||
/** lba format support */
|
||||
uint32_t lbaf[16];
|
||||
|
|
@ -1154,6 +1302,10 @@ void nvme_controller_data_swapbytes(struct nvme_controller_data *s)
|
|||
s->nn = le32toh(s->nn);
|
||||
s->oncs = le16toh(s->oncs);
|
||||
s->fuses = le16toh(s->fuses);
|
||||
s->awun = le16toh(s->awun);
|
||||
s->awupf = le16toh(s->awupf);
|
||||
s->acwu = le16toh(s->acwu);
|
||||
s->sgls = le32toh(s->sgls);
|
||||
for (i = 0; i < 32; i++)
|
||||
nvme_power_state_swapbytes(&s->power_state[i]);
|
||||
}
|
||||
|
|
@ -1166,6 +1318,13 @@ void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s)
|
|||
s->nsze = le64toh(s->nsze);
|
||||
s->ncap = le64toh(s->ncap);
|
||||
s->nuse = le64toh(s->nuse);
|
||||
s->nawun = le16toh(s->nawun);
|
||||
s->nawupf = le16toh(s->nawupf);
|
||||
s->nacwu = le16toh(s->nacwu);
|
||||
s->nabsn = le16toh(s->nabsn);
|
||||
s->nabo = le16toh(s->nabo);
|
||||
s->nabspf = le16toh(s->nabspf);
|
||||
s->noiob = le16toh(s->noiob);
|
||||
for (i = 0; i < 16; i++)
|
||||
s->lbaf[i] = le32toh(s->lbaf[i]);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user