Adjust the register layout to allow for 64bit registers in the
future for nf10bmac(4). Also, add support for and enable RX interrupts. MFC after: 2 weeks
This commit is contained in:
parent
08d56ebf0a
commit
3fd18f3945
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=265766
@ -135,13 +135,14 @@
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ethernet@7f005000 {
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compatible = "netfpag10g,nf10bmac";
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// TX, RX, LOOP
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reg = <0x7f005010 0xc
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0x7f005020 0xc
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0x7f005030 0x4>;
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// LOOP, TX, RX, INTR
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reg = <0x7f005000 0x20
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0x7f005020 0x30
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0x7f005050 0x30
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0x7f005100 0x10>;
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// RX
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#interrupts = <1>;
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#interrupt-parent = <&beripic>;
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interrupts = <1>;
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interrupt-parent = <&beripic>;
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};
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};
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@ -92,13 +92,15 @@ static poll_handler_t nf10bmac_poll;
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#define NF10BMAC_LOCK_ASSERT(_sc) \
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mtx_assert(&(_sc)->nf10bmac_mtx, MA_OWNED)
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#define NF10BMAC_TX_LEN 0x08
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#define NF10BMAC_TX_META 0x04
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#define NF10BMAC_TX_DATA 0x00
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#define NF10BMAC_RX_LEN 0x08
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#define NF10BMAC_RX_META 0x04
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#define NF10BMAC_RX_DATA 0x00
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#define NF10BMAC_CTRL0 0x00
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#define NF10BMAC_TX_DATA 0x00
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#define NF10BMAC_TX_META 0x08
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#define NF10BMAC_TX_LEN 0x10
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#define NF10BMAC_RX_DATA 0x00
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#define NF10BMAC_RX_META 0x08
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#define NF10BMAC_RX_LEN 0x10
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#define NF10BMAC_INTR_CLEAR_DIS 0x00
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#define NF10BMAC_INTR_CTRL 0x08
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#define NF10BMAC_TUSER_MAC0 (1 << 0)
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#define NF10BMAC_TUSER_CPU0 (1 << 1)
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@ -109,11 +111,12 @@ static poll_handler_t nf10bmac_poll;
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#define NF10BMAC_TUSER_MAC3 (1 << 6)
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#define NF10BMAC_TUSER_CPU3 (1 << 7)
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#define NF10BMAC_DATA_LEN_MASK 0x0000ffff
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#define NF10BMAC_DATA_DPORT_MASK 0xff000000
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#define NF10BMAC_DATA_DPORT_SHIFT 24
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#define NF10BMAC_DATA_SPORT_MASK 0x00ff0000
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#define NF10BMAC_DATA_SPORT_SHIFT 16
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#define NF10BMAC_DATA_LAST 0x00000080
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#define NF10BMAC_DATA_LAST 0x00008000
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#define NF10BMAC_DATA_STRB 0x0000000f
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@ -151,7 +154,7 @@ nf10bmac_read_4_be(struct resource *res, uint32_t reg,
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}
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#define NF10BMAC_WRITE_CTRL_4(sc, reg, val) \
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nf10bmac_write_4((sc)->nf10bmac_mem_res, (reg), (val), \
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nf10bmac_write_4((sc)->nf10bmac_ctrl_res, (reg), (val), \
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__func__, __LINE__)
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#define NF10BMAC_WRITE_4(sc, reg, val) \
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nf10bmac_write_4((sc)->nf10bmac_tx_mem_res, (reg), (val), \
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@ -166,6 +169,21 @@ nf10bmac_read_4_be(struct resource *res, uint32_t reg,
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nf10bmac_read_4_be((sc)->nf10bmac_rx_mem_res, (reg), \
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__func__, __LINE__)
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#define NF10BMAC_WRITE_INTR_4(sc, reg, val, _f, _l) \
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nf10bmac_write_4((sc)->nf10bmac_intr_res, (reg), (val), \
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(_f), (_l))
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#define NF10BMAC_RX_INTR_CLEAR_DIS(sc) \
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NF10BMAC_WRITE_INTR_4((sc), NF10BMAC_INTR_CLEAR_DIS, 1, \
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__func__, __LINE__)
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#define NF10BMAC_RX_INTR_ENABLE(sc) \
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NF10BMAC_WRITE_INTR_4((sc), NF10BMAC_INTR_CTRL, 1, \
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__func__, __LINE__)
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#define NF10BMAC_RX_INTR_DISABLE(sc) \
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NF10BMAC_WRITE_INTR_4((sc), NF10BMAC_INTR_CTRL, 0, \
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__func__, __LINE__)
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#ifdef ENABLE_WATCHDOG
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static void nf10bmac_tick(void *);
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#endif
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@ -318,7 +336,7 @@ nf10bmac_rx_locked(struct nf10bmac_softc *sc)
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* skip to tlast).
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*/
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len = NF10BMAC_READ_4(sc, NF10BMAC_RX_LEN);
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len = NF10BMAC_READ_4(sc, NF10BMAC_RX_LEN) & NF10BMAC_DATA_LEN_MASK;
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if (len > (MCLBYTES - ETHER_ALIGN)) {
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nf10bmac_eat_packet_munch_munch(sc);
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return (0);
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@ -435,6 +453,7 @@ nf10bmac_stop_locked(struct nf10bmac_softc *sc)
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ifp = sc->nf10bmac_ifp;
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ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
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NF10BMAC_RX_INTR_CLEAR_DIS(sc);
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sc->nf10bmac_flags &= ~NF10BMAC_FLAGS_LINK;
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if_link_state_change(ifp, LINK_STATE_DOWN);
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@ -498,6 +517,16 @@ nf10bmac_init_locked(struct nf10bmac_softc *sc)
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/* Instead drain the FIFO; or at least a possible first packet.. */
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nf10bmac_eat_packet_munch_munch(sc);
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#ifdef DEVICE_POLLING
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/* Only enable interrupts if we are not polling. */
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if (ifp->if_capenable & IFCAP_POLLING) {
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NF10BMAC_RX_INTR_CLEAR_DIS(sc);
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} else
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#endif
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{
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NF10BMAC_RX_INTR_ENABLE(sc);
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}
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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@ -556,6 +585,49 @@ nf10bmac_tick(void *xsc)
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}
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#endif
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static void
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nf10bmac_intr(void *arg)
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{
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struct nf10bmac_softc *sc;
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struct ifnet *ifp;
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int rx_npkts;
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sc = (struct nf10bmac_softc *)arg;
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ifp = sc->nf10bmac_ifp;
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NF10BMAC_LOCK(sc);
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#ifdef DEVICE_POLLING
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if (ifp->if_capenable & IFCAP_POLLING) {
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NF10BMAC_UNLOCK(sc);
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return;
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}
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#endif
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/* NF10BMAC_RX_INTR_DISABLE(sc); */
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NF10BMAC_RX_INTR_CLEAR_DIS(sc);
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/* We only have an RX interrupt and no status information. */
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rx_npkts = 0;
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while (rx_npkts < NF10BMAC_MAX_PKTS) {
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int c;
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c = nf10bmac_rx_locked(sc);
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rx_npkts += c;
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if (c == 0)
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break;
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}
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if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
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/* Re-enable interrupts. */
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NF10BMAC_RX_INTR_ENABLE(sc);
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if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
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nf10bmac_start_locked(ifp);
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}
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NF10BMAC_UNLOCK(sc);
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}
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#ifdef DEVICE_POLLING
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static int
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nf10bmac_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
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@ -649,10 +721,16 @@ nf10bmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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break;
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}
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NF10BMAC_RX_INTR_CLEAR_DIS(sc);
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/*
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* Do not allow disabling of polling if we do
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* not have interrupts.
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*/
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} else if (sc->nf10bmac_rx_irq_res != NULL) {
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error = ether_poll_deregister(ifp);
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/* Enable interrupts. */
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NF10BMAC_RX_INTR_ENABLE(sc);
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} else {
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ifp->if_capenable ^= IFCAP_POLLING;
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error = EINVAL;
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@ -673,7 +751,6 @@ nf10bmac_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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return (error);
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}
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/*
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* Generic device handling routines.
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*/
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@ -733,18 +810,40 @@ nf10bmac_attach(device_t dev)
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ifmedia_add(&sc->nf10bmac_media, IFM_ETHER | IFM_10G_T, 0, NULL);
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ifmedia_set(&sc->nf10bmac_media, IFM_ETHER | IFM_10G_T);
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/* Interrupts would go here. */
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/* Initialise. */
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error = 0;
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/* Hook up interrupts. Well the one. */
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if (sc->nf10bmac_rx_irq_res != NULL) {
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error = bus_setup_intr(dev, sc->nf10bmac_rx_irq_res,
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INTR_TYPE_NET | INTR_MPSAFE, NULL, nf10bmac_intr,
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sc, &sc->nf10bmac_rx_intrhand);
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if (error != 0) {
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device_printf(dev, "enabling RX IRQ failed\n");
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ether_ifdetach(ifp);
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goto err;
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}
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}
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if ((ifp->if_capenable & IFCAP_POLLING) != 0 ||
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sc->nf10bmac_rx_irq_res == NULL) {
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#ifdef DEVICE_POLLING
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ifp->if_capenable |= IFCAP_POLLING;
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device_printf(dev, "forcing to polling due to no interrupts\n");
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error = ether_poll_register(nf10bmac_poll, ifp);
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if (error != 0)
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goto err;
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/* If not on and no IRQs force it on. */
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if (sc->nf10bmac_rx_irq_res == NULL) {
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ifp->if_capenable |= IFCAP_POLLING;
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device_printf(dev,
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"forcing to polling due to no interrupts\n");
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}
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error = ether_poll_register(nf10bmac_poll, ifp);
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if (error != 0)
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goto err;
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#else
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device_printf(dev, "no DEVICE_POLLING in kernel and no IRQs\n");
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error = ENXIO;
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device_printf(dev, "no DEVICE_POLLING in kernel and no IRQs\n");
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error = ENXIO;
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#endif
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} else {
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NF10BMAC_RX_INTR_ENABLE(sc);
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}
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err:
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if (error != 0)
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@ -780,6 +879,10 @@ nf10bmac_detach(device_t dev)
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ether_ifdetach(ifp);
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}
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if (sc->nf10bmac_rx_intrhand)
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bus_teardown_intr(dev, sc->nf10bmac_rx_irq_res,
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sc->nf10bmac_rx_intrhand);
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if (ifp != NULL)
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if_free(ifp);
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ifmedia_removeall(&sc->nf10bmac_media);
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@ -797,10 +900,15 @@ nf10bmac_detach_resources(device_t dev)
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sc = device_get_softc(dev);
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if (sc->nf10bmac_mem_res != NULL) {
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if (sc->nf10bmac_rx_irq_res != NULL) {
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bus_release_resource(dev, SYS_RES_IRQ, sc->nf10bmac_rx_irq_rid,
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sc->nf10bmac_rx_irq_res);
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sc->nf10bmac_rx_irq_res = NULL;
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}
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if (sc->nf10bmac_intr_res != NULL) {
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bus_release_resource(dev, SYS_RES_MEMORY,
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sc->nf10bmac_mem_rid, sc->nf10bmac_mem_res);
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sc->nf10bmac_mem_res = NULL;
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sc->nf10bmac_intr_rid, sc->nf10bmac_intr_res);
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sc->nf10bmac_intr_res = NULL;
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}
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if (sc->nf10bmac_rx_mem_res != NULL) {
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bus_release_resource(dev, SYS_RES_MEMORY,
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@ -812,6 +920,11 @@ nf10bmac_detach_resources(device_t dev)
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sc->nf10bmac_tx_mem_rid, sc->nf10bmac_tx_mem_res);
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sc->nf10bmac_tx_mem_res = NULL;
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}
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if (sc->nf10bmac_ctrl_res != NULL) {
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bus_release_resource(dev, SYS_RES_MEMORY,
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sc->nf10bmac_ctrl_rid, sc->nf10bmac_ctrl_res);
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sc->nf10bmac_ctrl_res = NULL;
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}
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}
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int
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@ -85,16 +85,34 @@ nf10bmac_attach_fdt(device_t dev)
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/*
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* FDT lists our resources. For convenience we use three different
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* mappings. We need to attach them in the oder specified in .dts:
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* TX (size 0xc), RX (size 0xc), LOOP (size 0x4).
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* LOOP (size 0x1f), TX (0x2f), RX (0x2f), INTR (0xf).
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*/
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/*
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* LOOP memory region (this could be a general control region).
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* 0x00: 32bit register to enable a Y-"lopback".
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*/
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sc->nf10bmac_ctrl_rid = 0;
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sc->nf10bmac_ctrl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->nf10bmac_ctrl_rid, RF_ACTIVE);
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if (sc->nf10bmac_ctrl_res == NULL) {
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device_printf(dev, "failed to map memory for CTRL region\n");
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error = ENXIO;
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goto err;
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}
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if (bootverbose)
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device_printf(sc->nf10bmac_dev, "CTRL region at mem %p-%p\n",
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(void *)rman_get_start(sc->nf10bmac_ctrl_res),
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(void *)(rman_get_start(sc->nf10bmac_ctrl_res) +
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rman_get_size(sc->nf10bmac_ctrl_res)));
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/*
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* TX and TX metadata FIFO memory region.
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* 0x00: 32bit FIFO data,
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* 0x04: 32bit FIFO metadata,
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* 0x08: 32bit packet length.
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* 0x08: 32bit FIFO metadata,
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* 0x10: 32bit packet length.
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*/
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sc->nf10bmac_tx_mem_rid = 0;
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sc->nf10bmac_tx_mem_rid = 1;
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sc->nf10bmac_tx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->nf10bmac_tx_mem_rid, RF_ACTIVE);
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if (sc->nf10bmac_tx_mem_res == NULL) {
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@ -111,10 +129,10 @@ nf10bmac_attach_fdt(device_t dev)
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/*
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* RX and RXC metadata FIFO memory region.
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* 0x00: 32bit FIFO data,
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* 0x04: 32bit FIFO metadata,
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* 0x08: 32bit packet length.
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* 0x08: 32bit FIFO metadata,
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* 0x10: 32bit packet length.
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*/
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sc->nf10bmac_rx_mem_rid = 1;
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sc->nf10bmac_rx_mem_rid = 2;
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sc->nf10bmac_rx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->nf10bmac_rx_mem_rid, RF_ACTIVE);
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if (sc->nf10bmac_rx_mem_res == NULL) {
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@ -129,22 +147,28 @@ nf10bmac_attach_fdt(device_t dev)
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rman_get_size(sc->nf10bmac_rx_mem_res)));
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/*
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* LOOP memory region (this could be a general control region).
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* 0x00: 32bit register to enable a Y-"lopback".
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* Interrupt handling registers.
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* 0x00: 32bit register to clear (and disable) the RX interrupt.
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* 0x08: 32bit register to enable or disable the RX interrupt.
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*/
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sc->nf10bmac_mem_rid = 2;
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sc->nf10bmac_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->nf10bmac_mem_rid, RF_ACTIVE);
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if (sc->nf10bmac_mem_res == NULL) {
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device_printf(dev, "failed to map memory for CTRL region\n");
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sc->nf10bmac_intr_rid = 3;
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sc->nf10bmac_intr_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->nf10bmac_intr_rid, RF_ACTIVE);
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if (sc->nf10bmac_intr_res == NULL) {
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device_printf(dev, "failed to map memory for INTR region\n");
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error = ENXIO;
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goto err;
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}
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if (bootverbose)
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device_printf(sc->nf10bmac_dev, "CTRL region at mem %p-%p\n",
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(void *)rman_get_start(sc->nf10bmac_mem_res),
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(void *)(rman_get_start(sc->nf10bmac_mem_res) +
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rman_get_size(sc->nf10bmac_mem_res)));
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device_printf(sc->nf10bmac_dev, "INTR region at mem %p-%p\n",
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(void *)rman_get_start(sc->nf10bmac_intr_res),
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(void *)(rman_get_start(sc->nf10bmac_intr_res) +
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rman_get_size(sc->nf10bmac_intr_res)));
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/* (Optional) RX and TX IRQ. */
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sc->nf10bmac_rx_irq_rid = 0;
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sc->nf10bmac_rx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&sc->nf10bmac_rx_irq_rid, RF_ACTIVE | RF_SHAREABLE);
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error = nf10bmac_attach(dev);
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if (error)
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@ -35,15 +35,20 @@
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struct nf10bmac_softc {
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struct ifnet *nf10bmac_ifp;
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struct resource *nf10bmac_ctrl_res;
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struct resource *nf10bmac_tx_mem_res;
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struct resource *nf10bmac_rx_mem_res;
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struct resource *nf10bmac_mem_res;
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struct resource *nf10bmac_intr_res;
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struct resource *nf10bmac_rx_irq_res;
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void *nf10bmac_rx_intrhand;
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uint8_t *nf10bmac_tx_buf;
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device_t nf10bmac_dev;
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int nf10bmac_unit;
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int nf10bmac_ctrl_rid;
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int nf10bmac_tx_mem_rid;
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int nf10bmac_rx_mem_rid;
|
||||
int nf10bmac_mem_rid;
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||||
int nf10bmac_intr_rid;
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||||
int nf10bmac_rx_irq_rid;
|
||||
int nf10bmac_if_flags;
|
||||
uint32_t nf10bmac_flags;
|
||||
#define NF10BMAC_FLAGS_LINK 0x00000001
|
||||
|
Loading…
Reference in New Issue
Block a user