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sfxge(4): move Tx config to ef10 NIC board config

Browse Source 
Submitted by:   Andy Moreton <amoreton at solarflare.com>
Sponsored by:   Solarflare Communications, Inc.
Differential Revision:  https://reviews.freebsd.org/D18191
This commit is contained in:
Andrew Rybchenko 2018-11-28 06:55:36 +00:00
parent 69aff9bb81
commit 40f5e54c62
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=341115
4 changed files with 10 additions and 30 deletions
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10
sys/dev/sfxge/common/ef10_nic.c
View File

@ -1672,6 +1672,16 @@ ef10_nic_board_cfg(
*/
encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)

10
sys/dev/sfxge/common/hunt_nic.c
View File

@ -232,10 +232,6 @@ hunt_board_cfg(
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@ -281,12 +277,6 @@ hunt_board_cfg(
encp->enc_intr_vec_base = base;
encp->enc_intr_limit = nvec;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
goto fail7;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;

10
sys/dev/sfxge/common/medford2_nic.c
View File

@ -166,10 +166,6 @@ medford2_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@ -216,12 +212,6 @@ medford2_board_cfg(
encp->enc_intr_vec_base = base;
encp->enc_intr_limit = nvec;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
/*
* Medford2 stores a single global copy of VPD, not per-PF as on
* Huntington.

10
sys/dev/sfxge/common/medford_nic.c
View File

@ -163,10 +163,6 @@ medford_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@ -213,12 +209,6 @@ medford_board_cfg(
encp->enc_intr_vec_base = base;
encp->enc_intr_limit = nvec;
/*
* Maximum number of bytes into the frame the TCP header can start for
* firmware assisted TSO to work.
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
/*
* Medford stores a single global copy of VPD, not per-PF as on
* Huntington.