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Sort printing of the ID registers on arm64 to be identical to the

Browse Source 
documentation. This will simplify checking new fields when they are added.

MFC after:	2 weeks
Sponsored by:	DARPA, AFRL
This commit is contained in:
Andrew Turner 2019-03-25 18:02:04 +00:00
parent 7c96d54f20
commit 40fcc4760e
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=345510
1 changed files with 78 additions and 78 deletions
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156
sys/arm64/arm64/identcpu.c
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@ -494,6 +494,50 @@ print_cpu_features(u_int cpu)
printed = 0;
sbuf_printf(sb, " Instruction Set Attributes 0 = <");
switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_DP_NONE:
break;
case ID_AA64ISAR0_DP_IMPL:
sbuf_printf(sb, "%sDotProd", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown DP", SEP_STR);
break;
}
switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SM4_NONE:
break;
case ID_AA64ISAR0_SM4_IMPL:
sbuf_printf(sb, "%sSM4", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown SM4", SEP_STR);
break;
}
switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SM3_NONE:
break;
case ID_AA64ISAR0_SM3_IMPL:
sbuf_printf(sb, "%sSM3", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown SM3", SEP_STR);
break;
}
switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SHA3_NONE:
break;
case ID_AA64ISAR0_SHA3_IMPL:
sbuf_printf(sb, "%sSHA3", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown SHA3", SEP_STR);
break;
}
switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_RDM_NONE:
break;
@ -514,28 +558,14 @@ print_cpu_features(u_int cpu)
sbuf_printf(sb, "%sUnknown Atomic", SEP_STR);
}
switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_AES_NONE:
switch (ID_AA64ISAR0_CRC32(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_CRC32_NONE:
break;
case ID_AA64ISAR0_AES_BASE:
sbuf_printf(sb, "%sAES", SEP_STR);
break;
case ID_AA64ISAR0_AES_PMULL:
sbuf_printf(sb, "%sAES+PMULL", SEP_STR);
case ID_AA64ISAR0_CRC32_BASE:
sbuf_printf(sb, "%sCRC32", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown AES", SEP_STR);
break;
}
switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SHA1_NONE:
break;
case ID_AA64ISAR0_SHA1_BASE:
sbuf_printf(sb, "%sSHA1", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown SHA1", SEP_STR);
sbuf_printf(sb, "%sUnknown CRC32", SEP_STR);
break;
}
@ -553,58 +583,28 @@ print_cpu_features(u_int cpu)
break;
}
switch (ID_AA64ISAR0_CRC32(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_CRC32_NONE:
switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SHA1_NONE:
break;
case ID_AA64ISAR0_CRC32_BASE:
sbuf_printf(sb, "%sCRC32", SEP_STR);
case ID_AA64ISAR0_SHA1_BASE:
sbuf_printf(sb, "%sSHA1", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown CRC32", SEP_STR);
sbuf_printf(sb, "%sUnknown SHA1", SEP_STR);
break;
}
switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SHA3_NONE:
switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_AES_NONE:
break;
case ID_AA64ISAR0_SHA3_IMPL:
sbuf_printf(sb, "%sSHA3", SEP_STR);
case ID_AA64ISAR0_AES_BASE:
sbuf_printf(sb, "%sAES", SEP_STR);
break;
case ID_AA64ISAR0_AES_PMULL:
sbuf_printf(sb, "%sAES+PMULL", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown SHA3", SEP_STR);
break;
}
switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SM3_NONE:
break;
case ID_AA64ISAR0_SM3_IMPL:
sbuf_printf(sb, "%sSM3", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown SM3", SEP_STR);
break;
}
switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_SM4_NONE:
break;
case ID_AA64ISAR0_SM4_IMPL:
sbuf_printf(sb, "%sSM4", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown SM4", SEP_STR);
break;
}
switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) {
case ID_AA64ISAR0_DP_NONE:
break;
case ID_AA64ISAR0_DP_IMPL:
sbuf_printf(sb, "%sDotProd", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown DP", SEP_STR);
sbuf_printf(sb, "%sUnknown AES", SEP_STR);
break;
}
@ -868,17 +868,6 @@ print_cpu_features(u_int cpu)
break;
}
switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) {
case ID_AA64MMFR0_TGRAN16_NONE:
break;
case ID_AA64MMFR0_TGRAN16_IMPL:
sbuf_printf(sb, "%s16k Granule", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR);
break;
}
switch (ID_AA64MMFR0_TGRAN64(cpu_desc[cpu].id_aa64mmfr0)) {
case ID_AA64MMFR0_TGRAN64_NONE:
break;
@ -890,14 +879,14 @@ print_cpu_features(u_int cpu)
break;
}
switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) {
case ID_AA64MMFR0_BIGEND_FIXED:
switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) {
case ID_AA64MMFR0_TGRAN16_NONE:
break;
case ID_AA64MMFR0_BIGEND_MIXED:
sbuf_printf(sb, "%sMixedEndian", SEP_STR);
case ID_AA64MMFR0_TGRAN16_IMPL:
sbuf_printf(sb, "%s16k Granule", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR);
sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR);
break;
}
@ -923,6 +912,17 @@ print_cpu_features(u_int cpu)
break;
}
switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) {
case ID_AA64MMFR0_BIGEND_FIXED:
break;
case ID_AA64MMFR0_BIGEND_MIXED:
sbuf_printf(sb, "%sMixedEndian", SEP_STR);
break;
default:
sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR);
break;
}
switch (ID_AA64MMFR0_ASID_BITS(cpu_desc[cpu].id_aa64mmfr0)) {
case ID_AA64MMFR0_ASID_BITS_8:
sbuf_printf(sb, "%s8bit ASID", SEP_STR);