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Add support for Intel Arria 10 SoC Development Kit.

Browse Source 
Use standard DTS files for SOCKIT and SOCDK.

Sponsored by:	DARPA, AFRL
This commit is contained in:
Ruslan Bukin 2017-02-28 14:02:16 +00:00
parent 3a13860a1b
commit 428157830b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=314389
14 changed files with 284 additions and 326 deletions
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57
sys/arm/altera/socfpga/socfpga_machdep.c
View File

@ -1,5 +1,5 @@
/*-
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
* Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
@ -83,24 +83,43 @@ socfpga_devmap_init(platform_t plat)
return (0);
}
static int
socfpga_a10_devmap_init(platform_t plat)
{
/* UART */
devmap_add_entry(0xffc00000, 0x100000);
/* USB OTG */
devmap_add_entry(0xffb00000, 0x100000);
/* dwmmc */
devmap_add_entry(0xff800000, 0x100000);
/* scu */
devmap_add_entry(0xfff00000, 0x100000);
return (0);
}
static void
socfpga_cpu_reset(platform_t plat)
_socfpga_cpu_reset(platform_t plat, uint32_t reg)
{
uint32_t paddr;
bus_addr_t vaddr;
phandle_t node;
if (rstmgr_warmreset() == 0)
if (rstmgr_warmreset(reg) == 0)
goto end;
node = OF_finddevice("rstmgr");
node = OF_finddevice("/soc/rstmgr");
if (node == -1)
goto end;
if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) {
bus_space_write_4(fdtbus_bs_tag, vaddr,
RSTMGR_CTRL, CTRL_SWWARMRSTREQ);
reg, CTRL_SWWARMRSTREQ);
}
}
@ -108,16 +127,38 @@ socfpga_cpu_reset(platform_t plat)
while (1);
}
static void
socfpga_cpu_reset(platform_t plat)
{
_socfpga_cpu_reset(plat, RSTMGR_CTRL);
}
static void
socfpga_a10_cpu_reset(platform_t plat)
{
_socfpga_cpu_reset(plat, RSTMGR_A10_CTRL);
}
static platform_method_t socfpga_methods[] = {
PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init),
PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset),
#ifdef SMP
PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid),
PLATFORMMETHOD(platform_mp_start_ap, socfpga_mp_start_ap),
#endif
PLATFORMMETHOD_END,
};
FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200);
FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga", 0);
static platform_method_t socfpga_a10_methods[] = {
PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init),
PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset),
#ifdef SMP
PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid),
PLATFORMMETHOD(platform_mp_start_ap, socfpga_a10_mp_start_ap),
#endif
PLATFORMMETHOD_END,
};
FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200);

2
sys/arm/altera/socfpga/socfpga_manager.c
View File

@ -377,7 +377,7 @@ fpgamgr_probe(device_t dev)
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "altr,fpga-mgr"))
if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr"))
return (ENXIO);
device_set_desc(dev, "FPGA Manager");

57
sys/arm/altera/socfpga/socfpga_mp.c
View File

@ -1,5 +1,5 @@
/*-
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
* Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
@ -50,8 +50,10 @@ __FBSDID("$FreeBSD$");
#include <machine/platformvar.h>
#include <arm/altera/socfpga/socfpga_mp.h>
#include <arm/altera/socfpga/socfpga_rstmgr.h>
#define SCU_PHYSBASE 0xFFFEC000
#define SCU_PHYSBASE_A10 0xFFFFC000
#define SCU_SIZE 0x100
#define SCU_CONTROL_REG 0x00
@ -69,11 +71,12 @@ __FBSDID("$FreeBSD$");
#define RSTMGR_PHYSBASE 0xFFD05000
#define RSTMGR_SIZE 0x100
#define MPUMODRST 0x10
#define MPUMODRST_CPU1 (1 << 1)
#define RAM_PHYSBASE 0x0
#define RAM_SIZE 0x1000
#define RAM_SIZE 0x1000
#define SOCFPGA_SOCKIT 1
#define SOCFPGA_SOCDK 2
extern char *mpentry_addr;
static void socfpga_trampoline(void);
@ -109,15 +112,22 @@ socfpga_mp_setmaxid(platform_t plat)
mp_maxid = ncpu - 1;
}
void
socfpga_mp_start_ap(platform_t plat)
static void
_socfpga_mp_start_ap(platform_t plat, uint32_t platid)
{
bus_space_handle_t scu, rst, ram;
int reg;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
SCU_SIZE, 0, &scu) != 0)
if (platid == SOCFPGA_SOCDK) {
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
} else {
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
}
if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
RSTMGR_SIZE, 0, &rst) != 0)
panic("Couldn't map the reset manager (RSTMGR)\n");
@ -139,7 +149,13 @@ socfpga_mp_start_ap(platform_t plat)
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
/* Put CPU1 to reset state */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, MPUMODRST_CPU1);
if (platid == SOCFPGA_SOCDK) {
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
} else {
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, MPUMODRST_CPU1);
}
/* Enable the SCU, then clean the cache on this core */
reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
@ -154,7 +170,13 @@ socfpga_mp_start_ap(platform_t plat)
dcache_wbinv_poc_all();
/* Put CPU1 out from reset */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
if (platid == SOCFPGA_SOCDK) {
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, 0);
} else {
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, 0);
}
dsb();
sev();
@ -163,3 +185,18 @@ socfpga_mp_start_ap(platform_t plat)
bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
}
void
socfpga_a10_mp_start_ap(platform_t plat)
{
_socfpga_mp_start_ap(plat, SOCFPGA_SOCDK);
}
void
socfpga_mp_start_ap(platform_t plat)
{
_socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT);
}

1
sys/arm/altera/socfpga/socfpga_mp.h
View File

@ -30,5 +30,6 @@
void socfpga_mp_setmaxid(platform_t);
void socfpga_mp_start_ap(platform_t);
void socfpga_a10_mp_start_ap(platform_t);
#endif /* _SOCFPGA_MP_H_ */

8
sys/arm/altera/socfpga/socfpga_rstmgr.c
View File

@ -1,5 +1,5 @@
/*-
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
* Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
@ -166,7 +166,7 @@ rstmgr_sysctl(SYSCTL_HANDLER_ARGS)
}
int
rstmgr_warmreset(void)
rstmgr_warmreset(uint32_t reg)
{
struct rstmgr_softc *sc;
@ -175,8 +175,7 @@ rstmgr_warmreset(void)
return (1);
/* Request warm reset */
WRITE4(sc, RSTMGR_CTRL,
CTRL_SWWARMRSTREQ);
WRITE4(sc, reg, CTRL_SWWARMRSTREQ);
return (0);
}
@ -214,6 +213,7 @@ rstmgr_probe(device_t dev)
return (ENXIO);
device_set_desc(dev, "Reset Manager");
return (BUS_PROBE_DEFAULT);
}

6
sys/arm/altera/socfpga/socfpga_rstmgr.h
View File

@ -35,6 +35,7 @@
#define CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */
#define RSTMGR_COUNTS 0x8 /* Reset Cycles Count */
#define RSTMGR_MPUMODRST 0x10 /* MPU Module Reset */
#define MPUMODRST_CPU1 (1 << 1)
#define RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */
#define RSTMGR_PER2MODRST 0x18 /* Peripheral 2 Module Reset */
#define RSTMGR_BRGMODRST 0x1C /* Bridge Module Reset */
@ -43,4 +44,7 @@
#define BRGMODRST_HPS2FPGA (1 << 0)
#define RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */
int rstmgr_warmreset(void);
#define RSTMGR_A10_CTRL 0xC /* Control */
#define RSTMGR_A10_MPUMODRST 0x20 /* MPU Module Reset */
int rstmgr_warmreset(uint32_t reg);

30
sys/arm/conf/SOCDK Normal file
View File

@ -0,0 +1,30 @@
#
# Kernel configuration for Altera Arria10 SOC Development Kit.
#
# For more information on this file, please read the config(5) manual page,
# and/or the handbook section on Kernel Configuration Files:
#
# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
#NO_UNIVERSE
include "SOCFPGA"
ident SOCDK
options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\"
# Flattened Device Tree
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=socfpga_arria10_socdk_sdmmc.dts

7
sys/arm/conf/SOCKIT.common → sys/arm/conf/SOCFPGA
View File

@ -1,5 +1,5 @@
#
# Kernel configuration for Terasic SoCKit (Altera Cyclone V SoC).
# Kernel configuration for Altera SOCFPGA development kits.
#
# For more information on this file, please read the config(5) manual page,
# and/or the handbook section on Kernel Configuration Files:
@ -18,6 +18,7 @@
#
# $FreeBSD$
ident SOCFPGA
include "std.armv6"
include "../altera/socfpga/std.socfpga"
@ -29,6 +30,7 @@ options SCHED_ULE # ULE scheduler
options PLATFORM # Platform based SoC
options PLATFORM_SMP
options SMP # Enable multiple cores
options MULTIDELAY
# NFS root from boopt/dhcp
#options BOOTP
@ -60,7 +62,6 @@ device gpio
# USB support
options USB_HOST_ALIGN=64 # Align usb buffers to cache line size.
device usb
#device musb
device dwcotg
device umass
@ -70,7 +71,7 @@ device pass
# Serial ports
device uart
device uart_ns8250
device uart_snps
# I2C (TWSI)
device iic

6
sys/arm/conf/SOCKIT
View File

@ -20,11 +20,11 @@
#NO_UNIVERSE
include "SOCFPGA"
ident SOCKIT
include "SOCKIT.common"
options ROOTDEVNAME=\"ufs:/dev/da0\"
options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\"
# Flattened Device Tree
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=socfpga-sockit.dts
makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_sdmmc.dts

6
sys/arm/conf/SOCKIT-BERI
View File

@ -18,8 +18,10 @@
#
# $FreeBSD$
#NO_UNIVERSE
include "SOCFPGA"
ident SOCKIT-BERI
include "SOCKIT.common"
options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\"
@ -32,4 +34,4 @@ device altera_pio
# Flattened Device Tree
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=socfpga-sockit-beri.dts
makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_beri_sdmmc.dts

200
sys/boot/fdt/dts/arm/socfpga.dtsi
View File

@ -1,200 +0,0 @@
/*-
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
compatible = "altr,socfpga";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&GIC>;
aliases {
soc = &SOC;
rstmgr = &rstmgr;
l3regs = &l3regs;
serial0 = &serial0;
serial1 = &serial1;
};
SOC: socfpga {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
bus-frequency = <0>;
GIC: interrupt-controller@fffed000 {
compatible = "arm,gic";
reg = < 0xfffed000 0x1000 >, /* Distributor */
< 0xfffec100 0x100 >; /* CPU Interface */
interrupt-controller;
#interrupt-cells = <1>;
};
mp_tmr@40002100 {
compatible = "arm,mpcore-timers";
clock-frequency = <200000000>;
#address-cells = <1>;
#size-cells = <0>;
reg = < 0xfffec200 0x100 >, /* Global Timer */
< 0xfffec600 0x100 >; /* Private Timer */
interrupts = < 27 29 >;
interrupt-parent = < &GIC >;
};
sysmgr: sysmgr@ffd08000 {
compatible = "altr,sys-mgr";
reg = <0xffd08000 0x1000>;
};
clkmgr: clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
};
rstmgr: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
};
l3regs: l3regs@ff800000 {
compatible = "altr,l3regs";
reg = <0xff800000 0x1000>;
};
fpgamgr: fpgamgr@ff706000 {
compatible = "altr,fpga-mgr";
reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
<0xffb90000 0x1000>; /* FPGAMGRDATA */
interrupts = < 207 >;
interrupt-parent = <&GIC>;
};
gpio0: gpio@ff708000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <29>;
};
};
gpio1: gpio@ff709000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <29>;
};
};
gpio2: gpio@ff70a000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <27>;
};
};
serial0: serial@ffc02000 {
compatible = "ns16550";
reg = <0xffc02000 0x1000>;
reg-shift = <2>;
interrupts = <194>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 100000000 >;
status = "disabled";
};
serial1: serial@ffc03000 {
compatible = "ns16550";
reg = <0xffc03000 0x1000>;
reg-shift = <2>;
interrupts = <195>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 100000000 >;
status = "disabled";
};
usb0: usb@ffb00000 {
compatible = "synopsys,designware-hs-otg2";
reg = <0xffb00000 0xffff>;
interrupts = <157>;
interrupt-parent = <&GIC>;
status = "disabled";
};
usb1: usb@ffb40000 {
compatible = "synopsys,designware-hs-otg2";
reg = <0xffb40000 0xffff>;
interrupts = <160>;
interrupt-parent = <&GIC>;
dr_mode = "host";
status = "disabled";
};
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac",
"snps,dwmac-3.70a", "snps,dwmac";
reg = <0xff700000 0x2000>;
interrupts = <147>;
interrupt-parent = <&GIC>;
phy-mode = "rgmii";
status = "disabled";
};
gmac1: ethernet@ff702000 {
compatible = "altr,socfpga-stmmac",
"snps,dwmac-3.70a", "snps,dwmac";
reg = <0xff702000 0x2000>;
interrupts = <152>;
interrupt-parent = <&GIC>;
phy-mode = "rgmii";
status = "disabled";
};
mmc: dwmmc@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <171>;
interrupt-parent = <&GIC>;
fifo-depth = <0x400>;
status = "disabled";
};
};
};

82
sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts Normal file
View File

@ -0,0 +1,82 @@
/*-
* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
/ {
model = "Altera SOCFPGA Arria 10";
compatible = "altr,socfpga-arria10", "altr,socfpga";
/* Reserve first page for secondary CPU trampoline code */
memreserve = < 0x00000000 0x1000 >;
soc {
/* Local timer */
timer@ffffc600 {
clock-frequency = <200000000>;
};
/* Global timer */
global_timer: timer@ffffc200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xffffc200 0x20>;
interrupts = <1 11 0x301>;
clock-frequency = <200000000>;
};
};
chosen {
stdin = "serial1";
stdout = "serial1";
};
};
&uart1 {
clock-frequency = < 50000000 >;
};
&mmc {
status = "okay";
num-slots = <1>;
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
bus-frequency = <200000000>;
};
&i2c1 {
lcd@28 {
compatible = "newhaven,nhd-0216k3z-nsw-bbw";
reg = <0x28>;
};
};

78
sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts → sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts
View File

@ -1,9 +1,9 @@
/*-
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
@ -30,58 +30,29 @@
* $FreeBSD$
*/
/dts-v1/;
/include/ "socfpga.dtsi"
/* /dts-v1/; */
#include "socfpga_cyclone5_sockit.dts"
/ {
model = "Terasic SoCKit";
model = "Terasic SoCkit";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */
< 0x00001000 0x1000 >, /* virtio block */
< 0x00002000 0x1000 >; /* virtio net */
memory {
device_type = "memory";
reg = < 0x00000000 0x40000000 >; /* 1G RAM */
};
SOC: socfpga {
serial0: serial@ffc02000 {
status = "okay";
soc {
/* Local timer */
timer@fffec600 {
clock-frequency = <200000000>;
};
usb1: usb@ffb40000 {
status = "okay";
};
gmac1: ethernet@ff702000 {
status = "okay";
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <2600>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
};
mmc: dwmmc@ff704000 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
bus-frequency = <25000000>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
/* Global timer */
global_timer: timer@fffec200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xfffec200 0x20>;
interrupts = <1 11 0xf04>;
clock-frequency = <200000000>;
};
beri_mem0: mem@d0000000 {
@ -94,7 +65,6 @@
compatible = "altr,pio";
reg = <0xc0020000 0x1000>; /* recv */
interrupts = < 76 >;
interrupt-parent = <&GIC>;
status = "okay";
};
@ -102,7 +72,6 @@
compatible = "altr,pio";
reg = <0xc0021000 0x1000>; /* send */
interrupts = < 82 >; /* not in use on arm side */
interrupt-parent = <&GIC>;
status = "okay";
};
@ -110,7 +79,6 @@
compatible = "altr,pio";
reg = <0xc0022000 0x1000>; /* recv */
interrupts = < 77 >;
interrupt-parent = <&GIC>;
status = "okay";
};
@ -118,7 +86,6 @@
compatible = "altr,pio";
reg = <0xc0023000 0x1000>; /* send */
interrupts = < 83 >; /* not in use on arm side */
interrupt-parent = <&GIC>;
status = "okay";
};
@ -144,7 +111,6 @@
compatible = "sri-cambridge,beri-ring";
reg = <0xc0000000 0x3000>;
interrupts = < 72 73 >;
interrupt-parent = <&GIC>;
device_name = "beri_debug";
data_size = <0x1000>;
data_read = <0x0>;
@ -158,7 +124,6 @@
compatible = "sri-cambridge,beri-ring";
reg = <0xc0004000 0x3000>;
interrupts = < 74 75 >;
interrupt-parent = <&GIC>;
device_name = "beri_console";
data_size = <0x1000>;
data_read = <0x0>;
@ -170,8 +135,19 @@
};
chosen {
bootargs = "-v";
stdin = "serial0";
stdout = "serial0";
};
};
&mmc0 {
bus-frequency = <25000000>;
};
&uart0 {
clock-frequency = <100000000>;
};
&uart1 {
status = "disabled";
};

70
sys/boot/fdt/dts/arm/socfpga-sockit.dts → sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts
View File

@ -1,9 +1,9 @@
/*-
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
@ -30,61 +30,45 @@
* $FreeBSD$
*/
/dts-v1/;
/include/ "socfpga.dtsi"
/* /dts-v1/; */
#include "socfpga_cyclone5_sockit.dts"
/ {
model = "Terasic SoCKit";
model = "Terasic SoCkit";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
/* Reserve first page for secondary CPU trampoline code */
memreserve = < 0x00000000 0x1000 >;
memory {
device_type = "memory";
reg = < 0x00000000 0x40000000 >; /* 1G RAM */
};
SOC: socfpga {
serial0: serial@ffc02000 {
status = "okay";
soc {
/* Local timer */
timer@fffec600 {
clock-frequency = <200000000>;
};
usb1: usb@ffb40000 {
status = "okay";
};
gmac1: ethernet@ff702000 {
status = "okay";
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <2600>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
};
mmc: dwmmc@ff704000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
bus-frequency = <25000000>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
/* Global timer */
global_timer: timer@fffec200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xfffec200 0x20>;
interrupts = <1 11 0xf04>;
clock-frequency = <200000000>;
};
};
chosen {
bootargs = "-v";
stdin = "serial0";
stdout = "serial0";
};
};
&mmc0 {
bus-frequency = <25000000>;
};
&uart0 {
clock-frequency = <100000000>;
};
&uart1 {
status = "disabled";
};