Add support for Intel Arria 10 SoC Development Kit.
Use standard DTS files for SOCKIT and SOCDK. Sponsored by: DARPA, AFRL
This commit is contained in:
parent
3a13860a1b
commit
428157830b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=314389
@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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@ -83,24 +83,43 @@ socfpga_devmap_init(platform_t plat)
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return (0);
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}
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static int
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socfpga_a10_devmap_init(platform_t plat)
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{
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/* UART */
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devmap_add_entry(0xffc00000, 0x100000);
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/* USB OTG */
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devmap_add_entry(0xffb00000, 0x100000);
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/* dwmmc */
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devmap_add_entry(0xff800000, 0x100000);
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/* scu */
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devmap_add_entry(0xfff00000, 0x100000);
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return (0);
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}
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static void
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socfpga_cpu_reset(platform_t plat)
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_socfpga_cpu_reset(platform_t plat, uint32_t reg)
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{
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uint32_t paddr;
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bus_addr_t vaddr;
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phandle_t node;
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if (rstmgr_warmreset() == 0)
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if (rstmgr_warmreset(reg) == 0)
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goto end;
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node = OF_finddevice("rstmgr");
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node = OF_finddevice("/soc/rstmgr");
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if (node == -1)
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goto end;
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if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
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if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) {
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bus_space_write_4(fdtbus_bs_tag, vaddr,
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RSTMGR_CTRL, CTRL_SWWARMRSTREQ);
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reg, CTRL_SWWARMRSTREQ);
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}
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}
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@ -108,16 +127,38 @@ socfpga_cpu_reset(platform_t plat)
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while (1);
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}
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static void
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socfpga_cpu_reset(platform_t plat)
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{
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_socfpga_cpu_reset(plat, RSTMGR_CTRL);
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}
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static void
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socfpga_a10_cpu_reset(platform_t plat)
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{
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_socfpga_cpu_reset(plat, RSTMGR_A10_CTRL);
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}
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static platform_method_t socfpga_methods[] = {
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PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init),
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PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset),
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#ifdef SMP
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PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid),
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PLATFORMMETHOD(platform_mp_start_ap, socfpga_mp_start_ap),
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#endif
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PLATFORMMETHOD_END,
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};
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FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200);
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FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga", 0);
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static platform_method_t socfpga_a10_methods[] = {
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PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init),
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PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset),
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#ifdef SMP
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PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid),
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PLATFORMMETHOD(platform_mp_start_ap, socfpga_a10_mp_start_ap),
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#endif
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PLATFORMMETHOD_END,
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};
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FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200);
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@ -377,7 +377,7 @@ fpgamgr_probe(device_t dev)
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "altr,fpga-mgr"))
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if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr"))
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return (ENXIO);
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device_set_desc(dev, "FPGA Manager");
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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@ -50,8 +50,10 @@ __FBSDID("$FreeBSD$");
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#include <machine/platformvar.h>
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#include <arm/altera/socfpga/socfpga_mp.h>
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#include <arm/altera/socfpga/socfpga_rstmgr.h>
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#define SCU_PHYSBASE 0xFFFEC000
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#define SCU_PHYSBASE_A10 0xFFFFC000
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#define SCU_SIZE 0x100
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#define SCU_CONTROL_REG 0x00
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@ -69,11 +71,12 @@ __FBSDID("$FreeBSD$");
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#define RSTMGR_PHYSBASE 0xFFD05000
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#define RSTMGR_SIZE 0x100
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#define MPUMODRST 0x10
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#define MPUMODRST_CPU1 (1 << 1)
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#define RAM_PHYSBASE 0x0
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#define RAM_SIZE 0x1000
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#define RAM_SIZE 0x1000
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#define SOCFPGA_SOCKIT 1
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#define SOCFPGA_SOCDK 2
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extern char *mpentry_addr;
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static void socfpga_trampoline(void);
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@ -109,15 +112,22 @@ socfpga_mp_setmaxid(platform_t plat)
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mp_maxid = ncpu - 1;
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}
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void
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socfpga_mp_start_ap(platform_t plat)
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static void
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_socfpga_mp_start_ap(platform_t plat, uint32_t platid)
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{
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bus_space_handle_t scu, rst, ram;
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int reg;
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
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SCU_SIZE, 0, &scu) != 0)
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if (platid == SOCFPGA_SOCDK) {
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
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SCU_SIZE, 0, &scu) != 0)
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panic("Couldn't map the SCU\n");
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} else {
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
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SCU_SIZE, 0, &scu) != 0)
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panic("Couldn't map the SCU\n");
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}
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if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
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RSTMGR_SIZE, 0, &rst) != 0)
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panic("Couldn't map the reset manager (RSTMGR)\n");
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@ -139,7 +149,13 @@ socfpga_mp_start_ap(platform_t plat)
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
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/* Put CPU1 to reset state */
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bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, MPUMODRST_CPU1);
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if (platid == SOCFPGA_SOCDK) {
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
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} else {
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_MPUMODRST, MPUMODRST_CPU1);
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}
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/* Enable the SCU, then clean the cache on this core */
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reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
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@ -154,7 +170,13 @@ socfpga_mp_start_ap(platform_t plat)
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dcache_wbinv_poc_all();
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/* Put CPU1 out from reset */
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bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
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if (platid == SOCFPGA_SOCDK) {
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_A10_MPUMODRST, 0);
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} else {
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_MPUMODRST, 0);
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}
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dsb();
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sev();
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@ -163,3 +185,18 @@ socfpga_mp_start_ap(platform_t plat)
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bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
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bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
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}
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void
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socfpga_a10_mp_start_ap(platform_t plat)
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{
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_socfpga_mp_start_ap(plat, SOCFPGA_SOCDK);
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}
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void
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socfpga_mp_start_ap(platform_t plat)
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{
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_socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT);
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}
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@ -30,5 +30,6 @@
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void socfpga_mp_setmaxid(platform_t);
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void socfpga_mp_start_ap(platform_t);
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void socfpga_a10_mp_start_ap(platform_t);
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#endif /* _SOCFPGA_MP_H_ */
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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@ -166,7 +166,7 @@ rstmgr_sysctl(SYSCTL_HANDLER_ARGS)
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}
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int
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rstmgr_warmreset(void)
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rstmgr_warmreset(uint32_t reg)
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{
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struct rstmgr_softc *sc;
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@ -175,8 +175,7 @@ rstmgr_warmreset(void)
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return (1);
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/* Request warm reset */
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WRITE4(sc, RSTMGR_CTRL,
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CTRL_SWWARMRSTREQ);
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WRITE4(sc, reg, CTRL_SWWARMRSTREQ);
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return (0);
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}
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@ -214,6 +213,7 @@ rstmgr_probe(device_t dev)
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return (ENXIO);
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device_set_desc(dev, "Reset Manager");
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return (BUS_PROBE_DEFAULT);
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}
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@ -35,6 +35,7 @@
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#define CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */
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#define RSTMGR_COUNTS 0x8 /* Reset Cycles Count */
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#define RSTMGR_MPUMODRST 0x10 /* MPU Module Reset */
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#define MPUMODRST_CPU1 (1 << 1)
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#define RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */
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#define RSTMGR_PER2MODRST 0x18 /* Peripheral 2 Module Reset */
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#define RSTMGR_BRGMODRST 0x1C /* Bridge Module Reset */
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@ -43,4 +44,7 @@
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#define BRGMODRST_HPS2FPGA (1 << 0)
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#define RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */
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int rstmgr_warmreset(void);
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#define RSTMGR_A10_CTRL 0xC /* Control */
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#define RSTMGR_A10_MPUMODRST 0x20 /* MPU Module Reset */
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int rstmgr_warmreset(uint32_t reg);
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30
sys/arm/conf/SOCDK
Normal file
30
sys/arm/conf/SOCDK
Normal file
@ -0,0 +1,30 @@
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#
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# Kernel configuration for Altera Arria10 SOC Development Kit.
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#
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# For more information on this file, please read the config(5) manual page,
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# and/or the handbook section on Kernel Configuration Files:
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#
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# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
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#
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# The handbook is also available locally in /usr/share/doc/handbook
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# if you've installed the doc distribution, otherwise always see the
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# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
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# latest information.
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#
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# An exhaustive list of options and more detailed explanations of the
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# device lines is also present in the ../../conf/NOTES and NOTES files.
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# If you are in doubt as to the purpose or necessity of a line, check first
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# in NOTES.
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#
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# $FreeBSD$
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#NO_UNIVERSE
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include "SOCFPGA"
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ident SOCDK
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options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\"
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# Flattened Device Tree
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options FDT_DTB_STATIC
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makeoptions FDT_DTS_FILE=socfpga_arria10_socdk_sdmmc.dts
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@ -1,5 +1,5 @@
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#
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# Kernel configuration for Terasic SoCKit (Altera Cyclone V SoC).
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# Kernel configuration for Altera SOCFPGA development kits.
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#
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# For more information on this file, please read the config(5) manual page,
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# and/or the handbook section on Kernel Configuration Files:
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@ -18,6 +18,7 @@
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#
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# $FreeBSD$
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ident SOCFPGA
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include "std.armv6"
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include "../altera/socfpga/std.socfpga"
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@ -29,6 +30,7 @@ options SCHED_ULE # ULE scheduler
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options PLATFORM # Platform based SoC
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options PLATFORM_SMP
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options SMP # Enable multiple cores
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options MULTIDELAY
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# NFS root from boopt/dhcp
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#options BOOTP
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@ -60,7 +62,6 @@ device gpio
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# USB support
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options USB_HOST_ALIGN=64 # Align usb buffers to cache line size.
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device usb
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#device musb
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device dwcotg
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device umass
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@ -70,7 +71,7 @@ device pass
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# Serial ports
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device uart
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device uart_ns8250
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device uart_snps
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# I2C (TWSI)
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device iic
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@ -20,11 +20,11 @@
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#NO_UNIVERSE
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include "SOCFPGA"
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ident SOCKIT
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include "SOCKIT.common"
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options ROOTDEVNAME=\"ufs:/dev/da0\"
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options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\"
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# Flattened Device Tree
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options FDT_DTB_STATIC
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makeoptions FDT_DTS_FILE=socfpga-sockit.dts
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makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_sdmmc.dts
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@ -18,8 +18,10 @@
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#
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# $FreeBSD$
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#NO_UNIVERSE
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include "SOCFPGA"
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ident SOCKIT-BERI
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include "SOCKIT.common"
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options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\"
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@ -32,4 +34,4 @@ device altera_pio
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# Flattened Device Tree
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options FDT_DTB_STATIC
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makeoptions FDT_DTS_FILE=socfpga-sockit-beri.dts
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makeoptions FDT_DTS_FILE=socfpga_cyclone5_sockit_beri_sdmmc.dts
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@ -1,200 +0,0 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
|
||||
*
|
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* This software was developed by SRI International and the University of
|
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/ {
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compatible = "altr,socfpga";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&GIC>;
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aliases {
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soc = &SOC;
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rstmgr = &rstmgr;
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l3regs = &l3regs;
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serial0 = &serial0;
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serial1 = &serial1;
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};
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SOC: socfpga {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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bus-frequency = <0>;
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GIC: interrupt-controller@fffed000 {
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compatible = "arm,gic";
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reg = < 0xfffed000 0x1000 >, /* Distributor */
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< 0xfffec100 0x100 >; /* CPU Interface */
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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mp_tmr@40002100 {
|
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compatible = "arm,mpcore-timers";
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clock-frequency = <200000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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||||
reg = < 0xfffec200 0x100 >, /* Global Timer */
|
||||
< 0xfffec600 0x100 >; /* Private Timer */
|
||||
interrupts = < 27 29 >;
|
||||
interrupt-parent = < &GIC >;
|
||||
};
|
||||
|
||||
sysmgr: sysmgr@ffd08000 {
|
||||
compatible = "altr,sys-mgr";
|
||||
reg = <0xffd08000 0x1000>;
|
||||
};
|
||||
|
||||
clkmgr: clkmgr@ffd04000 {
|
||||
compatible = "altr,clk-mgr";
|
||||
reg = <0xffd04000 0x1000>;
|
||||
};
|
||||
|
||||
rstmgr: rstmgr@ffd05000 {
|
||||
compatible = "altr,rst-mgr";
|
||||
reg = <0xffd05000 0x1000>;
|
||||
};
|
||||
|
||||
l3regs: l3regs@ff800000 {
|
||||
compatible = "altr,l3regs";
|
||||
reg = <0xff800000 0x1000>;
|
||||
};
|
||||
|
||||
fpgamgr: fpgamgr@ff706000 {
|
||||
compatible = "altr,fpga-mgr";
|
||||
reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
|
||||
<0xffb90000 0x1000>; /* FPGAMGRDATA */
|
||||
interrupts = < 207 >;
|
||||
interrupt-parent = <&GIC>;
|
||||
};
|
||||
|
||||
gpio0: gpio@ff708000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff708000 0x1000>;
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
snps,nr-gpios = <29>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@ff709000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff709000 0x1000>;
|
||||
portb: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
snps,nr-gpios = <29>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@ff70a000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff70a000 0x1000>;
|
||||
portc: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
snps,nr-gpios = <27>;
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@ffc02000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0xffc02000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <194>;
|
||||
interrupt-parent = <&GIC>;
|
||||
current-speed = <115200>;
|
||||
clock-frequency = < 100000000 >;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial1: serial@ffc03000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0xffc03000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <195>;
|
||||
interrupt-parent = <&GIC>;
|
||||
current-speed = <115200>;
|
||||
clock-frequency = < 100000000 >;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb0: usb@ffb00000 {
|
||||
compatible = "synopsys,designware-hs-otg2";
|
||||
reg = <0xffb00000 0xffff>;
|
||||
interrupts = <157>;
|
||||
interrupt-parent = <&GIC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb@ffb40000 {
|
||||
compatible = "synopsys,designware-hs-otg2";
|
||||
reg = <0xffb40000 0xffff>;
|
||||
interrupts = <160>;
|
||||
interrupt-parent = <&GIC>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: ethernet@ff700000 {
|
||||
compatible = "altr,socfpga-stmmac",
|
||||
"snps,dwmac-3.70a", "snps,dwmac";
|
||||
reg = <0xff700000 0x2000>;
|
||||
interrupts = <147>;
|
||||
interrupt-parent = <&GIC>;
|
||||
phy-mode = "rgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac1: ethernet@ff702000 {
|
||||
compatible = "altr,socfpga-stmmac",
|
||||
"snps,dwmac-3.70a", "snps,dwmac";
|
||||
reg = <0xff702000 0x2000>;
|
||||
interrupts = <152>;
|
||||
interrupt-parent = <&GIC>;
|
||||
phy-mode = "rgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc: dwmmc@ff704000 {
|
||||
compatible = "altr,socfpga-dw-mshc";
|
||||
reg = <0xff704000 0x1000>;
|
||||
interrupts = <171>;
|
||||
interrupt-parent = <&GIC>;
|
||||
fifo-depth = <0x400>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
82
sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts
Normal file
82
sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts
Normal file
@ -0,0 +1,82 @@
|
||||
/*-
|
||||
* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
|
||||
* ("CTSRD"), as part of the DARPA CRASH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "socfpga_arria10_socdk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA Arria 10";
|
||||
compatible = "altr,socfpga-arria10", "altr,socfpga";
|
||||
|
||||
/* Reserve first page for secondary CPU trampoline code */
|
||||
memreserve = < 0x00000000 0x1000 >;
|
||||
|
||||
soc {
|
||||
/* Local timer */
|
||||
timer@ffffc600 {
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
/* Global timer */
|
||||
global_timer: timer@ffffc200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xffffc200 0x20>;
|
||||
interrupts = <1 11 0x301>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdin = "serial1";
|
||||
stdout = "serial1";
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = < 50000000 >;
|
||||
};
|
||||
|
||||
&mmc {
|
||||
status = "okay";
|
||||
num-slots = <1>;
|
||||
cap-sd-highspeed;
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
bus-frequency = <200000000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
lcd@28 {
|
||||
compatible = "newhaven,nhd-0216k3z-nsw-bbw";
|
||||
reg = <0x28>;
|
||||
};
|
||||
};
|
@ -1,9 +1,9 @@
|
||||
/*-
|
||||
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
|
||||
* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
|
||||
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
|
||||
* ("CTSRD"), as part of the DARPA CRASH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -30,58 +30,29 @@
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "socfpga.dtsi"
|
||||
/* /dts-v1/; */
|
||||
#include "socfpga_cyclone5_sockit.dts"
|
||||
|
||||
/ {
|
||||
model = "Terasic SoCKit";
|
||||
model = "Terasic SoCkit";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */
|
||||
< 0x00001000 0x1000 >, /* virtio block */
|
||||
< 0x00002000 0x1000 >; /* virtio net */
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = < 0x00000000 0x40000000 >; /* 1G RAM */
|
||||
};
|
||||
|
||||
SOC: socfpga {
|
||||
serial0: serial@ffc02000 {
|
||||
status = "okay";
|
||||
soc {
|
||||
/* Local timer */
|
||||
timer@fffec600 {
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
usb1: usb@ffb40000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac1: ethernet@ff702000 {
|
||||
status = "okay";
|
||||
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <2600>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <2000>;
|
||||
};
|
||||
|
||||
mmc: dwmmc@ff704000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
bus-frequency = <25000000>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
/* Global timer */
|
||||
global_timer: timer@fffec200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xfffec200 0x20>;
|
||||
interrupts = <1 11 0xf04>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
beri_mem0: mem@d0000000 {
|
||||
@ -94,7 +65,6 @@
|
||||
compatible = "altr,pio";
|
||||
reg = <0xc0020000 0x1000>; /* recv */
|
||||
interrupts = < 76 >;
|
||||
interrupt-parent = <&GIC>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -102,7 +72,6 @@
|
||||
compatible = "altr,pio";
|
||||
reg = <0xc0021000 0x1000>; /* send */
|
||||
interrupts = < 82 >; /* not in use on arm side */
|
||||
interrupt-parent = <&GIC>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -110,7 +79,6 @@
|
||||
compatible = "altr,pio";
|
||||
reg = <0xc0022000 0x1000>; /* recv */
|
||||
interrupts = < 77 >;
|
||||
interrupt-parent = <&GIC>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -118,7 +86,6 @@
|
||||
compatible = "altr,pio";
|
||||
reg = <0xc0023000 0x1000>; /* send */
|
||||
interrupts = < 83 >; /* not in use on arm side */
|
||||
interrupt-parent = <&GIC>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -144,7 +111,6 @@
|
||||
compatible = "sri-cambridge,beri-ring";
|
||||
reg = <0xc0000000 0x3000>;
|
||||
interrupts = < 72 73 >;
|
||||
interrupt-parent = <&GIC>;
|
||||
device_name = "beri_debug";
|
||||
data_size = <0x1000>;
|
||||
data_read = <0x0>;
|
||||
@ -158,7 +124,6 @@
|
||||
compatible = "sri-cambridge,beri-ring";
|
||||
reg = <0xc0004000 0x3000>;
|
||||
interrupts = < 74 75 >;
|
||||
interrupt-parent = <&GIC>;
|
||||
device_name = "beri_console";
|
||||
data_size = <0x1000>;
|
||||
data_read = <0x0>;
|
||||
@ -170,8 +135,19 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "-v";
|
||||
stdin = "serial0";
|
||||
stdout = "serial0";
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
bus-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
};
|
@ -1,9 +1,9 @@
|
||||
/*-
|
||||
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
|
||||
* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
|
||||
* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
|
||||
* ("CTSRD"), as part of the DARPA CRASH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -30,61 +30,45 @@
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "socfpga.dtsi"
|
||||
/* /dts-v1/; */
|
||||
#include "socfpga_cyclone5_sockit.dts"
|
||||
|
||||
/ {
|
||||
model = "Terasic SoCKit";
|
||||
model = "Terasic SoCkit";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
/* Reserve first page for secondary CPU trampoline code */
|
||||
memreserve = < 0x00000000 0x1000 >;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = < 0x00000000 0x40000000 >; /* 1G RAM */
|
||||
};
|
||||
|
||||
SOC: socfpga {
|
||||
serial0: serial@ffc02000 {
|
||||
status = "okay";
|
||||
soc {
|
||||
/* Local timer */
|
||||
timer@fffec600 {
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
usb1: usb@ffb40000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac1: ethernet@ff702000 {
|
||||
status = "okay";
|
||||
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <2600>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <2000>;
|
||||
};
|
||||
|
||||
mmc: dwmmc@ff704000 {
|
||||
status = "okay";
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
bus-frequency = <25000000>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
/* Global timer */
|
||||
global_timer: timer@fffec200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xfffec200 0x20>;
|
||||
interrupts = <1 11 0xf04>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "-v";
|
||||
stdin = "serial0";
|
||||
stdout = "serial0";
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
bus-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
};
|
Loading…
Reference in New Issue
Block a user