d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mpc85xx/pci: Conditionally reset PCI bridges

Browse Source 
Sometimes we need to reset a PCIe bus, but sometimes it breaks the
downstream device(s).  Since, from my testing, this is only needed for
Radeon cards installed in the AmigaOne machines because the card was
already initialized by firmware, make the reset dependent on a device
hint (hint.pcib.X.reset=1).  With this, AmigaOne X5000 machines can have
other devices in the secondary PCIe slots.
This commit is contained in:
Justin Hibbits 2022-07-29 21:43:42 -04:00
parent 150486f6a9
commit 43eebd0364
1 changed files with 16 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
sys/powerpc/mpc85xx/pci_mpc85xx.c
View File

@ -313,7 +313,7 @@ fsl_pcib_attach(device_t dev)
struct fsl_pcib_softc *sc;
phandle_t node;
uint32_t cfgreg, brctl, ipreg;
int error, rid;
int do_reset, error, rid;
uint8_t ltssm, capptr;
sc = device_get_softc(dev);
@ -374,17 +374,21 @@ fsl_pcib_attach(device_t dev)
PCIM_CMD_PORTEN;
fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
/* Reset the bus. Needed for Radeon video cards. */
brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
PCIR_BRIDGECTL_1, 1);
brctl |= PCIB_BCR_SECBUS_RESET;
fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
PCIR_BRIDGECTL_1, brctl, 1);
DELAY(100000);
brctl &= ~PCIB_BCR_SECBUS_RESET;
fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
PCIR_BRIDGECTL_1, brctl, 1);
DELAY(100000);
do_reset = 0;
resource_int_value("pcib", device_get_unit(dev), "reset", &do_reset);
if (do_reset) {
/* Reset the bus. Needed for Radeon video cards. */
brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
PCIR_BRIDGECTL_1, 1);
brctl |= PCIB_BCR_SECBUS_RESET;
fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
PCIR_BRIDGECTL_1, brctl, 1);
DELAY(100000);
brctl &= ~PCIB_BCR_SECBUS_RESET;
fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
PCIR_BRIDGECTL_1, brctl, 1);
DELAY(100000);
}
if (sc->sc_pcie) {
ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);