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mips: remove saf1761

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The saf1761 OTG support was only for mips targets (BERI?). Retire it.

Sponsored by:		Netflix
Reviewed by:		brooks
Differential Revision:	https://reviews.freebsd.org/D33706
This commit is contained in:
Warner Losh 2022-01-04 15:24:23 -07:00
parent 822fa6758b
commit 44796b7e82
8 changed files with 1 additions and 4573 deletions
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8
stand/usb/usbcore.mk
View File

@ -126,14 +126,6 @@ CFLAGS += -DUSB_PCI_PROBE_LIST="\"uss820dci\""
KSRCS+= uss820dci.c
.endif
.if defined(HAVE_SAF1761OTG)
CFLAGS += -DUSB_PCI_PROBE_LIST="\"saf1761otg\""
CFLAGS += -DUSB_PCI_MEMORY_ADDRESS=0x900000007f100000ULL
CFLAGS += -DUSB_PCI_MEMORY_SIZE=0x40000U
KSRCS+= saf1761_otg.c
KSRCS+= saf1761_otg_boot.c
.endif
#
# USB core and templates
#

3657
sys/dev/usb/controller/saf1761_otg.c
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File diff suppressed because it is too large Load Diff

175
sys/dev/usb/controller/saf1761_otg.h
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@ -1,175 +0,0 @@
/* $FreeBSD$ */
/*-
* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _SAF1761_OTG_H_
#define _SAF1761_OTG_H_
#define SOTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32)
#define SOTG_FS_MAX_PACKET_SIZE 64
#define SOTG_HS_MAX_PACKET_SIZE 512
#define SOTG_NUM_PORTS 2 /* one Device and one Host port */
#define SOTG_HOST_PORT_NUM 1
#define SOTG_DEVICE_PORT_NUM 2
#define SOTG_HOST_CHANNEL_MAX (3 * 32)
/* Macros used for reading and writing little endian registers */
#define SAF1761_READ_LE_4(sc, reg) ({ uint32_t _temp; \
_temp = bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg)); \
le32toh(_temp); })
#define SAF1761_WRITE_LE_4(sc, reg, data) do { \
uint32_t _temp = (data); \
bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg), htole32(_temp)); \
} while (0)
/* 90ns delay macro */
#define SAF1761_90NS_DELAY(sc) do { \
(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
(void) SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID); \
} while (0)
struct saf1761_otg_softc;
struct saf1761_otg_td;
typedef uint8_t (saf1761_otg_cmd_t)(struct saf1761_otg_softc *, struct saf1761_otg_td *td);
struct saf1761_otg_td {
struct saf1761_otg_td *obj_next;
saf1761_otg_cmd_t *func;
struct usb_page_cache *pc;
uint32_t offset;
uint32_t remainder;
uint32_t dw1_value;
uint16_t max_packet_size;
uint8_t ep_index;
uint8_t ep_type;
uint8_t channel;
uint8_t uframe;
uint8_t interval;
uint8_t error_any:1;
uint8_t error_stall:1;
uint8_t alt_next:1;
uint8_t short_pkt:1;
uint8_t did_stall:1;
uint8_t toggle:1;
uint8_t set_toggle:1;
};
struct saf1761_otg_std_temp {
saf1761_otg_cmd_t *func;
struct usb_page_cache *pc;
struct saf1761_otg_td *td;
struct saf1761_otg_td *td_next;
uint32_t len;
uint32_t offset;
uint16_t max_frame_size;
uint8_t short_pkt;
/*
* short_pkt = 0: transfer should be short terminated
* short_pkt = 1: transfer should not be short terminated
*/
uint8_t setup_alt_next;
uint8_t did_stall;
};
struct saf1761_otg_config_desc {
struct usb_config_descriptor confd;
struct usb_interface_descriptor ifcd;
struct usb_endpoint_descriptor endpd;
} __packed;
union saf1761_otg_hub_temp {
uWord wValue;
struct usb_port_status ps;
};
struct saf1761_otg_flags {
uint8_t change_connect:1;
uint8_t change_suspend:1;
uint8_t status_suspend:1; /* set if suspended */
uint8_t status_vbus:1; /* set if present */
uint8_t status_bus_reset:1; /* set if reset complete */
uint8_t clocks_off:1;
uint8_t port_powered:1;
uint8_t port_enabled:1;
uint8_t d_pulled_up:1;
};
struct saf1761_otg_softc {
struct usb_bus sc_bus;
union saf1761_otg_hub_temp sc_hub_temp;
struct usb_device *sc_devices[SOTG_MAX_DEVICES];
struct resource *sc_io_res;
struct resource *sc_irq_res;
void *sc_intr_hdl;
bus_size_t sc_io_size;
bus_space_tag_t sc_io_tag;
bus_space_handle_t sc_io_hdl;
uint32_t sc_host_async_busy_map[2];
uint32_t sc_host_async_map;
uint32_t sc_host_async_suspend_map;
uint32_t sc_host_intr_busy_map[2];
uint32_t sc_host_intr_map;
uint32_t sc_host_intr_suspend_map;
uint32_t sc_host_isoc_busy_map[2];
uint32_t sc_host_isoc_map;
uint32_t sc_host_isoc_suspend_map;
uint32_t sc_intr_enable; /* enabled interrupts */
uint32_t sc_hw_mode; /* hardware mode */
uint32_t sc_interrupt_cfg; /* interrupt configuration */
uint32_t sc_xfer_complete;
uint32_t sc_bounce_buffer[1024 / 4];
uint8_t sc_rt_addr; /* root HUB address */
uint8_t sc_dv_addr; /* device address */
uint8_t sc_conf; /* root HUB config */
uint8_t sc_isreset; /* host mode */
uint8_t sc_hub_idata[1];
struct saf1761_otg_flags sc_flags;
};
/* prototypes */
usb_error_t saf1761_otg_init(struct saf1761_otg_softc *sc);
void saf1761_otg_uninit(struct saf1761_otg_softc *sc);
driver_filter_t saf1761_otg_filter_interrupt;
driver_intr_t saf1761_otg_interrupt;
#endif /* _SAF1761_OTG_H_ */

140
sys/dev/usb/controller/saf1761_otg_boot.c
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@ -1,140 +0,0 @@
/* $FreeBSD$ */
/*-
* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include USB_GLOBAL_INCLUDE_FILE
#include <dev/usb/controller/saf1761_otg.h>
#include <dev/usb/controller/saf1761_otg_reg.h>
static device_probe_t saf1761_otg_fdt_probe;
static device_attach_t saf1761_otg_fdt_attach;
static device_detach_t saf1761_otg_fdt_detach;
static device_method_t saf1761_otg_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, saf1761_otg_fdt_probe),
DEVMETHOD(device_attach, saf1761_otg_fdt_attach),
DEVMETHOD(device_detach, saf1761_otg_fdt_detach),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD_END
};
static driver_t saf1761_otg_driver = {
.name = "saf1761otg",
.methods = saf1761_otg_methods,
.size = sizeof(struct saf1761_otg_softc),
};
static devclass_t saf1761_otg_devclass;
DRIVER_MODULE(saf1761otg, pci, saf1761_otg_driver, saf1761_otg_devclass, 0, 0);
MODULE_DEPEND(saf1761otg, usb, 1, 1, 1);
static int
saf1761_otg_fdt_probe(device_t dev)
{
if (device_get_unit(dev) != 0)
return (ENXIO);
device_set_desc(dev, "ISP1761/SAF1761 DCI USB 2.0 Device Controller");
return (0);
}
static int
saf1761_otg_fdt_attach(device_t dev)
{
struct saf1761_otg_softc *sc = device_get_softc(dev);
int err;
/* 32-bit data bus */
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH;
/* initialise some bus fields */
sc->sc_bus.parent = dev;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = SOTG_MAX_DEVICES;
sc->sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), NULL))
return (ENOMEM);
sc->sc_io_res = (void *)1;
sc->sc_io_tag = (void *)1;
sc->sc_io_hdl = (void *)USB_PCI_MEMORY_ADDRESS;
sc->sc_io_size = USB_PCI_MEMORY_SIZE;
sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
if (sc->sc_bus.bdev == NULL)
goto error;
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
device_set_interrupt(dev, &saf1761_otg_filter_interrupt, &saf1761_otg_interrupt, sc);
err = saf1761_otg_init(sc);
if (err) {
device_printf(dev, "Init failed\n");
goto error;
}
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err) {
device_printf(dev, "USB probe and attach failed\n");
goto error;
}
return (0);
error:
saf1761_otg_fdt_detach(dev);
return (ENXIO);
}
static int
saf1761_otg_fdt_detach(device_t dev)
{
struct saf1761_otg_softc *sc = device_get_softc(dev);
/* during module unload there are lots of children leftover */
device_delete_children(dev);
if (sc->sc_irq_res) {
/*
* Only call uninit() after init()
*/
saf1761_otg_uninit(sc);
}
usb_bus_mem_free_all(&sc->sc_bus, NULL);
return (0);
}

269
sys/dev/usb/controller/saf1761_otg_fdt.c
View File

@ -1,269 +0,0 @@
/* $FreeBSD$ */
/*-
* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef USB_GLOBAL_INCLUDE_FILE
#include USB_GLOBAL_INCLUDE_FILE
#else
#include <sys/stdint.h>
#include <sys/stddef.h>
#include <sys/param.h>
#include <sys/queue.h>
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/sysctl.h>
#include <sys/sx.h>
#include <sys/unistd.h>
#include <sys/callout.h>
#include <sys/malloc.h>
#include <sys/priv.h>
#include <sys/rman.h>
#include <dev/fdt/fdt_common.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/usb/usb.h>
#include <dev/usb/usbdi.h>
#include <dev/usb/usb_core.h>
#include <dev/usb/usb_busdma.h>
#include <dev/usb/usb_process.h>
#include <dev/usb/usb_transfer.h>
#include <dev/usb/usb_device.h>
#include <dev/usb/usb_hub.h>
#include <dev/usb/usb_util.h>
#include <dev/usb/usb_controller.h>
#include <dev/usb/usb_bus.h>
#endif /* USB_GLOBAL_INCLUDE_FILE */
#include <dev/usb/controller/saf1761_otg.h>
#include <dev/usb/controller/saf1761_otg_reg.h>
static device_probe_t saf1761_otg_fdt_probe;
static device_attach_t saf1761_otg_fdt_attach;
static device_detach_t saf1761_otg_fdt_detach;
static device_method_t saf1761_otg_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, saf1761_otg_fdt_probe),
DEVMETHOD(device_attach, saf1761_otg_fdt_attach),
DEVMETHOD(device_detach, saf1761_otg_fdt_detach),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD_END
};
static driver_t saf1761_otg_driver = {
.name = "saf1761otg",
.methods = saf1761_otg_methods,
.size = sizeof(struct saf1761_otg_softc),
};
static devclass_t saf1761_otg_devclass;
DRIVER_MODULE(saf1761otg, simplebus, saf1761_otg_driver, saf1761_otg_devclass, 0, 0);
MODULE_DEPEND(saf1761otg, usb, 1, 1, 1);
static int
saf1761_otg_fdt_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "nxp,usb-isp1761"))
return (ENXIO);
device_set_desc(dev, "ISP1761/SAF1761 DCI USB 2.0 Device Controller");
return (0);
}
static int
saf1761_otg_fdt_attach(device_t dev)
{
struct saf1761_otg_softc *sc = device_get_softc(dev);
char param[24];
int err;
int rid;
/* get configuration from FDT */
/* get bus-width, if any */
if (OF_getprop(ofw_bus_get_node(dev), "bus-width",
&param, sizeof(param)) > 0) {
param[sizeof(param) - 1] = 0;
if (strcmp(param, "32") == 0)
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH;
} else {
/* assume 32-bit data bus */
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH;
}
/* get analog over-current setting */
if (OF_getprop(ofw_bus_get_node(dev), "analog-oc",
&param, sizeof(param)) > 0) {
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_ANA_DIGI_OC;
}
/* get DACK polarity */
if (OF_getprop(ofw_bus_get_node(dev), "dack-polarity",
&param, sizeof(param)) > 0) {
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DACK_POL;
}
/* get DREQ polarity */
if (OF_getprop(ofw_bus_get_node(dev), "dreq-polarity",
&param, sizeof(param)) > 0) {
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DREQ_POL;
}
/* get IRQ polarity */
if (OF_getprop(ofw_bus_get_node(dev), "int-polarity",
&param, sizeof(param)) > 0) {
sc->sc_interrupt_cfg |= SOTG_INTERRUPT_CFG_INTPOL;
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_INTR_POL;
}
/* get IRQ level triggering */
if (OF_getprop(ofw_bus_get_node(dev), "int-level",
&param, sizeof(param)) > 0) {
sc->sc_interrupt_cfg |= SOTG_INTERRUPT_CFG_INTLVL;
sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_INTR_LEVEL;
}
/* initialise some bus fields */
sc->sc_bus.parent = dev;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = SOTG_MAX_DEVICES;
sc->sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus,
USB_GET_DMA_TAG(dev), NULL)) {
return (ENOMEM);
}
rid = 0;
sc->sc_io_res =
bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (sc->sc_io_res == NULL)
goto error;
sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
/* try to allocate the HC interrupt first */
rid = 1;
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
/* try to allocate a common IRQ second */
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL)
goto error;
}
sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
if (sc->sc_bus.bdev == NULL)
goto error;
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_TTY | INTR_MPSAFE,
&saf1761_otg_filter_interrupt, &saf1761_otg_interrupt, sc, &sc->sc_intr_hdl);
if (err) {
sc->sc_intr_hdl = NULL;
goto error;
}
err = saf1761_otg_init(sc);
if (err) {
device_printf(dev, "Init failed\n");
goto error;
}
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err) {
device_printf(dev, "USB probe and attach failed\n");
goto error;
}
return (0);
error:
saf1761_otg_fdt_detach(dev);
return (ENXIO);
}
static int
saf1761_otg_fdt_detach(device_t dev)
{
struct saf1761_otg_softc *sc = device_get_softc(dev);
int err;
/* during module unload there are lots of children leftover */
device_delete_children(dev);
if (sc->sc_irq_res && sc->sc_intr_hdl) {
/*
* Only call uninit() after init()
*/
saf1761_otg_uninit(sc);
err = bus_teardown_intr(dev, sc->sc_irq_res,
sc->sc_intr_hdl);
sc->sc_intr_hdl = NULL;
}
if (sc->sc_irq_res) {
bus_release_resource(dev, SYS_RES_IRQ, 0,
sc->sc_irq_res);
sc->sc_irq_res = NULL;
}
if (sc->sc_io_res) {
bus_release_resource(dev, SYS_RES_MEMORY, 0,
sc->sc_io_res);
sc->sc_io_res = NULL;
}
usb_bus_mem_free_all(&sc->sc_bus, NULL);
return (0);
}

274
sys/dev/usb/controller/saf1761_otg_reg.h
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@ -1,274 +0,0 @@
/* $FreeBSD$ */
/*-
* Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _SAF1761_OTG_REG_H_
#define _SAF1761_OTG_REG_H_
/* Global registers */
#define SOTG_VEND_PROD_ID 0x370
#define SOTG_VEND_ID(x) ((x) & 0xFFFF)
#define SOTG_PROD_ID(x) (((x) >> 16) & 0xFFFF)
#define SOTG_CTRL_SET_CLR 0x374
#define SOTG_CTRL_SET(x) ((x) & 0xFFFF)
#define SOTG_CTRL_CLR(x) (((x) << 16) & 0xFFFF0000)
#define SOTG_CTRL_OTG_DISABLE (1 << 10)
#define SOTG_CTRL_OTG_SE0_EN (1 << 9)
#define SOTG_CTRL_BDIS_ACON_EN (1 << 8)
#define SOTG_CTRL_SW_SEL_HC_DC (1 << 7)
#define SOTG_CTRL_VBUS_CHRG (1 << 6)
#define SOTG_CTRL_VBUS_DISCHRG (1 << 5)
#define SOTG_CTRL_VBUS_DRV (1 << 4)
#define SOTG_CTRL_SEL_CP_EXT (1 << 3)
#define SOTG_CTRL_DM_PULL_DOWN (1 << 2)
#define SOTG_CTRL_DP_PULL_DOWN (1 << 1)
#define SOTG_CTRL_DP_PULL_UP (1 << 0)
#define SOTG_STATUS 0x378
#define SOTG_STATUS_B_SE0_SRP (1 << 8)
#define SOTG_STATUS_B_SESS_END (1 << 7)
#define SOTG_STATUS_RMT_CONN (1 << 4)
#define SOTG_STATUS_ID (1 << 3)
#define SOTG_STATUS_DP_SRP (1 << 2)
#define SOTG_STATUS_A_B_SESS_VLD (1 << 1)
#define SOTG_STATUS_VBUS_VLD (1 << 0)
#define SOTG_IRQ_LATCH_SET_CLR 0x37C
#define SOTG_IRQ_LATCH_SET(x) ((x) & 0xFFFF)
#define SOTG_IRQ_LATCH_CLR(x) (((x) << 16) & 0xFFFF0000)
#define SOTG_IRQ_ENABLE_SET_CLR 0x380
#define SOTG_IRQ_ENABLE_SET(x) ((x) & 0xFFFF)
#define SOTG_IRQ_ENABLE_CLR(x) (((x) << 16) & 0xFFFF0000)
#define SOTG_IRQ_RISE_SET_CLR 0x384
#define SOTG_IRQ_RISE_SET(x) ((x) & 0xFFFF)
#define SOTG_IRQ_RISE_CLR(x) (((x) << 16) & 0xFFFF0000)
#define SOTG_IRQ_OTG_TMR_TIMEOUT (1 << 9)
#define SOTG_IRQ_B_SE0_SRP (1 << 8)
#define SOTG_IRQ_B_SESS_END (1 << 7)
#define SOTG_IRQ_BDIS_ACON (1 << 6)
#define SOTG_IRQ_OTG_RESUME (1 << 5)
#define SOTG_IRQ_RMT_CONN (1 << 4)
#define SOTG_IRQ_ID (1 << 3)
#define SOTG_IRQ_DP_SRP (1 << 2)
#define SOTG_IRQ_A_B_SESS_VLD (1 << 1)
#define SOTG_IRQ_VBUS_VLD (1 << 0)
#define SOTG_TIMER_LOW_SET_CLR 0x388
#define SOTG_TIMER_LOW_SET(x) ((x) & 0xFFFF)
#define SOTG_TIMER_LOW_CLR(x) (((x) << 16) & 0xFFFF0000)
#define SOTG_TIMER_HIGH_SET_CLR 0x38C
#define SOTG_TIMER_HIGH_SET(x) ((x) & 0xFFFF)
#define SOTG_TIMER_HIGH_CLR(x) (((x) << 16) & 0xFFFF0000)
#define SOTG_TIMER_HIGH_START (1U << 15)
#define SOTG_MEMORY_REG 0x33c
/* Peripheral controller specific registers */
#define SOTG_ADDRESS 0x200
#define SOTG_ADDRESS_ENABLE (1 << 7)
#define SOTG_MODE 0x20C
#define SOTG_MODE_DMACLK_ON (1 << 9)
#define SOTG_MODE_VBUSSTAT (1 << 8)
#define SOTG_MODE_CLKAON (1 << 7)
#define SOTG_MODE_SNDRSU (1 << 6)
#define SOTG_MODE_GOSUSP (1 << 5)
#define SOTG_MODE_SFRESET (1 << 4)
#define SOTG_MODE_GLINTENA (1 << 3)
#define SOTG_MODE_WKUPCS (1 << 2)
#define SOTG_INTERRUPT_CFG 0x210
#define SOTG_INTERRUPT_CFG_DEBUG_SET (1 << 16)
#define SOTG_INTERRUPT_CFG_CDBGMOD (1 << 6) /* ACK only */
#define SOTG_INTERRUPT_CFG_DDBGMODIN (1 << 4) /* ACK only */
#define SOTG_INTERRUPT_CFG_DDBGMODOUT (1 << 2) /* ACK and NYET only */
#define SOTG_INTERRUPT_CFG_INTLVL (1 << 1)
#define SOTG_INTERRUPT_CFG_INTPOL (1 << 0)
#define SOTG_DCINTERRUPT_EN 0x214
#define SOTG_HW_MODE_CTRL 0x300
#define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1 << 31)
#define SOTG_HW_MODE_CTRL_ANA_DIGI_OC (1 << 15)
#define SOTG_HW_MODE_CTRL_DEV_DMA (1 << 11)
#define SOTG_HW_MODE_CTRL_COMN_INT (1 << 10)
#define SOTG_HW_MODE_CTRL_COMN_DMA (1 << 9)
#define SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH (1 << 8)
#define SOTG_HW_MODE_CTRL_DACK_POL (1 << 6)
#define SOTG_HW_MODE_CTRL_DREQ_POL (1 << 5)
#define SOTG_HW_MODE_CTRL_INTR_POL (1 << 2)
#define SOTG_HW_MODE_CTRL_INTR_LEVEL (1 << 1)
#define SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN (1 << 0)
#define SOTG_OTG_CTRL 0x374
#define SOTG_EP_INDEX 0x22c
#define SOTG_EP_INDEX_EP0SETUP (1 << 5)
#define SOTG_EP_INDEX_ENDP_INDEX_MASK (15 << 1)
#define SOTG_EP_INDEX_ENDP_INDEX_SHIFT 1
#define SOTG_EP_INDEX_DIR_IN (1 << 0)
#define SOTG_EP_INDEX_DIR_OUT 0
#define SOTG_CTRL_FUNC 0x228
#define SOTG_CTRL_FUNC_CLBUF (1 << 4)
#define SOTG_CTRL_FUNC_VENDP (1 << 3)
#define SOTG_CTRL_FUNC_DSEN (1 << 2)
#define SOTG_CTRL_FUNC_STATUS (1 << 1)
#define SOTG_CTRL_FUNC_STALL (1 << 0)
#define SOTG_DATA_PORT 0x220
#define SOTG_BUF_LENGTH 0x21C
#define SOTG_BUF_LENGTH_BUFLEN_MASK 0xFFFF
#define SOTG_BUF_LENGTH_FILLED_MASK (3 << 16)
#define SOTG_EP_MAXPACKET 0x204
#define SOTG_EP_TYPE 0x208
#define SOTG_EP_TYPE_NOEMPPKT (1 << 4)
#define SOTG_EP_TYPE_ENABLE (1 << 3)
#define SOTG_EP_TYPE_DBLBUF (1 << 2)
#define SOTG_EP_TYPE_EP_TYPE (3 << 0)
#define SOTG_DMA_CMD 0x230
#define SOTG_DMA_XFER_COUNT 0x234
#define SOTG_DCDMA_CFG 0x238
#define SOTG_DMA_HW 0x23C
#define SOTG_DMA_IRQ_REASON 0x250
#define SOTG_DMA_IRQ_ENABLE 0x254
#define SOTG_DMA_EP 0x258
#define SOTG_BURST_COUNTER 0x264
#define SOTG_DCINTERRUPT 0x218
#define SOTG_DCINTERRUPT_IEPRX(n) (1 << (10 + (2*(n))))
#define SOTG_DCINTERRUPT_IEPTX(n) (1 << (11 + (2*(n))))
#define SOTG_DCINTERRUPT_IEP0SETUP (1 << 8)
#define SOTG_DCINTERRUPT_IEVBUS (1 << 7)
#define SOTG_DCINTERRUPT_IEDMA (1 << 6)
#define SOTG_DCINTERRUPT_IEHS_STA (1 << 5)
#define SOTG_DCINTERRUPT_IERESM (1 << 4)
#define SOTG_DCINTERRUPT_IESUSP (1 << 3)
#define SOTG_DCINTERRUPT_IEPSOF (1 << 2)
#define SOTG_DCINTERRUPT_IESOF (1 << 1)
#define SOTG_DCINTERRUPT_IEBRST (1 << 0)
#define SOTG_DCCHIP_ID 0x270
#define SOTG_FRAME_NUM 0x274
#define SOTG_FRAME_NUM_MICROSOFR_MASK 0x3800
#define SOTG_FRAME_NUM_MICROSOFR_SHIFT 11
#define SOTG_FRAME_NUM_SOFR_MASK 0x7FF
#define SOTG_DCSCRATCH 0x278
#define SOTG_UNLOCK_DEVICE 0x27C
#define SOTG_UNLOCK_DEVICE_CODE 0xAA37
#define SOTG_IRQ_PULSE_WIDTH 0x280
#define SOTG_TEST_MODE 0x284
#define SOTG_TEST_MODE_FORCEHS (1 << 7)
#define SOTG_TEST_MODE_FORCEFS (1 << 4)
#define SOTG_TEST_MODE_PRBS (1 << 3)
#define SOTG_TEST_MODE_KSTATE (1 << 2)
#define SOTG_TEST_MODE_JSTATE (1 << 1)
#define SOTG_TEST_MODE_SE0_NAK (1 << 0)
/* Host controller specific registers */
#define SOTG_FRINDEX 0x002c
#define SOTG_FRINDEX_MASK 0x3fff
#define SOTG_CONFIGFLAG 0x0060
#define SOTG_CONFIGFLAG_ENABLE (1 << 0)
#define SOTG_PORTSC1 0x0064
#define SOTG_PORTSC1_PIC (3 << 14)
#define SOTG_PORTSC1_PO (1 << 13)
#define SOTG_PORTSC1_PP (1 << 12)
#define SOTG_PORTSC1_LS (3 << 10)
#define SOTG_PORTSC1_PR (1 << 8)
#define SOTG_PORTSC1_SUSP (1 << 7)
#define SOTG_PORTSC1_FPR (1 << 6)
#define SOTG_PORTSC1_PED (1 << 2)
#define SOTG_PORTSC1_ECSC (1 << 1)
#define SOTG_PORTSC1_ECCS (1 << 0)
#define SOTG_PTD_DW0 0
#define SOTG_PTD_DW0_VALID 1U
#define SOTG_PTD_DW1 4
#define SOTG_PTD_DW1_ENABLE_SPLIT (1 << 14)
#define SOTG_PTD_DW2 8
#define SOTG_PTD_DW2_RL (0xf << 25)
#define SOTG_PTD_DW3 12
#define SOTG_PTD_DW3_NRL (0xf << 19)
#define SOTG_PTD_DW3_ACTIVE (1U << 31)
#define SOTG_PTD_DW3_HALTED (1U << 30)
#define SOTG_PTD_DW3_ERRORS (3U << 28)
#define SOTG_PTD_DW3_CERR_3 (3U << 23)
#define SOTG_PTD_DW3_CERR_2 (2U << 23) /* infinite NAKs */
#define SOTG_PTD_DW3_CERR_1 (1U << 23)
#define SOTG_PTD_DW3_XFER_COUNT_HS 0x7FFF
#define SOTG_PTD_DW3_XFER_COUNT_SPLIT 0x03FF
#define SOTG_PTD_DW4 16
#define SOTG_PTD_DW5 20
#define SOTG_PTD_DW6 24
#define SOTG_PTD_DW7 28
#define SOTG_DATA_ADDR(x) (0x1000 + (512 * (x)))
#define SOTG_ASYNC_PTD(x) (0xC00 + ((x) * 32))
#define SOTG_INTR_PTD(x) (0x800 + ((x) * 32))
#define SOTG_ISOC_PTD(x) (0x400 + ((x) * 32))
#define SOTG_PTD(x) (0x400 + ((x) * 32))
#define SOTG_HC_MEMORY_ADDR(x) (((x) - 0x400) >> 3)
#define SOTG_SW_RESET 0x30C
#define SOTG_SW_RESET_HC (1 << 1)
#define SOTG_SW_RESET_ALL (1 << 0)
#define SOTG_POWER_DOWN 0x354
#define SOTG_POWER_DOWN_PORT3_PD (1 << 12)
#define SOTG_POWER_DOWN_PORT2_PD (1 << 11)
#define SOTG_POWER_DOWN_VBATDET_PWR (1 << 10)
#define SOTG_POWER_DOWN_BIAS_EN (1 << 5)
#define SOTG_POWER_DOWN_VREG_ON (1 << 4)
#define SOTG_POWER_DOWN_OC3_PWR (1 << 3)
#define SOTG_POWER_DOWN_OC2_PWR (1 << 2)
#define SOTG_POWER_DOWN_OC1_PWR (1 << 1)
#define SOTG_POWER_DOWN_HC_CLK_EN (1 << 0)
#define SOTG_USBCMD 0x20
#define SOTG_USBCMD_LHCR (1 << 7)
#define SOTG_USBCMD_HCRESET (1 << 1)
#define SOTG_USBCMD_RS (1 << 0)
#define SOTG_HCSCRATCH 0x308
#define SOTG_HCINTERRUPT 0x310
#define SOTG_HCINTERRUPT_OTG_IRQ (1 << 10)
#define SOTG_HCINTERRUPT_ISO_IRQ (1 << 9)
#define SOTG_HCINTERRUPT_ALT_IRQ (1 << 8)
#define SOTG_HCINTERRUPT_INT_IRQ (1 << 7)
#define SOTG_HCINTERRUPT_CLKREADY (1 << 6)
#define SOTG_HCINTERRUPT_HCSUSP (1 << 5)
#define SOTG_HCINTERRUPT_DMAEOTINT (1 << 3)
#define SOTG_HCINTERRUPT_SOFITLINT (1 << 1)
#define SOTG_HCINTERRUPT_ENABLE 0x314
#define SOTG_ATL_PTD_DONE_PTD 0x150
#define SOTG_ATL_PTD_SKIP_PTD 0x154
#define SOTG_ATL_PTD_LAST_PTD 0x158
#define SOTG_INT_PTD_DONE_PTD 0x140
#define SOTG_INT_PTD_SKIP_PTD 0x144
#define SOTG_INT_PTD_LAST_PTD 0x148
#define SOTG_ISO_PTD_DONE_PTD 0x130
#define SOTG_ISO_PTD_SKIP_PTD 0x134
#define SOTG_ISO_PTD_LAST_PTD 0x138
#define SOTG_HCBUFFERSTATUS 0x334
#define SOTG_HCBUFFERSTATUS_ISO_BUF_FILL (1 << 2)
#define SOTG_HCBUFFERSTATUS_INT_BUF_FILL (1 << 1)
#define SOTG_HCBUFFERSTATUS_ATL_BUF_FILL (1 << 0)
#define SOTG_ISO_IRQ_MASK_OR 0x318
#define SOTG_INT_IRQ_MASK_OR 0x31C
#define SOTG_ATL_IRQ_MASK_OR 0x320
#define SOTG_ISO_IRQ_MASK_AND 0x324
#define SOTG_INT_IRQ_MASK_AND 0x328
#define SOTG_ATL_IRQ_MASK_AND 0x32C
#endif /* _SAF1761_OTG_REG_H_ */

9
sys/modules/usb/Makefile
View File

@ -45,7 +45,7 @@ MAKE+=" DEBUG_FLAGS+=-DUSB_REQ_DEBUG"
SUBDIR = usb
SUBDIR += ${_dwc_otg} ehci ${_musb} ohci uhci xhci ${_uss820dci} \
${_atmegadci} ${_avr32dci} ${_rsu} ${_rsufw} ${_saf1761otg}
${_atmegadci} ${_avr32dci} ${_rsu} ${_rsufw}
SUBDIR += ${_rum} ${_run} ${_runfw} ${_uath} upgt usie ural ${_zyd} ${_urtw}
SUBDIR += atp cfumass uhid uhid_snes ukbd ums udbp uep wmt wsp ugold uled \
usbhid
@ -76,12 +76,9 @@ _zyd= zyd
_kue= kue
_run= run
_rsu= rsu
.if ${MACHINE_CPUARCH} != "mips"
_rsufw= rsufw
_runfw= runfw
.endif
.endif
.if ${MACHINE_CPUARCH} == "amd64"
_urtw= urtw
@ -102,10 +99,6 @@ _urtw= urtw
_avr32dci= avr32dci
.endif
.if ${MACHINE_CPUARCH} == "mips"
_saf1761otg= saf1761otg
.endif
.if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \
${MACHINE_CPUARCH} == "i386"
_uacpi= uacpi

42
sys/modules/usb/saf1761otg/Makefile
View File

@ -1,42 +0,0 @@
#
# $FreeBSD$
#
# Copyright (c) 2014 Hans Petter Selasky. All rights reserved.
#
# This software was developed by SRI International and the University of
# Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
# ("CTSRD"), as part of the DARPA CRASH research programme.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
S= ${SRCTOP}/sys
.PATH: $S/dev/usb/controller
KMOD= saf1761otg
SRCS= bus_if.h device_if.h usb_if.h \
opt_bus.h opt_usb.h ofw_bus_if.h \
saf1761_otg.c saf1761_otg_fdt.c \
pci_if.h
.include <bsd.kmod.mk>