From 450d86fc7f1c2d0fe394727618bb77f94c6ea6dc Mon Sep 17 00:00:00 2001 From: Jung-uk Kim Date: Mon, 22 Jun 2020 20:42:58 +0000 Subject: [PATCH] Assume all TSCs are synchronized for AMD Family 17h processors and later when it has passed the synchronization test. "Processor Programming Reference (PPR) for AMD Family 17h" states that the TSC uses a common reference for all sockets, cores and threads. MFC after: 1 month --- sys/x86/x86/tsc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.c index 98ffdc9b4e6b..c8e9be0c3cd5 100644 --- a/sys/x86/x86/tsc.c +++ b/sys/x86/x86/tsc.c @@ -525,6 +525,13 @@ test_tsc(int adj_max_count) switch (cpu_vendor_id) { case CPU_VENDOR_AMD: case CPU_VENDOR_HYGON: + /* + * Processor Programming Reference (PPR) for AMD + * Family 17h states that the TSC uses a common + * reference for all sockets, cores and threads. + */ + if (CPUID_TO_FAMILY(cpu_id) >= 0x17) + return (1000); /* * Starting with Family 15h processors, TSC clock * source is in the north bridge. Check whether