From 45b4eca56d9f3f330b0669411e4b6a4915c6f13d Mon Sep 17 00:00:00 2001 From: Benno Rice Date: Wed, 10 Jul 2002 12:21:54 +0000 Subject: [PATCH] Add DDB support. --- sys/conf/files.powerpc | 1 + sys/powerpc/aim/machdep.c | 4 + sys/powerpc/include/db_machdep.h | 20 +- sys/powerpc/powerpc/db_disasm.c | 962 +++++++++++++++++++++++++++++ sys/powerpc/powerpc/db_hwwatch.c | 58 ++ sys/powerpc/powerpc/db_interface.c | 377 +++++++++++ sys/powerpc/powerpc/db_memrw.c | 109 ++++ sys/powerpc/powerpc/db_trace.c | 293 +++++++++ sys/powerpc/powerpc/machdep.c | 4 + 9 files changed, 1824 insertions(+), 4 deletions(-) create mode 100644 sys/powerpc/powerpc/db_disasm.c create mode 100644 sys/powerpc/powerpc/db_hwwatch.c create mode 100644 sys/powerpc/powerpc/db_interface.c create mode 100644 sys/powerpc/powerpc/db_memrw.c create mode 100644 sys/powerpc/powerpc/db_trace.c diff --git a/sys/conf/files.powerpc b/sys/conf/files.powerpc index 2923498110ae..1cb888ae717e 100644 --- a/sys/conf/files.powerpc +++ b/sys/conf/files.powerpc @@ -42,6 +42,7 @@ powerpc/powerpc/vm_machdep.c standard powerpc/powerpc/db_disasm.c optional ddb powerpc/powerpc/db_interface.c optional ddb +powerpc/powerpc/db_hwwatch.c optional ddb powerpc/powerpc/db_memrw.c optional ddb powerpc/powerpc/db_trace.c optional ddb diff --git a/sys/powerpc/aim/machdep.c b/sys/powerpc/aim/machdep.c index 7a7712423e04..17836fae6f71 100644 --- a/sys/powerpc/aim/machdep.c +++ b/sys/powerpc/aim/machdep.c @@ -372,6 +372,10 @@ powerpc_init(u_int startkernel, u_int endkernel, u_int basekernel, void *mdp) printf("powerpc_init: no loader metadata.\n"); } +#ifdef DDB + kdb_init(); +#endif + /* * XXX: Initialize the interrupt tables. */ diff --git a/sys/powerpc/include/db_machdep.h b/sys/powerpc/include/db_machdep.h index 55c0a0373402..c8c67236bce2 100644 --- a/sys/powerpc/include/db_machdep.h +++ b/sys/powerpc/include/db_machdep.h @@ -31,8 +31,10 @@ /* * Machine-dependent defines for new kernel debugger. */ -#ifndef _PPC_DB_MACHDEP_H_ -#define _PPC_DB_MACHDEP_H_ +#ifndef _POWERPC_DB_MACHDEP_H_ +#define _POWERPC_DB_MACHDEP_H_ + +#define PPC_MPC6XX #include @@ -45,6 +47,13 @@ struct powerpc_saved_state { u_int32_t r[32]; /* data registers */ u_int32_t iar; u_int32_t msr; + u_int32_t lr; + u_int32_t ctr; + u_int32_t cr; + u_int32_t xer; + u_int32_t dear; + u_int32_t esr; + u_int32_t pid; }; typedef struct powerpc_saved_state db_regs_t; extern db_regs_t ddb_regs; /* register state */ @@ -57,7 +66,7 @@ extern db_regs_t ddb_regs; /* register state */ #define BKPT_SIZE (4) /* size of breakpoint inst */ #define BKPT_SET(inst) (BKPT_INST) -#define FIXUP_PC_AFTER_BREAK(regs) ((regs)->iar -= 4) +#define FIXUP_PC_AFTER_BREAK (DDB_REGS)->iar -= 4; #define SR_SINGLESTEP 0x400 #define db_clear_single_step(regs) ((regs)->msr &= ~SR_SINGLESTEP) @@ -89,6 +98,9 @@ extern db_regs_t ddb_regs; /* register state */ #define inst_load(ins) 0 #define inst_store(ins) 0 +#define DB_SMALL_VALUE_MAX (0x7fffffff) +#define DB_SMALL_VALUE_MIN (-0x40001) + #ifdef _KERNEL void kdb_kintr(void *); @@ -96,4 +108,4 @@ int kdb_trap(int, void *); #endif /* _KERNEL */ -#endif /* _PPC_DB_MACHDEP_H_ */ +#endif /* _POWERPC_DB_MACHDEP_H_ */ diff --git a/sys/powerpc/powerpc/db_disasm.c b/sys/powerpc/powerpc/db_disasm.c new file mode 100644 index 000000000000..e598eb50f0b8 --- /dev/null +++ b/sys/powerpc/powerpc/db_disasm.c @@ -0,0 +1,962 @@ +/* $FreeBSD$ */ +/* $NetBSD: db_disasm.c,v 1.12 2002/01/05 22:07:26 jhawk Exp $ */ +/* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +enum function_mask { + Op_A = 0x00000001, + Op_B = 0x00000002, + Op_BI = 0x00000004, + Op_BO = 0x00000008, + Op_CRM = 0x00000010, + Op_D = 0x00000020, /* yes, Op_S and Op_D are the same */ + Op_S = 0x00000020, + Op_FM = 0x00000040, + Op_IMM = 0x00000080, + Op_LK = 0x00000100, + Op_Rc = 0x00000200, + Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ + Op_LKM = Op_AA, + Op_RcM = Op_AA, + Op_OE = 0x00000400, + Op_SR = 0x00000800, + Op_TO = 0x00001000, + Op_sign = 0x00002000, + Op_const = 0x00004000, + Op_SIMM = Op_const | Op_sign, + Op_UIMM = Op_const, + Op_d = Op_const | Op_sign, + Op_crbA = 0x00008000, + Op_crbB = 0x00010000, + Op_WS = Op_crbB, /* kludge, same field as crbB */ + Op_crbD = 0x00020000, + Op_crfD = 0x00040000, + Op_crfS = 0x00080000, + Op_ds = 0x00100000, + Op_me = 0x00200000, + Op_spr = 0x00400000, + Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ + Op_tbr = 0x00800000, + + Op_L = 0x01000000, + Op_BD = 0x02000000, + Op_LI = 0x04000000, + Op_C = 0x08000000, + + Op_NB = 0x10000000, + + Op_sh_mb_sh = 0x20000000, + Op_sh = 0x40000000, + Op_SH = Op_sh | Op_sh_mb_sh, + Op_mb = 0x80000000, + Op_MB = Op_mb | Op_sh_mb_sh, + Op_ME = Op_MB, + +}; + +struct opcode { + char *name; + u_int32_t mask; + u_int32_t code; + enum function_mask func; +}; + +typedef u_int32_t instr_t; +typedef void (op_class_func) (instr_t, vm_offset_t); + +u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); +void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, + char *disasm_str); +void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc); + +op_class_func op_ill, op_base; +op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; +op_class_func op_cl_x3a, op_cl_x3b; +op_class_func op_cl_x3e, op_cl_x3f; + +op_class_func *opcodes_base[] = { +/*x00*/ op_ill, op_ill, op_base, op_ill, +/*x04*/ op_ill, op_ill, op_ill, op_base, +/*x08*/ op_base, op_base, op_ill, op_base, +/*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, +/*x10*/ op_base, op_base, op_base, op_cl_x13, +/*x14*/ op_base, op_base, op_ill, op_base, +/*x18*/ op_base, op_base, op_base, op_base, +/*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, +/*x20*/ op_base, op_base, op_base, op_base, +/*x24*/ op_base, op_base, op_base, op_base, +/*x28*/ op_base, op_base, op_base, op_base, +/*x2C*/ op_base, op_base, op_base, op_base, +/*x30*/ op_base, op_base, op_base, op_base, +/*x34*/ op_base, op_base, op_base, op_base, +/*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, +/*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f +}; + + +/* This table could be modified to make significant the "reserved" fields + * of the opcodes, But I didn't feel like it when typing in the table, + * I would recommend that this table be looked over for errors, + * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) + * PowerPC Microprocessor Family: The Programming Environments + */ + +const struct opcode opcodes[] = { + { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, + { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, + { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, + { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, + { "cmpli", 0xfc000000, 0x28000000, Op_crfD | Op_L | Op_A | Op_SIMM }, + { "cmpi", 0xfc000000, 0x2c000000, Op_crfD | Op_L | Op_A | Op_SIMM }, + { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, + { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, + { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, + { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, + { "bc", 0xfc000000, 0x40000000, Op_BO | Op_BI | Op_BD | Op_AA | Op_LK }, + { "sc", 0xffffffff, 0x44000002, Op_BO | Op_BI | Op_BD | Op_AA | Op_LK }, + { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, + + { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, + { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, + { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, + + { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, + { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, + { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, + { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, + + { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, + { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, + + { "lwz", 0xfc000000, 0x80000000, Op_D | Op_A | Op_d }, + { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_A | Op_d }, + { "lbz", 0xfc000000, 0x88000000, Op_D | Op_A | Op_d }, + { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_A | Op_d }, + { "stw", 0xfc000000, 0x90000000, Op_S | Op_A | Op_d }, + { "stwu", 0xfc000000, 0x94000000, Op_S | Op_A | Op_d }, + { "stb", 0xfc000000, 0x98000000, Op_S | Op_A | Op_d }, + { "stbu", 0xfc000000, 0x9c000000, Op_S | Op_A | Op_d }, + + { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_A | Op_d }, + { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_A | Op_d }, + { "lha", 0xfc000000, 0xa8000000, Op_D | Op_A | Op_d }, + { "lhau", 0xfc000000, 0xac000000, Op_D | Op_A | Op_d }, + { "sth", 0xfc000000, 0xb0000000, Op_S | Op_A | Op_d }, + { "sthu", 0xfc000000, 0xb4000000, Op_S | Op_A | Op_d }, + { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_A | Op_d }, + { "stmw", 0xfc000000, 0xbc000000, Op_S | Op_A | Op_d }, + + { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_A | Op_d }, + { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_A | Op_d }, + { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_A | Op_d }, + { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_A | Op_d }, + + { "stfs", 0xfc000000, 0xd0000000, Op_S | Op_A | Op_d }, + { "stfsu", 0xfc000000, 0xd4000000, Op_S | Op_A | Op_d }, + { "stfd", 0xfc000000, 0xd8000000, Op_S | Op_A | Op_d }, + { "stfdu", 0xfc000000, 0xdc000000, Op_S | Op_A | Op_d }, + { "", 0x0, 0x0, 0 } + +}; +/* 13 * 4 = 4c */ +const struct opcode opcodes_13[] = { +/* 0x13 << 2 */ + { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, + { "bclr", 0xfc0007fe, 0x4c000020, Op_BO | Op_BI | Op_LK }, + { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, + { "rfi", 0xfc0007fe, 0x4c000064, 0 }, + { "crandc", 0xfc0007fe, 0x4c000102, Op_BO | Op_BI | Op_LK }, + { "isync", 0xfc0007fe, 0x4c00012c, 0 }, + { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, + { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, + { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, + { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, + { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, + { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, + { "bcctr", 0xfc0007fe, 0x4c000420, Op_BO | Op_BI | Op_LK }, + { "", 0x0, 0x0, 0 } +}; + +/* 1e * 4 = 78 */ +const struct opcode opcodes_1e[] = { + { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, + { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, + { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, + { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, + { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, + { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, + { "", 0x0, 0x0, 0 } +}; + +/* 1f * 4 = 7c */ +const struct opcode opcodes_1f[] = { +/* 1f << 2 */ + { "cmp", 0xfc0007fe, 0x7c000000, Op_S | Op_A | Op_B | Op_me | Op_Rc }, + { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, + { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, + { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, + + { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, + { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, + { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, + { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, + { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, + { "cntlzw", 0xfc0007fe, 0x7c000034, Op_D | Op_A | Op_Rc }, + { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, + { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, + { "cmpl", 0xfc0007fe, 0x7c000040, Op_crfD | Op_L | Op_A | Op_B }, + { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, + { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, + { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, + { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, + { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, + { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, + { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, + { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, + { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, + { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, + { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, + { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, + { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, + { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, + { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, + { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, + { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, + { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, + { "stdx", 0xfc0007fe, 0x7c00012a, Op_S | Op_A | Op_B }, + { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_S | Op_A | Op_B }, + { "stwx", 0xfc0007fe, 0x7c00012e, Op_S | Op_A | Op_B }, + { "wrteei", 0xfc0003fe, 0x7c000146 }, /* XXX: out of flags! */ + { "stdux", 0xfc0007fe, 0x7c00016a, Op_S | Op_A | Op_B }, + { "stwux", 0xfc0007fe, 0x7c00016e, Op_S | Op_A | Op_B }, + { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, + { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, + { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, + { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_S | Op_A | Op_B }, + { "stbx", 0xfc0007fe, 0x7c0001ae, Op_S | Op_A | Op_B }, + { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, + { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, + { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, + { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, + { "stbux", 0xfc0007fe, 0x7c0001ee, Op_S | Op_A | Op_B }, + { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, + { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, + { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, + { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, + { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, + { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, + { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, + { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, + { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, + { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, + { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, + { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, + { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, + { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, + { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, + { "sthx", 0xfc0007fe, 0x7c00032e, Op_S | Op_A | Op_B }, + { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, + { "ecowx", 0xfc0007fe, 0x7c00036c, Op_S | Op_A | Op_B | Op_Rc }, + { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, + { "sthux", 0xfc0007fe, 0x7c00036e, Op_S | Op_A | Op_B }, + { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, + { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, + { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, + { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, + { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, + { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, + { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, + { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, + { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, + { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, + { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, + { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, + { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, + { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, + { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, + { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, + { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, + { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, + { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, + { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, + { "sync", 0xfc0007fe, 0x7c0004ac, 0 }, + { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, + { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, + { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, + { "stswx", 0xfc0007fe, 0x7c00052a, Op_S | Op_A | Op_B }, + { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_S | Op_A | Op_B }, + { "stfsx", 0xfc0007fe, 0x7c00052e, Op_S | Op_A | Op_B }, + { "stfsux", 0xfc0007fe, 0x7c00056e, Op_S | Op_A | Op_B }, + { "stswi", 0xfc0007fe, 0x7c0005aa, Op_S | Op_A | Op_NB }, + { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_S | Op_A | Op_B }, + { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_S | Op_A | Op_B }, + { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, + { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, + { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, + { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_B | Op_Rc }, + { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, + { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, + { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, + { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_S | Op_A | Op_B }, + { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_B | Op_Rc }, + { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, + { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, + { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, + { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, + { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_S | Op_A | Op_B }, + { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, + { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, + { "", 0x0, 0x0, 0 } +}; + +/* 3a * 4 = e8 */ +const struct opcode opcodes_3a[] = { + { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, + { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, + { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, + { "", 0x0, 0x0, 0 } +}; +/* 3b * 4 = ec */ +const struct opcode opcodes_3b[] = { + { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, + { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, + + { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, + { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, + { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, + { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, + { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "", 0x0, 0x0, 0 } +}; +/* 3e * 4 = f8 */ +const struct opcode opcodes_3e[] = { + { "std", 0xfc000003, 0xf8000000, Op_S | Op_A | Op_ds }, + { "stdu", 0xfc000003, 0xf8000001, Op_S | Op_A | Op_ds }, + { "", 0x0, 0x0, 0 } +}; + +/* 3f * 4 = fc */ +const struct opcode opcodes_3f[] = { + { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, + { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, + { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, + { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, + + { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, + { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, + { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, + { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, + { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, + { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, + { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, + + { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, + { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, + { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, + { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, + { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, + { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, + { "mtfsfi", 0xfc0007fe, 0xfc00010c, Op_crfD | Op_IMM | Op_Rc }, + + { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, + { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, + { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, + { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, + { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, + { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, + { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, + { "", 0x0, 0x0, 0 } +}; + + +struct specialreg { + int reg; + char *name; +}; + +const struct specialreg sprregs[] = { + { 0x001, "xer" }, + { 0x008, "lr" }, + { 0x009, "ctr" }, + { 0x012, "dsisr" }, + { 0x013, "dar" }, + { 0x016, "dec" }, + { 0x019, "sdr1" }, + { 0x01a, "srr0" }, + { 0x01b, "srr1" }, + { 0x100, "usprg0" }, + { 0x110, "sprg0" }, + { 0x111, "sprg1" }, + { 0x112, "sprg2" }, + { 0x113, "sprg3" }, + { 0x114, "sprg4" }, + { 0x115, "sprg5" }, + { 0x116, "sprg6" }, + { 0x117, "sprg7" }, + { 0x118, "asr" }, + { 0x11a, "aer" }, + { 0x11c, "tbl" }, + { 0x11d, "tbu" }, + { 0x11f, "pvr" }, + { 0x210, "ibat0u" }, + { 0x211, "ibat0l" }, + { 0x212, "ibat1u" }, + { 0x213, "ibat1l" }, + { 0x214, "ibat2u" }, + { 0x215, "ibat2l" }, + { 0x216, "ibat3u" }, + { 0x217, "ibat3l" }, + { 0x218, "dbat0u" }, + { 0x219, "dbat0l" }, + { 0x21a, "dbat1u" }, + { 0x21b, "dbat1l" }, + { 0x21c, "dbat2u" }, + { 0x21d, "dbat2l" }, + { 0x21e, "dbat3u" }, + { 0x21f, "dbat3l" }, + { 0x3b0, "zpr" }, + { 0x3b1, "pid" }, + { 0x3b3, "ccr0" }, + { 0x3b4, "iac3" }, + { 0x3b5, "iac4" }, + { 0x3b6, "dvc1" }, + { 0x3b7, "dvc2" }, + { 0x3b9, "sgr" }, + { 0x3ba, "dcwr" }, + { 0x3bb, "sler" }, + { 0x3bc, "su0r" }, + { 0x3bd, "dbcr1" }, + { 0x3d3, "icdbdr" }, + { 0x3d4, "esr" }, + { 0x3d5, "dear" }, + { 0x3d6, "evpr" }, + { 0x3d8, "tsr" }, + { 0x3da, "tcr" }, + { 0x3db, "pit" }, + { 0x3de, "srr2" }, + { 0x3df, "srr3" }, + { 0x3f0, "dbsr" }, + { 0x3f2, "dbcr0" }, + { 0x3f4, "iac1" }, + { 0x3f5, "iac2" }, + { 0x3f6, "dac1" }, + { 0x3f7, "dac2" }, + { 0x3f9, "l2cr" }, + { 0x3fa, "dccr" }, + { 0x3fb, "iccr" }, + { 0x3ff, "pir" }, + { 0, NULL } +}; + +const struct specialreg dcrregs[] = { + { 0x010, "sdram0_cfgaddr" }, + { 0x011, "sdram0_cfgdata" }, + { 0x012, "ebc0_cfgaddr" }, + { 0x013, "ebc0_cfgdata" }, + { 0x014, "dcp0_cfgaddr" }, + { 0x015, "dcp0_cfgdata" }, + { 0x018, "ocm0_isarc" }, + { 0x019, "ocm0_iscntl" }, + { 0x01a, "ocm0_dsarc" }, + { 0x01b, "ocm0_dscntl" }, + { 0x084, "plb0_besr" }, + { 0x086, "plb0_bear" }, + { 0x087, "plb0_acr" }, + { 0x0a0, "pob0_besr0" }, + { 0x0a2, "pob0_bear" }, + { 0x0a4, "pob0_besr1" }, + { 0x0b0, "cpc0_pllmr" }, + { 0x0b1, "cpc0_cr0" }, + { 0x0b2, "cpc0_cr1" }, + { 0x0b4, "cpc0_psr" }, + { 0x0b5, "cpc0_jtagid" }, + { 0x0b8, "cpc0_sr" }, + { 0x0b9, "cpc0_er" }, + { 0x0ba, "cpc0_fr" }, + { 0x0c0, "uic0_sr" }, + { 0x0c2, "uic0_er" }, + { 0x0c3, "uic0_cr" }, + { 0x0c4, "uic0_pr" }, + { 0x0c5, "uic0_tr" }, + { 0x0c6, "uic0_msr" }, + { 0x0c7, "uic0_vr" }, + { 0x0c8, "uic0_vcr" }, + { 0x100, "dma0_cr0" }, + { 0x101, "dma0_ct0" }, + { 0x102, "dma0_da0" }, + { 0x103, "dma0_sa0" }, + { 0x104, "dma0_sg0" }, + { 0x108, "dma0_cr1" }, + { 0x109, "dma0_ct1" }, + { 0x10a, "dma0_da1" }, + { 0x10b, "dma0_sa1" }, + { 0x10c, "dma0_sg1" }, + { 0x110, "dma0_cr2" }, + { 0x111, "dma0_ct2" }, + { 0x112, "dma0_da2" }, + { 0x113, "dma0_sa2" }, + { 0x114, "dma0_sg2" }, + { 0x118, "dma0_cr3" }, + { 0x119, "dma0_ct3" }, + { 0x11a, "dma0_da3" }, + { 0x11b, "dma0_sa3" }, + { 0x11c, "dma0_sg3" }, + { 0x120, "dma0_sr" }, + { 0x123, "dma0_sgc" }, + { 0x125, "dma0_slp" }, + { 0x126, "dma0_pol" }, + { 0x180, "mal0_cfg" }, + { 0x181, "mal0_esr" }, + { 0x182, "mal0_ier" }, + { 0x184, "mal0_txcasr" }, + { 0x185, "mal0_txcarr" }, + { 0x186, "mal0_txeobisr" }, + { 0x187, "mal0_txdeir" }, + { 0x190, "mal0_rxcasr" }, + { 0x191, "mal0_rxcarr" }, + { 0x192, "mal0_rxeobisr" }, + { 0x193, "mal0_rxdeir" }, + { 0x1a0, "mal0_txctp0r" }, + { 0x1a1, "mal0_txctp1r" }, + { 0x1a2, "mal0_txctp2r" }, + { 0x1a3, "mal0_txctp3r" }, + { 0x1c0, "mal0_rxctp0r" }, + { 0x1e0, "mal0_rcbs0" }, + { 0, NULL } +}; + +void +op_ill(instr_t instr, vm_offset_t loc) +{ + db_printf("illegal instruction %x\n", instr); +} + +u_int32_t +extract_field(u_int32_t value, u_int32_t base, u_int32_t width) +{ + u_int32_t mask = (1 << width) - 1; + return ((value >> base) & mask); +} + +const struct opcode * search_op(const struct opcode *); + +void +disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, + char *disasm_str) +{ + char * pstr; + enum function_mask func; + + pstr = disasm_str; + + func = popcode->func; + if (func & Op_OE) { + u_int OE; + /* also for Op_S (they are the same) */ + OE = extract_field(instr, 31 - 21, 1); + if (OE) { + pstr += sprintf(pstr, "o"); + } + func &= ~Op_OE; + } + switch (func & Op_LKM) { + case Op_Rc: + if (instr & 0x1) { + pstr += sprintf(pstr, "."); + } + break; + case Op_AA: + if (instr & 0x2) { + pstr += sprintf(pstr, "a"); + loc = 0; /* Absolute address */ + } + case Op_LK: + if (instr & 0x1) { + pstr += sprintf(pstr, "l"); + } + break; + default: + func &= ~Op_LKM; + } + pstr += sprintf(pstr, "\t"); + + /* XXX: special cases here, out of flags in a 32bit word. */ + if (strcmp(popcode->name, "wrteei") == 0) { + int E; + E = extract_field(instr, 31 - 16, 5); + pstr += sprintf(pstr, "%d", E); + return; + } + /* XXX: end of special cases here. */ + + if (func & Op_D) { + u_int D; + /* also for Op_S (they are the same) */ + D = extract_field(instr, 31 - 10, 5); + pstr += sprintf(pstr, "r%d, ", D); + func &= ~Op_D; + } + if (func & Op_crbD) { + u_int crbD; + crbD = extract_field(instr, 31 - 10, 5); + pstr += sprintf(pstr, "crb%d, ", crbD); + func &= ~Op_crbD; + } + if (func & Op_crfD) { + u_int crfD; + crfD = extract_field(instr, 31 - 8, 3); + pstr += sprintf(pstr, "crf%d, ", crfD); + func &= ~Op_crfD; + } + if (func & Op_L) { + u_int L; + L = extract_field(instr, 31 - 10, 1); + if (L) { + pstr += sprintf(pstr, "L, "); + } + func &= ~Op_L; + } + if (func & Op_FM) { + u_int FM; + FM = extract_field(instr, 31 - 10, 8); + pstr += sprintf(pstr, "%d, ", FM); + func &= ~Op_FM; + } + if (func & Op_TO) { + u_int TO; + TO = extract_field(instr, 31 - 10, 1); + pstr += sprintf(pstr, "%d, ", TO); + func &= ~Op_TO; + } + if (func & Op_crfS) { + u_int crfS; + crfS = extract_field(instr, 31 - 13, 3); + pstr += sprintf(pstr, "%d, ", crfS); + func &= ~Op_crfS; + } + if (func & Op_BO) { + u_int BO; + BO = extract_field(instr, 31 - 10, 5); + pstr += sprintf(pstr, "%d, ", BO); + func &= ~Op_BO; + } + if (func & Op_A) { + u_int A; + A = extract_field(instr, 31 - 15, 5); + pstr += sprintf(pstr, "r%d, ", A); + func &= ~Op_A; + } + if (func & Op_B) { + u_int B; + B = extract_field(instr, 31 - 20, 5); + pstr += sprintf(pstr, "r%d, ", B); + func &= ~Op_B; + } + if (func & Op_C) { + u_int C; + C = extract_field(instr, 31 - 25, 5); + pstr += sprintf(pstr, "r%d, ", C); + func &= ~Op_C; + } + if (func & Op_BI) { + u_int BI; + BI = extract_field(instr, 31 - 10, 5); + pstr += sprintf(pstr, "%d, ", BI); + func &= ~Op_BI; + } + if (func & Op_crbA) { + u_int crbA; + crbA = extract_field(instr, 31 - 15, 5); + pstr += sprintf(pstr, "%d, ", crbA); + func &= ~Op_crbA; + } + if (func & Op_crbB) { + u_int crbB; + crbB = extract_field(instr, 31 - 20, 5); + pstr += sprintf(pstr, "%d, ", crbB); + func &= ~Op_crbB; + } + if (func & Op_CRM) { + u_int CRM; + CRM = extract_field(instr, 31 - 19, 8); + pstr += sprintf(pstr, "0x%x, ", CRM); + func &= ~Op_CRM; + } + if (func & Op_LI) { + int LI; + LI = extract_field(instr, 31 - 29, 24); + /* Need to sign extend and shift up 2, then add addr */ + LI = LI << 8; + LI = LI >> 6; + LI += loc; + db_symstr(pstr, LI, DB_STGY_ANY); + pstr += strlen(pstr); + func &= ~Op_LI; + } + switch (func & Op_SIMM) { + u_int IMM; + case Op_SIMM: /* same as Op_d */ + IMM = extract_field(instr, 31 - 31, 16); + if (IMM & 0x8000) { + pstr += sprintf(pstr, "-"); + IMM = 0x10000-IMM; + } + func &= ~Op_SIMM; + goto common; + case Op_UIMM: + IMM = extract_field(instr, 31 - 31, 16); + func &= ~Op_UIMM; + goto common; + common: + pstr += sprintf(pstr, "0x%x", IMM); + break; + default: + } + if (func & Op_BD) { + u_int BD; + BD = extract_field(instr, 31 - 29, 14); + pstr += sprintf(pstr, "0x%x, ", BD); + func &= ~Op_BD; + } + if (func & Op_ds) { + u_int ds; + ds = extract_field(instr, 31 - 29, 14) << 2; + pstr += sprintf(pstr, "0x%x, ", ds); + func &= ~Op_ds; + } + if (func & Op_spr) { + u_int spr; + u_int sprl; + u_int sprh; + const struct specialreg *regs; + int i; + sprl = extract_field(instr, 31 - 15, 5); + sprh = extract_field(instr, 31 - 20, 5); + spr = sprh << 5 | sprl; + + /* ugly hack - out of bitfields in the function mask */ + if (popcode->name[2] == 'd') /* m.Dcr */ + regs = dcrregs; + else + regs = sprregs; + for (i = 0; regs[i].name != NULL; i++) + if (spr == regs[i].reg) + break; + if (regs[i].reg == 0) + pstr += sprintf(pstr, "[unknown special reg (%d)]", spr); + else + pstr += sprintf(pstr, "%s", regs[i].name); + func &= ~Op_spr; + } + + if (func & Op_me) { + u_int me, mel, meh; + mel = extract_field(instr, 31 - 25, 4); + meh = extract_field(instr, 31 - 26, 1); + me = meh << 4 | mel; + pstr += sprintf(pstr, ", 0x%x", me); + func &= ~Op_me; + } + if ((func & Op_MB) && (func & Op_sh_mb_sh)) { + u_int MB; + u_int ME; + MB = extract_field(instr, 31 - 20, 5); + pstr += sprintf(pstr, ", %d", MB); + ME = extract_field(instr, 31 - 25, 5); + pstr += sprintf(pstr, ", %d", ME); + } + if ((func & Op_SH) && (func & Op_sh_mb_sh)) { + u_int SH; + SH = extract_field(instr, 31 - 20, 5); + pstr += sprintf(pstr, ", %d", SH); + } + if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { + u_int sh, shl, shh; + shl = extract_field(instr, 31 - 19, 4); + shh = extract_field(instr, 31 - 20, 1); + sh = shh << 4 | shl; + pstr += sprintf(pstr, ", %d", sh); + } + if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { + u_int mb, mbl, mbh; + mbl = extract_field(instr, 31 - 25, 4); + mbh = extract_field(instr, 31 - 26, 1); + mb = mbh << 4 | mbl; + pstr += sprintf(pstr, ", %d", mb); + } + if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { + u_int me, mel, meh; + mel = extract_field(instr, 31 - 25, 4); + meh = extract_field(instr, 31 - 26, 1); + me = meh << 4 | mel; + pstr += sprintf(pstr, ", %d", me); + } + if (func & Op_tbr) { + u_int tbr; + u_int tbrl; + u_int tbrh; + char *reg; + tbrl = extract_field(instr, 31 - 15, 5); + tbrh = extract_field(instr, 31 - 20, 5); + tbr = tbrh << 5 | tbrl; + + switch (tbr) { + case 268: + reg = "tbl"; + break; + case 269: + reg = "tbu"; + break; + default: + reg = 0; + } + if (reg == 0) + pstr += sprintf(pstr, ", [unknown tbr %d ]", tbr); + else + pstr += sprintf(pstr, ", %s", reg); + func &= ~Op_tbr; + } + if (func & Op_SR) { + u_int SR; + SR = extract_field(instr, 31 - 15, 3); + pstr += sprintf(pstr, ", sr%d", SR); + func &= ~Op_SR; + } + if (func & Op_NB) { + u_int NB; + NB = extract_field(instr, 31 - 20, 5); + if (NB == 0) + NB = 32; + pstr += sprintf(pstr, ", %d", NB); + func &= ~Op_SR; + } + if (func & Op_IMM) { + u_int IMM; + IMM = extract_field(instr, 31 - 19, 4); + pstr += sprintf(pstr, ", %d", IMM); + func &= ~Op_SR; + } +} + +void +op_base(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes, instr, loc); +} + +void +op_cl_x13(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes_13, instr, loc); +} + +void +op_cl_x1e(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes_1e, instr, loc); +} + +void +op_cl_x1f(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes_1f, instr, loc); +} + +void +op_cl_x3a(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes_3a, instr, loc); +} + +void +op_cl_x3b(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes_3b, instr, loc); +} + +void +op_cl_x3e(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes_3e, instr, loc); +} + +void +op_cl_x3f(instr_t instr, vm_offset_t loc) +{ + dis_ppc(opcodes_3f, instr, loc); +} + +void +dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc) +{ + const struct opcode *op; + int found = 0; + int i; + char disasm_str[30]; + + for (i = 0, op = &opcodeset[0]; + found == 0 && op->mask != 0; + i++, op = &opcodeset[i]) { + if ((instr & op->mask) == op->code) { + found = 1; + disasm_fields(op, instr, loc, disasm_str); + db_printf("%s%s\n", op->name, disasm_str); + return; + } + } + op_ill(instr, loc); +} + +db_addr_t +db_disasm(db_addr_t loc, boolean_t extended) +{ + int class; + instr_t opcode; + opcode = *(instr_t *)(loc); + class = opcode >> 26; + (opcodes_base[class])(opcode, loc); + + return (loc + 4); +} + +vm_offset_t opc_disasm(vm_offset_t loc, int); + +vm_offset_t +opc_disasm(vm_offset_t loc, int xin) +{ + int class; + instr_t opcode; + opcode = xin; + class = opcode >> 26; + (opcodes_base[class])(opcode, loc); + + return (loc + 4); +} diff --git a/sys/powerpc/powerpc/db_hwwatch.c b/sys/powerpc/powerpc/db_hwwatch.c new file mode 100644 index 000000000000..fe8680e97f10 --- /dev/null +++ b/sys/powerpc/powerpc/db_hwwatch.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2002 Benno Rice. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ +#include + +#include + +#include +#include +#include +#include +#include + +int db_md_set_watchpoint(db_expr_t, db_expr_t); +int db_md_clr_watchpoint(db_expr_t, db_expr_t); +void db_md_list_watchpoints(void); + +int +db_md_set_watchpoint(db_expr_t addr, db_expr_t size) +{ + + return (0); +} + +int +db_md_clr_watchpoint(db_expr_t addr, db_expr_t size) +{ + + return (0); +} + +void +db_md_list_watchpoints(void) +{ +} diff --git a/sys/powerpc/powerpc/db_interface.c b/sys/powerpc/powerpc/db_interface.c new file mode 100644 index 000000000000..8eda5c465559 --- /dev/null +++ b/sys/powerpc/powerpc/db_interface.c @@ -0,0 +1,377 @@ +/* $FreeBSD$ */ +/* $NetBSD: db_interface.c,v 1.20 2002/05/13 20:30:09 matt Exp $ */ +/* $OpenBSD: db_interface.c,v 1.2 1996/12/28 06:21:50 rahnds Exp $ */ + +#define USERACC + +#include "opt_ddb.h" + +#include +#include +#include + +#include +#include +#include +#ifdef PPC_IBM4XX +#include +#include +#include +#endif + +#ifdef DDB +#include +#include +#include +#include +#include +#endif + +#ifdef KGDB +#include +#endif + +#include + +int db_active = 0; + +db_regs_t ddb_regs; + +void ddb_trap(void); /* Call into trap_subr.S */ +int ddb_trap_glue(struct trapframe *); /* Called from trap_subr.S */ +#ifdef PPC_IBM4XX +static void db_ppc4xx_ctx(db_expr_t, int, db_expr_t, char *); +static void db_ppc4xx_pv(db_expr_t, int, db_expr_t, char *); +static void db_ppc4xx_reset(db_expr_t, int, db_expr_t, char *); +static void db_ppc4xx_tf(db_expr_t, int, db_expr_t, char *); +static void db_ppc4xx_dumptlb(db_expr_t, int, db_expr_t, char *); +#ifdef USERACC +static void db_ppc4xx_useracc(db_expr_t, int, db_expr_t, char *); +#endif +#endif /* PPC_IBM4XX */ + +#ifdef DDB +void +Debugger(const char *msg) +{ + db_printf("Welcome to Debugger, %s\n", msg); + ddb_trap(); +} +#endif + +int +ddb_trap_glue(frame) + struct trapframe *frame; +{ + if (!(frame->srr1 & PSL_PR) + && (frame->exc == EXC_TRC || frame->exc == EXC_RUNMODETRC + || (frame->exc == EXC_PGM + && (frame->srr1 & 0x20000)) + || frame->exc == EXC_BPT)) { + int type = frame->exc; + if (type == EXC_PGM && (frame->srr1 & 0x20000)) { + type = T_BREAKPOINT; + } + return kdb_trap(type, frame); + } + return 0; +} + +int +kdb_trap(type, v) + int type; + void *v; +{ + struct trapframe *frame = v; + +#if 0 + switch (type) { + case T_BREAKPOINT: + case -1: + break; + default: + if (!db_onpanic && db_recover == 0) + return 0; + if (db_recover != 0) { + db_error("Faulted in DDB; continuing...\n"); + /*NOTREACHED*/ + } + } +#endif + + /* XXX Should switch to kdb's own stack here. */ + + memcpy(DDB_REGS->r, frame->fixreg, 32 * sizeof(u_int32_t)); + DDB_REGS->iar = frame->srr0; + DDB_REGS->msr = frame->srr1; + DDB_REGS->lr = frame->lr; + DDB_REGS->ctr = frame->ctr; + DDB_REGS->cr = frame->cr; + DDB_REGS->xer = frame->xer; +#ifdef PPC_IBM4XX + DDB_REGS->dear = frame->dear; + DDB_REGS->esr = frame->esr; + DDB_REGS->pid = frame->pid; +#endif + +#ifdef DDB + db_active++; + cndbctl(1); + db_trap(type, 0); + cndbctl(0); + db_active--; +#elif defined(KGDB) + if (!kgdb_trap(type, DDB_REGS)) + return 0; +#endif + + /* KGDB isn't smart about advancing PC if we + * take a breakpoint trap after kgdb_active is set. + * Therefore, we help out here. + */ + if (IS_BREAKPOINT_TRAP(type, 0)) { + int bkpt; + db_read_bytes(PC_REGS(DDB_REGS),BKPT_SIZE,(void *)&bkpt); + if (bkpt== BKPT_INST) { + PC_REGS(DDB_REGS) += BKPT_SIZE; + } + } + + memcpy(frame->fixreg, DDB_REGS->r, 32 * sizeof(u_int32_t)); + frame->srr0 = DDB_REGS->iar; + frame->srr1 = DDB_REGS->msr; + frame->lr = DDB_REGS->lr; + frame->ctr = DDB_REGS->ctr; + frame->cr = DDB_REGS->cr; + frame->xer = DDB_REGS->xer; +#ifdef PPC_IBM4XX + frame->dear = DDB_REGS->dear; + frame->esr = DDB_REGS->esr; + frame->pid = DDB_REGS->pid; +#endif + + return 1; +} + +#ifdef PPC_IBM4XX +const struct db_command db_machine_command_table[] = { + { "ctx", db_ppc4xx_ctx, 0, 0 }, + { "pv", db_ppc4xx_pv, 0, 0 }, + { "reset", db_ppc4xx_reset, 0, 0 }, + { "tf", db_ppc4xx_tf, 0, 0 }, + { "tlb", db_ppc4xx_dumptlb, 0, 0 }, +#ifdef USERACC + { "user", db_ppc4xx_useracc, 0, 0 }, +#endif + { NULL, } +}; + +static void +db_ppc4xx_ctx(db_expr_t addr, int have_addr, db_expr_t count, char *modif) +{ + struct proc *p; + + /* XXX LOCKING XXX */ + for (p = allproc.lh_first; p != 0; p = p->p_list.le_next) { + if (p->p_stat) { + db_printf("process %p:", p); + db_printf("pid:%d pmap:%p ctx:%d %s\n", + p->p_pid, p->p_vmspace->vm_map.pmap, + p->p_vmspace->vm_map.pmap->pm_ctx, + p->p_comm); + } + } + return; +} + +static void +db_ppc4xx_pv(db_expr_t addr, int have_addr, db_expr_t count, char *modif) +{ + struct pv_entry { + struct pv_entry *pv_next; /* Linked list of mappings */ + vaddr_t pv_va; /* virtual address of mapping */ + struct pmap *pv_pm; + }; + struct pv_entry *pa_to_pv(paddr_t); + struct pv_entry *pv; + + if (!have_addr) { + db_printf("pv: \n"); + return; + } + pv = pa_to_pv(addr); + db_printf("pv at %p\n", pv); + while (pv && pv->pv_pm) { + db_printf("next %p va %p pmap %p\n", pv->pv_next, + (void *)pv->pv_va, pv->pv_pm); + pv = pv->pv_next; + } +} + +static void +db_ppc4xx_reset(db_expr_t addr, int have_addr, db_expr_t count, char *modif) +{ + printf("Reseting...\n"); + ppc4xx_reset(); +} + +static void +db_ppc4xx_tf(db_expr_t addr, int have_addr, db_expr_t count, char *modif) +{ + struct trapframe *f; + + + if (have_addr) { + f = (struct trapframe *)addr; + + db_printf("r0-r3: \t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[0], f->fixreg[1], + f->fixreg[2], f->fixreg[3]); + db_printf("r4-r7: \t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[4], f->fixreg[5], + f->fixreg[6], f->fixreg[7]); + db_printf("r8-r11: \t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[8], f->fixreg[9], + f->fixreg[10], f->fixreg[11]); + db_printf("r12-r15:\t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[12], f->fixreg[13], + f->fixreg[14], f->fixreg[15]); + db_printf("r16-r19:\t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[16], f->fixreg[17], + f->fixreg[18], f->fixreg[19]); + db_printf("r20-r23:\t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[20], f->fixreg[21], + f->fixreg[22], f->fixreg[23]); + db_printf("r24-r27:\t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[24], f->fixreg[25], + f->fixreg[26], f->fixreg[27]); + db_printf("r28-r31:\t%8.8x %8.8x %8.8x %8.8x\n", + f->fixreg[28], f->fixreg[29], + f->fixreg[30], f->fixreg[31]); + + db_printf("lr: %8.8x cr: %8.8x xer: %8.8x ctr: %8.8x\n", + f->lr, f->cr, f->xer, f->ctr); + db_printf("srr0(pc): %8.8x srr1(msr): %8.8x " + "dear: %8.8x esr: %8.8x\n", + f->srr0, f->srr1, f->dear, f->esr); + db_printf("exc: %8.8x pid: %8.8x\n", + f->exc, f->pid); + } + return; +} + +static const char *const tlbsizes[] = { + "1kB", + "4kB", + "16kB", + "64kB", + "256kB", + "1MB", + "4MB", + "16MB" +}; + +static void +db_ppc4xx_dumptlb(db_expr_t addr, int have_addr, db_expr_t count, char *modif) +{ + int i, zone, tlbsize; + u_int zpr, pid, opid, msr; + u_long tlblo, tlbhi, tlbmask; + + zpr = mfspr(SPR_ZPR); + for (i = 0; i < NTLB; i++) { + asm volatile("mfmsr %3;" + "mfpid %4;" + "li %0,0;" + "mtmsr %0;" + "sync; isync;" + "tlbre %0,%5,1;" + "tlbre %1,%5,0;" + "mfpid %2;" + "mtpid %4;" + "mtmsr %3;" + "sync; isync" + : "=&r" (tlblo), "=&r" (tlbhi), "=r" (pid), + "=&r" (msr), "=&r" (opid) : "r" (i)); + + if (strchr(modif, 'v') && !(tlbhi & TLB_VALID)) + continue; + + tlbsize = (tlbhi & TLB_SIZE_MASK) >> TLB_SIZE_SHFT; + /* map tlbsize 0 .. 7 to masks for 1kB .. 16MB */ + tlbmask = ~(1 << (tlbsize * 2 + 10)) + 1; + + if (have_addr && ((tlbhi & tlbmask) != (addr & tlbmask))) + continue; + + zone = (tlblo & TLB_ZSEL_MASK) >> TLB_ZSEL_SHFT; + db_printf("tlb%c%2d", tlbhi & TLB_VALID ? ' ' : '*', i); + db_printf(" PID %3d EPN 0x%08lx %-5s", + pid, + tlbhi & tlbmask, + tlbsizes[tlbsize]); + db_printf(" RPN 0x%08lx ZONE %2d%c %s %s %c%c%c%c%c %s", + tlblo & tlbmask, + zone, + "NTTA"[(zpr >> ((15 - zone) * 2)) & 3], + tlblo & TLB_EX ? "EX" : " ", + tlblo & TLB_WR ? "WR" : " ", + tlblo & TLB_W ? 'W' : ' ', + tlblo & TLB_I ? 'I' : ' ', + tlblo & TLB_M ? 'M' : ' ', + tlblo & TLB_G ? 'G' : ' ', + tlbhi & TLB_ENDIAN ? 'E' : ' ', + tlbhi & TLB_U0 ? "U0" : " "); + db_printf("\n"); + } +} + +#ifdef USERACC +static void +db_ppc4xx_useracc(db_expr_t addr, int have_addr, db_expr_t count, char *modif) +{ + static paddr_t oldaddr = -1; + int instr = 0; + int data; + extern vaddr_t opc_disasm(vaddr_t loc, int); + + + if (!have_addr) { + addr = oldaddr; + } + if (addr == -1) { + db_printf("no address\n"); + return; + } + addr &= ~0x3; /* align */ + { + register char c, *cp = modif; + while ((c = *cp++) != 0) + if (c == 'i') + instr = 1; + } + while (count--) { + if (db_print_position() == 0) { + /* Always print the address. */ + db_printf("%8.4lx:\t", addr); + } + oldaddr=addr; + copyin((void *)addr, &data, sizeof(data)); + if (instr) { + opc_disasm(addr, data); + } else { + db_printf("%4.4x\n", data); + } + addr += 4; + db_end_line(); + } + +} +#endif + +#endif /* PPC_IBM4XX */ + +void +db_show_mdpcpu(struct pcpu *pc) +{ +} diff --git a/sys/powerpc/powerpc/db_memrw.c b/sys/powerpc/powerpc/db_memrw.c new file mode 100644 index 000000000000..eb3de2a1cf95 --- /dev/null +++ b/sys/powerpc/powerpc/db_memrw.c @@ -0,0 +1,109 @@ +/* $FreeBSD$ */ +/* $NetBSD: db_memrw.c,v 1.5 2001/12/27 10:25:41 dbj Exp $ */ +/* $OpenBSD: db_memrw.c,v 1.2 1996/12/28 06:21:52 rahnds Exp $ */ + +/* + * Mach Operating System + * Copyright (c) 1992 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + */ + +/* + * Interface to the debugger for virtual memory read/write. + * This is a simple version for kernels with writable text. + * For an example of read-only kernel text, see the file: + * sys/arch/sun3/sun3/db_memrw.c + * + * ALERT! If you want to access device registers with a + * specific size, then the read/write functions have to + * make sure to do the correct sized pointer access. + */ + +#include +#include + +#include +#include + +#include + +#include + +/* + * Read bytes from kernel address space for debugger. + */ +void +db_read_bytes(addr, size, data) + vm_offset_t addr; + register size_t size; + register char *data; +{ + register char *src = (char*)addr; + + if (size == 4) { + *((int*)data) = *((int*)src); + return; + } + + if (size == 2) { + *((short*)data) = *((short*)src); + return; + } + + while (size > 0) { + --size; + *data++ = *src++; + } +} + +/* + * Write bytes to kernel address space for debugger. + */ +void +db_write_bytes(addr, size, data) + vm_offset_t addr; + register size_t size; + register char *data; +{ + register char *dst = (char *)addr; + + if (size == 4) { + + *((int*)dst) = *((int*)data); + + } else if (size == 2) { + + *((short*)dst) = *((short*)data); + + } else { + + while (size > 0) { + --size; + *dst++ = *data++; + } + + } + + __syncicache((void *)addr, size); +} + diff --git a/sys/powerpc/powerpc/db_trace.c b/sys/powerpc/powerpc/db_trace.c new file mode 100644 index 000000000000..fe5efce57212 --- /dev/null +++ b/sys/powerpc/powerpc/db_trace.c @@ -0,0 +1,293 @@ +/* $FreeBSD$ */ +/* $NetBSD: db_trace.c,v 1.20 2002/05/13 20:30:09 matt Exp $ */ +/* $OpenBSD: db_trace.c,v 1.3 1997/03/21 02:10:48 niklas Exp $ */ + +/* + * Mach Operating System + * Copyright (c) 1992 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +struct db_variable db_regs[] = { + { "r0", (long *)&ddb_regs.r[0], FCN_NULL }, + { "r1", (long *)&ddb_regs.r[1], FCN_NULL }, + { "r2", (long *)&ddb_regs.r[2], FCN_NULL }, + { "r3", (long *)&ddb_regs.r[3], FCN_NULL }, + { "r4", (long *)&ddb_regs.r[4], FCN_NULL }, + { "r5", (long *)&ddb_regs.r[5], FCN_NULL }, + { "r6", (long *)&ddb_regs.r[6], FCN_NULL }, + { "r7", (long *)&ddb_regs.r[7], FCN_NULL }, + { "r8", (long *)&ddb_regs.r[8], FCN_NULL }, + { "r9", (long *)&ddb_regs.r[9], FCN_NULL }, + { "r10", (long *)&ddb_regs.r[10], FCN_NULL }, + { "r11", (long *)&ddb_regs.r[11], FCN_NULL }, + { "r12", (long *)&ddb_regs.r[12], FCN_NULL }, + { "r13", (long *)&ddb_regs.r[13], FCN_NULL }, + { "r14", (long *)&ddb_regs.r[14], FCN_NULL }, + { "r15", (long *)&ddb_regs.r[15], FCN_NULL }, + { "r16", (long *)&ddb_regs.r[16], FCN_NULL }, + { "r17", (long *)&ddb_regs.r[17], FCN_NULL }, + { "r18", (long *)&ddb_regs.r[18], FCN_NULL }, + { "r19", (long *)&ddb_regs.r[19], FCN_NULL }, + { "r20", (long *)&ddb_regs.r[20], FCN_NULL }, + { "r21", (long *)&ddb_regs.r[21], FCN_NULL }, + { "r22", (long *)&ddb_regs.r[22], FCN_NULL }, + { "r23", (long *)&ddb_regs.r[23], FCN_NULL }, + { "r24", (long *)&ddb_regs.r[24], FCN_NULL }, + { "r25", (long *)&ddb_regs.r[25], FCN_NULL }, + { "r26", (long *)&ddb_regs.r[26], FCN_NULL }, + { "r27", (long *)&ddb_regs.r[27], FCN_NULL }, + { "r28", (long *)&ddb_regs.r[28], FCN_NULL }, + { "r29", (long *)&ddb_regs.r[29], FCN_NULL }, + { "r30", (long *)&ddb_regs.r[30], FCN_NULL }, + { "r31", (long *)&ddb_regs.r[31], FCN_NULL }, + { "iar", (long *)&ddb_regs.iar, FCN_NULL }, + { "msr", (long *)&ddb_regs.msr, FCN_NULL }, + { "lr", (long *)&ddb_regs.lr, FCN_NULL }, + { "ctr", (long *)&ddb_regs.ctr, FCN_NULL }, + { "cr", (long *)&ddb_regs.cr, FCN_NULL }, + { "xer", (long *)&ddb_regs.xer, FCN_NULL }, +#ifdef PPC_IBM4XX + { "dear", (long *)&ddb_regs.dear, FCN_NULL }, + { "esr", (long *)&ddb_regs.esr, FCN_NULL }, + { "pid", (long *)&ddb_regs.pid, FCN_NULL }, +#endif +}; +struct db_variable *db_eregs = db_regs + sizeof (db_regs)/sizeof (db_regs[0]); + +extern int trapexit[]; +extern int end[]; + +/* + * Frame tracing. + */ +void +db_stack_trace_print(addr, have_addr, count, modif, pr) + db_expr_t addr; + int have_addr; + db_expr_t count; + char *modif; + void (*pr) __P((const char *, ...)); +{ + db_addr_t frame, lr, caller, *args; + db_addr_t fakeframe[2]; + db_expr_t diff; + db_sym_t sym; + char *symname; + boolean_t kernel_only = TRUE; + boolean_t trace_thread = FALSE; + boolean_t full = FALSE; + + { + register char *cp = modif; + register char c; + + while ((c = *cp++) != 0) { + if (c == 't') + trace_thread = TRUE; + if (c == 'u') + kernel_only = FALSE; + if (c == 'f') + full = TRUE; + } + } + + if (have_addr) { +#if 0 + if (trace_thread) { + struct proc *p; + struct user *u; + + (*pr)("trace: pid %d ", (int)addr); + p = pfind(addr); + if (p == NULL) { + (*pr)("not found\n"); + return; + } + if (!(p->p_flag&P_INMEM)) { + (*pr)("swapped out\n"); + return; + } + u = p->p_addr; + frame = (db_addr_t)u->u_pcb.pcb_sp; + (*pr)("at %p\n", frame); + } else +#endif + frame = (db_addr_t)addr; + } else { + frame = (db_addr_t)ddb_regs.r[1]; + } + for (;;) { + if (frame < PAGE_SIZE) + break; +#ifdef PPC_MPC6XX + if (kernel_only && + ((frame > (db_addr_t) end && + frame < VM_MIN_KERNEL_ADDRESS) || + frame >= VM_MAX_KERNEL_ADDRESS)) + break; +#endif + frame = *(db_addr_t *)frame; + next_frame: + args = (db_addr_t *)(frame + 8); + if (frame < PAGE_SIZE) + break; +#ifdef PPC_MPC6XX + if (kernel_only && + ((frame > (db_addr_t) end && + frame < VM_MIN_KERNEL_ADDRESS) || + frame >= VM_MAX_KERNEL_ADDRESS)) + break; +#endif + if (count-- == 0) + break; + + lr = *(db_addr_t *)(frame + 4) - 4; + if ((lr & 3) || (lr < 0x100)) { + (*pr)("saved LR(0x%x) is invalid.", lr); + break; + } + if ((caller = (db_addr_t)vtophys(lr)) == 0) + caller = lr; + + if (frame != (db_addr_t) fakeframe) { + (*pr)("0x%08lx: ", frame); + } else { + (*pr)(" : "); + } + if (caller + 4 == (db_addr_t) &trapexit) { + const char *trapstr; + struct trapframe *tf = (struct trapframe *) (frame+8); + (*pr)("%s ", tf->srr1 & PSL_PR ? "user" : "kernel"); + switch (tf->exc) { + case EXC_DSI: +#ifdef PPC_MPC6XX + (*pr)("DSI %s trap @ %#x by ", + tf->dsisr & DSISR_STORE ? "write" : "read", + tf->dar); +#endif +#ifdef PPC_IBM4XX + (*pr)("DSI %s trap @ %#x by ", + tf->esr & ESR_DST ? "write" : "read", + tf->dear); +#endif + goto print_trap; + case EXC_ISI: trapstr = "ISI"; break; + case EXC_PGM: trapstr = "PGM"; break; + case EXC_SC: trapstr = "SC"; break; + case EXC_EXI: trapstr = "EXI"; break; + case EXC_MCHK: trapstr = "MCHK"; break; + case EXC_VEC: trapstr = "VEC"; break; + case EXC_FPU: trapstr = "FPU"; break; + case EXC_FPA: trapstr = "FPA"; break; + case EXC_DECR: trapstr = "DECR"; break; + case EXC_ALI: trapstr = "ALI"; break; + case EXC_BPT: trapstr = "BPT"; break; + case EXC_TRC: trapstr = "TRC"; break; + case EXC_RUNMODETRC: trapstr = "RUNMODETRC"; break; + case EXC_PERF: trapstr = "PERF"; break; + case EXC_SMI: trapstr = "SMI"; break; + case EXC_RST: trapstr = "RST"; break; + default: trapstr = NULL; break; + } + if (trapstr != NULL) { + (*pr)("%s trap by ", trapstr); + } else { + (*pr)("trap %#x by ", tf->exc); + } + print_trap: + lr = (db_addr_t) tf->srr0; + if ((caller = (db_addr_t)vtophys(lr)) == 0) + caller = lr; + diff = 0; + symname = NULL; + sym = db_search_symbol(caller, DB_STGY_ANY, &diff); + db_symbol_values(sym, &symname, 0); + if (symname == NULL || !strcmp(symname, "end")) { + (*pr)("%p: srr1=%#x\n", caller, tf->srr1); + } else { + (*pr)("%s+%x: srr1=%#x\n", symname, diff, + tf->srr1); + } + (*pr)("%-10s r1=%#x cr=%#x xer=%#x ctr=%#x", + "", tf->fixreg[1], tf->cr, tf->xer, tf->ctr); +#ifdef PPC_MPC6XX + if (tf->exc == EXC_DSI) + (*pr)(" dsisr=%#x", tf->dsisr); +#endif +#ifdef PPC_IBM4XX + if (tf->exc == EXC_DSI) + (*pr)(" dear=%#x", tf->dear); + (*pr)(" esr=%#x pid=%#x", tf->esr, tf->pid); +#endif + (*pr)("\n"); + fakeframe[0] = (db_addr_t) tf->fixreg[1]; + fakeframe[1] = (db_addr_t) tf->lr; + frame = (db_addr_t) fakeframe; + if (kernel_only && (tf->srr1 & PSL_PR)) + break; + goto next_frame; + } + + diff = 0; + symname = NULL; + sym = db_search_symbol(caller, DB_STGY_ANY, &diff); + db_symbol_values(sym, &symname, 0); + if (symname == NULL || !strcmp(symname, "end")) + (*pr)("at %p", caller); + else + (*pr)("at %s+%#x", symname, diff); + if (full) + /* Print all the args stored in that stackframe. */ + (*pr)("(%lx, %lx, %lx, %lx, %lx, %lx, %lx, %lx)", + args[0], args[1], args[2], args[3], + args[4], args[5], args[6], args[7]); + (*pr)("\n"); + } +} + +void +db_stack_trace_cmd(db_expr_t addr, boolean_t have_addr, db_expr_t count, + char *modif) +{ + + db_stack_trace_print(addr, have_addr, count, modif, db_printf); +} + diff --git a/sys/powerpc/powerpc/machdep.c b/sys/powerpc/powerpc/machdep.c index 7a7712423e04..17836fae6f71 100644 --- a/sys/powerpc/powerpc/machdep.c +++ b/sys/powerpc/powerpc/machdep.c @@ -372,6 +372,10 @@ powerpc_init(u_int startkernel, u_int endkernel, u_int basekernel, void *mdp) printf("powerpc_init: no loader metadata.\n"); } +#ifdef DDB + kdb_init(); +#endif + /* * XXX: Initialize the interrupt tables. */