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On amd64, enable workarounds for several Ryzen erratas as described in

Browse Source 
the AMD document 55449 'Revision Guide for AMD Family 17h Models
00h-0Fh Processors' rev 1.12.

The errata numbers are mentioned near each action.

It seems that newer BIOSes already include required chicken bits
settings, so the magic MSR updates are only needed when BIOS cannot be
updated.  On the other hand, MWAIT avoidance seems to be important.

Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
This commit is contained in:
Konstantin Belousov 2018-07-27 15:31:20 +00:00
parent 029a2d652e
commit 45ed991d96
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=336763
2 changed files with 31 additions and 0 deletions
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24
sys/amd64/amd64/initcpu.c
View File

@ -130,6 +130,30 @@ init_amd(void)
}
}
/* Ryzen erratas. */
if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1 &&
(cpu_feature2 & CPUID2_HV) == 0) {
/* 1021 */
msr = rdmsr(0xc0011029);
msr |= 0x2000;
wrmsr(0xc0011029, msr);
/* 1033 */
msr = rdmsr(0xc0011020);
msr |= 0x10;
wrmsr(0xc0011020, msr);
/* 1049 */
msr = rdmsr(0xc0011028);
msr |= 0x10;
wrmsr(0xc0011028, msr);
/* 1095 */
msr = rdmsr(0xc0011020);
msr |= 0x200000000000000;
wrmsr(0xc0011020, msr);
}
/*
* Work around a problem on Ryzen that is triggered by executing
* code near the top of user memory, in our case the signal

7
sys/x86/x86/cpu_machdep.c
View File

@ -709,6 +709,13 @@ cpu_idle_tun(void *unused __unused)
if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
cpu_idle_selector(tunvar);
else if (cpu_vendor_id == CPU_VENDOR_AMD &&
CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
/* Ryzen erratas 1057, 1109. */
cpu_idle_selector("hlt");
idle_mwait = 0;
}
if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
/*
* Apollo Lake errata APL31 (public errata APL30).