On amd64, enable workarounds for several Ryzen erratas as described in
the AMD document 55449 'Revision Guide for AMD Family 17h Models 00h-0Fh Processors' rev 1.12. The errata numbers are mentioned near each action. It seems that newer BIOSes already include required chicken bits settings, so the magic MSR updates are only needed when BIOS cannot be updated. On the other hand, MWAIT avoidance seems to be important. Sponsored by: The FreeBSD Foundation MFC after: 1 week
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=336763
@ -130,6 +130,30 @@ init_amd(void)
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}
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}
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/* Ryzen erratas. */
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if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1 &&
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(cpu_feature2 & CPUID2_HV) == 0) {
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/* 1021 */
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msr = rdmsr(0xc0011029);
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msr |= 0x2000;
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wrmsr(0xc0011029, msr);
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/* 1033 */
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msr = rdmsr(0xc0011020);
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msr |= 0x10;
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wrmsr(0xc0011020, msr);
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/* 1049 */
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msr = rdmsr(0xc0011028);
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msr |= 0x10;
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wrmsr(0xc0011028, msr);
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/* 1095 */
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msr = rdmsr(0xc0011020);
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msr |= 0x200000000000000;
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wrmsr(0xc0011020, msr);
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}
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/*
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* Work around a problem on Ryzen that is triggered by executing
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* code near the top of user memory, in our case the signal
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@ -709,6 +709,13 @@ cpu_idle_tun(void *unused __unused)
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if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
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cpu_idle_selector(tunvar);
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else if (cpu_vendor_id == CPU_VENDOR_AMD &&
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CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
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/* Ryzen erratas 1057, 1109. */
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cpu_idle_selector("hlt");
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idle_mwait = 0;
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}
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if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
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/*
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* Apollo Lake errata APL31 (public errata APL30).
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