Unbreak Promise SATAII/150 controllers caused by the DMA dump changes.
This commit is contained in:
Søren Schmidt
parent
0a3a1935b3
commit
466be09c2a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=155479
@ -542,8 +542,8 @@ ata_boot_attach(void)
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/* release the hook that got us here, we are only needed once during boot */
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if (ata_delayed_attach) {
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config_intrhook_disestablish(ata_delayed_attach);
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ata_delayed_attach = NULL;
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free(ata_delayed_attach, M_TEMP);
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ata_delayed_attach = NULL;
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}
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mtx_unlock(&Giant); /* newbus suckage dealt with, release Giant */
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@ -413,7 +413,6 @@ struct ata_device {
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struct ata_params param; /* ata param structure */
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int mode; /* current transfermode */
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u_int32_t max_iosize; /* max IO size */
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int cmd; /* last cmd executed */
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int flags;
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#define ATA_D_USE_CHS 0x0001
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#define ATA_D_MEDIA_CHANGED 0x0002
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@ -2861,10 +2861,10 @@ ata_promise_ident(device_t dev)
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{ ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
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{ ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
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{ ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
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{ ATA_PDC20571, 0, PRMIO, PRSATA2, ATA_SA150, "PDC20571" },
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{ ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
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{ ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
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{ ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
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{ ATA_PDC20771, 0, PRMIO, PRSATA2, ATA_SA300, "PDC20771" },
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{ ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
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{ ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
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{ ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
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{ ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
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@ -2925,6 +2925,7 @@ static int
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ata_promise_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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int fake_reg, stat_reg;
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if (ata_setup_interrupt(dev))
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return ENXIO;
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@ -2962,8 +2963,7 @@ ata_promise_chipinit(device_t dev)
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&ctlr->r_rid2, RF_ACTIVE)))
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goto failnfree;
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switch (ctlr->chip->cfg2) {
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case PRSX4X: {
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if (ctlr->chip->cfg2 == PRSX4X) {
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struct ata_promise_sx4 *hpkt;
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u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
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@ -2998,58 +2998,55 @@ ata_promise_chipinit(device_t dev)
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ctlr->setmode = ata_promise_setmode;
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ctlr->channels = 4;
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return 0;
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}
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case PRPATA:
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case PRCMBO:
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case PRSATA:
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/*
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* older "mio" type controllers need an interrupt intercept
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* function to compensate for the "reset on read" type interrupt
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* status register they have.
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*/
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if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
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}
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/* mio type controllers need an interrupt intercept */
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if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
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bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
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ata_promise_mio_intr, ctlr, &ctlr->handle)) {
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device_printf(dev, "unable to setup interrupt\n");
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goto failnfree;
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}
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/* prime fake interrupt register */
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ATA_OUTL(ctlr->r_res2, 0x060, 0xffffffff);
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}
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switch (ctlr->chip->cfg2) {
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case PRPATA:
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ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
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((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
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goto sata150;
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case PRCMBO:
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ctlr->channels = 3;
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goto sata150;
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case PRSATA:
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ctlr->channels = 4;
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sata150:
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fake_reg = 0x60;
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stat_reg = 0x6c;
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break;
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case PRCMBO2:
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ctlr->channels = 3;
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goto sataii;
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case PRSATA2:
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default:
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ctlr->channels = 4;
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sataii:
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fake_reg = 0x54;
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stat_reg = 0x60;
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break;
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}
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/* prime fake interrupt register */
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ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
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/* clear SATA status */
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ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
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ctlr->allocate = ata_promise_mio_allocate;
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ctlr->reset = ata_promise_mio_reset;
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ctlr->dmainit = ata_promise_mio_dmainit;
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ctlr->setmode = ata_promise_mio_setmode;
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switch (ctlr->chip->cfg2) {
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case PRPATA:
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ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
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((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
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return 0;
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case PRCMBO:
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ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
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ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 3;
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return 0;
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case PRSATA:
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ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
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ctlr->channels = 4;
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return 0;
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case PRCMBO2:
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ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
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ctlr->channels = 3;
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return 0;
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case PRSATA2:
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ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
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ctlr->channels = 4;
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return 0;
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}
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return 0;
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}
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failnfree:
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@ -3297,7 +3294,21 @@ ata_promise_mio_intr(void *data)
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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int unit;
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u_int32_t vector;
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int unit, fake_reg;
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switch (ctlr->chip->cfg2) {
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case PRPATA:
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case PRCMBO:
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case PRSATA:
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fake_reg = 0x60;
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break;
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case PRCMBO2:
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case PRSATA2:
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default:
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fake_reg = 0x54;
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break;
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}
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/*
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* since reading interrupt status register on early "mio" chips
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@ -3306,13 +3317,16 @@ ata_promise_mio_intr(void *data)
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* store the bits in an unused register in the chip so we can read
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* it from there safely to get around this "feature".
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*/
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ATA_OUTL(ctlr->r_res2, 0x060, ATA_INL(ctlr->r_res2, 0x040));
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vector = ATA_INL(ctlr->r_res2, 0x040);
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ATA_OUTL(ctlr->r_res2, 0x040, vector);
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ATA_OUTL(ctlr->r_res2, fake_reg, vector);
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for (unit = 0; unit < ctlr->channels; unit++) {
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if ((ch = ctlr->interrupt[unit].argument))
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ctlr->interrupt[unit].function(ch);
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}
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ATA_OUTL(ctlr->r_res2, 0x060, 0xffffffff);
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ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
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}
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static int
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@ -3321,37 +3335,30 @@ ata_promise_mio_status(device_t dev)
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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struct ata_connect_task *tp;
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u_int32_t vector, status;
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u_int32_t fake_reg, stat_reg, vector, status;
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switch (ctlr->chip->cfg2) {
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case PRPATA:
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case PRSATA:
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case PRCMBO:
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/* read and acknowledge interrupt */
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vector = ATA_INL(ctlr->r_res2, 0x0060);
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/* read and clear interface status */
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status = ATA_INL(ctlr->r_res2, 0x006c);
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ATA_OUTL(ctlr->r_res2, 0x006c, status & (0x00000011 << ch->unit));
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case PRSATA:
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fake_reg = 0x60;
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stat_reg = 0x6c;
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break;
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case PRCMBO2:
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case PRSATA2:
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case PRCMBO2:
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critical_enter();
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/* read and acknowledge interrupt */
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vector = ATA_INL(ctlr->r_res2, 0x0040);
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ATA_OUTL(ctlr->r_res2, 0x0040, (1 << (ch->unit + 1)));
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/* read and clear interface status */
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status = ATA_INL(ctlr->r_res2, 0x0060);
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ATA_OUTL(ctlr->r_res2, 0x0060, status & (0x00000011 << ch->unit));
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critical_exit();
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break;
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default:
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return 0;
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fake_reg = 0x54;
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stat_reg = 0x60;
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break;
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}
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/* read and acknowledge interrupt */
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vector = ATA_INL(ctlr->r_res2, fake_reg);
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/* read and clear interface status */
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status = ATA_INL(ctlr->r_res2, stat_reg);
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ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
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/* check for and handle disconnect events */
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if ((status & (0x00000001 << ch->unit)) &&
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(tp = (struct ata_connect_task *)
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