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Decode all Arm GIC feature ID bits

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The AWS Graviton3 CPU features a GIC 4.1 CPU Interface. Teach the CPU
identift code to decode it.

Sponsored by:	The FreeBSD Foundation
This commit is contained in:
Andrew Turner 2022-05-24 11:03:13 +01:00
parent 969da7c749
commit 477204e70b
2 changed files with 4 additions and 0 deletions
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3
sys/arm64/arm64/identcpu.c
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@ -1127,6 +1127,9 @@ static struct mrs_field_value id_aa64pfr0_ras[] = {
static struct mrs_field_value id_aa64pfr0_gic[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN),
MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""),
MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"),
MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"),
MRS_FIELD_VALUE_END,
};

1
sys/arm64/include/armreg.h
View File

@ -891,6 +891,7 @@
#define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK)
#define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_RAS_SHIFT 28
#define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK)