TEGRA: Add basic driver for memory controller.
For now, it only reports memory and SMMU access errors.
This commit is contained in:
Michal Meloun
parent
bccf798278
commit
47a232c660
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=308286
@ -33,6 +33,7 @@ arm/nvidia/tegra_efuse.c standard
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arm/nvidia/tegra_soctherm_if.m standard
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arm/nvidia/tegra_soctherm.c standard
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arm/nvidia/tegra_lic.c standard
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arm/nvidia/tegra_mc.c standard
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#arm/nvidia/tegra_hda.c optional snd_hda
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#arm/nvidia/drm2/hdmi.c optional drm2
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#arm/nvidia/drm2/tegra_drm_if.m optional drm2
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311
sys/arm/nvidia/tegra_mc.c
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311
sys/arm/nvidia/tegra_mc.c
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@ -0,0 +1,311 @@
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/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Memory controller driver for Tegra SoCs.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "clock_if.h"
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#define MC_INTSTATUS 0x000
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#define MC_INTMASK 0x004
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#define MC_INT_DECERR_MTS (1 << 16)
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#define MC_INT_SECERR_SEC (1 << 13)
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#define MC_INT_DECERR_VPR (1 << 12)
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#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
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#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
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#define MC_INT_ARBITRATION_EMEM (1 << 9)
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#define MC_INT_SECURITY_VIOLATION (1 << 8)
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#define MC_INT_DECERR_EMEM (1 << 6)
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#define MC_INT_INT_MASK (MC_INT_DECERR_MTS | \
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MC_INT_SECERR_SEC | \
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MC_INT_DECERR_VPR | \
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MC_INT_INVALID_APB_ASID_UPDATE | \
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MC_INT_INVALID_SMMU_PAGE | \
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MC_INT_ARBITRATION_EMEM | \
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MC_INT_SECURITY_VIOLATION | \
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MC_INT_DECERR_EMEM)
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#define MC_ERR_STATUS 0x008
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#define MC_ERR_TYPE(x) (((x) >> 28) & 0x7)
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#define MC_ERR_TYPE_DECERR_EMEM 2
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#define MC_ERR_TYPE_SECURITY_TRUSTZONE 3
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#define MC_ERR_TYPE_SECURITY_CARVEOUT 4
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#define MC_ERR_TYPE_INVALID_SMMU_PAGE 6
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#define MC_ERR_INVALID_SMMU_PAGE_READABLE (1 << 27)
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#define MC_ERR_INVALID_SMMU_PAGE_WRITABLE (1 << 26)
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#define MC_ERR_INVALID_SMMU_PAGE_NONSECURE (1 << 25)
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#define MC_ERR_ADR_HI(x) (((x) >> 20) & 0x3)
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#define MC_ERR_SWAP (1 << 18)
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#define MC_ERR_SECURITY (1 << 17)
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#define MC_ERR_RW (1 << 16)
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#define MC_ERR_ADR1(x) (((x) >> 12) & 0x7)
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#define MC_ERR_ID(x) (((x) >> 0) & 07F)
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#define MC_ERR_ADDR 0x00C
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#define MC_EMEM_CFG 0x050
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#define MC_EMEM_ADR_CFG 0x054
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#define MC_EMEM_NUMDEV(x) (((x) >> 0 ) & 0x1)
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#define MC_EMEM_ADR_CFG_DEV0 0x058
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#define MC_EMEM_ADR_CFG_DEV1 0x05C
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#define EMEM_DEV_DEVSIZE(x) (((x) >> 16) & 0xF)
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#define EMEM_DEV_BANKWIDTH(x) (((x) >> 8) & 0x3)
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#define EMEM_DEV_COLWIDTH(x) (((x) >> 8) & 0x3)
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#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
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#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
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#define LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define SLEEP(_sc, timeout) mtx_sleep(sc, &sc->mtx, 0, "tegra_mc", timeout);
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#define LOCK_INIT(_sc) \
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mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_mc", MTX_DEF)
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#define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx)
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#define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED)
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#define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED)
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-mc", 1},
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{NULL, 0}
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};
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struct tegra_mc_softc {
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device_t dev;
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struct mtx mtx;
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struct resource *mem_res;
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struct resource *irq_res;
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void *irq_h;
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clk_t clk;
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};
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static char *smmu_err_tbl[16] = {
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"reserved", /* 0 */
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"reserved", /* 1 */
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"DRAM decode", /* 2 */
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"Trustzome Security", /* 3 */
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"Security carveout", /* 4 */
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"reserved", /* 5 */
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"Invalid SMMU page", /* 6 */
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"reserved", /* 7 */
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};
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static void
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tegra_mc_intr(void *arg)
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{
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struct tegra_mc_softc *sc;
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uint32_t stat, err;
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uint64_t addr;
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sc = (struct tegra_mc_softc *)arg;
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stat = RD4(sc, MC_INTSTATUS);
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if ((stat & MC_INT_INT_MASK) == 0) {
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WR4(sc, MC_INTSTATUS, stat);
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return;
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}
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device_printf(sc->dev, "Memory Controller Interrupt:\n");
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if (stat & MC_INT_DECERR_MTS)
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printf(" - MTS carveout violation\n");
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if (stat & MC_INT_SECERR_SEC)
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printf(" - SEC carveout violation\n");
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if (stat & MC_INT_DECERR_VPR)
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printf(" - VPR requirements violated\n");
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if (stat & MC_INT_INVALID_APB_ASID_UPDATE)
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printf(" - ivalid APB ASID update\n");
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if (stat & MC_INT_INVALID_SMMU_PAGE)
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printf(" - SMMU address translation error\n");
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if (stat & MC_INT_ARBITRATION_EMEM)
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printf(" - arbitration deadlock-prevention threshold hit\n");
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if (stat & MC_INT_SECURITY_VIOLATION)
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printf(" - SMMU address translation security error\n");
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if (stat & MC_INT_DECERR_EMEM)
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printf(" - SMMU address decode error\n");
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if ((stat & (MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
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MC_INT_DECERR_EMEM)) != 0) {
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err = RD4(sc, MC_ERR_STATUS);
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addr = RD4(sc, MC_ERR_STATUS);
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addr |= (uint64_t)(MC_ERR_ADR_HI(err)) << 32;
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printf(" at 0x%012llX [%s %s %s] - %s error.\n",
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addr,
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stat & MC_ERR_SWAP ? "Swap, " : "",
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stat & MC_ERR_SECURITY ? "Sec, " : "",
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stat & MC_ERR_RW ? "Write" : "Read",
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smmu_err_tbl[MC_ERR_TYPE(err)]);
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}
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WR4(sc, MC_INTSTATUS, stat);
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}
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static void
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tegra_mc_init_hw(struct tegra_mc_softc *sc)
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{
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/* Disable and acknowledge all interrupts */
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WR4(sc, MC_INTMASK, 0);
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WR4(sc, MC_INTSTATUS, MC_INT_INT_MASK);
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}
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static int
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tegra_mc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Tegra Memory Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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tegra_mc_attach(device_t dev)
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{
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int rv, rid;
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struct tegra_mc_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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LOCK_INIT(sc);
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/* Get the memory resource for the register mapping. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Cannot map registers.\n");
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rv = ENXIO;
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goto fail;
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}
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/* Allocate our IRQ resource. */
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "Cannot allocate interrupt.\n");
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rv = ENXIO;
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goto fail;
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}
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/* OFW resources. */
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rv = clk_get_by_ofw_name(dev, 0, "mc", &sc->clk);
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if (rv != 0) {
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device_printf(dev, "Cannot get mc clock: %d\n", rv);
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goto fail;
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}
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rv = clk_enable(sc->clk);
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if (rv != 0) {
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device_printf(dev, "Cannot enable clock: %d\n", rv);
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goto fail;
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}
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/* Init hardware. */
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tegra_mc_init_hw(sc);
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/* Setup interrupt */
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rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, tegra_mc_intr, sc, &sc->irq_h);
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if (rv) {
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device_printf(dev, "Cannot setup interrupt.\n");
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goto fail;
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}
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/* Enable Interrupts */
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WR4(sc, MC_INTMASK, MC_INT_INT_MASK);
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return (bus_generic_attach(dev));
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fail:
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if (sc->clk != NULL)
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clk_release(sc->clk);
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if (sc->irq_h != NULL)
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bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
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if (sc->irq_res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
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LOCK_DESTROY(sc);
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return (rv);
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}
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static int
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tegra_mc_detach(device_t dev)
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{
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struct tegra_mc_softc *sc;
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sc = device_get_softc(dev);
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if (sc->irq_h != NULL)
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bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
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if (sc->irq_res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
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LOCK_DESTROY(sc);
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return (bus_generic_detach(dev));
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}
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static device_method_t tegra_mc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, tegra_mc_probe),
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DEVMETHOD(device_attach, tegra_mc_attach),
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DEVMETHOD(device_detach, tegra_mc_detach),
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DEVMETHOD_END
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};
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static devclass_t tegra_mc_devclass;
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static DEFINE_CLASS_0(mc, tegra_mc_driver, tegra_mc_methods,
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sizeof(struct tegra_mc_softc));
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DRIVER_MODULE(tegra_mc, simplebus, tegra_mc_driver, tegra_mc_devclass,
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NULL, NULL);
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