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A little more cleanup from AMD, if we don't have the right microcode

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there is no reason to mess with the chip.

MFC after:	3 days
This commit is contained in:
Robert Noland 2009-04-03 19:21:39 +00:00
parent c8da4f07d7
commit 47c63e764d
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=190674
2 changed files with 37 additions and 38 deletions
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68
sys/dev/drm/r600_cp.c
View File

@ -286,20 +286,6 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
const u32 *pfp;
int i;
r600_do_cp_stop(dev_priv);
RADEON_WRITE(R600_CP_RB_CNTL,
R600_RB_NO_UPDATE |
R600_RB_BLKSZ(15) |
R600_RB_BUFSZ(3));
RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
RADEON_READ(R600_GRBM_SOFT_RESET);
DRM_UDELAY(15000);
RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
switch (dev_priv->flags & RADEON_FAMILY_MASK) {
case CHIP_R600:
DRM_INFO("Loading R600 Microcode\n");
@ -337,19 +323,32 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
pfp = RS780_pfp_microcode;
break;
default:
goto no_microcode;
return;
}
for (i = 0; i != PM4_UCODE_SIZE; i++) {
r600_do_cp_stop(dev_priv);
RADEON_WRITE(R600_CP_RB_CNTL,
R600_RB_NO_UPDATE |
R600_RB_BLKSZ(15) |
R600_RB_BUFSZ(3));
RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
RADEON_READ(R600_GRBM_SOFT_RESET);
DRM_UDELAY(15000);
RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
for (i = 0; i < PM4_UCODE_SIZE; i++) {
RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
}
RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
for (i = 0; i != PFP_UCODE_SIZE; i++)
for (i = 0; i < PFP_UCODE_SIZE; i++)
RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
no_microcode:;
RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
@ -415,21 +414,9 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
const u32 *cp;
int i;
r600_do_cp_stop(dev_priv);
RADEON_WRITE(R600_CP_RB_CNTL,
R600_RB_NO_UPDATE |
(15 << 8) |
(3 << 0));
RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
RADEON_READ(R600_GRBM_SOFT_RESET);
DRM_UDELAY(15000);
RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
switch (dev_priv->flags & RADEON_FAMILY_MASK) {
case CHIP_RV770:
DRM_INFO("Loading RV770 Microcode\n");
DRM_INFO("Loading RV770/RV790 Microcode\n");
pfp = RV770_pfp_microcode;
cp = RV770_cp_microcode;
break;
@ -444,19 +431,30 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
cp = RV710_cp_microcode;
break;
default:
goto no_microcode;
return;
}
r600_do_cp_stop(dev_priv);
RADEON_WRITE(R600_CP_RB_CNTL,
R600_RB_NO_UPDATE |
(15 << 8) |
(3 << 0));
RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
RADEON_READ(R600_GRBM_SOFT_RESET);
DRM_UDELAY(15000);
RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
for (i = 0; i != R700_PFP_UCODE_SIZE; i++)
for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
for (i = 0; i != R700_PM4_UCODE_SIZE; i++)
for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
no_microcode:;
RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);

7
sys/dev/drm/radeon_cp.c
View File

@ -460,9 +460,6 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
DRM_DEBUG("\n");
radeon_do_wait_for_idle(dev_priv);
RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
switch (dev_priv->flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV100:
@ -516,6 +513,10 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
return;
}
radeon_do_wait_for_idle(dev_priv);
RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
for (i = 0; i != 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);