drm/i915: Reduce diff with Linux 3.8
There is no functional change. The goal is to ease the future update to Linux 3.8's i915 driver. MFC after: 2 months
This commit is contained in:
Jean-Sébastien Pédron
parent
f1d04a2543
commit
48332b1c7a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=290070
@ -42,6 +42,44 @@ __FBSDID("$FreeBSD$");
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#include "fb_if.h"
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int intel_iommu_enabled = 0;
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TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
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int intel_iommu_gfx_mapped = 0;
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TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
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int i915_prefault_disable;
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TUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable);
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int i915_semaphores = -1;
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TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
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static int i915_try_reset = 1;
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TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
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unsigned int i915_lvds_downclock = 0;
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TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
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int i915_vbt_sdvo_panel_type = -1;
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TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
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unsigned int i915_powersave = 1;
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TUNABLE_INT("drm.i915.powersave", &i915_powersave);
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int i915_enable_fbc = 0;
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TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
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int i915_enable_rc6 = 0;
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TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
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int i915_lvds_channel_mode;
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TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
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int i915_panel_use_ssc = -1;
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TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
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int i915_panel_ignore_lid = 0;
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TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
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int i915_panel_invert_brightness;
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TUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness);
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int i915_modeset = 1;
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TUNABLE_INT("drm.i915.modeset", &i915_modeset);
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int i915_enable_ppgtt = -1;
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TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
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int i915_enable_hangcheck = 1;
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TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
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static int i915_enable_unsupported = 0;
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TUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported);
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/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
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static drm_pci_id_list_t i915_pciidlist[] = {
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i915_PCI_IDS
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@ -229,7 +267,7 @@ static const struct intel_device_info intel_haswell_m_info = {
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static const struct intel_gfx_device_id {
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int device;
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const struct intel_device_info *info;
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} pciidlist[] = { /* aka */
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} i915_infolist[] = { /* aka */
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INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
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INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
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INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
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@ -316,7 +354,61 @@ static const struct intel_gfx_device_id {
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{0, 0}
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};
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static int i915_enable_unsupported;
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#define PCI_VENDOR_INTEL 0x8086
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#define INTEL_PCH_DEVICE_ID_MASK 0xff00
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#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
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#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
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#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
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#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
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void intel_detect_pch(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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device_t pch;
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uint32_t id;
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pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
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if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
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id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
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if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_IBX;
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dev_priv->num_pch_pll = 2;
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DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
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} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_CPT;
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dev_priv->num_pch_pll = 2;
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DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
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/* PantherPoint is CPT compatible */
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dev_priv->pch_type = PCH_CPT;
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dev_priv->num_pch_pll = 2;
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DRM_DEBUG_KMS("Found PatherPoint PCH\n");
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} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_LPT;
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dev_priv->num_pch_pll = 0;
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DRM_DEBUG_KMS("Found LynxPoint PCH\n");
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} else
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DRM_DEBUG_KMS("No PCH detected\n");
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KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
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("num_pch_pll %d\n", dev_priv->num_pch_pll));
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} else
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DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
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}
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bool i915_semaphore_is_enabled(struct drm_device *dev)
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{
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if (INTEL_INFO(dev)->gen < 6)
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return 0;
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if (i915_semaphores >= 0)
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return i915_semaphores;
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/* Enable semaphores on SNB when IO remapping is off */
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if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
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return false;
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return 1;
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}
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static int i915_drm_freeze(struct drm_device *dev)
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{
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@ -355,7 +447,7 @@ static int i915_suspend(device_t kdev)
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int error;
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dev = device_get_softc(kdev);
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if (dev == NULL || dev->dev_private == NULL) {
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if (!dev || !dev->dev_private) {
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DRM_ERROR("DRM not initialized, aborting suspend.\n");
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return ENODEV;
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}
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@ -363,7 +455,7 @@ static int i915_suspend(device_t kdev)
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DRM_DEBUG_KMS("starting suspend\n");
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error = i915_drm_freeze(dev);
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if (error)
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return (-error);
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return -error;
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error = bus_generic_suspend(kdev);
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DRM_DEBUG_KMS("finished suspend %d\n", error);
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@ -429,8 +521,8 @@ static int i915_resume(device_t kdev)
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#endif
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ret = i915_drm_thaw(dev);
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if (ret != 0)
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return (-ret);
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if (ret)
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return -ret;
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drm_kms_helper_poll_enable(dev);
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ret = bus_generic_resume(kdev);
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@ -438,25 +530,286 @@ static int i915_resume(device_t kdev)
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return (ret);
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}
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static int
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i915_probe(device_t kdev)
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static int i8xx_do_reset(struct drm_device *dev)
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{
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const struct intel_device_info *info;
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int error;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int onems;
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error = drm_probe_helper(kdev, i915_pciidlist);
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if (error != 0)
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return (-error);
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info = i915_get_device_id(pci_get_device(kdev));
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if (info == NULL)
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return (ENXIO);
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return (0);
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if (IS_I85X(dev))
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return -ENODEV;
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onems = hz / 1000;
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if (onems == 0)
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onems = 1;
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I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
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POSTING_READ(D_STATE);
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if (IS_I830(dev) || IS_845G(dev)) {
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I915_WRITE(DEBUG_RESET_I830,
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DEBUG_RESET_DISPLAY |
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DEBUG_RESET_RENDER |
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DEBUG_RESET_FULL);
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POSTING_READ(DEBUG_RESET_I830);
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pause("i8xxrst1", onems);
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I915_WRITE(DEBUG_RESET_I830, 0);
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POSTING_READ(DEBUG_RESET_I830);
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}
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pause("i8xxrst2", onems);
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I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
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POSTING_READ(D_STATE);
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return 0;
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}
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int i915_modeset;
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static int i965_reset_complete(struct drm_device *dev)
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{
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u8 gdrst;
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static int
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i915_attach(device_t kdev)
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gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
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return (gdrst & GRDOM_RESET_ENABLE) == 0;
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}
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static int i965_do_reset(struct drm_device *dev)
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{
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int ret;
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u8 gdrst;
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/*
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* Set the domains we want to reset (GRDOM/bits 2 and 3) as
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* well as the reset bit (GR/bit 0). Setting the GR bit
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* triggers the reset; when done, the hardware will clear it.
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*/
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gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
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pci_write_config(dev->dev, I965_GDRST,
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gdrst | GRDOM_RENDER |
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GRDOM_RESET_ENABLE, 1);
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ret = wait_for(i965_reset_complete(dev), 500);
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if (ret)
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return ret;
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/* We can't reset render&media without also resetting display ... */
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gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
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pci_write_config(dev->dev, I965_GDRST,
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gdrst | GRDOM_MEDIA |
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GRDOM_RESET_ENABLE, 1);
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return wait_for(i965_reset_complete(dev), 500);
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}
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static int ironlake_do_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 gdrst;
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int ret;
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gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
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I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
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gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
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ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
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if (ret)
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return ret;
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/* We can't reset render&media without also resetting display ... */
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gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
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I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
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gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
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return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
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}
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static int gen6_do_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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/* Hold gt_lock across reset to prevent any register access
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* with forcewake not set correctly
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*/
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mtx_lock(&dev_priv->gt_lock);
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/* Reset the chip */
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/* GEN6_GDRST is not in the gt power well, no need to check
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* for fifo space for the write or forcewake the chip for
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* the read
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*/
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I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
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/* Spin waiting for the device to ack the reset request */
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ret = _intel_wait_for(dev,
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(I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
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500, 0, "915rst");
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/* If reset with a user forcewake, try to restore, otherwise turn it off */
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if (dev_priv->forcewake_count)
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dev_priv->display.force_wake_get(dev_priv);
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else
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dev_priv->display.force_wake_put(dev_priv);
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/* Restore fifo count */
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dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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mtx_unlock(&dev_priv->gt_lock);
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return ret;
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}
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int intel_gpu_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret = -ENODEV;
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switch (INTEL_INFO(dev)->gen) {
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case 7:
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case 6:
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ret = gen6_do_reset(dev);
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break;
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case 5:
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ret = ironlake_do_reset(dev);
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break;
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case 4:
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ret = i965_do_reset(dev);
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break;
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case 2:
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ret = i8xx_do_reset(dev);
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break;
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}
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/* Also reset the gpu hangman. */
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if (dev_priv->stop_rings) {
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DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
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dev_priv->stop_rings = 0;
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if (ret == -ENODEV) {
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DRM_ERROR("Reset not implemented, but ignoring "
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"error for simulated gpu hangs\n");
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ret = 0;
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}
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}
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return ret;
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}
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/**
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* i915_reset - reset chip after a hang
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* @dev: drm device to reset
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*
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* Reset the chip. Useful if a hang is detected. Returns zero on successful
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* reset or otherwise an error code.
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*
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* Procedure is fairly simple:
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* - reset the chip using the reset reg
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* - re-init context state
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* - re-init hardware status page
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* - re-init ring buffer
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* - re-init interrupt state
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* - re-init display
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*/
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int i915_reset(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int ret;
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if (!i915_try_reset)
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return 0;
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if (!sx_try_xlock(&dev->dev_struct_lock))
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return (-EBUSY);
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dev_priv->stop_rings = 0;
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i915_gem_reset(dev);
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ret = -ENODEV;
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if (time_second - dev_priv->last_gpu_reset < 5)
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DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
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else
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ret = intel_gpu_reset(dev);
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dev_priv->last_gpu_reset = time_second;
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if (ret) {
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DRM_ERROR("Failed to reset chip.\n");
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DRM_UNLOCK(dev);
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return ret;
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}
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/* Ok, now get things going again... */
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/*
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* Everything depends on having the GTT running, so we need to start
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* there. Fortunately we don't need to do this unless we reset the
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* chip at a PCI level.
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*
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* Next we need to restore the context, but we don't use those
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* yet either...
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*
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* Ring buffer needs to be re-initialized in the KMS case, or if X
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* was running at the time of the reset (i.e. we weren't VT
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* switched away).
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*/
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if (drm_core_check_feature(dev, DRIVER_MODESET) ||
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!dev_priv->mm.suspended) {
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struct intel_ring_buffer *ring;
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int i;
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dev_priv->mm.suspended = 0;
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i915_gem_init_swizzling(dev);
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for_each_ring(ring, dev_priv, i)
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ring->init(ring);
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i915_gem_context_init(dev);
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i915_gem_init_ppgtt(dev);
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/*
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* It would make sense to re-init all the other hw state, at
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* least the rps/rc6/emon init done within modeset_init_hw. For
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* some unknown reason, this blows up my ilk, so don't.
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*/
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DRM_UNLOCK(dev);
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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intel_modeset_init_hw(dev);
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drm_irq_uninstall(dev);
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drm_irq_install(dev);
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} else {
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DRM_UNLOCK(dev);
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}
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return 0;
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}
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const struct intel_device_info *
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i915_get_device_id(int device)
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{
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const struct intel_gfx_device_id *did;
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for (did = &i915_infolist[0]; did->device != 0; did++) {
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if (did->device != device)
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continue;
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if (did->info->not_supported && !i915_enable_unsupported)
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return (NULL);
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return (did->info);
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}
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return (NULL);
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}
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static int i915_probe(device_t kdev)
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{
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const struct intel_device_info *intel_info =
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i915_get_device_id(pci_get_device(kdev));
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||||
|
||||
if (intel_info == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
return -drm_probe_helper(kdev, i915_pciidlist);
|
||||
}
|
||||
|
||||
static int i915_attach(device_t kdev)
|
||||
{
|
||||
|
||||
if (i915_modeset == 1)
|
||||
@ -483,21 +836,6 @@ i915_fb_helper_getinfo(device_t kdev)
|
||||
return (info);
|
||||
}
|
||||
|
||||
const struct intel_device_info *
|
||||
i915_get_device_id(int device)
|
||||
{
|
||||
const struct intel_gfx_device_id *did;
|
||||
|
||||
for (did = &pciidlist[0]; did->device != 0; did++) {
|
||||
if (did->device != device)
|
||||
continue;
|
||||
if (did->info->not_supported && !i915_enable_unsupported)
|
||||
return (NULL);
|
||||
return (did->info);
|
||||
}
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
static device_method_t i915_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, i915_probe),
|
||||
@ -527,99 +865,12 @@ MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
|
||||
MODULE_DEPEND(i915kms, iic, 1, 1, 1);
|
||||
MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
|
||||
|
||||
int intel_iommu_enabled = 0;
|
||||
TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
|
||||
int intel_iommu_gfx_mapped = 0;
|
||||
TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
|
||||
|
||||
int i915_prefault_disable;
|
||||
TUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable);
|
||||
int i915_semaphores = -1;
|
||||
TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
|
||||
static int i915_try_reset = 1;
|
||||
TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
|
||||
unsigned int i915_lvds_downclock = 0;
|
||||
TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
|
||||
int i915_vbt_sdvo_panel_type = -1;
|
||||
TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
|
||||
unsigned int i915_powersave = 1;
|
||||
TUNABLE_INT("drm.i915.powersave", &i915_powersave);
|
||||
int i915_enable_fbc = 0;
|
||||
TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
|
||||
int i915_enable_rc6 = 0;
|
||||
TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
|
||||
int i915_lvds_channel_mode;
|
||||
TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
|
||||
int i915_panel_use_ssc = -1;
|
||||
TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
|
||||
int i915_panel_ignore_lid = 0;
|
||||
TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
|
||||
int i915_panel_invert_brightness;
|
||||
TUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness);
|
||||
int i915_modeset = 1;
|
||||
TUNABLE_INT("drm.i915.modeset", &i915_modeset);
|
||||
int i915_enable_ppgtt = -1;
|
||||
TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
|
||||
int i915_enable_hangcheck = 1;
|
||||
TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
|
||||
TUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported);
|
||||
|
||||
#define PCI_VENDOR_INTEL 0x8086
|
||||
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
|
||||
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
|
||||
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
|
||||
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
|
||||
#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
|
||||
|
||||
void intel_detect_pch(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv;
|
||||
device_t pch;
|
||||
uint32_t id;
|
||||
|
||||
dev_priv = dev->dev_private;
|
||||
pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
|
||||
if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
|
||||
id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
|
||||
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
|
||||
dev_priv->pch_type = PCH_IBX;
|
||||
dev_priv->num_pch_pll = 2;
|
||||
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
|
||||
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
|
||||
dev_priv->pch_type = PCH_CPT;
|
||||
dev_priv->num_pch_pll = 2;
|
||||
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
|
||||
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
|
||||
/* PantherPoint is CPT compatible */
|
||||
dev_priv->pch_type = PCH_CPT;
|
||||
dev_priv->num_pch_pll = 2;
|
||||
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
|
||||
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
|
||||
dev_priv->pch_type = PCH_LPT;
|
||||
dev_priv->num_pch_pll = 0;
|
||||
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
|
||||
} else
|
||||
DRM_DEBUG_KMS("No PCH detected\n");
|
||||
KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
|
||||
("num_pch_pll %d\n", dev_priv->num_pch_pll));
|
||||
} else
|
||||
DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
|
||||
}
|
||||
|
||||
bool i915_semaphore_is_enabled(struct drm_device *dev)
|
||||
{
|
||||
if (INTEL_INFO(dev)->gen < 6)
|
||||
return 0;
|
||||
|
||||
if (i915_semaphores >= 0)
|
||||
return i915_semaphores;
|
||||
|
||||
/* Enable semaphores on SNB when IO remapping is off */
|
||||
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
|
||||
return false;
|
||||
|
||||
return 1;
|
||||
}
|
||||
/* We give fast paths for the really cool registers */
|
||||
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
|
||||
(((dev_priv)->info->gen >= 6) && \
|
||||
((reg) < 0x40000) && \
|
||||
((reg) != FORCEWAKE)) && \
|
||||
(!IS_VALLEYVIEW((dev_priv)->dev))
|
||||
|
||||
void
|
||||
__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
|
||||
@ -753,264 +1004,6 @@ void vlv_force_wake_put(struct drm_i915_private *dev_priv)
|
||||
POSTING_READ(FORCEWAKE_VLV);
|
||||
}
|
||||
|
||||
static int i8xx_do_reset(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int onems;
|
||||
|
||||
if (IS_I85X(dev))
|
||||
return -ENODEV;
|
||||
|
||||
onems = hz / 1000;
|
||||
if (onems == 0)
|
||||
onems = 1;
|
||||
|
||||
I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
|
||||
POSTING_READ(D_STATE);
|
||||
|
||||
if (IS_I830(dev) || IS_845G(dev)) {
|
||||
I915_WRITE(DEBUG_RESET_I830,
|
||||
DEBUG_RESET_DISPLAY |
|
||||
DEBUG_RESET_RENDER |
|
||||
DEBUG_RESET_FULL);
|
||||
POSTING_READ(DEBUG_RESET_I830);
|
||||
pause("i8xxrst1", onems);
|
||||
|
||||
I915_WRITE(DEBUG_RESET_I830, 0);
|
||||
POSTING_READ(DEBUG_RESET_I830);
|
||||
}
|
||||
|
||||
pause("i8xxrst2", onems);
|
||||
|
||||
I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
|
||||
POSTING_READ(D_STATE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i965_reset_complete(struct drm_device *dev)
|
||||
{
|
||||
u8 gdrst;
|
||||
|
||||
gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
|
||||
return (gdrst & GRDOM_RESET_ENABLE) == 0;
|
||||
}
|
||||
|
||||
static int i965_do_reset(struct drm_device *dev)
|
||||
{
|
||||
int ret;
|
||||
u8 gdrst;
|
||||
|
||||
/*
|
||||
* Set the domains we want to reset (GRDOM/bits 2 and 3) as
|
||||
* well as the reset bit (GR/bit 0). Setting the GR bit
|
||||
* triggers the reset; when done, the hardware will clear it.
|
||||
*/
|
||||
gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
|
||||
pci_write_config(dev->dev, I965_GDRST,
|
||||
gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE, 1);
|
||||
|
||||
ret = wait_for(i965_reset_complete(dev), 500);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* We can't reset render&media without also resetting display ... */
|
||||
gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
|
||||
pci_write_config(dev->dev, I965_GDRST,
|
||||
gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE, 1);
|
||||
|
||||
return wait_for(i965_reset_complete(dev), 500);
|
||||
}
|
||||
|
||||
static int ironlake_do_reset(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
u32 gdrst;
|
||||
int ret;
|
||||
|
||||
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
|
||||
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
|
||||
gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
|
||||
ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* We can't reset render&media without also resetting display ... */
|
||||
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
|
||||
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
|
||||
gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
|
||||
return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
|
||||
}
|
||||
|
||||
static int gen6_do_reset(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
/* Hold gt_lock across reset to prevent any register access
|
||||
* with forcewake not set correctly
|
||||
*/
|
||||
mtx_lock(&dev_priv->gt_lock);
|
||||
|
||||
/* Reset the chip */
|
||||
|
||||
/* GEN6_GDRST is not in the gt power well, no need to check
|
||||
* for fifo space for the write or forcewake the chip for
|
||||
* the read
|
||||
*/
|
||||
I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
|
||||
|
||||
/* Spin waiting for the device to ack the reset request */
|
||||
ret = _intel_wait_for(dev,
|
||||
(I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
|
||||
500, 0, "915rst");
|
||||
|
||||
/* If reset with a user forcewake, try to restore, otherwise turn it off */
|
||||
if (dev_priv->forcewake_count)
|
||||
dev_priv->display.force_wake_get(dev_priv);
|
||||
else
|
||||
dev_priv->display.force_wake_put(dev_priv);
|
||||
|
||||
/* Restore fifo count */
|
||||
dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
|
||||
|
||||
mtx_unlock(&dev_priv->gt_lock);
|
||||
return (ret);
|
||||
}
|
||||
|
||||
int intel_gpu_reset(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int ret = -ENODEV;
|
||||
|
||||
switch (INTEL_INFO(dev)->gen) {
|
||||
case 7:
|
||||
case 6:
|
||||
ret = gen6_do_reset(dev);
|
||||
break;
|
||||
case 5:
|
||||
ret = ironlake_do_reset(dev);
|
||||
break;
|
||||
case 4:
|
||||
ret = i965_do_reset(dev);
|
||||
break;
|
||||
case 2:
|
||||
ret = i8xx_do_reset(dev);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Also reset the gpu hangman. */
|
||||
if (dev_priv->stop_rings) {
|
||||
DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
|
||||
dev_priv->stop_rings = 0;
|
||||
if (ret == -ENODEV) {
|
||||
DRM_ERROR("Reset not implemented, but ignoring "
|
||||
"error for simulated gpu hangs\n");
|
||||
ret = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i915_reset - reset chip after a hang
|
||||
* @dev: drm device to reset
|
||||
*
|
||||
* Reset the chip. Useful if a hang is detected. Returns zero on successful
|
||||
* reset or otherwise an error code.
|
||||
*
|
||||
* Procedure is fairly simple:
|
||||
* - reset the chip using the reset reg
|
||||
* - re-init context state
|
||||
* - re-init hardware status page
|
||||
* - re-init ring buffer
|
||||
* - re-init interrupt state
|
||||
* - re-init display
|
||||
*/
|
||||
int i915_reset(struct drm_device *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
if (!i915_try_reset)
|
||||
return 0;
|
||||
|
||||
if (!sx_try_xlock(&dev->dev_struct_lock))
|
||||
return (-EBUSY);
|
||||
|
||||
dev_priv->stop_rings = 0;
|
||||
|
||||
i915_gem_reset(dev);
|
||||
|
||||
ret = -ENODEV;
|
||||
if (time_second - dev_priv->last_gpu_reset < 5)
|
||||
DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
|
||||
else
|
||||
ret = intel_gpu_reset(dev);
|
||||
|
||||
dev_priv->last_gpu_reset = time_second;
|
||||
if (ret) {
|
||||
DRM_ERROR("Failed to reset chip.\n");
|
||||
DRM_UNLOCK(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Ok, now get things going again... */
|
||||
|
||||
/*
|
||||
* Everything depends on having the GTT running, so we need to start
|
||||
* there. Fortunately we don't need to do this unless we reset the
|
||||
* chip at a PCI level.
|
||||
*
|
||||
* Next we need to restore the context, but we don't use those
|
||||
* yet either...
|
||||
*
|
||||
* Ring buffer needs to be re-initialized in the KMS case, or if X
|
||||
* was running at the time of the reset (i.e. we weren't VT
|
||||
* switched away).
|
||||
*/
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET) ||
|
||||
!dev_priv->mm.suspended) {
|
||||
struct intel_ring_buffer *ring;
|
||||
int i;
|
||||
|
||||
dev_priv->mm.suspended = 0;
|
||||
|
||||
i915_gem_init_swizzling(dev);
|
||||
|
||||
for_each_ring(ring, dev_priv, i)
|
||||
ring->init(ring);
|
||||
|
||||
i915_gem_context_init(dev);
|
||||
i915_gem_init_ppgtt(dev);
|
||||
|
||||
/*
|
||||
* It would make sense to re-init all the other hw state, at
|
||||
* least the rps/rc6/emon init done within modeset_init_hw. For
|
||||
* some unknown reason, this blows up my ilk, so don't.
|
||||
*/
|
||||
DRM_UNLOCK(dev);
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
intel_modeset_init_hw(dev);
|
||||
|
||||
drm_irq_uninstall(dev);
|
||||
drm_irq_install(dev);
|
||||
} else {
|
||||
DRM_UNLOCK(dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* We give fast paths for the really cool registers */
|
||||
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
|
||||
(((dev_priv)->info->gen >= 6) && \
|
||||
((reg) < 0x40000) && \
|
||||
((reg) != FORCEWAKE)) && \
|
||||
(!IS_VALLEYVIEW((dev_priv)->dev))
|
||||
|
||||
#define __i915_read(x, y) \
|
||||
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
|
||||
u##x val = 0; \
|
||||
@ -1018,12 +1011,12 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
|
||||
mtx_lock(&dev_priv->gt_lock); \
|
||||
if (dev_priv->forcewake_count == 0) \
|
||||
dev_priv->display.force_wake_get(dev_priv); \
|
||||
val = DRM_READ##y(dev_priv->mmio_map, reg); \
|
||||
val = DRM_READ##x(dev_priv->mmio_map, reg); \
|
||||
if (dev_priv->forcewake_count == 0) \
|
||||
dev_priv->display.force_wake_put(dev_priv); \
|
||||
mtx_unlock(&dev_priv->gt_lock); \
|
||||
} else { \
|
||||
val = DRM_READ##y(dev_priv->mmio_map, reg); \
|
||||
val = DRM_READ##x(dev_priv->mmio_map, reg); \
|
||||
} \
|
||||
trace_i915_reg_rw(false, reg, val, sizeof(val)); \
|
||||
return val; \
|
||||
@ -1042,7 +1035,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
|
||||
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
|
||||
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
|
||||
} \
|
||||
DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
|
||||
DRM_WRITE##x(dev_priv->mmio_map, reg, val); \
|
||||
if (__predict_false(__fifo_ret)) { \
|
||||
gen6_gt_check_fifodbg(dev_priv); \
|
||||
} \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user