Add ARM Generic Timer driver.
Submitted by: Ruslan Bukin <br@bsdpad.com>
This commit is contained in:
Aleksandr Rybalko
parent
83bee1a9ba
commit
48d5dbc7a2
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=252372
374
sys/arm/arm/generic_timer.c
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374
sys/arm/arm/generic_timer.c
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/*-
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* Copyright (c) 2011 The FreeBSD Foundation
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* Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* Cortex-A15 (and probably A7) Generic Timer
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#define GENERIC_TIMER_CTRL_ENABLE (1 << 0)
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#define GENERIC_TIMER_CTRL_INT_MASK (1 << 1)
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#define GENERIC_TIMER_CTRL_INT_STAT (1 << 2)
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#define GENERIC_TIMER_REG_CTRL 0
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#define GENERIC_TIMER_REG_TVAL 1
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#define CNTPSIRQ 29
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struct arm_tmr_softc {
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struct resource *irq_res;
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uint32_t clkfreq;
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struct eventtimer et;
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};
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static struct arm_tmr_softc *arm_tmr_sc = NULL;
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static timecounter_get_t arm_tmr_get_timecount;
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static struct timecounter arm_tmr_timecount = {
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.tc_name = "ARM MPCore Timecounter",
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.tc_get_timecount = arm_tmr_get_timecount,
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.tc_poll_pps = NULL,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 1000,
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};
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static inline int
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get_freq(void)
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{
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uint32_t val;
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__asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
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return (val);
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}
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static inline int
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set_freq(uint32_t val)
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{
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__asm volatile("mcr p15, 0, %[val], c14, c0, 0" : :
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[val] "r" (val));
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isb();
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return (val);
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}
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static inline long
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get_cntpct(void)
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{
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uint64_t val;
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__asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val));
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return (val);
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}
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static inline int
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set_ctrl(uint32_t val)
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{
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__asm volatile("mcr p15, 0, %[val], c14, c2, 1" : :
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[val] "r" (val));
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isb();
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return (0);
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}
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static inline int
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set_tval(uint32_t val)
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{
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__asm volatile("mcr p15, 0, %[val], c14, c2, 0" : :
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[val] "r" (val));
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isb();
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return (0);
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}
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static inline int
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get_ctrl(void)
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{
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uint32_t val;
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__asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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return (val);
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}
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static inline int
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get_tval(void)
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{
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uint32_t val;
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__asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
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return (val);
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}
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static inline void
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disable_user_access(void)
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{
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uint32_t cntkctl;
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__asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
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cntkctl &= ~((3 << 8) | (7 << 0));
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__asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
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isb();
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}
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static unsigned
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arm_tmr_get_timecount(struct timecounter *tc)
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{
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return (get_cntpct());
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}
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static int
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arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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struct arm_tmr_softc *sc;
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int counts, ctrl;
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sc = (struct arm_tmr_softc *)et->et_priv;
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if (first != 0) {
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counts = ((uint32_t)et->et_frequency * first) >> 32;
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ctrl = get_ctrl();
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ctrl &= ~GENERIC_TIMER_CTRL_INT_MASK;
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ctrl |= GENERIC_TIMER_CTRL_ENABLE;
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set_tval(counts);
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set_ctrl(ctrl);
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return (0);
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}
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return (EINVAL);
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}
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static int
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arm_tmr_stop(struct eventtimer *et)
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{
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int ctrl;
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ctrl = get_ctrl();
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ctrl &= GENERIC_TIMER_CTRL_ENABLE;
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set_ctrl(ctrl);
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return (0);
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}
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static int
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arm_tmr_intr(void *arg)
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{
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struct arm_tmr_softc *sc;
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int ctrl;
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sc = (struct arm_tmr_softc *)arg;
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ctrl = get_ctrl();
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if (ctrl & GENERIC_TIMER_CTRL_INT_STAT) {
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ctrl |= GENERIC_TIMER_CTRL_INT_MASK;
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set_ctrl(ctrl);
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}
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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static int
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arm_tmr_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "arm,armv7-timer"))
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return (ENXIO);
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device_set_desc(dev, "ARMv7 Generic Timer");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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arm_tmr_attach(device_t dev)
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{
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struct arm_tmr_softc *sc;
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phandle_t node;
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pcell_t clock;
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void *ihl;
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int rid;
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int error;
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sc = device_get_softc(dev);
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if (arm_tmr_sc)
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return (ENXIO);
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/* Get the base clock frequency */
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node = ofw_bus_get_node(dev);
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error = OF_getprop(node, "clock-frequency", &clock, sizeof(clock));
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if (error <= 0) {
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device_printf(dev, "missing clock-frequency "
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"attribute in FDT\n");
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return (ENXIO);
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}
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sc->clkfreq = fdt32_to_cpu(clock);
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rid = 0;
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sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
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CNTPSIRQ, CNTPSIRQ, 1, RF_SHAREABLE | RF_ACTIVE);
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arm_tmr_sc = sc;
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/* Setup and enable the timer */
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if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK, arm_tmr_intr,
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NULL, sc, &ihl) != 0) {
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bus_release_resource(dev, SYS_RES_IRQ, rid, sc->irq_res);
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device_printf(dev, "Unable to setup the CLK irq handler.\n");
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return (ENXIO);
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}
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set_freq(sc->clkfreq);
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disable_user_access();
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arm_tmr_timecount.tc_frequency = sc->clkfreq;
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tc_init(&arm_tmr_timecount);
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sc->et.et_name = "ARM MPCore Eventtimer";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = sc->clkfreq;
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sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = arm_tmr_start;
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sc->et.et_stop = arm_tmr_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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return (0);
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}
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static device_method_t arm_tmr_methods[] = {
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DEVMETHOD(device_probe, arm_tmr_probe),
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DEVMETHOD(device_attach, arm_tmr_attach),
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{ 0, 0 }
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};
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static driver_t arm_tmr_driver = {
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"generic_timer",
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arm_tmr_methods,
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sizeof(struct arm_tmr_softc),
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};
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static devclass_t arm_tmr_devclass;
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DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0);
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void
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cpu_initclocks(void)
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{
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if (PCPU_GET(cpuid) == 0)
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cpu_initclocks_bsp();
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else
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cpu_initclocks_ap();
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}
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void
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DELAY(int usec)
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{
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int32_t counts, counts_per_usec;
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uint32_t first, last;
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/*
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* Check the timers are setup, if not just
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* use a for loop for the meantime
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*/
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if (arm_tmr_sc == NULL) {
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for (; usec > 0; usec--)
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for (counts = 200; counts > 0; counts--)
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/*
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* Prevent gcc from optimizing
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* out the loop
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*/
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cpufunc_nullop();
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return;
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}
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/* Get the number of times to count */
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counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
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/*
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* Clamp the timeout at a maximum value (about 32 seconds with
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* a 66MHz clock). *Nobody* should be delay()ing for anywhere
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* near that length of time and if they are, they should be hung
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* out to dry.
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*/
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if (usec >= (0x80000000U / counts_per_usec))
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counts = (0x80000000U / counts_per_usec) - 1;
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else
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counts = usec * counts_per_usec;
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first = get_cntpct();
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while (counts > 0) {
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last = get_cntpct();
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counts -= (int32_t)(last - first);
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first = last;
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}
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}
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