Add some missing AR934x register definitions.
These are needed for ethernet bootstrap. Approved by: re@ (gjb)
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50c5514227
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490cbcd9cb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=256175
@ -336,6 +336,7 @@ typedef enum {
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#define MAC_MII_CFG_SCAN_AUTO_INC (1 << 5)
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#define MAC_MII_CFG_PREAMBLE_SUP (1 << 4)
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#define MAC_MII_CFG_CLOCK_SELECT_MASK 0x7
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#define MAC_MII_CFG_CLOCK_SELECT_MASK_AR933X 0xf
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#define MAC_MII_CFG_CLOCK_DIV_4 0
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#define MAC_MII_CFG_CLOCK_DIV_6 2
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#define MAC_MII_CFG_CLOCK_DIV_8 3
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@ -343,6 +344,17 @@ typedef enum {
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#define MAC_MII_CFG_CLOCK_DIV_14 5
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#define MAC_MII_CFG_CLOCK_DIV_20 6
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#define MAC_MII_CFG_CLOCK_DIV_28 7
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/* .. and the AR933x/AR934x extensions */
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#define MAC_MII_CFG_CLOCK_DIV_34 8
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#define MAC_MII_CFG_CLOCK_DIV_42 9
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#define MAC_MII_CFG_CLOCK_DIV_50 10
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#define MAC_MII_CFG_CLOCK_DIV_58 11
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#define MAC_MII_CFG_CLOCK_DIV_66 12
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#define MAC_MII_CFG_CLOCK_DIV_74 13
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#define MAC_MII_CFG_CLOCK_DIV_82 14
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#define MAC_MII_CFG_CLOCK_DIV_98 15
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#define AR71XX_MAC_MII_CMD 0x24
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#define MAC_MII_CMD_SCAN_CYCLE (1 << 1)
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#define MAC_MII_CMD_READ 1
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@ -29,6 +29,8 @@
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#ifndef __AR934X_REG_H__
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#define __AR934X_REG_H__
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#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define AR934X_GMAC_SIZE 0x14
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_EHCI_BASE 0x1b000000
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@ -36,6 +38,23 @@
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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/* AR934x GMAC configuration */
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#define AR934X_GMAC_REG_ETH_CFG (AR934X_GMAC_BASE + 0x00)
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#define AR934X_ETH_CFG_RGMII_GMAC0 (1 << 0)
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#define AR934X_ETH_CFG_MII_GMAC0 (1 << 1)
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#define AR934X_ETH_CFG_GMII_GMAC0 (1 << 2)
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#define AR934X_ETH_CFG_MII_GMAC0_MASTER (1 << 3)
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#define AR934X_ETH_CFG_MII_GMAC0_SLAVE (1 << 4)
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#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN (1 << 5)
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#define AR934X_ETH_CFG_SW_ONLY_MODE (1 << 6)
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#define AR934X_ETH_CFG_SW_PHY_SWAP (1 << 7)
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#define AR934X_ETH_CFG_SW_APB_ACCESS (1 << 9)
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#define AR934X_ETH_CFG_RMII_GMAC0 (1 << 10)
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#define AR933X_ETH_CFG_MII_CNTL_SPEED (1 << 11)
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#define AR934X_ETH_CFG_RMII_GMAC0_MASTER (1 << 12)
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#define AR934X_ETH_CFG_SW_ACC_MSB_FIRST (1 << 13)
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#define AR934X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
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#define AR934X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
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#define AR934X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
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@ -45,6 +64,9 @@
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#define AR934X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00)
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#define AR934X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08)
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#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x24)
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#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL (1 << 6)
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#define AR934X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c)
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#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@ -81,7 +103,13 @@
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#define AR934X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0)
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#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac)
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#define AR934X_RESET_GE1_MDIO (1 << 23)
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#define AR934X_RESET_GE0_MDIO (1 << 22)
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#define AR934X_RESET_GE1_MAC (1 << 13)
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#define AR934X_RESET_ETH_SWITCH_ANALOG (1 << 12)
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#define AR934X_RESET_USB_PHY_ANALOG (1 << 11)
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#define AR934X_RESET_GE0_MAC (1 << 9)
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#define AR934X_RESET_ETH_SWITCH (1 << 8)
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#define AR934X_RESET_USB_HOST (1 << 5)
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#define AR934X_RESET_USB_PHY (1 << 4)
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#define AR934X_RESET_USBSUS_OVERRIDE (1 << 3)
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@ -153,4 +181,9 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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/* XXX verify! */
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#define AR934X_PLL_VAL_1000 0x16000000
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#define AR934X_PLL_VAL_100 0x00000101
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#define AR934X_PLL_VAL_10 0x00001616
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#endif /* __AR934X_REG_H__ */
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