Add initial support for the floating point implementation register.
- Save the current FIR in the global 'cpuinfo' structure in a new 'fpu_id' member. - Decode flags in the FIR when displaying other CPU flags during boot. - Use the existing "dummy" slot in the floating point register structure to export the FIR in process core dumps and via ptrace(). Note that while the FIR register is not volatile, this practice of storing the FIR in the floating-point register set is used in other OS's. Reviewed by: kan MFC after: 1 month Sponsored by: DARPA / AFRL Differential Revision: https://reviews.freebsd.org/D10617
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=318067
@ -75,6 +75,7 @@ struct mips_cpuinfo {
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u_int8_t dc_nways;
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u_int16_t dc_nsets;
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} l2;
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u_int32_t fpu_id;
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};
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extern struct mips_cpuinfo cpuinfo;
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@ -134,7 +134,7 @@ struct trapframe {
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f_register_t f30;
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f_register_t f31;
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register_t fsr;
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register_t fdummy;
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register_t fir;
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};
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#endif /* !_MACHINE_FRAME_H_ */
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@ -52,6 +52,7 @@ extern int vm_page_dump_size;
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extern vm_offset_t kstack0;
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extern vm_offset_t kernel_kseg0_end;
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uint32_t MipsFPID(void);
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void MipsSaveCurFPState(struct thread *);
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void fork_trampoline(void);
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uintptr_t MipsEmulateBranch(struct trapframe *, uintptr_t, int, uintptr_t);
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@ -160,7 +160,7 @@
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#define F30 (FPBASE+30)
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#define F31 (FPBASE+31)
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#define FSR (FPBASE+32)
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#define FSR_DUMMY (FPBASE+33) /* For 8 byte alignment */
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#define FIR (FPBASE+33)
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#define NUMFPREGS 34
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@ -204,5 +204,6 @@
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#define F30_NUM (30)
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#define F31_NUM (31)
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#define FSR_NUM (32)
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#define FIR_NUM (33)
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#endif /* !_MACHINE_REGNUM_H_ */
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@ -184,6 +184,10 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
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cfg3 = mips_rd_config3();
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}
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/* Save FP implementation revision if FP is present. */
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if (cfg1 & MIPS_CONFIG1_FP)
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cpuinfo->fpu_id = MipsFPID();
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/* Check to see if UserLocal register is implemented. */
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if (cfg3 & MIPS_CONFIG3_ULR) {
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/* UserLocal register is implemented, enable it. */
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@ -474,6 +478,19 @@ cpu_identify(void)
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printf(" Config1=0x%b\n", cfg1,
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"\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU");
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if (cpuinfo.fpu_id != 0)
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printf(" FPU ID=0x%b\n", cpuinfo.fpu_id,
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"\020"
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"\020S"
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"\021D"
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"\022PS"
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"\0233D"
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"\024W"
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"\025L"
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"\026F64"
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"\0272008"
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"\034UFRP");
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/* If config register selection 2 does not exist, exit. */
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if (!(cfg1 & MIPS_CONFIG_CM))
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return;
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@ -60,6 +60,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm_extern.h>
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#include <sys/user.h>
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#include <sys/uio.h>
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#include <machine/cpuinfo.h>
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#include <machine/reg.h>
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#include <machine/md_var.h>
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#include <machine/sigframe.h>
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@ -378,7 +379,8 @@ fill_fpregs(struct thread *td, struct fpreg *fpregs)
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{
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if (td == PCPU_GET(fpcurthread))
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MipsSaveCurFPState(td);
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memcpy(fpregs, &td->td_frame->f0, sizeof(struct fpreg));
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memcpy(fpregs, &td->td_frame->f0, sizeof(struct fpreg));
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fpregs->r_regs[FIR_NUM] = cpuinfo.fpu_id;
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return 0;
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}
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@ -524,6 +524,44 @@ LEAF(MipsSwitchFPState)
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.set pop
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END(MipsSwitchFPState)
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/*----------------------------------------------------------------------------
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*
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* MipsFPID --
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*
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* Read and return the floating point implementation register.
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*
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* uint32_t
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* MipsFPID(void)
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*
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* Results:
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* Floating point implementation register.
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*
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* Side effects:
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* None.
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(MipsFPID)
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.set push
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.set hardfloat
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mfc0 t1, MIPS_COP_0_STATUS # Save the status register.
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HAZARD_DELAY
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#if defined(__mips_n64)
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or t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR
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#else
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or t0, t1, MIPS_SR_COP_1_BIT
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#endif
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mtc0 t0, MIPS_COP_0_STATUS # Enable the coprocessor
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HAZARD_DELAY
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ITLBNOPFIX
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cfc1 v0, MIPS_FPU_ID
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mtc0 t1, MIPS_COP_0_STATUS # Restore the status register.
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ITLBNOPFIX
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j ra
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nop
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.set pop
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END(MipsFPID)
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/*----------------------------------------------------------------------------
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*
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* MipsSaveCurFPState --
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