o) Add support for the Lanner MR-321X/MR-325, which is just a modified MR-320.
o) On the Lanner MR-730, disable PCIe lane swap, per vendor.
This commit is contained in:
parent
3693ce5732
commit
4a7b75273b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=216476
@ -223,6 +223,7 @@ enum cvmx_board_types_enum {
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CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
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#if defined(OCTEON_VENDOR_LANNER)
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CVMX_BOARD_TYPE_CUST_LANNER_MR320= 20002,
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CVMX_BOARD_TYPE_CUST_LANNER_MR321X=20007,
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#endif
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CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
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@ -336,6 +337,7 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
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#if defined(OCTEON_VENDOR_LANNER)
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR320)
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR321X)
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#endif
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
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@ -276,6 +276,7 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
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return ipd_port;
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return -1;
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case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
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case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
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/* Port 0 is a Marvell 88E6161 switch, ports 1 and 2 are Marvell
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88E1111 interfaces. */
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switch (ipd_port) {
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@ -417,6 +418,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
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is_broadcom_phy = 1;
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break;
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case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
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case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
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/* Port 0 connects to the switch */
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if (ipd_port == 0)
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{
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@ -860,6 +862,7 @@ cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
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case CVMX_BOARD_TYPE_LANAI2_G:
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#if defined(OCTEON_VENDOR_LANNER)
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case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
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case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
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#endif
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return USB_CLOCK_TYPE_CRYSTAL_12;
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}
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@ -239,6 +239,7 @@ int __cvmx_helper_rgmii_enable(int interface)
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#if defined(OCTEON_VENDOR_LANNER)
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switch (cvmx_sysinfo_get()->board_type) {
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case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
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case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
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if (port == 0) {
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cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 4);
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} else {
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@ -392,7 +392,16 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
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/* Lane swap needs to be manually enabled for CN52XX */
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if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1))
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{
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pescx_ctl_status.s.lane_swp = 1;
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switch (cvmx_sysinfo_get()->board_type)
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{
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#if defined(OCTEON_VENDOR_LANNER)
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case CVMX_BOARD_TYPE_CUST_LANNER_MR730:
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break;
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#endif
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default:
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pescx_ctl_status.s.lane_swp = 1;
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break;
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}
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cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),pescx_ctl_status.u64);
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}
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@ -294,6 +294,7 @@ int cvm_oct_common_init(struct ifnet *ifp)
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switch (cvmx_sysinfo_get()->board_type) {
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#if defined(OCTEON_VENDOR_LANNER)
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case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
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case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
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if (priv->phy_id == 16)
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cvm_oct_mv88e61xx_setup_device(ifp);
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break;
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