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o) Add support for the Lanner MR-321X/MR-325, which is just a modified MR-320.

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o) On the Lanner MR-730, disable PCIe lane swap, per vendor.
This commit is contained in:
Juli Mallett 2010-12-16 07:20:38 +00:00
parent 3693ce5732
commit 4a7b75273b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=216476
5 changed files with 17 additions and 1 deletions
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2
sys/contrib/octeon-sdk/cvmx-app-init.h
View File

@ -223,6 +223,7 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
#if defined(OCTEON_VENDOR_LANNER)
CVMX_BOARD_TYPE_CUST_LANNER_MR320= 20002,
CVMX_BOARD_TYPE_CUST_LANNER_MR321X=20007,
#endif
CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
@ -336,6 +337,7 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
#if defined(OCTEON_VENDOR_LANNER)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR320)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR321X)
#endif
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)

3
sys/contrib/octeon-sdk/cvmx-helper-board.c
View File

@ -276,6 +276,7 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
return ipd_port;
return -1;
case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
/* Port 0 is a Marvell 88E6161 switch, ports 1 and 2 are Marvell
88E1111 interfaces. */
switch (ipd_port) {
@ -417,6 +418,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
is_broadcom_phy = 1;
break;
case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
/* Port 0 connects to the switch */
if (ipd_port == 0)
{
@ -860,6 +862,7 @@ cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
case CVMX_BOARD_TYPE_LANAI2_G:
#if defined(OCTEON_VENDOR_LANNER)
case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
#endif
return USB_CLOCK_TYPE_CRYSTAL_12;
}

1
sys/contrib/octeon-sdk/cvmx-helper-rgmii.c
View File

@ -239,6 +239,7 @@ int __cvmx_helper_rgmii_enable(int interface)
#if defined(OCTEON_VENDOR_LANNER)
switch (cvmx_sysinfo_get()->board_type) {
case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
if (port == 0) {
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 4);
} else {

11
sys/contrib/octeon-sdk/cvmx-pcie.c
View File

@ -392,7 +392,16 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
/* Lane swap needs to be manually enabled for CN52XX */
if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1))
{
pescx_ctl_status.s.lane_swp = 1;
switch (cvmx_sysinfo_get()->board_type)
{
#if defined(OCTEON_VENDOR_LANNER)
case CVMX_BOARD_TYPE_CUST_LANNER_MR730:
break;
#endif
default:
pescx_ctl_status.s.lane_swp = 1;
break;
}
cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),pescx_ctl_status.u64);
}

1
sys/mips/cavium/octe/ethernet-common.c
View File

@ -294,6 +294,7 @@ int cvm_oct_common_init(struct ifnet *ifp)
switch (cvmx_sysinfo_get()->board_type) {
#if defined(OCTEON_VENDOR_LANNER)
case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
if (priv->phy_id == 16)
cvm_oct_mv88e61xx_setup_device(ifp);
break;