Add more and update existing mlx5 core firmware structure definitions and bits.
This change is part of coming ibcore and mlx5ib updates. Sponsored by: Mellanox Technologies MFC after: 1 week
This commit is contained in:
parent
53d7bb46d5
commit
4b109912f1
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=325662
@ -100,6 +100,35 @@ __mlx5_mask(typ, fld))
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#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
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#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
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__mlx5_64_off(typ, fld)))
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#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
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type_t tmp; \
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switch (sizeof(tmp)) { \
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case sizeof(u8): \
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tmp = (__force type_t)MLX5_GET(typ, p, fld); \
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break; \
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case sizeof(u16): \
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tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
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break; \
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case sizeof(u32): \
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tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
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break; \
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case sizeof(u64): \
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tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
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break; \
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} \
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tmp; \
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})
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#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
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#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
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#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
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#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
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MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
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MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
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enum {
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MLX5_MAX_COMMANDS = 32,
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MLX5_CMD_DATA_BLOCK_SIZE = 512,
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@ -326,6 +355,17 @@ enum {
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MLX5_CAP_OFF_CMDIF_CSUM = 46,
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};
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enum {
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/*
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* Max wqe size for rdma read is 512 bytes, so this
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* limits our max_sge_rd as the wqe needs to fit:
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* - ctrl segment (16 bytes)
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* - rdma segment (16 bytes)
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* - scatter elements (16 bytes each)
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*/
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MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
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};
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struct mlx5_inbox_hdr {
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__be16 opcode;
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u8 rsvd[4];
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@ -648,9 +688,9 @@ enum {
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};
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enum {
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CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
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CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
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CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
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MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
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MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
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MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
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};
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enum {
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@ -1288,6 +1328,7 @@ enum {
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MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
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MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
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MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
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MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
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MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
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};
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@ -306,6 +306,11 @@ struct cmd_msg_cache {
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};
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struct mlx5_traffic_counter {
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u64 packets;
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u64 octets;
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};
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struct mlx5_cmd_stats {
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u64 sum;
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u64 n;
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@ -743,6 +748,13 @@ struct mlx5_pas {
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u8 log_sz;
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};
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enum port_state_policy {
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MLX5_POLICY_DOWN = 0,
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MLX5_POLICY_UP = 1,
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MLX5_POLICY_FOLLOW = 2,
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MLX5_POLICY_INVALID = 0xffffffff
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};
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static inline void *
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mlx5_buf_offset(struct mlx5_buf *buf, int offset)
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{
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@ -811,6 +823,11 @@ static inline void *mlx5_vmalloc(unsigned long size)
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return rtn;
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}
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static inline u32 mlx5_base_mkey(const u32 key)
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{
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return key & 0xffffff00u;
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}
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void mlx5_enter_error_state(struct mlx5_core_dev *dev);
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int mlx5_cmd_init(struct mlx5_core_dev *dev);
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void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
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@ -59,13 +59,6 @@ enum {
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MLX5_IB_CACHE_LINE_SIZE = 64,
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};
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enum {
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MLX5_RQ_NUM_STATE = MLX5_RQC_STATE_ERR + 1,
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MLX5_SQ_NUM_STATE = MLX5_SQC_STATE_ERR + 1,
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MLX5_QP_STATE = MLX5_QP_NUM_STATE + 1,
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MLX5_QP_STATE_BAD = MLX5_QP_STATE + 1,
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};
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static const u32 mlx5_ib_opcode[] = {
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[IB_WR_SEND] = MLX5_OPCODE_SEND,
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[IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
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@ -761,7 +761,8 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
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u8 multi_pkt_send_wqe[0x2];
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u8 wqe_inline_mode[0x2];
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u8 rss_ind_tbl_cap[0x4];
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u8 reserved_1[0x3];
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u8 scatter_fcs[0x1];
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u8 reserved_1[0x2];
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u8 tunnel_lso_const_out_ip_id[0x1];
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u8 tunnel_lro_gre[0x1];
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u8 tunnel_lro_vxlan[0x1];
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@ -1050,10 +1051,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 cd[0x1];
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u8 atm[0x1];
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u8 apm[0x1];
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u8 reserved_32[0x7];
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u8 imaicl[0x1];
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u8 reserved_32[0x6];
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u8 qkv[0x1];
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u8 pkv[0x1];
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u8 reserved_33[0x4];
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u8 set_deth_sqpn[0x1];
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u8 reserved_33[0x3];
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u8 xrc[0x1];
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u8 ud[0x1];
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u8 uc[0x1];
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@ -1805,7 +1808,7 @@ enum {
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struct mlx5_ifc_qpc_bits {
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u8 state[0x4];
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u8 reserved_0[0x4];
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u8 lag_tx_port_affinity[0x4];
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u8 st[0x8];
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u8 reserved_1[0x3];
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u8 pm_state[0x2];
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@ -1867,7 +1870,10 @@ struct mlx5_ifc_qpc_bits {
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u8 reserved_16[0x8];
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u8 cqn_snd[0x18];
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u8 reserved_17[0x40];
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u8 reserved_at_400[0x8];
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u8 deth_sqpn[0x18];
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u8 reserved_17[0x20];
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u8 reserved_18[0x8];
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u8 last_acked_psn[0x18];
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@ -2065,7 +2071,11 @@ struct mlx5_ifc_traffic_counter_bits {
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};
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struct mlx5_ifc_tisc_bits {
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u8 reserved_0[0xc];
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u8 strict_lag_tx_port_affinity[0x1];
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u8 reserved_at_1[0x3];
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u8 lag_tx_port_affinity[0x04];
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u8 reserved_at_8[0x4];
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u8 prio[0x4];
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u8 reserved_1[0x10];
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@ -4662,30 +4672,29 @@ struct mlx5_ifc_query_flow_group_in_bits {
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struct mlx5_ifc_query_flow_counter_out_bits {
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u8 status[0x8];
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u8 reserved_0[0x18];
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u8 reserved_at_8[0x18];
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u8 syndrome[0x20];
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u8 reserved_1[0x40];
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u8 reserved_at_40[0x40];
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struct mlx5_ifc_traffic_counter_bits flow_statistics;
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u8 reserved_2[0x700];
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struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
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};
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struct mlx5_ifc_query_flow_counter_in_bits {
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u8 opcode[0x10];
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u8 reserved_0[0x10];
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u8 reserved_at_10[0x10];
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u8 reserved_1[0x10];
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u8 reserved_at_20[0x10];
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u8 op_mod[0x10];
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u8 reserved_2[0x80];
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u8 reserved_at_40[0x80];
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u8 clear[0x1];
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u8 reserved_3[0x1f];
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u8 reserved_at_c1[0xf];
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u8 num_of_counters[0x10];
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u8 reserved_4[0x10];
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u8 reserved_at_e0[0x10];
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u8 flow_counter_id[0x10];
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};
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@ -5111,6 +5120,15 @@ struct mlx5_ifc_modify_tis_out_bits {
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u8 reserved_1[0x40];
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};
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struct mlx5_ifc_modify_tis_bitmask_bits {
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u8 reserved_at_0[0x20];
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u8 reserved_at_20[0x1d];
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u8 lag_tx_port_affinity[0x1];
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u8 strict_lag_tx_port_affinity[0x1];
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u8 prio[0x1];
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};
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struct mlx5_ifc_modify_tis_in_bits {
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u8 opcode[0x10];
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u8 reserved_0[0x10];
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@ -5123,7 +5141,7 @@ struct mlx5_ifc_modify_tis_in_bits {
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u8 reserved_3[0x20];
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u8 modify_bitmask[0x40];
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struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
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u8 reserved_4[0x40];
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@ -5271,12 +5289,9 @@ struct mlx5_ifc_modify_rq_out_bits {
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u8 reserved_1[0x40];
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};
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struct mlx5_ifc_rq_bitmask_bits {
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u8 reserved[0x20];
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u8 reserved1[0x1e];
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u8 vlan_strip_disable[0x1];
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u8 reserved2[0x1];
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enum {
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MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
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MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
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};
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struct mlx5_ifc_modify_rq_in_bits {
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@ -5292,7 +5307,7 @@ struct mlx5_ifc_modify_rq_in_bits {
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u8 reserved_3[0x20];
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struct mlx5_ifc_rq_bitmask_bits bitmask;
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u8 modify_bitmask[0x40];
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u8 reserved_4[0x40];
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@ -8133,6 +8148,36 @@ struct mlx5_ifc_phys_layer_cntrs_bits {
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u8 reserved_0[0x180];
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};
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struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
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u8 symbol_error_counter[0x10];
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u8 link_error_recovery_counter[0x8];
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u8 link_downed_counter[0x8];
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u8 port_rcv_errors[0x10];
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u8 port_rcv_remote_physical_errors[0x10];
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u8 port_rcv_switch_relay_errors[0x10];
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u8 port_xmit_discards[0x10];
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u8 port_xmit_constraint_errors[0x8];
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u8 port_rcv_constraint_errors[0x8];
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u8 reserved_at_70[0x8];
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u8 link_overrun_errors[0x8];
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u8 reserved_at_80[0x10];
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u8 vl_15_dropped[0x10];
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u8 reserved_at_a0[0xa0];
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};
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struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
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u8 time_since_last_clear_high[0x20];
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@ -28,9 +28,7 @@
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#ifndef MLX5_QP_H
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#define MLX5_QP_H
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#include <dev/mlx5/device.h>
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#include <dev/mlx5/driver.h>
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#include <dev/mlx5/mlx5_ifc.h>
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#define MLX5_INVALID_LKEY 0x100
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#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
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@ -45,6 +43,7 @@
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#define MLX5_BSF_REPEAT_BLOCK (1 << 7)
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#define MLX5_BSF_APPTAG_ESCAPE 0x1
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#define MLX5_BSF_APPREF_ESCAPE 0x2
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#define MLX5_WQE_DS_UNITS 16
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enum mlx5_qp_optpar {
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MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
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@ -78,7 +77,16 @@ enum mlx5_qp_state {
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MLX5_QP_STATE_ERR = 6,
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MLX5_QP_STATE_SQ_DRAINING = 7,
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MLX5_QP_STATE_SUSPENDED = 9,
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MLX5_QP_NUM_STATE
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MLX5_QP_NUM_STATE,
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MLX5_QP_STATE,
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MLX5_QP_STATE_BAD,
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};
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enum {
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MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
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MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
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MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
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MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
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};
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enum {
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@ -157,6 +165,7 @@ enum {
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enum {
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MLX5_FENCE_MODE_NONE = 0 << 5,
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MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
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MLX5_FENCE_MODE_FENCE = 2 << 5,
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MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
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MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
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};
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@ -198,6 +207,8 @@ struct mlx5_wqe_ctrl_seg {
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__be32 imm;
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};
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#define MLX5_WQE_CTRL_DS_MASK 0x3f
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enum {
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MLX5_MLX_FLAG_MASK_VL15 = 0x40,
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MLX5_MLX_FLAG_MASK_SLR = 0x20,
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@ -221,10 +232,10 @@ enum {
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};
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enum {
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MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 0,
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MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 1,
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MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 4,
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MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 5,
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MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0,
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MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1,
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MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4,
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MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5,
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};
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struct mlx5_wqe_eth_seg {
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@ -415,6 +426,42 @@ struct mlx5_stride_block_ctrl_seg {
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__be16 num_entries;
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};
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enum mlx5_pagefault_flags {
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MLX5_PFAULT_REQUESTOR = 1 << 0,
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MLX5_PFAULT_WRITE = 1 << 1,
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MLX5_PFAULT_RDMA = 1 << 2,
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};
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/* Contains the details of a pagefault. */
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struct mlx5_pagefault {
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u32 bytes_committed;
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u8 event_subtype;
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enum mlx5_pagefault_flags flags;
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union {
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/* Initiator or send message responder pagefault details. */
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struct {
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/* Received packet size, only valid for responders. */
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u32 packet_size;
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/*
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* WQE index. Refers to either the send queue or
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* receive queue, according to event_subtype.
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*/
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u16 wqe_index;
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} wqe;
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/* RDMA responder pagefault details */
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struct {
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u32 r_key;
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/*
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* Received packet size, minimal size page fault
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* resolution required for forward progress.
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*/
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u32 packet_size;
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u32 rdma_op_len;
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u64 rdma_va;
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} rdma;
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};
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};
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struct mlx5_core_qp {
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struct mlx5_core_rsc_common common; /* must be first */
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void (*event) (struct mlx5_core_qp *, int);
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@ -462,7 +509,8 @@ struct mlx5_qp_context {
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u8 reserved2[4];
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__be32 next_send_psn;
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__be32 cqn_send;
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u8 reserved3[8];
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__be32 deth_sqpn;
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u8 reserved3[4];
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__be32 last_acked_psn;
|
||||
__be32 ssn;
|
||||
__be32 params2;
|
||||
|
Loading…
Reference in New Issue
Block a user