Add jz4780 internal codec initialization driver.
Sponsored by: DARPA, AFRL
This commit is contained in:
Ruslan Bukin
parent
9373759d13
commit
4b3fae2c2d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=309715
242
sys/mips/ingenic/jz4780_codec.c
Normal file
242
sys/mips/ingenic/jz4780_codec.c
Normal file
@ -0,0 +1,242 @@
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Ingenic JZ4780 CODEC. */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <mips/ingenic/jz4780_common.h>
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#include <mips/ingenic/jz4780_codec.h>
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struct codec_softc {
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device_t dev;
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struct resource *res[1];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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};
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static struct resource_spec codec_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int codec_probe(device_t dev);
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static int codec_attach(device_t dev);
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static int codec_detach(device_t dev);
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void codec_print_registers(struct codec_softc *sc);
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static int
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codec_write(struct codec_softc *sc, uint32_t reg, uint32_t val)
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{
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uint32_t tmp;
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tmp = (reg << RGADW_RGADDR_S);
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tmp |= (val << RGADW_RGDIN_S);
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tmp |= RGADW_RGWR;
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WRITE4(sc, CODEC_RGADW, tmp);
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while(READ4(sc, CODEC_RGADW) & RGADW_RGWR)
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;
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return (0);
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}
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static int
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codec_read(struct codec_softc *sc, uint32_t reg)
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{
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uint32_t tmp;
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tmp = (reg << RGADW_RGADDR_S);
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WRITE4(sc, CODEC_RGADW, tmp);
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tmp = READ4(sc, CODEC_RGDATA);
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return (tmp);
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}
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void
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codec_print_registers(struct codec_softc *sc)
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{
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printf("codec SR %x\n", codec_read(sc, SR));
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printf("codec SR2 %x\n", codec_read(sc, SR2));
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printf("codec MR %x\n", codec_read(sc, MR));
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printf("codec AICR_DAC %x\n", codec_read(sc, AICR_DAC));
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printf("codec AICR_ADC %x\n", codec_read(sc, AICR_ADC));
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printf("codec CR_LO %x\n", codec_read(sc, CR_LO));
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printf("codec CR_HP %x\n", codec_read(sc, CR_HP));
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printf("codec CR_DMIC %x\n", codec_read(sc, CR_DMIC));
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printf("codec CR_MIC1 %x\n", codec_read(sc, CR_MIC1));
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printf("codec CR_MIC2 %x\n", codec_read(sc, CR_MIC2));
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printf("codec CR_LI1 %x\n", codec_read(sc, CR_LI1));
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printf("codec CR_LI2 %x\n", codec_read(sc, CR_LI2));
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printf("codec CR_DAC %x\n", codec_read(sc, CR_DAC));
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printf("codec CR_ADC %x\n", codec_read(sc, CR_ADC));
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printf("codec CR_MIX %x\n", codec_read(sc, CR_MIX));
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printf("codec DR_MIX %x\n", codec_read(sc, DR_MIX));
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printf("codec CR_VIC %x\n", codec_read(sc, CR_VIC));
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printf("codec CR_CK %x\n", codec_read(sc, CR_CK));
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printf("codec FCR_DAC %x\n", codec_read(sc, FCR_DAC));
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printf("codec FCR_ADC %x\n", codec_read(sc, FCR_ADC));
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printf("codec CR_TIMER_MSB %x\n", codec_read(sc, CR_TIMER_MSB));
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printf("codec CR_TIMER_LSB %x\n", codec_read(sc, CR_TIMER_LSB));
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printf("codec ICR %x\n", codec_read(sc, ICR));
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printf("codec IMR %x\n", codec_read(sc, IMR));
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printf("codec IFR %x\n", codec_read(sc, IFR));
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printf("codec IMR2 %x\n", codec_read(sc, IMR2));
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printf("codec IFR2 %x\n", codec_read(sc, IFR2));
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printf("codec GCR_HPL %x\n", codec_read(sc, GCR_HPL));
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printf("codec GCR_HPR %x\n", codec_read(sc, GCR_HPR));
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printf("codec GCR_LIBYL %x\n", codec_read(sc, GCR_LIBYL));
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printf("codec GCR_LIBYR %x\n", codec_read(sc, GCR_LIBYR));
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printf("codec GCR_DACL %x\n", codec_read(sc, GCR_DACL));
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printf("codec GCR_DACR %x\n", codec_read(sc, GCR_DACR));
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printf("codec GCR_MIC1 %x\n", codec_read(sc, GCR_MIC1));
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printf("codec GCR_MIC2 %x\n", codec_read(sc, GCR_MIC2));
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printf("codec GCR_ADCL %x\n", codec_read(sc, GCR_ADCL));
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printf("codec GCR_ADCR %x\n", codec_read(sc, GCR_ADCR));
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printf("codec GCR_MIXDACL %x\n", codec_read(sc, GCR_MIXDACL));
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printf("codec GCR_MIXDACR %x\n", codec_read(sc, GCR_MIXDACR));
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printf("codec GCR_MIXADCL %x\n", codec_read(sc, GCR_MIXADCL));
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printf("codec GCR_MIXADCR %x\n", codec_read(sc, GCR_MIXADCR));
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printf("codec CR_ADC_AGC %x\n", codec_read(sc, CR_ADC_AGC));
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printf("codec DR_ADC_AGC %x\n", codec_read(sc, DR_ADC_AGC));
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}
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static int
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codec_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-codec"))
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return (ENXIO);
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device_set_desc(dev, "Ingenic JZ4780 CODEC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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codec_attach(device_t dev)
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{
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struct codec_softc *sc;
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uint8_t reg;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, codec_spec, sc->res)) {
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device_printf(dev, "could not allocate resources for device\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* Initialize codec. */
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reg = codec_read(sc, CR_VIC);
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reg &= ~(VIC_SB_SLEEP | VIC_SB);
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codec_write(sc, CR_VIC, reg);
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reg = codec_read(sc, CR_DAC);
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reg &= ~(DAC_SB | DAC_MUTE);
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codec_write(sc, CR_DAC, reg);
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/* I2S, 16-bit, 96 kHz. */
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reg = codec_read(sc, AICR_DAC);
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reg &= ~(AICR_DAC_SB | DAC_ADWL_M);
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reg |= DAC_ADWL_16;
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reg &= ~(AUDIOIF_M);
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reg |= AUDIOIF_I2S;
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codec_write(sc, AICR_DAC, reg);
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reg = FCR_DAC_96;
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codec_write(sc, FCR_DAC, reg);
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/* Unmute headphones. */
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reg = codec_read(sc, CR_HP);
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reg &= ~(HP_SB | HP_MUTE);
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codec_write(sc, CR_HP, 0);
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return (0);
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}
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static int
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codec_detach(device_t dev)
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{
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struct codec_softc *sc;
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sc = device_get_softc(dev);
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bus_release_resources(dev, codec_spec, sc->res);
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return (0);
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}
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static device_method_t codec_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, codec_probe),
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DEVMETHOD(device_attach, codec_attach),
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DEVMETHOD(device_detach, codec_detach),
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DEVMETHOD_END
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};
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static driver_t codec_driver = {
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"codec",
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codec_methods,
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sizeof(struct codec_softc),
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};
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static devclass_t codec_devclass;
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DRIVER_MODULE(codec, simplebus, codec_driver, codec_devclass, 0, 0);
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101
sys/mips/ingenic/jz4780_codec.h
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101
sys/mips/ingenic/jz4780_codec.h
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@ -0,0 +1,101 @@
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define CODEC_RGADW 0x00 /* Address, data in and write command */
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#define RGADW_ICRST (1 << 31) /* Reset internal CODEC */
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#define RGADW_RGWR (1 << 16) /* Issue a write command to CODEC */
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#define RGADW_RGADDR_S 8 /* CODEC register's address. */
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#define RGADW_RGADDR_M (0x7f << RGADW_RGADDR_S)
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#define RGADW_RGDIN_S 0 /* CODEC register data to write */
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#define RGADW_RGDIN_M (0xff << RGADW_RGDIN_S)
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#define CODEC_RGDATA 0x04 /* The data read out */
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#define SR 0x00 /* Status Register */
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#define SR2 0x01 /* Status Register 2 */
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#define MR 0x07 /* Mode status register */
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#define AICR_DAC 0x08 /* DAC Audio Interface Control Register */
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#define DAC_ADWL_S 6 /* Audio Data Word Length for DAC path. */
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#define DAC_ADWL_M (0x3 << DAC_ADWL_S)
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#define DAC_ADWL_16 (0 << DAC_ADWL_S)
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#define AICR_DAC_SB (1 << 4) /* DAC audio interface in power-down mode */
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#define AUDIOIF_S 0
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#define AUDIOIF_M (0x3 << AUDIOIF_S)
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#define AUDIOIF_I2S 0x3 /* I2S interface */
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#define AUDIOIF_DSP 0x2 /* DSP interface */
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#define AUDIOIF_LJ 0x1 /* Left-justified interface */
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#define AUDIOIF_P 0x0 /* Parallel interface */
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#define AICR_ADC 0x09 /* ADC Audio Interface Control Register */
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#define CR_LO 0x0B /* Differential line-out Control Register */
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#define CR_HP 0x0D /* HeadPhone Control Register */
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#define HP_MUTE (1 << 7) /* no signal on headphone outputs */
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#define HP_SB (1 << 4) /* power-down */
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#define CR_DMIC 0x10 /* Digital Microphone register */
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#define CR_MIC1 0x11 /* Microphone1 Control register */
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#define CR_MIC2 0x12 /* Microphone2 Control register */
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#define CR_LI1 0x13 /* Control Register for line1 inputs */
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#define CR_LI2 0x14 /* Control Register for line2 inputs */
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#define CR_DAC 0x17 /* DAC Control Register */
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#define DAC_MUTE (1 << 7) /* puts the DAC in soft mute mode */
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#define DAC_SB (1 << 4) /* power-down */
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#define CR_ADC 0x18 /* ADC Control Register */
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#define CR_MIX 0x19 /* Digital Mixer Control Register */
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#define DR_MIX 0x1A /* Digital Mixer Data Register */
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#define CR_VIC 0x1B /* Control Register for the ViC */
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#define VIC_SB_SLEEP (1 << 1) /* sleep mode */
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#define VIC_SB (1 << 0) /* complete power-down */
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#define CR_CK 0x1C /* Clock Control Register */
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#define FCR_DAC 0x1D /* DAC Frequency Control Register */
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#define FCR_DAC_96 10 /* 96 kHz. */
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#define FCR_ADC 0x20 /* ADC Frequency Control Register */
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#define CR_TIMER_MSB 0x21 /* MSB of programmable counter */
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#define CR_TIMER_LSB 0x22 /* LSB of programmable counter */
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#define ICR 0x23 /* Interrupt Control Register */
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#define IMR 0x24 /* Interrupt Mask Register */
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#define IFR 0x25 /* Interrupt Flag Register */
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#define IMR2 0x26 /* Interrupt Mask Register 2 */
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#define IFR2 0x27 /* Interrupt Flag Register 2 */
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#define GCR_HPL 0x28 /* Left channel headphone Control Gain Register */
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#define GCR_HPR 0x29 /* Right channel headphone Control Gain Register */
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#define GCR_LIBYL 0x2A /* Left channel bypass line Control Gain Register */
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#define GCR_LIBYR 0x2B /* Right channel bypass line Control Gain Register */
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#define GCR_DACL 0x2C /* Left channel DAC Gain Control Register */
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#define GCR_DACR 0x2D /* Right channel DAC Gain Control Register */
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#define GCR_MIC1 0x2E /* Microphone 1 Gain Control Register */
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#define GCR_MIC2 0x2F /* Microphone 2 Gain Control Register */
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#define GCR_ADCL 0x30 /* Left ADC Gain Control Register */
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#define GCR_ADCR 0x31 /* Right ADC Gain Control Register */
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#define GCR_MIXDACL 0x34 /* DAC Digital Mixer Control Register */
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#define GCR_MIXDACR 0x35 /* DAC Digital Mixer Control Register */
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#define GCR_MIXADCL 0x36 /* ADC Digital Mixer Control Register */
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#define GCR_MIXADCR 0x37 /* ADC Digital Mixer Control Register */
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#define CR_ADC_AGC 0x3A /* Automatic Gain Control Register */
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#define DR_ADC_AGC 0x3B /* Automatic Gain Control Data Register */
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36
sys/mips/ingenic/jz4780_common.h
Normal file
36
sys/mips/ingenic/jz4780_common.h
Normal file
@ -0,0 +1,36 @@
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
|
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
|
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* ("CTSRD"), as part of the DARPA CRASH research programme.
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
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* $FreeBSD$
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*/
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#define READ4(_sc, _reg) \
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bus_space_read_4(_sc->bst, _sc->bsh, _reg)
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#define WRITE4(_sc, _reg, _val) \
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bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
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