Add vendor specific capability interface support in mlx5core.
Add the ability to access the vendor specific space gateway in order to support reading and writing data into the different configuration domains. Submitted by: Matthew Finlay <matt@mellanox.com> MFC after: 1 week Sponsored by: Mellanox Technologies
This commit is contained in:
Hans Petter Selasky
parent
fba294620c
commit
4b95c6659a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=330651
@ -4757,6 +4757,8 @@ dev/mlx5/mlx5_core/mlx5_uar.c optional mlx5 pci \
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compile-with "${OFED_C}"
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dev/mlx5/mlx5_core/mlx5_vport.c optional mlx5 pci \
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compile-with "${OFED_C}"
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dev/mlx5/mlx5_core/mlx5_vsc.c optional mlx5 pci \
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compile-with "${OFED_C}"
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dev/mlx5/mlx5_core/mlx5_wq.c optional mlx5 pci \
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compile-with "${OFED_C}"
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@ -138,6 +138,26 @@ __mlx5_mask(typ, fld))
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MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
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MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
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/* insert a value to a struct */
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#define MLX5_VSC_SET(typ, p, fld, v) do { \
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BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
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BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
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*((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
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cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
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(~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
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<< __mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
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__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
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__mlx5_mask(typ, fld))
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#define MLX5_VSC_GET_PR(typ, p, fld) ({ \
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u32 ___t = MLX5_VSC_GET(typ, p, fld); \
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pr_debug(#fld " = 0x%x\n", ___t); \
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___t; \
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})
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enum {
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MLX5_MAX_COMMANDS = 32,
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MLX5_CMD_DATA_BLOCK_SIZE = 512,
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@ -221,6 +221,16 @@ enum mlx5_link_mode {
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MLX5_LINK_MODES_NUMBER,
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};
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enum {
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MLX5_VSC_SPACE_SUPPORTED = 0x1,
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MLX5_VSC_SPACE_OFFSET = 0x4,
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MLX5_VSC_COUNTER_OFFSET = 0x8,
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MLX5_VSC_SEMA_OFFSET = 0xC,
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MLX5_VSC_ADDR_OFFSET = 0x10,
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MLX5_VSC_DATA_OFFSET = 0x14,
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MLX5_VSC_MAX_RETRIES = 0x1000,
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};
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#define MLX5_PROT_MASK(link_mode) (1 << link_mode)
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struct mlx5_uuar_info {
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@ -627,6 +637,7 @@ struct mlx5_core_dev {
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struct mlx5_priv priv;
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struct mlx5_profile *profile;
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atomic_t num_qps;
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u32 vsc_addr;
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u32 issi;
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struct mlx5_special_contexts special_contexts;
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unsigned int module_status[MLX5_MAX_PORTS];
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@ -1001,6 +1012,12 @@ int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
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int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
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u8 num_of_samples, u16 sample_index,
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void *out, int out_size);
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int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
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int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
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void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
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int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
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int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
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int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
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static inline u32 mlx5_mkey_to_idx(u32 mkey)
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{
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return mkey >> 8;
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@ -846,6 +846,9 @@ static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
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goto err_clr_master;
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}
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if (mlx5_vsc_find_cap(dev))
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dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n");
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return 0;
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err_clr_master:
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@ -1184,7 +1187,6 @@ static int init_one(struct pci_dev *pdev,
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goto clean_health;
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}
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return 0;
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clean_health:
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204
sys/dev/mlx5/mlx5_core/mlx5_vsc.c
Normal file
204
sys/dev/mlx5/mlx5_core/mlx5_vsc.c
Normal file
@ -0,0 +1,204 @@
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/*-
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* Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <dev/mlx5/driver.h>
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#include <dev/mlx5/device.h>
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#include <dev/mlx5/mlx5_core/mlx5_core.h>
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struct mlx5_ifc_vsc_space_bits {
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u8 status[0x3];
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u8 reserved0[0xd];
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u8 space[0x10];
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};
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struct mlx5_ifc_vsc_addr_bits {
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u8 flag[0x1];
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u8 reserved0[0x1];
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u8 address[0x1e];
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};
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int mlx5_vsc_lock(struct mlx5_core_dev *mdev)
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{
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device_t dev = mdev->pdev->dev.bsddev;
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int vsc_addr = mdev->vsc_addr;
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int retries = 0;
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u32 lock_val;
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u32 counter;
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if (!vsc_addr) {
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mlx5_core_warn(mdev, "Unable to acquire vsc lock, vsc_addr not initialized\n");
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return EINVAL;
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}
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while (true) {
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if (retries > MLX5_VSC_MAX_RETRIES)
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return EBUSY;
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if (pci_read_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 4)) {
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retries++;
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/*
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* The PRM suggests random 0 - 10ms to prevent multiple
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* waiters on the same interval in order to avoid starvation
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*/
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DELAY((random() % 11) * 1000);
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continue;
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}
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counter = pci_read_config(dev, vsc_addr + MLX5_VSC_COUNTER_OFFSET, 4);
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pci_write_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, counter, 4);
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lock_val = pci_read_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 4);
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if (lock_val == counter)
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break;
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retries++;
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}
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return 0;
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}
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void mlx5_vsc_unlock(struct mlx5_core_dev *mdev)
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{
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device_t dev = mdev->pdev->dev.bsddev;
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int vsc_addr = mdev->vsc_addr;
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if (!vsc_addr) {
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mlx5_core_warn(mdev, "Unable to release vsc lock, vsc_addr not initialized\n");
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return;
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}
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pci_write_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 0, 4);
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}
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static int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected)
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{
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device_t dev = mdev->pdev->dev.bsddev;
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int vsc_addr = mdev->vsc_addr;
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int retries = 0;
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u32 flag;
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while (true) {
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if (retries > MLX5_VSC_MAX_RETRIES)
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return EBUSY;
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flag = pci_read_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, 4);
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if (expected == MLX5_VSC_GET(vsc_addr, &flag, flag))
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break;
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retries++;
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DELAY(10);
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}
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return 0;
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}
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int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space)
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{
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device_t dev = mdev->pdev->dev.bsddev;
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int vsc_addr = mdev->vsc_addr;
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u32 vsc_space = 0;
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if (!vsc_addr) {
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mlx5_core_warn(mdev, "Unable to set vsc space, vsc_addr not initialized\n");
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return EINVAL;
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}
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MLX5_VSC_SET(vsc_space, &vsc_space, space, space);
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pci_write_config(dev, vsc_addr + MLX5_VSC_SPACE_OFFSET, vsc_space, 4);
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vsc_space = pci_read_config(dev, vsc_addr + MLX5_VSC_SPACE_OFFSET, 4);
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if (MLX5_VSC_GET(vsc_space, &vsc_space, status) != MLX5_VSC_SPACE_SUPPORTED) {
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mlx5_core_warn(mdev, "Space 0x%x is not supported.\n", space);
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return ENOTSUP;
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}
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return 0;
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}
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int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, u32 *data)
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{
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device_t dev = mdev->pdev->dev.bsddev;
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int vsc_addr = mdev->vsc_addr;
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u32 in = 0;
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int err;
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if (!vsc_addr) {
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mlx5_core_warn(mdev, "Unable to call vsc write, vsc_addr not initialized\n");
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return EINVAL;
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}
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MLX5_VSC_SET(vsc_addr, &in, address, addr);
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MLX5_VSC_SET(vsc_addr, &in, flag, 1);
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pci_write_config(dev, vsc_addr + MLX5_VSC_DATA_OFFSET, *data, 4);
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pci_write_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, in, 4);
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err = mlx5_vsc_wait_on_flag(mdev, 0);
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if (err)
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mlx5_core_warn(mdev, "Failed waiting for write flag!\n");
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return err;
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}
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int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data)
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{
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device_t dev = mdev->pdev->dev.bsddev;
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int vsc_addr = mdev->vsc_addr;
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int err;
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u32 in;
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if (!vsc_addr) {
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mlx5_core_warn(mdev, "Unable to call vsc read, vsc_addr not initialized\n");
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return EINVAL;
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}
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MLX5_VSC_SET(vsc_addr, &in, address, addr);
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pci_write_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, in, 4);
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err = mlx5_vsc_wait_on_flag(mdev, 1);
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if (err) {
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mlx5_core_warn(mdev, "Failed waiting for read complete flag!\n");
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return err;
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}
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*data = pci_read_config(dev, vsc_addr + MLX5_VSC_DATA_OFFSET, 4);
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return 0;
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}
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int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev)
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{
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int *capreg = &mdev->vsc_addr;
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int err;
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err = pci_find_cap(mdev->pdev->dev.bsddev, PCIY_VENDOR, capreg);
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if (err)
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*capreg = 0;
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return err;
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}
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@ -9328,6 +9328,13 @@ struct mlx5_ifc_mtt_bits {
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u8 rd_en[0x1];
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};
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/* Vendor Specific Capabilities, VSC */
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enum {
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MLX5_VSC_DOMAIN_ICMD = 0x1,
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MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6,
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MLX5_VSC_DOMAIN_SEMAPHORES = 0xA,
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};
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struct mlx5_ifc_vendor_specific_cap_bits {
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u8 type[0x8];
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u8 length[0x8];
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@ -24,6 +24,7 @@ mlx5_srq.c \
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mlx5_transobj.c \
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mlx5_uar.c \
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mlx5_vport.c \
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mlx5_vsc.c \
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mlx5_wq.c \
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device_if.h bus_if.h vnode_if.h pci_if.h \
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opt_inet.h opt_inet6.h opt_rss.h
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