Add a driver for the Allwinner Reduced Serial Bus (RSB).
The RSB controller speaks a simplified two wire protocol at speeds up to 20MHz. It is used on sun8i and sun9i family SoCs to communicate with power management ICs. RSB isn't really I2C or SMBus, but the driver exposes an iicbus interface to simplify power management IC drivers (which may need to support both RSB and I2C connectivity).
This commit is contained in:
Jared McNeill
parent
0cfd65ecdc
commit
4b9a54a9fc
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=299781
506
sys/arm/allwinner/aw_rsb.c
Normal file
506
sys/arm/allwinner/aw_rsb.c
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@ -0,0 +1,506 @@
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/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner RSB (Reduced Serial Bus)
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "iicbus_if.h"
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#define RSB_CTRL 0x00
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#define START_TRANS (1 << 7)
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#define GLOBAL_INT_ENB (1 << 1)
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#define SOFT_RESET (1 << 0)
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#define RSB_CCR 0x04
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#define RSB_INTE 0x08
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#define RSB_INTS 0x0c
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#define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf)
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#define INT_LOAD_BSY (1 << 2)
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#define INT_TRANS_ERR (1 << 1)
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#define INT_TRANS_OVER (1 << 0)
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#define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER)
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#define RSB_DADDR0 0x10
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#define RSB_DADDR1 0x14
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#define RSB_DLEN 0x18
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#define DLEN_READ (1 << 4)
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#define RSB_DATA0 0x1c
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#define RSB_DATA1 0x20
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#define RSB_CMD 0x2c
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#define CMD_SRTA 0xe8
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#define CMD_RD8 0x8b
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#define CMD_RD16 0x9c
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#define CMD_RD32 0xa6
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#define CMD_WR8 0x4e
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#define CMD_WR16 0x59
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#define CMD_WR32 0x63
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#define RSB_DAR 0x30
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#define DAR_RTA (0xff << 16)
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#define DAR_RTA_SHIFT 16
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#define DAR_DA (0xffff << 0)
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#define DAR_DA_SHIFT 0
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#define RSB_MAXLEN 8
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#define RSB_RESET_RETRY 100
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#define RSB_I2C_TIMEOUT hz
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#define RSB_ADDR_PMIC_PRIMARY 0x3a3
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#define RSB_ADDR_PMIC_SECONDARY 0x745
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#define RSB_ADDR_PERIPH_IC 0xe89
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun8i-a23-rsb", 1 },
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{ NULL, 0 }
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};
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static struct resource_spec rsb_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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/*
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* Device address to Run-time address mappings.
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*
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* Run-time address (RTA) is an 8-bit value used to address the device during
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* a read or write transaction. The following are valid RTAs:
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* 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff
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*
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* Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC,
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* and 0x4e for the peripheral IC (where applicable).
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*/
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static const struct {
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uint16_t addr;
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uint8_t rta;
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} rsb_rtamap[] = {
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{ .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d },
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{ .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a },
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{ .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e },
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{ .addr = 0, .rta = 0 }
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};
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struct rsb_softc {
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struct resource *res[2];
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struct mtx mtx;
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clk_t clk;
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hwreset_t rst;
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device_t iicbus;
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void *ih;
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int busy;
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uint32_t status;
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uint16_t cur_addr;
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struct iic_msg *msg;
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};
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#define RSB_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
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#define RSB_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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static phandle_t
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rsb_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static int
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rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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{
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struct rsb_softc *sc;
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int retry;
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sc = device_get_softc(dev);
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RSB_LOCK(sc);
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/* Write soft-reset bit and wait for it to self-clear. */
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RSB_WRITE(sc, RSB_CTRL, SOFT_RESET);
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for (retry = RSB_RESET_RETRY; retry > 0; retry--)
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if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0)
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break;
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RSB_UNLOCK(sc);
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if (retry == 0) {
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device_printf(dev, "soft reset timeout\n");
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return (ETIMEDOUT);
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}
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return (IIC_ENOADDR);
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}
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static uint32_t
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rsb_encode(const uint8_t *buf, u_int len, u_int off)
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{
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uint32_t val;
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u_int n;
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val = 0;
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for (n = off; n < MIN(len, 4 + off); n++)
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val |= ((uint32_t)buf[n] << ((n - off) * NBBY));
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return val;
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}
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static void
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rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off)
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{
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u_int n;
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for (n = off; n < MIN(len, 4 + off); n++)
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buf[n] = (val >> ((n - off) * NBBY)) & 0xff;
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}
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static int
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rsb_start(device_t dev)
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{
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struct rsb_softc *sc;
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int error, retry;
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sc = device_get_softc(dev);
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RSB_ASSERT_LOCKED(sc);
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/* Enable interrupts */
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if (!cold)
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RSB_WRITE(sc, RSB_INTE, INT_MASK);
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/* Start the transfer */
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RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS);
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/* Wait for transfer to complete */
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if (cold) {
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error = ETIMEDOUT;
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for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) {
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sc->status |= RSB_READ(sc, RSB_INTS);
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if ((sc->status & INT_TRANS_OVER) != 0) {
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error = 0;
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break;
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}
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DELAY((1000 * hz) / RSB_I2C_TIMEOUT);
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}
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} else {
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error = mtx_sleep(sc, &sc->mtx, 0, "i2ciowait",
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RSB_I2C_TIMEOUT);
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}
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if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) {
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device_printf(dev, "transfer error, status 0x%08x\n",
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sc->status);
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error = EIO;
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}
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/* Disable interrupts */
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RSB_WRITE(sc, RSB_INTE, 0);
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return (error);
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}
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static int
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rsb_set_rta(device_t dev, uint16_t addr)
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{
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struct rsb_softc *sc;
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uint8_t rta;
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int i;
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sc = device_get_softc(dev);
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RSB_ASSERT_LOCKED(sc);
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/* Lookup run-time address for given device address */
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for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++)
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if (rsb_rtamap[i].addr == addr) {
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rta = rsb_rtamap[i].rta;
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break;
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}
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if (rta == 0) {
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device_printf(dev, "RTA not known for address %#x\n", addr);
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return (ENXIO);
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}
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/* Set run-time address */
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RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
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RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT));
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RSB_WRITE(sc, RSB_CMD, CMD_SRTA);
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return (rsb_start(dev));
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}
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static int
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rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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{
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struct rsb_softc *sc;
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uint32_t daddr[2], data[2], dlen;
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uint16_t device_addr;
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uint8_t cmd;
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int error;
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sc = device_get_softc(dev);
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/*
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* RSB is not really an I2C or SMBus controller, so there are some
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* restrictions imposed by the driver.
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*
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* Transfers must contain exactly two messages. The first is always
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* a write, containing a single data byte offset. Data will either
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* be read from or written to the corresponding data byte in the
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* second message. The slave address in both messages must be the
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* same.
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*/
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if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD ||
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(msgs[0].slave >> 1) != (msgs[1].slave >> 1) ||
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msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN)
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return (EINVAL);
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/* The controller can read or write 1, 2, or 4 bytes at a time. */
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if ((msgs[1].flags & IIC_M_RD) != 0) {
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switch (msgs[1].len) {
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case 1:
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cmd = CMD_RD8;
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break;
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case 2:
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cmd = CMD_RD16;
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break;
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case 4:
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cmd = CMD_RD32;
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break;
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default:
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return (EINVAL);
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}
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} else {
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switch (msgs[1].len) {
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case 1:
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cmd = CMD_WR8;
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break;
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case 2:
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cmd = CMD_WR16;
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break;
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case 4:
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cmd = CMD_WR32;
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break;
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default:
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return (EINVAL);
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}
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}
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RSB_LOCK(sc);
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while (sc->busy)
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mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
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sc->busy = 1;
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sc->status = 0;
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/* Select current run-time address if necessary */
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device_addr = msgs[0].slave >> 1;
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if (sc->cur_addr != device_addr) {
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error = rsb_set_rta(dev, device_addr);
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if (error != 0)
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goto done;
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sc->cur_addr = device_addr;
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sc->status = 0;
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}
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/* Clear interrupt status */
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RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
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/* Program data access address registers */
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daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0);
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RSB_WRITE(sc, RSB_DADDR0, daddr[0]);
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/* Write data */
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if ((msgs[1].flags & IIC_M_RD) == 0) {
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data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0);
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RSB_WRITE(sc, RSB_DATA0, data[0]);
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}
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/* Set command type */
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RSB_WRITE(sc, RSB_CMD, cmd);
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/* Program data length register and transfer direction */
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dlen = msgs[0].len - 1;
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if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD)
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dlen |= DLEN_READ;
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RSB_WRITE(sc, RSB_DLEN, dlen);
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/* Start transfer */
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error = rsb_start(dev);
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if (error != 0)
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goto done;
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/* Read data */
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if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) {
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data[0] = RSB_READ(sc, RSB_DATA0);
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rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0);
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}
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done:
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sc->msg = NULL;
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sc->busy = 0;
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wakeup(sc);
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RSB_UNLOCK(sc);
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return (error);
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}
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static void
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rsb_intr(void *arg)
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{
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struct rsb_softc *sc;
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uint32_t val;
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sc = arg;
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RSB_LOCK(sc);
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val = RSB_READ(sc, RSB_INTS);
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RSB_WRITE(sc, RSB_INTS, val);
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sc->status |= val;
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if ((sc->status & INT_MASK) != 0)
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wakeup(sc);
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RSB_UNLOCK(sc);
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}
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static int
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rsb_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner RSB");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rsb_attach(device_t dev)
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{
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struct rsb_softc *sc;
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int error;
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sc = device_get_softc(dev);
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mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF);
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if (clk_get_by_ofw_index(dev, 0, &sc->clk) == 0) {
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error = clk_enable(sc->clk);
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if (error != 0) {
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device_printf(dev, "cannot enable clock\n");
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goto fail;
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}
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}
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if (hwreset_get_by_ofw_idx(dev, 0, &sc->rst) == 0) {
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error = hwreset_deassert(sc->rst);
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if (error != 0) {
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device_printf(dev, "cannot de-assert reset\n");
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goto fail;
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}
|
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}
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if (bus_alloc_resources(dev, rsb_spec, sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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error = ENXIO;
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goto fail;
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}
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error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, rsb_intr, sc, &sc->ih);
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if (error != 0) {
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device_printf(dev, "cannot setup interrupt handler\n");
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goto fail;
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}
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sc->iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->iicbus == NULL) {
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device_printf(dev, "cannot add iicbus child device\n");
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error = ENXIO;
|
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goto fail;
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}
|
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bus_generic_attach(dev);
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||||
|
||||
return (0);
|
||||
|
||||
fail:
|
||||
if (sc->ih != NULL)
|
||||
bus_teardown_intr(dev, sc->res[1], sc->ih);
|
||||
bus_release_resources(dev, rsb_spec, sc->res);
|
||||
if (sc->rst != NULL)
|
||||
hwreset_release(sc->rst);
|
||||
if (sc->clk != NULL)
|
||||
clk_release(sc->clk);
|
||||
mtx_destroy(&sc->mtx);
|
||||
return (error);
|
||||
}
|
||||
|
||||
static device_method_t rsb_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, rsb_probe),
|
||||
DEVMETHOD(device_attach, rsb_attach),
|
||||
|
||||
/* OFW methods */
|
||||
DEVMETHOD(ofw_bus_get_node, rsb_get_node),
|
||||
|
||||
/* iicbus interface */
|
||||
DEVMETHOD(iicbus_callback, iicbus_null_callback),
|
||||
DEVMETHOD(iicbus_reset, rsb_reset),
|
||||
DEVMETHOD(iicbus_transfer, rsb_transfer),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t rsb_driver = {
|
||||
"iichb",
|
||||
rsb_methods,
|
||||
sizeof(struct rsb_softc),
|
||||
};
|
||||
|
||||
static devclass_t rsb_devclass;
|
||||
|
||||
DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0);
|
||||
DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0);
|
||||
MODULE_VERSION(rsb, 1);
|
||||
Loading…
Reference in New Issue
Block a user