hdac_intr_handler: keep working until global interrupt status clears
It is plausible that the hardware interrupts a host only when GIS goes from zero to one. GIS is formed by OR-ing multiple hardware statuses, so it's possible that a previously cleared status gets set again while another status has not been cleared yet. Thus, there will be no new interrupt as GIS always stayed set. If we don't re-examine GIS then we can leave it set and never get another interrupt again. Without this change I frequently saw a problem where snd_hda would stop working. Setting dev.hdac.1.polling=1 would bring it back to life and afterwards I could set polling back to zero. Sometimes the problem started right after a boot, sometimes it happened after resuming from S3, frequently it would occur when sound output and input are active concurrently (such as during conferencing). I looked at HDAC_INTSTS while the sound was not working and I saw that both HDAC_INTSTS_GIS and HDAC_INTSTS_CIS were set, but there were no interrupts. I have collected some statistics over a period of several days about how many loops (calls to hdac_one_intr) the new code did for a single interrupt: +--------+--------------+ |Loops |Times Happened| +--------+--------------+ |0 |301 | |1 |12857746 | |2 |280 | |3 |2 | |4+ |0 | +--------+--------------+ I believe that previously the sound would get stuck each time we had to loop more than once. The tested hardware is: hdac1: <AMD (0x15e3) HDA Controller> mem 0xfe680000-0xfe687fff at device 0.6 on pci4 hdacc1: <Realtek ALC269 HDA CODEC> at cad 0 on hdac1 No objections: mav MFC after: 5 weeks Differential Revision: https://reviews.freebsd.org/D25128
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=362294
@ -303,30 +303,13 @@ hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
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}
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}
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/****************************************************************************
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* void hdac_intr_handler(void *)
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*
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* Interrupt handler. Processes interrupts received from the hdac.
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****************************************************************************/
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static void
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hdac_intr_handler(void *context)
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hdac_one_intr(struct hdac_softc *sc, uint32_t intsts)
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{
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struct hdac_softc *sc;
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device_t dev;
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uint32_t intsts;
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uint8_t rirbsts;
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int i;
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sc = (struct hdac_softc *)context;
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hdac_lock(sc);
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/* Do we have anything to do? */
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intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
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if ((intsts & HDAC_INTSTS_GIS) == 0) {
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hdac_unlock(sc);
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return;
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}
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/* Was this a controller interrupt? */
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if (intsts & HDAC_INTSTS_CIS) {
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rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
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@ -346,16 +329,45 @@ hdac_intr_handler(void *context)
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if ((intsts & (1 << i)) == 0)
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continue;
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HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
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HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
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HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
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if ((dev = sc->streams[i].dev) != NULL) {
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HDAC_STREAM_INTR(dev,
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sc->streams[i].dir, sc->streams[i].stream);
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}
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}
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}
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}
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HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
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/****************************************************************************
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* void hdac_intr_handler(void *)
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*
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* Interrupt handler. Processes interrupts received from the hdac.
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****************************************************************************/
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static void
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hdac_intr_handler(void *context)
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{
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struct hdac_softc *sc;
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uint32_t intsts;
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sc = (struct hdac_softc *)context;
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/*
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* Loop until HDAC_INTSTS_GIS gets clear.
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* It is plausible that hardware interrupts a host only when GIS goes
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* from zero to one. GIS is formed by OR-ing multiple hardware
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* statuses, so it's possible that a previously cleared status gets set
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* again while another status has not been cleared yet. Thus, there
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* will be no new interrupt as GIS always stayed set. If we don't
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* re-examine GIS then we can leave it set and never get an interrupt
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* again.
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*/
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intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
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while ((intsts & HDAC_INTSTS_GIS) != 0) {
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hdac_lock(sc);
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hdac_one_intr(sc, intsts);
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hdac_unlock(sc);
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intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
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}
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}
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static void
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