Use the newer "+" modifier on output contraints when a register or
memory datum is used for both input and output instead of using matching constraints.
This commit is contained in:
parent
3d5500fc51
commit
4c86c028ac
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=105958
@ -372,8 +372,8 @@ alpha_pal_wripir(u_int64_t ipir)
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register u_int64_t a0 __asm__("$16") = ipir;
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__asm__ __volatile__ (
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"call_pal 0xd #PAL_ipir"
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: "=r" (a0)
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: "0" (a0)
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: "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -395,8 +395,8 @@ alpha_pal_wrmces(u_int64_t mces)
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register u_int64_t a0 __asm__("$16") = mces;
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__asm__ __volatile__ (
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"call_pal 0x11 #PAL_wrmces"
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: "=r" (a0)
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: "0" (a0)
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: "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -406,8 +406,8 @@ alpha_pal_wrfen(u_int64_t fen)
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register u_int64_t a0 __asm__("$16") = fen;
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__asm__ __volatile__ (
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"call_pal 0x2b #PAL_wrfen"
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: "=r" (a0)
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: "0" (a0)
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: "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -417,8 +417,8 @@ alpha_pal_wrvptptr(u_int64_t vptptr)
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register u_int64_t a0 __asm__("$16") = vptptr;
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__asm__ __volatile__ (
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"call_pal 0x2d #PAL_wrvptptr"
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: "=r" (a0)
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: "0" (a0)
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: "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -429,8 +429,8 @@ alpha_pal_swpctx(u_int64_t pcb)
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register u_int64_t v0 __asm__("$0");
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__asm__ __volatile__ (
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"call_pal 0x30 #PAL_OSF1_swpctx"
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: "=r" (v0), "=r" (a0)
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: "1" (a0)
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: "=r" (v0), "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25", "memory");
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return v0;
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}
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@ -441,8 +441,8 @@ alpha_pal_wrval(u_int64_t sysvalue)
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register u_int64_t a0 __asm__("$16") = sysvalue;
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__asm__ __volatile__ (
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"call_pal 0x31 #PAL_wrval"
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: "=r" (a0)
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: "0" (a0)
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: "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -465,8 +465,8 @@ alpha_pal_tbi(u_int64_t op, u_int64_t va)
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register u_int64_t a1 __asm__("$17") = va;
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__asm__ __volatile__ (
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"call_pal 0x33 #PAL_OSF1_tbi"
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: "=r" (a0), "=r" (a1)
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: "0" (a0), "1" (a1)
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: "+r" (a0), "+r" (a1)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -477,8 +477,8 @@ alpha_pal_wrent(void *ent, u_int64_t which)
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register u_int64_t a1 __asm__("$17") = which;
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__asm__ __volatile__ (
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"call_pal 0x34 #PAL_OSF1_wrent"
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: "=r" (a0), "=r" (a1)
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: "0" (a0), "1" (a1)
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: "+r" (a0), "+r" (a1)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -489,8 +489,8 @@ alpha_pal_swpipl(u_int64_t newipl)
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register u_int64_t v0 __asm__("$0");
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__asm__ __volatile__ (
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"call_pal 0x35 #PAL_OSF1_swpipl"
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: "=r" (v0), "=r" (a0)
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: "1" (a0)
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: "=r" (v0), "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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return v0;
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}
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@ -513,8 +513,8 @@ alpha_pal_wrusp(u_int64_t usp)
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register u_int64_t a0 __asm__("$16") = usp;
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__asm__ __volatile__ (
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"call_pal 0x38 #PAL_wrusp"
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: "=r" (a0)
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: "0" (a0)
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: "+r" (a0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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}
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@ -526,8 +526,8 @@ alpha_pal_wrperfmon(u_int64_t arg0, u_int64_t arg1)
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register u_int64_t a1 __asm__("$17") = arg1;
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__asm__ __volatile__ (
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"call_pal 0x39 #PAL_OSF1_wrperfmon"
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: "=r" (a0), "=r" (a1), "=r" (v0)
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: "0" (a0), "1" (a1)
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: "+r" (a0), "+r" (a1), "=r" (v0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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return v0;
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}
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@ -72,16 +72,16 @@ static __inline void atomic_clear_32(volatile u_int32_t *p, u_int32_t v)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldl_l %0, %2\n\t" /* load old value */
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"bic %0, %3, %0\n\t" /* calculate new value */
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"1:\tldl_l %0, %1\n\t" /* load old value */
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"bic %0, %2, %0\n\t" /* calculate new value */
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"stl_c %0, %1\n\t" /* attempt to store */
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"beq %0, 2f\n\t" /* spin if failed */
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"mb\n\t" /* drain to memory */
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"2:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (temp), "=m" (*p)
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: "m" (*p), "r" (v)
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: "=&r" (temp), "+m" (*p)
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: "r" (v)
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: "memory");
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#endif
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}
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@ -92,16 +92,16 @@ static __inline void atomic_add_32(volatile u_int32_t *p, u_int32_t v)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldl_l %0, %2\n\t" /* load old value */
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"addl %0, %3, %0\n\t" /* calculate new value */
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"1:\tldl_l %0, %1\n\t" /* load old value */
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"addl %0, %2, %0\n\t" /* calculate new value */
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"stl_c %0, %1\n\t" /* attempt to store */
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"beq %0, 2f\n\t" /* spin if failed */
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"mb\n\t" /* drain to memory */
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"2:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (temp), "=m" (*p)
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: "m" (*p), "r" (v)
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: "=&r" (temp), "+m" (*p)
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: "r" (v)
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: "memory");
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#endif
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}
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@ -112,16 +112,16 @@ static __inline void atomic_subtract_32(volatile u_int32_t *p, u_int32_t v)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldl_l %0, %2\n\t" /* load old value */
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"subl %0, %3, %0\n\t" /* calculate new value */
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"1:\tldl_l %0, %1\n\t" /* load old value */
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"subl %0, %2, %0\n\t" /* calculate new value */
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"stl_c %0, %1\n\t" /* attempt to store */
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"beq %0, 2f\n\t" /* spin if failed */
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"mb\n\t" /* drain to memory */
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"2:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (temp), "=m" (*p)
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: "m" (*p), "r" (v)
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: "=&r" (temp), "+m" (*p)
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: "r" (v)
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: "memory");
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#endif
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}
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@ -133,15 +133,15 @@ static __inline u_int32_t atomic_readandclear_32(volatile u_int32_t *addr)
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#ifdef __GNUC__
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__asm __volatile (
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"wmb\n" /* ensure pending writes have drained */
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"1:\tldl_l %0,%3\n\t" /* load current value, asserting lock */
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"1:\tldl_l %0,%2\n\t" /* load current value, asserting lock */
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"ldiq %1,0\n\t" /* value to store */
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"stl_c %1,%2\n\t" /* attempt to store */
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"beq %1,2f\n\t" /* if the store failed, spin */
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"br 3f\n" /* it worked, exit */
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"2:\tbr 1b\n" /* *addr not updated, loop */
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"3:\tmb\n" /* it worked */
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: "=&r"(result), "=&r"(temp), "=m" (*addr)
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: "m"(*addr)
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: "=&r"(result), "=&r"(temp), "+m" (*addr)
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:
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: "memory");
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#endif
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@ -154,16 +154,16 @@ static __inline void atomic_set_64(volatile u_int64_t *p, u_int64_t v)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldq_l %0, %2\n\t" /* load old value */
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"bis %0, %3, %0\n\t" /* calculate new value */
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"1:\tldq_l %0, %1\n\t" /* load old value */
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"bis %0, %2, %0\n\t" /* calculate new value */
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"stq_c %0, %1\n\t" /* attempt to store */
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"beq %0, 2f\n\t" /* spin if failed */
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"mb\n\t" /* drain to memory */
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"2:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (temp), "=m" (*p)
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: "m" (*p), "r" (v)
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: "=&r" (temp), "+m" (*p)
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: "r" (v)
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: "memory");
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#endif
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}
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@ -174,16 +174,16 @@ static __inline void atomic_clear_64(volatile u_int64_t *p, u_int64_t v)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldq_l %0, %2\n\t" /* load old value */
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"bic %0, %3, %0\n\t" /* calculate new value */
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"1:\tldq_l %0, %1\n\t" /* load old value */
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"bic %0, %2, %0\n\t" /* calculate new value */
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"stq_c %0, %1\n\t" /* attempt to store */
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"beq %0, 2f\n\t" /* spin if failed */
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"mb\n\t" /* drain to memory */
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"2:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (temp), "=m" (*p)
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: "m" (*p), "r" (v)
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: "=&r" (temp), "+m" (*p)
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: "r" (v)
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: "memory");
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#endif
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}
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@ -194,16 +194,16 @@ static __inline void atomic_add_64(volatile u_int64_t *p, u_int64_t v)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldq_l %0, %2\n\t" /* load old value */
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"addq %0, %3, %0\n\t" /* calculate new value */
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"1:\tldq_l %0, %1\n\t" /* load old value */
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"addq %0, %2, %0\n\t" /* calculate new value */
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"stq_c %0, %1\n\t" /* attempt to store */
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"beq %0, 2f\n\t" /* spin if failed */
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"mb\n\t" /* drain to memory */
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"2:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (temp), "=m" (*p)
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: "m" (*p), "r" (v)
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: "=&r" (temp), "+m" (*p)
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: "r" (v)
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: "memory");
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#endif
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}
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@ -214,16 +214,16 @@ static __inline void atomic_subtract_64(volatile u_int64_t *p, u_int64_t v)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldq_l %0, %2\n\t" /* load old value */
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"subq %0, %3, %0\n\t" /* calculate new value */
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"1:\tldq_l %0, %1\n\t" /* load old value */
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"subq %0, %2, %0\n\t" /* calculate new value */
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"stq_c %0, %1\n\t" /* attempt to store */
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"beq %0, 2f\n\t" /* spin if failed */
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"mb\n\t" /* drain to memory */
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"2:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (temp), "=m" (*p)
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: "m" (*p), "r" (v)
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: "=&r" (temp), "+m" (*p)
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: "r" (v)
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: "memory");
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#endif
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}
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@ -235,15 +235,15 @@ static __inline u_int64_t atomic_readandclear_64(volatile u_int64_t *addr)
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#ifdef __GNUC__
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__asm __volatile (
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"wmb\n" /* ensure pending writes have drained */
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"1:\tldq_l %0,%3\n\t" /* load current value, asserting lock */
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"1:\tldq_l %0,%2\n\t" /* load current value, asserting lock */
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"ldiq %1,0\n\t" /* value to store */
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"stq_c %1,%2\n\t" /* attempt to store */
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"beq %1,2f\n\t" /* if the store failed, spin */
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"br 3f\n" /* it worked, exit */
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"2:\tbr 1b\n" /* *addr not updated, loop */
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"3:\tmb\n" /* it worked */
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: "=&r"(result), "=&r"(temp), "=m" (*addr)
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: "m"(*addr)
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: "=&r"(result), "=&r"(temp), "+m" (*addr)
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:
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: "memory");
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#endif
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@ -376,7 +376,7 @@ atomic_cmpset_32(volatile u_int32_t* p, u_int32_t cmpval, u_int32_t newval)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldl_l %0, %4\n\t" /* load old value */
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"1:\tldl_l %0, %1\n\t" /* load old value */
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"cmpeq %0, %2, %0\n\t" /* compare */
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"beq %0, 2f\n\t" /* exit if not equal */
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"mov %3, %0\n\t" /* value to store */
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@ -387,8 +387,8 @@ atomic_cmpset_32(volatile u_int32_t* p, u_int32_t cmpval, u_int32_t newval)
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"3:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (ret), "=m" (*p)
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: "r" ((long)(int)cmpval), "r" (newval), "m" (*p)
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: "=&r" (ret), "+m" (*p)
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: "r" ((long)(int)cmpval), "r" (newval)
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: "memory");
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#endif
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@ -407,7 +407,7 @@ atomic_cmpset_64(volatile u_int64_t* p, u_int64_t cmpval, u_int64_t newval)
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#ifdef __GNUC__
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__asm __volatile (
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"1:\tldq_l %0, %4\n\t" /* load old value */
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"1:\tldq_l %0, %1\n\t" /* load old value */
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"cmpeq %0, %2, %0\n\t" /* compare */
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"beq %0, 2f\n\t" /* exit if not equal */
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"mov %3, %0\n\t" /* value to store */
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@ -418,8 +418,8 @@ atomic_cmpset_64(volatile u_int64_t* p, u_int64_t cmpval, u_int64_t newval)
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".section .text3,\"ax\"\n" /* improve branch prediction */
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"3:\tbr 1b\n" /* try again */
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".previous\n"
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: "=&r" (ret), "=m" (*p)
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: "r" (cmpval), "r" (newval), "m" (*p)
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: "=&r" (ret), "+m" (*p)
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: "r" (cmpval), "r" (newval)
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: "memory");
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#endif
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