sfxge: pick up the new TLV structures
The header is auto-generated from firmware sources. Sponsored by: Solarflare Communications, Inc. MFC after: 2 days
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=291849
@ -194,7 +194,9 @@ struct tlv_port_mac {
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/* Static VPD.
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*
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* This is the portion of VPD which is set at manufacturing time and not
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* expected to change. It is formatted as a standard PCI VPD block.
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* expected to change. It is formatted as a standard PCI VPD block. There are
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* global and per-pf TLVs for this, the global TLV is new for Medford and is
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* used in preference to the per-pf TLV.
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*/
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#define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
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@ -205,11 +207,21 @@ struct tlv_pf_static_vpd {
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uint8_t bytes[];
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};
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#define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
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struct tlv_global_static_vpd {
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uint32_t tag;
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uint32_t length;
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uint8_t bytes[];
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};
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/* Dynamic VPD.
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*
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* This is the portion of VPD which may be changed (e.g. by firmware updates).
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* It is formatted as a standard PCI VPD block.
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* It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
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* for this, the global TLV is new for Medford and is used in preference to the
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* per-pf TLV.
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*/
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#define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
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@ -220,11 +232,21 @@ struct tlv_pf_dynamic_vpd {
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uint8_t bytes[];
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};
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#define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
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struct tlv_global_dynamic_vpd {
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uint32_t tag;
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uint32_t length;
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uint8_t bytes[];
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};
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/* "DBI" PCI config space changes.
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*
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* This is a set of edits made to the default PCI config space values before
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* the device is allowed to enumerate.
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* the device is allowed to enumerate. There are global and per-pf TLVs for
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* this, the global TLV is new for Medford and is used in preference to the
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* per-pf TLV.
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*/
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#define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
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@ -240,6 +262,19 @@ struct tlv_pf_dbi {
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};
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#define TLV_TAG_GLOBAL_DBI (0x00210000)
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struct tlv_global_dbi {
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uint32_t tag;
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uint32_t length;
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struct {
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uint16_t addr;
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uint16_t byte_enables;
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uint32_t value;
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} items[];
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};
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/* Partition subtype codes.
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*
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* A subtype may optionally be stored for each type of partition present in
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@ -289,7 +324,7 @@ struct tlv_pcie_config {
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int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
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uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
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uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
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uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
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uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
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#define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
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#define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
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};
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@ -305,13 +340,13 @@ struct tlv_per_pf_pcie_config {
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uint32_t tag;
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uint32_t length;
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uint8_t vfs_total;
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uint8_t port_allocation;
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uint8_t port_allocation;
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uint16_t vectors_per_pf;
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uint16_t vectors_per_vf;
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uint8_t pf_bar0_aperture;
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uint8_t pf_bar2_aperture;
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uint8_t vf_bar0_aperture;
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uint8_t vf_base;
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uint8_t vf_base;
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uint16_t supp_pagesz;
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uint16_t msix_vec_base;
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};
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@ -320,7 +355,8 @@ struct tlv_per_pf_pcie_config {
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/* Development ONLY. This is a single TLV tag for all the gubbins
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* that can be set through the MC command-line other than the PCIe
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* settings. This is a temporary measure. */
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#define TLV_TAG_TMP_GUBBINS (0x10090000)
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#define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
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#define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
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struct tlv_tmp_gubbins {
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uint32_t tag;
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@ -393,16 +429,16 @@ struct tlv_firmware_options {
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};
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/* Voltage settings
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*
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*
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* Intended for boards with A0 silicon where the core voltage may
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* need tweaking. Most likely set once when the pass voltage is
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* need tweaking. Most likely set once when the pass voltage is
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* determined. */
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#define TLV_TAG_0V9_SETTINGS (0x000c0000)
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struct tlv_0v9_settings {
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uint32_t tag;
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uint32_t length;
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uint32_t length;
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uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
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#define TLV_TAG_0V9_REQUIRES_FAN (1)
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uint16_t target_voltage; /* In millivolts */
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@ -411,17 +447,18 @@ struct tlv_0v9_settings {
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uint16_t warn_low; /* In millivolts */
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uint16_t warn_high; /* In millivolts */
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uint16_t panic_low; /* In millivolts */
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uint16_t panic_high; /* In millivolts */
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uint16_t panic_high; /* In millivolts */
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};
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/* Clock configuration */
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#define TLV_TAG_CLOCK_CONFIG (0x000d0000)
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#define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
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#define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
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struct tlv_clock_config {
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uint32_t tag;
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uint32_t length;
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uint32_t length;
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uint16_t clk_sys; /* MHz */
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uint16_t clk_dpcpu; /* MHz */
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uint16_t clk_icore; /* MHz */
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@ -460,7 +497,8 @@ struct tlv_global_mac {
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uint16_t reserved2;
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};
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#define TLV_TAG_ATB_0V9_TARGET (0x000f0000)
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#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
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#define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
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/* The target value for the 0v9 power rail measured on-chip at the
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* analogue test bus */
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@ -485,7 +523,7 @@ struct tlv_pcie_config_r2 {
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uint16_t visible_pfs; /**< Bitmap of visible PFs */
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uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
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uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
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uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
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uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
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};
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/* Dynamic port mode.
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