Driver 'pmspcv' added. Supports PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 SAS/SATA HBA Controllers.

svn path=/projects/pms/; revision=285242

sys/amd64/conf/GENERIC

@@ -170,6 +170,7 @@ device		ida			# Compaq Smart RAID
 device		mfi			# LSI MegaRAID SAS
 device		mlx			# Mylex DAC960 family
 device		mrsas			# LSI/Avago MegaRAID SAS/SATA, 6Gb/s and 12Gb/s
+device		pmspcv			# PMC-Sierra SAS/SATA Controller driver
 #XXX pointer/int warnings
 #device		pst			# Promise Supertrak SX6000
 device		twe			# 3ware ATA RAID

sys/amd64/conf/NOTES

@@ -485,6 +485,10 @@ options 	ISCI_LOGGING	# enable debugging in isci HAL
 device         nvme    # base NVMe driver
 device         nvd     # expose NVMe namespaces as disks, depends on nvme
 
+#
+# PMC-Sierra SAS/SATA controller
+device		pmspcv
+
 #
 # SafeNet crypto driver: can be moved to the MI NOTES as soon as
 # it's tested on a big-endian machine

sys/conf/files

@@ -2053,6 +2053,102 @@ dev/pdq/if_fea.c		optional fea eisa
 dev/pdq/if_fpa.c		optional fpa pci
 dev/pdq/pdq.c			optional nowerror fea eisa | fpa pci
 dev/pdq/pdq_ifsubr.c		optional nowerror fea eisa | fpa pci
+dev/pms/freebsd/driver/ini/src/agtiapi.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sadisc.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/mpi.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/saframe.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sahw.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sainit.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/saint.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sampicmd.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sampirsp.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/saphy.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/saport.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sasata.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sasmp.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sassp.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/satimer.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/sautil.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sallsdk/spc/mpidebug.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/discovery/dm/dminit.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/discovery/dm/dmsmp.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/discovery/dm/dmdisc.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/discovery/dm/dmport.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/discovery/dm/dmtimer.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/discovery/dm/dmmisc.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sat/src/sminit.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sat/src/smmisc.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sat/src/smsat.c				optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sat/src/smsatcb.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sat/src/smsathw.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/sat/src/smtimer.c			optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdinit.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdmisc.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdesgl.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdport.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdint.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdioctl.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdhw.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/ossacmnapi.c	optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tddmcmnapi.c	optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdsmcmnapi.c	optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/common/tdtimers.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/sas/ini/itdio.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/sas/ini/itdcb.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/sas/ini/itdinit.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/sas/ini/itddisc.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/sata/host/sat.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/sata/host/ossasat.c	optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
+dev/pms/RefTisa/tisa/sassata/sata/host/sathw.c		optional pmspcv \
+	compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
 dev/ppbus/if_plip.c		optional plip
 dev/ppbus/immio.c		optional vpo
 dev/ppbus/lpbb.c		optional lpbb

sys/dev/pms/RefTisa/discovery/api/dm.h

@@ -0,0 +1,163 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+**    
+*   dm.h 
+*
+*   Abstract:   This module defines the contants, enum and #define definition used
+*               by Discovery Moduled (DM).
+*     
+********************************************************************************/
+
+#ifndef DM_H
+
+#define DM_H
+
+/*************************************************
+ *   constants for type field in agsaMem_t
+ *************************************************/
+#define DM_CACHED_MEM                             0x00     /**< CACHED memory type */
+#define DM_DMA_MEM                                0x01     /**< DMA memory type */
+#define DM_CACHED_DMA_MEM                         0x02     /**< CACHED DMA memory type */
+
+/*************************************************
+ *   constants for API return values
+ *************************************************/
+#define DM_RC_SUCCESS                             0x00     /**< Successful function return value */
+#define DM_RC_FAILURE                             0x01     /**< Failed function return value */
+#define DM_RC_BUSY                                0x02     /**< Busy function return value */
+#define DM_RC_VERSION_INCOMPATIBLE                0x03     /**< Version miss match */
+#define DM_RC_VERSION_UNTESTED                    0x04     /**< Version not tested */
+
+
+
+/*************************************************
+ *   Discovery option
+ *************************************************/
+#define DM_DISCOVERY_OPTION_FULL_START			0x00     /**< Full discovery */
+#define DM_DISCOVERY_OPTION_INCREMENTAL_START		0x01     /**< Incremental discovery */
+#define DM_DISCOVERY_OPTION_ABORT			0x02     /**< Discovery abort */
+
+
+/*************************************************
+ *   Discovery status
+ *************************************************/
+enum dmDiscoveryState_e
+{
+  dmDiscCompleted  = 0,
+  dmDiscFailed,
+  dmDiscAborted,
+  dmDiscAbortFailed,
+  dmDiscInProgress,
+  dmDiscAbortInvalid, /* no discovery to abort */   
+  dmDiscAbortInProgress, /* abort in progress */   
+
+};
+
+/*************************************************
+ *   Device status
+ *************************************************/
+enum dmDeviceState_e
+{
+  dmDeviceNoChange = 0,
+  dmDeviceArrival,
+  dmDeviceRemoval,
+  dmDeviceMCNChange,
+  dmDeviceRateChange,
+};
+
+typedef struct  dmContext_s {
+		void		*tdData;
+		void		*dmData;
+} dmContext_t;
+
+typedef struct{
+        bit16	smpTimeout;
+        bit16	it_NexusTimeout;
+        bit16	firstBurstSize;
+        bit8	 flag;
+        bit8	 devType_S_Rate;
+        bit8 	sasAddressHi[4]; 
+        bit8 	sasAddressLo[4];
+        bit8    initiator_ssp_stp_smp;
+        bit8    target_ssp_stp_smp;
+        /* bit8 - bit14 are set by the user of DM such as TDM for directly attached expander
+           0 - 7; PhyID 
+           8: non SMP or not
+           9 - 10: types of expander, valid only when bit8 is set
+                   10b (2): edge expander
+                   11b (3): fanout expander
+           11 - 14: MCN
+        */
+        bit16   ext;
+        bit8    sataDeviceType;
+        bit8    reserved;
+} dmDeviceInfo_t;
+
+
+typedef struct{
+	void 	*virtPtr;
+	void 	*osHandle;
+	bit32 	physAddrUpper;
+	bit32 	physAddrLower;
+	bit32 	totalLength;
+	bit32 	numElements;
+	bit32 	singleElementLength;
+	bit32 	alignment;
+	bit32 	type;
+	bit32 	reserved;
+} dmMem_t;
+
+#define DM_NUM_MEM_CHUNKS 8
+
+typedef struct{
+	bit32 		count;
+	dmMem_t 	dmMemory[DM_NUM_MEM_CHUNKS];
+} dmMemoryRequirement_t;
+
+typedef    dmContext_t    dmPortContext_t;
+
+typedef    dmContext_t    dmRoot_t;
+
+typedef struct{
+ bit32   numDevHandles;
+ bit32   tbd1;
+ bit32   tbd2;
+#ifdef DM_DEBUG
+ bit32   DMDebugLevel;
+#endif
+ bit32   itNexusTimeout;
+} dmSwConfig_t;
+
+typedef struct{
+               bit8  	sasRemoteAddressHi[4]; 
+               bit8  	sasRemoteAddressLo[4]; 
+               bit8  	sasLocalAddressHi[4]; 
+               bit8  	sasLocalAddressLo[4]; 
+               bit32    flag;
+} dmPortInfo_t;
+
+
+#endif  /* DM_H */

sys/dev/pms/RefTisa/discovery/api/dmapi.h

@@ -0,0 +1,89 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+**
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+*   dmapi.h 
+*
+*   Abstract:   This module contains function prototype of the Discovery
+*               Module (DM) API for initiator.
+*******************************************************************************/
+
+#ifndef DMAPI_H
+#define DMAPI_H
+
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+
+osGLOBAL bit32  dmCreatePort(  
+       dmRoot_t        *dmRoot,
+       dmPortContext_t *dmPortContext,
+       dmPortInfo_t    *dmPortInfo);
+
+osGLOBAL bit32  dmDestroyPort(  
+       dmRoot_t        *dmRoot,
+       dmPortContext_t *dmPortContext,
+       dmPortInfo_t    *dmPortInfo);
+
+osGLOBAL bit32  dmRegisterDevice(  
+       dmRoot_t        *dmRoot,
+       dmPortContext_t *dmPortContext,
+       dmDeviceInfo_t  *dmDeviceInfo,
+       agsaDevHandle_t *agDevHandle);
+
+osGLOBAL bit32  dmDiscover(  
+       dmRoot_t        *dmRoot,
+       dmPortContext_t *dmPortContext,
+       bit32            option);
+
+osGLOBAL void dmGetRequirements(
+       dmRoot_t              *dmRoot,
+       dmSwConfig_t          *swConfig,
+       dmMemoryRequirement_t *memoryRequirement,
+       bit32                 *usecsPerTick,
+       bit32                 *maxNumLocks);
+
+osGLOBAL void dmNotifyBC(
+       dmRoot_t        *dmRoot,
+       dmPortContext_t *dmPortContext,
+       bit32            type);
+
+osGLOBAL bit32  dmQueryDiscovery(  
+       dmRoot_t        *dmRoot,
+       dmPortContext_t *dmPortContext);
+       
+osGLOBAL bit32 	
+dmResetFailedDiscovery(  
+                 dmRoot_t               *dmRoot,
+                 dmPortContext_t        *dmPortContext);
+
+osGLOBAL bit32  dmInitialize(
+       dmRoot_t             *dmRoot,
+       agsaRoot_t           *agRoot,
+       dmMemoryRequirement_t *memoryAllocated,
+       dmSwConfig_t          *swConfig,
+       bit32                 usecsPerTick );
+
+osGLOBAL void   dmTimerTick ( dmRoot_t  *dmRoot );
+
+#endif  /* DMAPI_H */

sys/dev/pms/RefTisa/discovery/api/tddmapi.h

@@ -0,0 +1,119 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+*   tmdmapi.h 
+*
+*   Abstract:   This module contains function prototype of the Discovery
+*               Module (DM) API callback for initiator.
+*******************************************************************************/
+
+#ifndef TDDMAPI_H
+
+#define TDDMAPI_H
+
+osGLOBAL void tddmCacheFlush(
+				dmRoot_t 	*dmRoot,
+				void 		*tdMemHandle,
+				void 		*virtPtr,
+				bit32 		length
+				);
+
+osGLOBAL void tddmCacheInvalidate(
+				dmRoot_t 	*dmRoot,
+				void 		*tdMemHandle,
+				void 		*virtPtr,
+				bit32 		length
+				);
+
+osGLOBAL void tddmCachePreFlush(
+				dmRoot_t 	*dmRoot,
+				void 		*tdMemHandle,
+				void 		*virtPtr,
+				bit32 		length
+				);
+
+osGLOBAL void tddmDiscoverCB(
+				dmRoot_t 		*dmRoot,
+				dmPortContext_t		*dmPortContext,
+				bit32			eventStatus
+				);
+
+osGLOBAL void tddmQueryDiscoveryCB(
+				dmRoot_t 		*dmRoot,
+				dmPortContext_t		*dmPortContext,
+				bit32          		discType,
+				bit32			discState
+				);
+
+osGLOBAL void tddmReportDevice(
+				dmRoot_t 		*dmRoot,
+				dmPortContext_t		*dmPortContext,
+				dmDeviceInfo_t		*dmDeviceInfo,
+                                dmDeviceInfo_t		*dmExpDeviceInfo,
+				bit32                   flag				
+				);
+
+osGLOBAL bit8 tddmSATADeviceTypeDecode(bit8 * pSignature);
+
+osGLOBAL void tddmSingleThreadedEnter(
+				       dmRoot_t 		*dmRoot,
+				       bit32    		syncLockId
+				      );
+				      
+osGLOBAL void tddmSingleThreadedLeave(
+				       dmRoot_t 		*dmRoot,
+				       bit32    		syncLockId
+				      );
+osGLOBAL bit32 tddmGetTransportParam(
+                        dmRoot_t    *dmRoot,
+                        char        *key,
+                        char        *subkey1,
+                        char        *subkey2,
+                        char        *subkey3,
+                        char        *subkey4,
+                        char        *subkey5,
+                        char        *valueName,
+                        char        *buffer,
+                        bit32       bufferLen,
+                        bit32       *lenReceived
+                        );
+osGLOBAL bit32 
+tddmRotateQnumber(
+                  dmRoot_t          *dmRoot,
+                  agsaDevHandle_t   *agDevHandle
+                 );
+#ifndef tddmLogDebugString 
+GLOBAL void tddmLogDebugString(
+                         dmRoot_t     *dmRoot,
+                         bit32        level,
+                         char         *string,
+                         void         *ptr1,
+                         void         *ptr2,
+                         bit32        value1,
+                         bit32        value2
+                         );
+#endif
+
+
+#endif  /* TDDMAPI_H */

sys/dev/pms/RefTisa/discovery/dm/dminit.c

@@ -0,0 +1,933 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+
+#include <dev/pms/RefTisa/discovery/dm/dmdefs.h>
+#include <dev/pms/RefTisa/discovery/dm/dmtypes.h>
+#include <dev/pms/RefTisa/discovery/dm/dmproto.h>
+
+#ifdef DM_DEBUG
+bit32 gDMDebugLevel = 1;
+#endif
+
+osGLOBAL void	
+dmGetRequirements(
+                  dmRoot_t 	  		*dmRoot,
+                  dmSwConfig_t			*swConfig,
+                  dmMemoryRequirement_t		*memoryRequirement,
+                  bit32 			*usecsPerTick,
+                  bit32				*maxNumLocks)
+{
+  bit32               memoryReqCount = 0;
+  bit32               max_expander = DM_MAX_EXPANDER_DEV; 
+  char    *buffer;
+  bit32   buffLen;
+  bit32   lenRecv = 0;
+  static char    tmpBuffer[DEFAULT_KEY_BUFFER_SIZE];
+  char    *pLastUsedChar = agNULL;
+  char    globalStr[]     = "Global";
+  char    iniParmsStr[]   = "InitiatorParms";
+  char    SwParmsStr[]    = "SWParms";    
+   
+  DM_DBG3(("dmGetRequirements: start\n"));
+  /* sanity check */
+  DM_ASSERT((agNULL != swConfig), "");
+  DM_ASSERT((agNULL != memoryRequirement), "");
+  DM_ASSERT((agNULL != usecsPerTick), "");
+  DM_ASSERT((agNULL != maxNumLocks), ""); 
+  
+  /* memory requirement for dmRoot, CACHE memory */
+  memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].singleElementLength = sizeof(dmIntRoot_t);
+  memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].numElements = 1;
+  memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].totalLength = 
+      (memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].numElements);
+  memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].alignment = 4;
+  memoryRequirement->dmMemory[DM_ROOT_MEM_INDEX].type = DM_CACHED_MEM;
+  memoryReqCount++;
+  
+  /* memory requirement for Port Context Links, CACHE memory */
+  memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].singleElementLength = sizeof(dmIntPortContext_t);
+  memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].numElements = DM_MAX_PORT_CONTEXT; 
+  memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].totalLength = 
+      (memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].numElements);
+  memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].alignment = 4;
+  memoryRequirement->dmMemory[DM_PORT_MEM_INDEX].type = DM_CACHED_MEM;
+  memoryReqCount++;
+
+  /* memory requirement for Device Links, CACHE memory */
+  memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].singleElementLength = sizeof(dmDeviceData_t);
+  memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].numElements = DM_MAX_DEV; 
+  memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].totalLength = 
+      (memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].numElements);
+  memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].alignment = 4;
+  memoryRequirement->dmMemory[DM_DEVICE_MEM_INDEX].type = DM_CACHED_MEM;
+  memoryReqCount++;
+
+  /* memory requirement for Expander Device Links, CACHE memory */
+  /*
+     Maximum number of expanders are configurable
+     The default is DM_MAX_EXPANDER_DEV
+  */
+  buffer = tmpBuffer;
+  buffLen = sizeof(tmpBuffer);
+  
+  dm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  
+  if ((tddmGetTransportParam(
+                             dmRoot, 
+                             globalStr,
+                             iniParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "MaxExpanders",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == DM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      max_expander = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      max_expander = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+  }
+  DM_DBG3(("dmGetRequirements: max_expander %d\n", max_expander));
+  
+  
+  memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].singleElementLength = sizeof(dmExpander_t);
+  memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].numElements = max_expander; 
+  memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].totalLength = 
+      (memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].numElements);
+  memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].alignment = 4;
+  memoryRequirement->dmMemory[DM_EXPANDER_MEM_INDEX].type = DM_CACHED_MEM;
+  memoryReqCount++;
+
+  /* memory requirement for SMP command Links, CACHE memory */
+  memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].singleElementLength = sizeof(dmSMPRequestBody_t);
+  memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].numElements = DM_MAX_SMP; 
+  memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].totalLength = 
+      (memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].numElements);
+  memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].alignment = 4;
+  memoryRequirement->dmMemory[DM_SMP_MEM_INDEX].type = DM_CACHED_MEM;
+  memoryReqCount++;
+  
+  /* memory requirement for INDIRECT SMP command/response Links, DMA memory */
+  memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].singleElementLength = SMP_INDIRECT_PAYLOAD; /* 512 */
+  memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].numElements = DM_MAX_INDIRECT_SMP; 
+  memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].totalLength = 
+      (memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].singleElementLength) * (memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].numElements);
+  memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].alignment = 4;
+  memoryRequirement->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].type = DM_DMA_MEM;
+  memoryReqCount++;
+  
+  
+  /* set up memory requirement count */
+  memoryRequirement->count = memoryReqCount;
+  
+  /* requirement for locks */
+  *maxNumLocks = DM_MAX_LOCKS;   
+
+  /* setup the time tick */  
+  *usecsPerTick = DM_USECS_PER_TICK;
+
+
+  /* set up the number of Expander device handles */
+  swConfig->numDevHandles = DM_MAX_DEV;
+  swConfig->itNexusTimeout = IT_NEXUS_TIMEOUT;   /* default is 2000 ms*/
+
+  dm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  
+  if ((tddmGetTransportParam(
+                             dmRoot, 
+                             globalStr,
+                             SwParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "IT_NEXUS_TIMEOUT",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == DM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      swConfig->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      swConfig->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+  }
+
+  DM_DBG1(("dmGetRequirements: swConfig->itNexusTimeout 0x%X\n", swConfig->itNexusTimeout));
+  
+  DM_DBG3(("dmGetRequirements: memoryReqCount %d\n", memoryRequirement->count));
+
+  return;
+}	   				
+/*
+  ??? processing swConfig
+*/
+osGLOBAL bit32	
+dmInitialize(
+             dmRoot_t			*dmRoot,
+             agsaRoot_t                 *agRoot,
+             dmMemoryRequirement_t	*memoryAllocated,
+             dmSwConfig_t		*swConfig,
+             bit32			usecsPerTick )
+{
+  dmIntRoot_t               *dmIntRoot;
+  dmIntPortContext_t        *dmIntPortContext;
+  dmDeviceData_t            *dmDevice;  
+  dmExpander_t              *dmExpander;
+  dmSMPRequestBody_t        *dmSMPRequest; 
+  bit8                      *dmIndirectSMPRequest; 
+  dmIntContext_t            *dmAllShared;
+  bit32              i;
+  bit32               max_expander = DM_MAX_EXPANDER_DEV; 
+  char    *buffer;
+  bit32   buffLen;
+  bit32   lenRecv = 0;
+  static char    tmpBuffer[DEFAULT_KEY_BUFFER_SIZE];
+  char    *pLastUsedChar = agNULL;
+  char    globalStr[]     = "Global";
+  char    iniParmsStr[]   = "InitiatorParms";
+  char    SwParmsStr[]    = "SWParms"; 
+  
+  DM_DBG3(("dmInitialize: start\n"));
+  /* sanity check */  
+  DM_ASSERT((agNULL != dmRoot), "");
+  DM_ASSERT((agNULL != agRoot), "");
+  DM_ASSERT((agNULL != memoryAllocated), "");
+  DM_ASSERT((agNULL != swConfig), "");
+  DM_ASSERT((DM_ROOT_MEM_INDEX < memoryAllocated->count), "");
+  DM_ASSERT((DM_PORT_MEM_INDEX < memoryAllocated->count), "");
+  DM_ASSERT((DM_DEVICE_MEM_INDEX < memoryAllocated->count), "");
+  DM_ASSERT((DM_EXPANDER_MEM_INDEX < memoryAllocated->count), "");
+  DM_ASSERT((DM_SMP_MEM_INDEX < memoryAllocated->count), "");  
+  DM_ASSERT((DM_INDIRECT_SMP_MEM_INDEX < memoryAllocated->count), "");  
+
+  /* Check the memory allocated */
+  for ( i = 0; i < memoryAllocated->count; i ++ )
+  {
+    /* If memory allocatation failed  */
+    if (memoryAllocated->dmMemory[i].singleElementLength &&
+        memoryAllocated->dmMemory[i].numElements)
+    {
+      if ( (0 != memoryAllocated->dmMemory[i].numElements)
+          && (0 == memoryAllocated->dmMemory[i].totalLength) )
+      {
+        /* return failure */
+        DM_DBG1(("dmInitialize: Memory[%d]  singleElementLength = 0x%0x  numElements = 0x%x NOT allocated!!!\n",
+          i,
+          memoryAllocated->dmMemory[i].singleElementLength,
+          memoryAllocated->dmMemory[i].numElements));
+        return DM_RC_FAILURE;
+      }
+    }
+  }
+  
+  /* DM's internal root */
+  dmIntRoot  = (dmIntRoot_t *) (memoryAllocated->dmMemory[DM_ROOT_MEM_INDEX].virtPtr);
+  dmRoot->dmData = (void *) dmIntRoot;
+  
+  dmAllShared = (dmIntContext_t *)&(dmIntRoot->dmAllShared);
+  /**<  Initialize the TDM data part of the interrupt context */
+  dmAllShared->dmRootOsData.dmRoot     = dmRoot;
+  dmAllShared->dmRootOsData.dmAllShared   = (void *) dmAllShared;
+  
+  /* Port Contexts */
+  dmIntPortContext = (dmIntPortContext_t *) (memoryAllocated->dmMemory[DM_PORT_MEM_INDEX].virtPtr);
+  dmAllShared->PortContextMem = (dmIntPortContext_t *)dmIntPortContext;
+  
+  /* Devices */
+  dmDevice = (dmDeviceData_t *) (memoryAllocated->dmMemory[DM_DEVICE_MEM_INDEX].virtPtr);
+  dmAllShared->DeviceMem = (dmDeviceData_t *)dmDevice;
+  
+  /* Expanders */
+  dmExpander = (dmExpander_t *) (memoryAllocated->dmMemory[DM_EXPANDER_MEM_INDEX].virtPtr);
+  dmAllShared->ExpanderMem = (dmExpander_t *)dmExpander;
+  
+  /* SMP commands */
+  dmSMPRequest = (dmSMPRequestBody_t *) (memoryAllocated->dmMemory[DM_SMP_MEM_INDEX].virtPtr);
+  dmAllShared->SMPMem = (dmSMPRequestBody_t *)dmSMPRequest;
+
+  /* DMAable SMP request/reponse pointed by dmSMPRequestBody_t */
+  dmIndirectSMPRequest = (bit8 *) (memoryAllocated->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].virtPtr);
+  dmAllShared->IndirectSMPMem = (bit8 *)dmIndirectSMPRequest;
+  dmAllShared->IndirectSMPUpper32 = memoryAllocated->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].physAddrUpper;
+  dmAllShared->IndirectSMPLower32 = memoryAllocated->dmMemory[DM_INDIRECT_SMP_MEM_INDEX].physAddrLower;
+    
+  dmAllShared->agRoot = agRoot;
+  
+     
+  dmAllShared->usecsPerTick = usecsPerTick;	   
+  dmAllShared->itNexusTimeout = IT_NEXUS_TIMEOUT;/*swConfig->itNexusTimeout;*/
+  dmAllShared->MaxRetryDiscovery = DISCOVERY_RETRIES;
+  dmAllShared->RateAdjust = 0;
+  /**< initializes timers */
+  dmInitTimers(dmRoot);
+
+  /**< initializes port contexts */
+  dmPortContextInit(dmRoot);
+  
+  /**< initializes devices */
+  dmDeviceDataInit(dmRoot);
+  
+  /**< initializes expander devices */
+  buffer = tmpBuffer;
+  buffLen = sizeof(tmpBuffer);
+  
+  dm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  
+  if ((tddmGetTransportParam(
+                             dmRoot, 
+                             globalStr,
+                             iniParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "MaxExpanders",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == DM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      max_expander = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      max_expander = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+  }  
+
+  dm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  
+  if ((tddmGetTransportParam(
+                             dmRoot, 
+                             globalStr,
+                             SwParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "IT_NEXUS_TIMEOUT",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == DM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      dmAllShared->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      dmAllShared->itNexusTimeout = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+  }
+
+  DM_DBG1(("dmAllShared->itNexusTimeout %d \n", dmAllShared->itNexusTimeout)); 
+
+  dm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  
+  if ((tddmGetTransportParam(
+                             dmRoot, 
+                             globalStr,
+                             SwParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "MaxRetryDiscovery",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == DM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      dmAllShared->MaxRetryDiscovery = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      dmAllShared->MaxRetryDiscovery = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+  }
+
+  DM_DBG1(("dmAllShared->MaxRetryDiscovery %d \n", dmAllShared->MaxRetryDiscovery)); 
+
+  dm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  if ((tddmGetTransportParam(
+                             dmRoot, 
+                             globalStr,
+                             SwParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "RateAdjust",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == DM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      dmAllShared->RateAdjust = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      dmAllShared->RateAdjust = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+  }
+  DM_DBG1(("dmAllShared->RateAdjust %d \n", dmAllShared->RateAdjust)); 
+
+  dmExpanderDeviceDataInit(dmRoot, max_expander);
+    
+  /**< initializes SMP commands */
+  dmSMPInit(dmRoot);
+
+#ifdef DM_DEBUG
+  gDMDebugLevel = swConfig->DMDebugLevel;
+#endif
+  return DM_RC_SUCCESS;
+}
+
+osGLOBAL void
+dmSMPInit(
+          dmRoot_t *dmRoot 
+         )
+{
+  dmIntRoot_t               *dmIntRoot    = (dmIntRoot_t *)dmRoot->dmData;
+  dmIntContext_t            *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;
+  dmSMPRequestBody_t        *dmSMPCommand = (dmSMPRequestBody_t *)dmAllShared->SMPMem;
+  bit8                      *dmIndirectSMPReqRsp = (bit8 *)dmAllShared->IndirectSMPMem;
+  bit32                     prev_PhysAddrLower;
+  
+  int i = 0;
+  DM_DBG3(("dmSMPInit: start \n"));
+  
+  DMLIST_INIT_HDR(&(dmAllShared->freeSMPList));
+  
+  for(i=0;i<DM_MAX_SMP;i++)
+  {
+    DMLIST_INIT_ELEMENT(&(dmSMPCommand[i].Link));
+    /* initialize expander fields */
+    dmSMPCommand[i].dmRoot = agNULL;
+    dmSMPCommand[i].dmDevice = agNULL;
+    dmSMPCommand[i].dmPortContext = agNULL;
+    dmSMPCommand[i].retries = 0;
+    dmSMPCommand[i].id = i;
+    dm_memset( &(dmSMPCommand[i].smpPayload), 0, sizeof(dmSMPCommand[i].smpPayload));
+    /* indirect SMP related */
+    dmSMPCommand[i].IndirectSMPResponse = agNULL;
+    dmSMPCommand[i].IndirectSMP = ((bit8 *)dmIndirectSMPReqRsp) + (i*SMP_INDIRECT_PAYLOAD);
+    dmSMPCommand[i].IndirectSMPUpper32 = dmAllShared->IndirectSMPUpper32;
+    dmSMPCommand[i].IndirectSMPLower32 = dmAllShared->IndirectSMPLower32;
+    
+    prev_PhysAddrLower = dmAllShared->IndirectSMPLower32;
+    dmAllShared->IndirectSMPLower32 = dmAllShared->IndirectSMPLower32 + SMP_INDIRECT_PAYLOAD;
+    if (dmAllShared->IndirectSMPLower32 <= prev_PhysAddrLower)
+    {
+      dmAllShared->IndirectSMPUpper32++;    
+    }
+    
+    DMLIST_ENQUEUE_AT_TAIL(&(dmSMPCommand[i].Link), &(dmAllShared->freeSMPList)); 
+  }
+  return;
+  
+}
+
+osGLOBAL void
+dmDeviceDataInit(
+                 dmRoot_t *dmRoot 
+                )
+{
+  dmIntRoot_t               *dmIntRoot    = (dmIntRoot_t *)dmRoot->dmData;
+  dmIntContext_t            *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;  
+  dmDeviceData_t            *dmDeviceData = (dmDeviceData_t *)dmAllShared->DeviceMem;
+  int i;
+  
+  DM_DBG3(("dmDeviceDataInit: start \n"));
+  
+  DMLIST_INIT_HDR(&(dmAllShared->MainDeviceList));
+  DMLIST_INIT_HDR(&(dmAllShared->FreeDeviceList));
+  
+  for(i=0;i<DM_MAX_DEV;i++)
+  {
+    DMLIST_INIT_ELEMENT(&(dmDeviceData[i].FreeLink));
+    DMLIST_INIT_ELEMENT(&(dmDeviceData[i].MainLink));
+    DMLIST_INIT_ELEMENT(&(dmDeviceData[i].IncDisLink));
+    dmDeviceData[i].id = i;
+    dmDeviceData[i].DeviceType = DM_DEFAULT_DEVICE;
+    dmDeviceData[i].dmRoot = agNULL;
+//    dmDeviceData[i].agDevHandle = agNULL;
+    
+    dmDeviceData[i].dmPortContext = agNULL;
+    dmDeviceData[i].dmExpander = agNULL;
+    dmDeviceData[i].ExpDevice = agNULL;
+    dmDeviceData[i].phyID = 0xFF;
+    dmDeviceData[i].SASAddressID.sasAddressHi = 0;
+    dmDeviceData[i].SASAddressID.sasAddressLo = 0;
+    dmDeviceData[i].valid = agFALSE;
+    dmDeviceData[i].valid2 = agFALSE;
+    dmDeviceData[i].processed = agFALSE;
+    dmDeviceData[i].initiator_ssp_stp_smp = 0;
+    dmDeviceData[i].target_ssp_stp_smp = 0;
+    dmDeviceData[i].numOfPhys = 0;
+//    dmDeviceData[i].registered = agFALSE;
+    dmDeviceData[i].directlyAttached = agFALSE;
+    dmDeviceData[i].SASSpecDeviceType = 0xFF;
+    dmDeviceData[i].IOStart = 0;
+    dmDeviceData[i].IOResponse = 0;
+    dmDeviceData[i].agDeviceResetContext.osData = agNULL;
+    dmDeviceData[i].agDeviceResetContext.sdkData = agNULL;
+    dmDeviceData[i].TRflag = agFALSE;
+    dmDeviceData[i].ResetCnt = 0;
+    dmDeviceData[i].registered = agFALSE;
+    dmDeviceData[i].reported = agFALSE;
+  
+    dmDeviceData[i].MCN = 0;
+    dmDeviceData[i].MCNDone = agFALSE;
+    dmDeviceData[i].PrevMCN = 0;
+    
+    dm_memset( &(dmDeviceData[i].dmDeviceInfo), 0, sizeof(dmDeviceInfo_t));
+    /* some other variables */
+    DMLIST_ENQUEUE_AT_TAIL(&(dmDeviceData[i].FreeLink), &(dmAllShared->FreeDeviceList)); 
+  }  
+  
+  return;
+}
+osGLOBAL void
+dmDeviceDataReInit(
+                   dmRoot_t		  *dmRoot,
+                   dmDeviceData_t         *oneDeviceData		     
+                  )
+{
+  DM_DBG3(("dmDeviceDataReInit: start \n"));
+  
+  oneDeviceData->DeviceType = DM_DEFAULT_DEVICE;
+//  oneDeviceData->agDevHandle = agNULL;
+    
+  oneDeviceData->dmPortContext = agNULL;
+  oneDeviceData->dmExpander = agNULL;
+  oneDeviceData->ExpDevice = agNULL;
+  oneDeviceData->phyID = 0xFF;
+  oneDeviceData->SASAddressID.sasAddressHi = 0;
+  oneDeviceData->SASAddressID.sasAddressLo = 0;
+  oneDeviceData->valid = agFALSE;
+  oneDeviceData->valid2 = agFALSE;
+  oneDeviceData->processed = agFALSE;
+  oneDeviceData->initiator_ssp_stp_smp = 0;
+  oneDeviceData->target_ssp_stp_smp = 0;
+  oneDeviceData->numOfPhys = 0;
+//  oneDeviceData->registered = agFALSE;
+  oneDeviceData->directlyAttached = agFALSE;
+  oneDeviceData->SASSpecDeviceType = 0xFF;
+  oneDeviceData->IOStart = 0;
+  oneDeviceData->IOResponse = 0;
+  oneDeviceData->agDeviceResetContext.osData = agNULL;
+  oneDeviceData->agDeviceResetContext.sdkData = agNULL;
+  oneDeviceData->TRflag = agFALSE;
+  oneDeviceData->ResetCnt = 0;   
+  oneDeviceData->registered = agFALSE;
+  oneDeviceData->reported = agFALSE;
+  
+  oneDeviceData->MCN = 0;
+  oneDeviceData->MCNDone = agFALSE;
+  oneDeviceData->PrevMCN = 0;
+    
+  dm_memset( &(oneDeviceData->dmDeviceInfo), 0, sizeof(dmDeviceInfo_t));
+  
+  return;
+}
+
+
+osGLOBAL void
+dmExpanderDeviceDataInit(
+                         dmRoot_t *dmRoot,
+                         bit32    max_exp  
+                        )
+{
+  dmIntRoot_t               *dmIntRoot    = (dmIntRoot_t *)dmRoot->dmData;
+  dmIntContext_t            *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;
+  dmExpander_t              *dmExpData = (dmExpander_t *)dmAllShared->ExpanderMem;
+  bit32 i = 0;
+  DM_DBG3(("dmExpanderDeviceDataInit: start \n"));
+  
+  DMLIST_INIT_HDR(&(dmAllShared->freeExpanderList));
+  DMLIST_INIT_HDR(&(dmAllShared->mainExpanderList));
+  
+  for(i=0;i<max_exp;i++)
+  {
+    DMLIST_INIT_ELEMENT(&(dmExpData[i].linkNode));
+    DMLIST_INIT_ELEMENT(&(dmExpData[i].upNode));
+    /* initialize expander fields */
+    dmExpData[i].dmRoot = agNULL;
+    dmExpData[i].agDevHandle = agNULL;
+    dmExpData[i].dmDevice = agNULL;
+    dmExpData[i].dmUpStreamExpander = agNULL;
+    dmExpData[i].dmCurrentDownStreamExpander = agNULL;
+    dmExpData[i].hasUpStreamDevice = agFALSE;
+    dmExpData[i].numOfUpStreamPhys = 0;
+    dmExpData[i].currentUpStreamPhyIndex = 0;
+    dmExpData[i].numOfDownStreamPhys = 0;
+    dmExpData[i].currentDownStreamPhyIndex = 0;
+    dmExpData[i].discoveringPhyId = 0;
+    dmExpData[i].underDiscovering = agFALSE;
+    dmExpData[i].id = i;
+    DM_DBG3(("dmExpanderDeviceDataInit: exp id %d\n", i));
+    
+    dmExpData[i].dmReturnginExpander = agNULL;
+    dmExpData[i].discoverSMPAllowed = agTRUE;
+    dm_memset( &(dmExpData[i].currentIndex), 0, sizeof(dmExpData[i].currentIndex));
+    dm_memset( &(dmExpData[i].upStreamPhys), 0, sizeof(dmExpData[i].upStreamPhys));
+    dm_memset( &(dmExpData[i].downStreamPhys), 0, sizeof(dmExpData[i].downStreamPhys));
+    dm_memset( &(dmExpData[i].routingAttribute), 0, sizeof(dmExpData[i].routingAttribute));
+    dmExpData[i].configSASAddrTableIndex = 0;
+    dm_memset( &(dmExpData[i].configSASAddressHiTable), 0, sizeof(dmExpData[i].configSASAddressHiTable));
+    dm_memset( &(dmExpData[i].configSASAddressLoTable), 0, sizeof(dmExpData[i].configSASAddressLoTable));
+    dmExpData[i].SAS2 = 0;  /* default is SAS 1.1 spec */ 
+    dmExpData[i].TTTSupported = agFALSE;  /* Table to Table is supported */
+    dmExpData[i].UndoDueToTTTSupported = agFALSE;
+    
+       
+    DMLIST_ENQUEUE_AT_TAIL(&(dmExpData[i].linkNode), &(dmAllShared->freeExpanderList)); 
+  }
+  return;
+}
+
+/* re-intialize an expander */
+osGLOBAL void
+dmExpanderDeviceDataReInit(
+                           dmRoot_t         *dmRoot, 
+                           dmExpander_t     *oneExpander
+                          )
+{
+  DM_DBG3(("dmExpanderDeviceDataReInit: start \n"));
+  oneExpander->dmRoot = agNULL;
+  oneExpander->agDevHandle = agNULL;
+  oneExpander->dmDevice = agNULL;
+  oneExpander->dmUpStreamExpander = agNULL;
+  oneExpander->dmCurrentDownStreamExpander = agNULL;
+  oneExpander->hasUpStreamDevice = agFALSE;
+  oneExpander->numOfUpStreamPhys = 0;
+  oneExpander->currentUpStreamPhyIndex = 0;
+  oneExpander->numOfDownStreamPhys = 0;
+  oneExpander->currentDownStreamPhyIndex = 0;
+  oneExpander->discoveringPhyId = 0;
+  oneExpander->underDiscovering = agFALSE;
+  oneExpander->dmReturnginExpander = agNULL;
+  oneExpander->discoverSMPAllowed = agTRUE;
+  dm_memset( &(oneExpander->currentIndex), 0, sizeof(oneExpander->currentIndex));
+  dm_memset( &(oneExpander->upStreamPhys), 0, sizeof(oneExpander->upStreamPhys));
+  dm_memset( &(oneExpander->downStreamPhys), 0, sizeof(oneExpander->downStreamPhys));
+  dm_memset( &(oneExpander->routingAttribute), 0, sizeof(oneExpander->routingAttribute));
+  oneExpander->configSASAddrTableIndex = 0;
+  dm_memset( &(oneExpander->configSASAddressHiTable), 0, sizeof(oneExpander->configSASAddressHiTable));
+  dm_memset( &(oneExpander->configSASAddressLoTable), 0, sizeof(oneExpander->configSASAddressLoTable));
+  oneExpander->SAS2 = 0;  /* default is SAS 1.1 spec */ 
+  oneExpander->TTTSupported = agFALSE;  /* Table to Table is supported */
+  oneExpander->UndoDueToTTTSupported = agFALSE;
+  
+  return;
+}			  
+
+osGLOBAL void
+dmPortContextInit(
+                  dmRoot_t *dmRoot 
+                 )
+{
+  dmIntRoot_t               *dmIntRoot    = (dmIntRoot_t *)dmRoot->dmData;
+  dmIntContext_t            *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;
+  dmIntPortContext_t        *dmPortContext = (dmIntPortContext_t *)dmAllShared->PortContextMem;
+  int i = 0;
+#ifdef TBD  
+  int j = 0;
+#endif  
+  
+  DM_DBG3(("dmPortContextInit: start \n"));
+  
+  DMLIST_INIT_HDR(&(dmAllShared->MainPortContextList));
+  DMLIST_INIT_HDR(&(dmAllShared->FreePortContextList));
+  for(i=0;i<DM_MAX_PORT_CONTEXT;i++)
+  {
+    DMLIST_INIT_ELEMENT(&(dmPortContext[i].FreeLink));
+    DMLIST_INIT_ELEMENT(&(dmPortContext[i].MainLink));
+
+    DMLIST_INIT_HDR(&(dmPortContext[i].discovery.discoveringExpanderList));
+    DMLIST_INIT_HDR(&(dmPortContext[i].discovery.UpdiscoveringExpanderList));
+    dmPortContext[i].discovery.type = DM_DISCOVERY_OPTION_FULL_START;
+    dmInitTimerRequest(dmRoot, &(dmPortContext[i].discovery.discoveryTimer));
+    dmInitTimerRequest(dmRoot, &(dmPortContext[i].discovery.configureRouteTimer));
+    dmInitTimerRequest(dmRoot, &(dmPortContext[i].discovery.deviceRegistrationTimer));
+    dmInitTimerRequest(dmRoot, &(dmPortContext[i].discovery.SMPBusyTimer));
+    dmInitTimerRequest(dmRoot, &(dmPortContext[i].discovery.BCTimer));
+    dmInitTimerRequest(dmRoot, &(dmPortContext[i].discovery.DiscoverySMPTimer));
+    dmPortContext[i].discovery.retries = 0;  
+    dmPortContext[i].discovery.configureRouteRetries = 0;  
+    dmPortContext[i].discovery.deviceRetistrationRetries = 0;  
+    dmPortContext[i].discovery.pendingSMP = 0;  
+    dmPortContext[i].discovery.SeenBC = agFALSE;  
+    dmPortContext[i].discovery.forcedOK = agFALSE;  
+    dmPortContext[i].discovery.SMPRetries = 0;  
+    dmPortContext[i].discovery.DeferredError = agFALSE;  
+    dmPortContext[i].discovery.ConfiguresOthers = agFALSE;  
+    dmPortContext[i].discovery.ResetTriggerred = agFALSE;  
+
+#ifdef INITIATOR_DRIVER  
+    dmPortContext[i].DiscoveryState = DM_DSTATE_NOT_STARTED;
+    dmPortContext[i].DiscoveryAbortInProgress = agFALSE;
+    dmPortContext[i].directAttatchedSAS = agFALSE;
+    dmPortContext[i].DiscoveryRdyGiven = agFALSE;
+    dmPortContext[i].SeenLinkUp = agFALSE;
+    
+#endif      
+    dmPortContext[i].id = i;
+#ifdef TBD    
+    dmPortContext[i].agPortContext = agNULL;
+#endif    
+    dmPortContext[i].LinkRate = 0;
+    dmPortContext[i].Count = 0;
+    dmPortContext[i].valid = agFALSE;
+    dmPortContext[i].RegFailed = agFALSE;
+    
+#ifdef TBD    
+    for (j=0;j<DM_MAX_NUM_PHYS;j++)
+    {
+      dmPortContext[i].PhyIDList[j] = agFALSE;
+    }
+#endif    
+    dmPortContext[i].RegisteredDevNums = 0;
+    dmPortContext[i].eventPhyID = 0xFF;
+    dmPortContext[i].Transient = agFALSE;
+
+    /* add more variables later */
+    DMLIST_ENQUEUE_AT_TAIL(&(dmPortContext[i].FreeLink), &(dmAllShared->FreePortContextList));
+  }
+
+#ifdef DM_INTERNAL_DEBUG  /* for debugging only */
+  for(i=0;i<DM_MAX_PORT_CONTEXT;i++)
+  {
+    DM_DBG6(("dmPortContextInit: index %d  &tdsaPortContext[] %p\n", i, &(dmPortContext[i])));
+  }
+  DM_DBG6(("dmPortContextInit: sizeof(tdsaPortContext_t) %d 0x%x\n", sizeof(dmIntPortContext_t), sizeof(dmIntPortContext_t)));
+#endif
+
+  return;
+}		 
+
+osGLOBAL void
+dmPortContextReInit(
+                    dmRoot_t		  *dmRoot,
+                    dmIntPortContext_t    *onePortContext		     
+                    )
+{
+  dmDiscovery_t   *discovery;
+  
+  DM_DBG3(("dmPortContextReInit: start \n"));
+  
+  discovery = &(onePortContext->discovery);
+
+  onePortContext->discovery.type = DM_DISCOVERY_OPTION_FULL_START;
+  onePortContext->discovery.retries = 0;  
+  onePortContext->discovery.configureRouteRetries = 0;  
+  onePortContext->discovery.deviceRetistrationRetries = 0;  
+  onePortContext->discovery.pendingSMP = 0;  
+  onePortContext->discovery.SeenBC = agFALSE;  
+  onePortContext->discovery.forcedOK = agFALSE;  
+  onePortContext->discovery.SMPRetries = 0;  
+  onePortContext->discovery.DeferredError = agFALSE;
+  onePortContext->discovery.ConfiguresOthers = agFALSE;
+  onePortContext->discovery.ResetTriggerred = agFALSE;
+  
+  /* free expander lists */
+  dmCleanAllExp(dmRoot, onePortContext);
+    
+  /* kill the discovery-related timers if they are running */  
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  if (discovery->discoveryTimer.timerRunning == agTRUE)
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+    dmKillTimer(
+                dmRoot,
+                &discovery->discoveryTimer
+               );
+  }
+  else
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+  }
+  
+  
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  if (discovery->configureRouteTimer.timerRunning == agTRUE)
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+    dmKillTimer(
+                dmRoot,
+                &discovery->configureRouteTimer
+               );
+  }
+  else
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+  }
+  
+  
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  if (discovery->deviceRegistrationTimer.timerRunning == agTRUE)
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+    dmKillTimer(
+                dmRoot,
+                &discovery->deviceRegistrationTimer
+               );
+  }
+  else
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+  }
+  
+  
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  if (discovery->BCTimer.timerRunning == agTRUE)
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+    dmKillTimer(
+                dmRoot,
+                &discovery->BCTimer
+               );
+  }
+  else
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+  }
+  
+  
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  if (discovery->SMPBusyTimer.timerRunning == agTRUE)
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+    dmKillTimer(
+                dmRoot,
+                &discovery->SMPBusyTimer
+               );
+  }    
+  else
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+  }
+  
+  
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  if (discovery->DiscoverySMPTimer.timerRunning == agTRUE)
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+    dmKillTimer(
+                dmRoot,
+                &discovery->DiscoverySMPTimer
+               );
+  }    
+  else
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+  }
+
+  onePortContext->DiscoveryState = DM_DSTATE_NOT_STARTED;
+  onePortContext->DiscoveryAbortInProgress = agFALSE;
+  onePortContext->directAttatchedSAS = agFALSE;
+  onePortContext->DiscoveryRdyGiven = agFALSE;
+  onePortContext->SeenLinkUp = agFALSE;
+  
+  onePortContext->dmPortContext->dmData = agNULL;
+  onePortContext->dmPortContext = agNULL;
+  onePortContext->dmRoot = agNULL;
+  
+  onePortContext->LinkRate = 0;
+  onePortContext->Count = 0;
+  onePortContext->valid = agFALSE;
+  onePortContext->RegisteredDevNums = 0;
+  onePortContext->eventPhyID = 0xFF;
+  onePortContext->Transient = agFALSE;
+    
+  return;
+}		    
+
+
+osGLOBAL void
+dmInitTimers(
+               dmRoot_t *dmRoot 
+               )
+{
+  dmIntRoot_t               *dmIntRoot    = (dmIntRoot_t *)dmRoot->dmData;
+  dmIntContext_t            *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;
+  
+#ifdef DM_DEBUG_ENABLE
+  dmIntPortContext_t *dmPortContext = (dmIntPortContext_t *)dmAllShared->PortContextMem;
+  
+  DM_DBG6(("dmInitTimers: start \n"));
+  DM_DBG6(("dmInitTimers: ******* tdsaRoot %p \n", dmIntRoot));
+  DM_DBG6(("dmInitTimers: ******* tdsaPortContext %p \n",dmPortContext));
+#endif
+  
+  /* initialize the timerlist */
+  DMLIST_INIT_HDR(&(dmAllShared->timerlist));
+
+  return;
+}
+#endif /* FDS_ DM */
+
+

sys/dev/pms/RefTisa/discovery/dm/dmlist.h

@@ -0,0 +1,161 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+
+#ifndef __DMLIST_H__
+#define __DMLIST_H__
+
+typedef struct dmList_s dmList_t;
+
+struct dmList_s {
+  dmList_t  *flink;
+  dmList_t  *blink;
+};
+
+#define DMLIST_INIT_HDR(hdr)                        \
+  do {                                              \
+    ((dmList_t *)(hdr))->flink = (dmList_t *)(hdr); \
+    ((dmList_t *)(hdr))->blink = (dmList_t *)(hdr); \
+  } while (0)
+
+#define DMLIST_INIT_ELEMENT(hdr)                     \
+  do {                                               \
+    ((dmList_t *)(hdr))->flink = (dmList_t *)agNULL; \
+    ((dmList_t *)(hdr))->blink = (dmList_t *)agNULL; \
+  } while (0)
+
+#define DMLIST_ENQUEUE_AT_HEAD(toAddHdr,listHdr)                                \
+  do {                                                                          \
+    ((dmList_t *)(toAddHdr))->flink           = ((dmList_t *)(listHdr))->flink; \
+    ((dmList_t *)(toAddHdr))->blink           = (dmList_t *)(listHdr) ;         \
+    ((dmList_t *)(listHdr))->flink->blink     = (dmList_t *)(toAddHdr);         \
+    ((dmList_t *)(listHdr))->flink            = (dmList_t *)(toAddHdr);         \
+  } while (0)
+
+#define DMLIST_ENQUEUE_AT_TAIL(toAddHdr,listHdr)                                \
+  do {                                                                          \
+    ((dmList_t *)(toAddHdr))->flink           = (dmList_t *)(listHdr);          \
+    ((dmList_t *)(toAddHdr))->blink           = ((dmList_t *)(listHdr))->blink; \
+    ((dmList_t *)(listHdr))->blink->flink     = (dmList_t *)(toAddHdr);         \
+    ((dmList_t *)(listHdr))->blink            = (dmList_t *)(toAddHdr);         \
+  } while (0)
+
+#define DMLIST_EMPTY(listHdr) \
+  (((dmList_t *)(listHdr))->flink == ((dmList_t *)(listHdr)))
+
+#define DMLIST_NOT_EMPTY(listHdr) \
+  (!DMLIST_EMPTY(listHdr))
+
+#define DMLIST_DEQUEUE_THIS(hdr)                                      \
+  do {                                                                \
+    ((dmList_t *)(hdr))->blink->flink = ((dmList_t *)(hdr))->flink;   \
+    ((dmList_t *)(hdr))->flink->blink = ((dmList_t *)(hdr))->blink;   \
+    ((dmList_t *)(hdr))->flink = ((dmList_t *)(hdr))->blink = agNULL; \
+  } while (0)
+
+#define DMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr)                              \
+  do {                                                                                \
+    *((dmList_t **)(atHeadHdr))                 = ((dmList_t *)(listHdr))->flink;     \
+    (*((dmList_t **)(atHeadHdr)))->flink->blink = (dmList_t *)(listHdr);              \
+    ((dmList_t *)(listHdr))->flink              = (*(dmList_t **)(atHeadHdr))->flink; \
+  } while (0)
+
+#define DMLIST_DEQUEUE_FROM_HEAD(atHeadHdr,listHdr)             \
+do {                                                            \
+  if (DMLIST_NOT_EMPTY((listHdr)))                              \
+  {                                                             \
+    DMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr);           \
+  }                                                             \
+  else                                                          \
+  {                                                             \
+    (*((dmList_t **)(atHeadHdr))) = (dmList_t *)agNULL;         \
+  }                                                             \
+} while (0)
+  
+#define DMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr)                                \
+  do {                                                                                  \
+    (*((dmList_t **)(atTailHdr)))               = ((dmList_t *)(listHdr))->blink;       \
+    (*((dmList_t **)(atTailHdr)))->blink->flink = (dmList_t *)(listHdr);                \
+    ((dmList_t *)(listHdr))->blink              = (*((dmList_t **)(atTailHdr)))->blink; \
+  } while (0)
+
+#define DMLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr)               \
+  do {                                                            \
+    if (DMLIST_NOT_EMPTY((listHdr)))                              \
+    {                                                             \
+      DMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr);           \
+    }                                                             \
+    else                                                          \
+    {                                                             \
+      (*((dmList_t **)(atTailHdr))) = (dmList_t *)agNULL;         \
+    }                                                             \
+  } while (0)
+
+#define DMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr)               \
+  do {                                                                        \
+    ((dmList_t *)toAddListHdr)->blink->flink = ((dmList_t *)listHdr);         \
+    ((dmList_t *)toAddListHdr)->flink->blink = ((dmList_t *)listHdr)->blink;  \
+    ((dmList_t *)listHdr)->blink->flink = ((dmList_t *)toAddListHdr)->flink;  \
+    ((dmList_t *)listHdr)->blink = ((dmList_t *)toAddListHdr)->blink;         \
+    DMLIST_INIT_HDR(toAddListHdr);                                            \
+  } while (0)
+
+#define DMLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr)                    \
+  do {                                                                        \
+    if (DMLIST_NOT_EMPTY(toAddListHdr))                                       \
+    {                                                                         \
+      DMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr);                \
+    }                                                                         \
+  } while (0)
+
+#define DMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr)               \
+  do {                                                                        \
+    ((dmList_t *)toAddListHdr)->blink->flink = ((dmList_t *)listHdr)->flink;  \
+    ((dmList_t *)toAddListHdr)->flink->blink = ((dmList_t *)listHdr);         \
+    ((dmList_t *)listHdr)->flink->blink = ((dmList_t *)toAddListHdr)->blink;  \
+    ((dmList_t *)listHdr)->flink = ((dmList_t *)toAddListHdr)->flink;         \
+    DMLIST_INIT_HDR(toAddListHdr);                                            \
+  } while (0)
+
+#define DMLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr)                    \
+  do {                                                                        \
+    if (DMLIST_NOT_EMPTY(toAddListHdr))                                       \
+    {                                                                         \
+      DMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr);                \
+    }                                                                         \
+  } while (0)
+
+#define TD_FIELD_OFFSET(baseType,fieldName) \
+                    ((bit32)((bitptr)(&(((baseType *)0)->fieldName))))
+
+#define DMLIST_OBJECT_BASE(baseType,fieldName,fieldPtr)         \
+                    (void *)fieldPtr == (void *)0 ? (baseType *)0 :             \
+                    ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName)))))
+
+
+
+
+#endif /* __DMLIST_H__ */
+
+

sys/dev/pms/RefTisa/discovery/dm/dmmisc.c

@@ -0,0 +1,98 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+
+#include <dev/pms/RefTisa/discovery/dm/dmdefs.h>
+#include <dev/pms/RefTisa/discovery/dm/dmtypes.h>
+#include <dev/pms/RefTisa/discovery/dm/dmproto.h>
+
+osGLOBAL void 
+*dm_memset(void *s, int c, bit32 n)
+{
+  bit32   i;
+
+  char *dst = (char *)s;
+  for (i=0; i < n; i++)
+  {
+    dst[i] = (char) c;
+  }
+  return (void *)(&dst[i-n]);
+}
+
+osGLOBAL void 
+*dm_memcpy(void *dst, void *src, bit32 count)
+{
+  bit32 x;
+  unsigned char *dst1 = (unsigned char *)dst;
+  unsigned char *src1 = (unsigned char *)src;
+
+  for (x=0; x < count; x++)
+    dst1[x] = src1[x];
+
+  return dst;
+
+}
+
+/** hexidecimal dump */
+osGLOBAL void 
+dmhexdump(const char *ptitle, bit8 *pbuf, int len)
+{
+  int i;
+  DM_DBG1(("%s - dmhexdump(len=%d):\n", ptitle, (int)len));
+  if (!pbuf)
+  {
+    DM_DBG1(("pbuf is NULL\n"));
+    return;
+  }
+  for (i = 0; i < len; )
+  {
+    if (len - i > 4)
+    {
+      DM_DBG1((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", pbuf[i], pbuf[i+1], pbuf[i+2], pbuf[i+3]));
+      i += 4;
+    }
+    else
+    {
+      DM_DBG1((" 0x%02x,", pbuf[i]));
+      i++;
+    }
+  }
+  DM_DBG1(("\n"));
+}
+#endif /* FDS_ DM */
+

sys/dev/pms/RefTisa/discovery/dm/dmport.c

@@ -0,0 +1,304 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+
+#include <dev/pms/RefTisa/discovery/dm/dmdefs.h>
+#include <dev/pms/RefTisa/discovery/dm/dmtypes.h>
+#include <dev/pms/RefTisa/discovery/dm/dmproto.h>
+
+/*****************************************************************************/
+/*! \brief dmCreatePort
+ *  
+ *
+ *  Purpose: A port context is created by this function 
+ *  
+ *  \param   dmRoot:              DM context handle.
+ *  \param   dmPortContext:       Pointer to this instance of port context 
+ * 
+ *  \return: 
+ *          DM_RC_SUCCESS
+ *          DM_RC_FAILURE
+ *
+ */
+/*****************************************************************************/
+osGLOBAL bit32  
+dmCreatePort(  
+             dmRoot_t        *dmRoot,
+             dmPortContext_t *dmPortContext,
+             dmPortInfo_t    *dmPortInfo)
+{
+  dmIntRoot_t               *dmIntRoot    = agNULL;
+  dmIntContext_t            *dmAllShared = agNULL;
+  dmIntPortContext_t        *onePortContext = agNULL;
+  dmList_t                  *PortContextList = agNULL;
+    
+  DM_DBG3(("dmCreatePort: start\n"));
+  
+  if (dmRoot == agNULL)
+  {
+    DM_DBG1(("dmCreatePort: dmRoot is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+  
+  if (dmPortContext == agNULL)
+  {
+    DM_DBG1(("dmCreatePort: dmPortContext is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+  
+  /* the duplicacy of a port is checked */
+  if (dmPortContext->dmData != agNULL)
+  {
+    DM_DBG1(("dmCreatePort: dmPortContext->dmData is not NULL, wrong, Already created!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+  
+  if (dmPortInfo == agNULL)
+  {
+    DM_DBG1(("dmCreatePort: dmPortInfo is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+  
+  dmIntRoot = (dmIntRoot_t *)dmRoot->dmData;
+  
+  if (dmIntRoot == agNULL)
+  {
+    DM_DBG1(("dmCreatePort: dmIntRoot is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+
+  dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;
+
+  if (dmAllShared == agNULL)
+  {
+    DM_DBG1(("dmCreatePort: dmAllShared is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+
+  tddmSingleThreadedEnter(dmRoot, DM_PORT_LOCK);
+  if (DMLIST_NOT_EMPTY(&(dmAllShared->FreePortContextList)))
+  {
+    DMLIST_DEQUEUE_FROM_HEAD(&PortContextList, &(dmAllShared->FreePortContextList));
+    tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK);
+    onePortContext = DMLIST_OBJECT_BASE(dmIntPortContext_t, FreeLink, PortContextList);
+    if (onePortContext == agNULL)
+    {
+      DM_DBG1(("dmCreatePort: onePortContext is NULL in allocation, wrong!!!\n"));
+      return DM_RC_FAILURE;	
+    }
+    
+    dmPortContext->dmData =  onePortContext;  
+    onePortContext->DiscoveryState = DM_DSTATE_NOT_STARTED;
+    onePortContext->discoveryOptions = DM_DISCOVERY_OPTION_FULL_START;
+
+    onePortContext->dmRoot = dmRoot;
+    onePortContext->dmPortContext = dmPortContext;
+    onePortContext->valid = agTRUE;
+    onePortContext->RegFailed = agFALSE;
+    
+    onePortContext->LinkRate = DM_GET_LINK_RATE(dmPortInfo->flag);
+    DM_DBG3(("dmCreatePort: linkrate %0x\n", onePortContext->LinkRate));
+
+    onePortContext->sasRemoteAddressHi = DM_GET_SAS_ADDRESSHI(dmPortInfo->sasRemoteAddressHi);
+    onePortContext->sasRemoteAddressLo = DM_GET_SAS_ADDRESSLO(dmPortInfo->sasRemoteAddressLo);
+    onePortContext->sasLocalAddressHi = DM_GET_SAS_ADDRESSHI(dmPortInfo->sasLocalAddressHi);
+    onePortContext->sasLocalAddressLo = DM_GET_SAS_ADDRESSLO(dmPortInfo->sasLocalAddressLo);
+    DM_DBG3(("dmCreatePort: pid %d\n", onePortContext->id));
+    DM_DBG3(("dmCreatePort: RemoteAddrHi 0x%08x RemoteAddrLo 0x%08x\n", onePortContext->sasRemoteAddressHi, onePortContext->sasRemoteAddressLo));
+    DM_DBG3(("dmCreatePort: LocalAddrHi 0x%08x LocaAddrLo 0x%08x\n", onePortContext->sasLocalAddressHi, onePortContext->sasLocalAddressLo));
+ 
+    tddmSingleThreadedEnter(dmRoot, DM_PORT_LOCK);
+    DMLIST_ENQUEUE_AT_TAIL(&(onePortContext->MainLink), &(dmAllShared->MainPortContextList));
+    tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK);
+  }
+  else
+  {
+    tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK);
+    DM_DBG1(("dmCreatePort: Attention. no more free PortContext!!!\n"));
+    return DM_RC_FAILURE;
+  }
+  
+  return DM_RC_SUCCESS;
+}	     	     
+
+/*****************************************************************************/
+/*! \brief dmDestroyPort
+ *  
+ *
+ *  Purpose: A port context is destroyed by this function 
+ *  
+ *  \param   dmRoot:              DM context handle.
+ *  \param   dmPortContext:       Pointer to this instance of port context 
+ * 
+ *  \return: 
+ *          DM_RC_SUCCESS
+ *          DM_RC_FAILURE
+ *
+ */
+/*****************************************************************************/
+osGLOBAL bit32  
+dmDestroyPort(
+          dmRoot_t        *dmRoot,
+          dmPortContext_t *dmPortContext,
+          dmPortInfo_t    *dmPortInfo)       
+{
+  dmIntRoot_t               *dmIntRoot    = agNULL;
+  dmIntContext_t            *dmAllShared = agNULL;
+  dmIntPortContext_t        *onePortContext = agNULL;
+  
+  DM_DBG1(("dmDestroyPort: start\n"));
+  if (dmRoot == agNULL)
+  {
+    DM_DBG1(("dmDestroyPort: dmRoot is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+  
+  if (dmPortContext == agNULL)
+  {
+    DM_DBG1(("dmDestroyPort: dmPortContext is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+  
+  if (dmPortInfo == agNULL)
+  {
+    DM_DBG1(("dmDestroyPort: dmPortInfo is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+
+  dmIntRoot = (dmIntRoot_t *)dmRoot->dmData;
+  
+  if (dmIntRoot == agNULL)
+  {
+    DM_DBG1(("dmDestroyPort: dmIntRoot is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+
+  dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;
+
+  if (dmAllShared == agNULL)
+  {
+    DM_DBG1(("dmDestroyPort: dmAllShared is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;	
+  }
+
+  /*
+    no device(expander) to be removed since all devices should
+    be in freelist at the end of discovery
+    But if the discovery is in progress, abort it and clean up
+  */
+  onePortContext = (dmIntPortContext_t *)dmPortContext->dmData;
+  
+  if (onePortContext == agNULL)
+  {
+    DM_DBG1(("dmDestroyPort: onePortContext is NULL, wrong!!!\n"));
+    return DM_RC_FAILURE;
+  }
+  
+#if 1
+  if (onePortContext->DiscoveryState != DM_DSTATE_COMPLETED)
+  {
+    dmDiscoverAbort(dmRoot, onePortContext);
+  }
+  else
+  {
+    /* move devices from dmAllShared->MainDeviceList to dmAllShared->FreeDeviceList; dmDiscoveryDeviceCleanUp()
+       move from dmAllShared->mainExpanderList to dmAllShared->freeExpanderList; dmDiscoveryExpanderCleanUp()
+    */
+  }
+#endif
+  
+  if (onePortContext->DiscoveryState != DM_DSTATE_COMPLETED)
+  {
+    /* move from dmAllShared->discoveringExpanderList to dmAllShared->mainExpanderList 
+       move from dmAllShared->UpdiscoveringExpanderList to dmAllShared->mainExpanderList     
+    */
+    dmCleanAllExp(dmRoot, onePortContext);
+  }
+  
+  /* move mainExpanderList then MainDeviceList */
+  DM_DBG3(("dmDestroyPort: before dmDiscoveryExpanderCleanUp\n"));
+  dmDumpAllMainExp(dmRoot, onePortContext);
+  
+  /* move from dmAllShared->mainExpanderList to dmAllShared->freeExpanderList */
+  dmDiscoveryExpanderCleanUp(dmRoot, onePortContext);
+  
+  DM_DBG3(("dmDestroyPort: after dmDiscoveryExpanderCleanUp\n"));
+  dmDumpAllMainExp(dmRoot, onePortContext);
+  
+  DM_DBG3(("dmDestroyPort: before dmDiscoveryDeviceCleanUp\n"));
+  dmDumpAllMainDevice(dmRoot, onePortContext);
+  /* move devices from dmAllShared->MainDeviceList to dmAllShared->FreeDeviceList */
+  dmDiscoveryDeviceCleanUp(dmRoot, onePortContext);
+  
+  DM_DBG3(("dmDestroyPort: after dmDiscoveryDeviceCleanUp\n"));
+  dmDumpAllMainDevice(dmRoot, onePortContext);  
+  
+  dmPortContextReInit(dmRoot, onePortContext);
+  
+  tddmSingleThreadedEnter(dmRoot, DM_PORT_LOCK);
+
+  if (DMLIST_NOT_EMPTY(&(onePortContext->MainLink)))
+  {
+    DMLIST_DEQUEUE_THIS(&(onePortContext->MainLink));
+  }
+  else
+  {
+    DM_DBG1(("dmDestroyPort: onePortContext->MainLink is NULL, wrong!!!\n"));
+  }
+
+  if (DMLIST_NOT_EMPTY(&(onePortContext->FreeLink)) && DMLIST_NOT_EMPTY(&(dmAllShared->FreePortContextList)))
+  {
+    DMLIST_ENQUEUE_AT_TAIL(&(onePortContext->FreeLink), &(dmAllShared->FreePortContextList));
+  }
+  else
+  {
+    DM_DBG1(("dmDestroyPort: onePortContext->FreeLink or dmAllShared->FreePortContextList is NULL, wrong!!!\n"));
+  }
+  
+  tddmSingleThreadedLeave(dmRoot, DM_PORT_LOCK);
+
+  return DM_RC_SUCCESS;
+}	     	     
+#endif /* FDS_ DM */
+
+
+
+
+
+
+
+

sys/dev/pms/RefTisa/discovery/dm/dmproto.h

@@ -0,0 +1,833 @@
+/*******************************************************************************
+*
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+#ifndef __DMPROTO_H__
+#define __DMPROTO_H__
+
+#include <dev/pms/RefTisa/discovery/dm/dmtypes.h>
+
+/***************** util ****************************************/
+osGLOBAL void 
+*dm_memset(void *s, int c, bit32 n);
+
+osGLOBAL void 
+*dm_memcpy(void *dst, void *src, bit32 count);
+
+osGLOBAL void 
+dmhexdump(const char *ptitle, bit8 *pbuf, int len);
+
+
+/* timer related */
+osGLOBAL void
+dmInitTimers(
+             dmRoot_t *dmRoot 
+            );
+osGLOBAL void
+dmInitTimerRequest(
+                   dmRoot_t                *dmRoot, 
+                   dmTimerRequest_t        *timerRequest
+                   );
+		   		   
+osGLOBAL void
+dmSetTimerRequest(
+                  dmRoot_t            *dmRoot,
+                  dmTimerRequest_t    *timerRequest,
+                  bit32               timeout,
+                  dmTimerCBFunc_t     CBFunc,
+                  void                *timerData1,
+                  void                *timerData2,
+                  void                *timerData3
+                  );
+		  
+osGLOBAL void
+dmAddTimer(
+           dmRoot_t            *dmRoot,
+           dmList_t            *timerListHdr, 
+           dmTimerRequest_t    *timerRequest
+          );
+	  
+osGLOBAL void
+dmKillTimer(
+            dmRoot_t            *dmRoot,
+            dmTimerRequest_t    *timerRequest
+           );
+	   
+osGLOBAL void 
+dmProcessTimers(
+                dmRoot_t *dmRoot
+                );
+	   
+	  
+
+osGLOBAL void
+dmPortContextInit(
+                  dmRoot_t *dmRoot 
+                 );
+		    
+osGLOBAL void
+dmPortContextReInit(
+                    dmRoot_t		  *dmRoot,
+                    dmIntPortContext_t    *onePortContext		     
+                    );
+
+osGLOBAL void
+dmDeviceDataInit(
+                 dmRoot_t *dmRoot 
+                );
+
+osGLOBAL void
+dmDeviceDataReInit(
+                   dmRoot_t		  *dmRoot,
+                   dmDeviceData_t         *oneDeviceData		     
+                  );
+		  
+osGLOBAL void
+dmExpanderDeviceDataInit(
+                         dmRoot_t *dmRoot,
+                         bit32    max_exp			  
+                        );
+		   
+osGLOBAL void
+dmExpanderDeviceDataReInit(
+                           dmRoot_t 	    *dmRoot, 
+                           dmExpander_t     *oneExpander
+                          );
+
+
+osGLOBAL void
+dmSMPInit(
+          dmRoot_t *dmRoot 
+         );
+
+
+osGLOBAL bit32
+dmDiscoverCheck(
+                dmRoot_t 	    	*dmRoot, 
+                dmIntPortContext_t      *onePortContext	
+                );
+osGLOBAL void
+dmDiscoverAbort(
+                dmRoot_t 	    	*dmRoot, 
+                dmIntPortContext_t      *onePortContext	
+                );
+
+
+osGLOBAL bit32
+dmFullDiscover(
+               dmRoot_t 	    	*dmRoot, 
+               dmIntPortContext_t       *onePortContext	
+              );
+
+osGLOBAL bit32
+dmIncrementalDiscover(
+                      dmRoot_t 	    	      *dmRoot, 
+                      dmIntPortContext_t      *onePortContext,
+		      bit32                   flag	
+                     );
+
+osGLOBAL dmExpander_t *
+dmDiscoveringExpanderAlloc(
+                           dmRoot_t                 *dmRoot,
+                           dmIntPortContext_t       *onePortContext,
+                           dmDeviceData_t           *oneDeviceData
+                          );
+osGLOBAL void
+dmDiscoveringExpanderAdd(
+                         dmRoot_t                 *dmRoot,
+                         dmIntPortContext_t       *onePortContext,
+                         dmExpander_t             *oneExpander
+                        );
+
+osGLOBAL void
+dmDiscoveringExpanderRemove(
+                            dmRoot_t                 *dmRoot,
+                            dmIntPortContext_t       *onePortContext,
+                            dmExpander_t             *oneExpander
+                           );
+
+osGLOBAL dmExpander_t *
+dmExpFind(
+          dmRoot_t            *dmRoot,
+          dmIntPortContext_t  *onePortContext,
+          bit32               sasAddrHi,
+          bit32               sasAddrLo
+         );
+
+osGLOBAL dmExpander_t *
+dmExpMainListFind(
+                  dmRoot_t            *dmRoot,
+                  dmIntPortContext_t  *onePortContext,
+                  bit32               sasAddrHi,
+                  bit32               sasAddrLo
+                 );
+	 
+osGLOBAL dmDeviceData_t *
+dmDeviceFind(
+             dmRoot_t            *dmRoot,
+             dmIntPortContext_t  *onePortContext,
+             bit32               sasAddrHi,
+             bit32               sasAddrLo
+            );
+	 
+osGLOBAL void
+dmUpStreamDiscoverStart(
+                        dmRoot_t             *dmRoot,
+                        dmIntPortContext_t   *onePortContext
+                       );
+		      
+osGLOBAL void
+dmUpStreamDiscovering(
+                      dmRoot_t              *dmRoot,
+                      dmIntPortContext_t    *onePortContext,
+                      dmDeviceData_t        *oneDeviceData
+                     );
+
+osGLOBAL void
+dmDownStreamDiscovering(
+                        dmRoot_t              *dmRoot,
+                        dmIntPortContext_t    *onePortContext,
+                        dmDeviceData_t        *oneDeviceData
+                       );
+
+osGLOBAL void
+dmDownStreamDiscoverStart(
+                          dmRoot_t              *dmRoot,
+                          dmIntPortContext_t    *onePortContext,
+                          dmDeviceData_t        *oneDeviceData
+                         );
+		     
+osGLOBAL void
+dmCleanAllExp(
+              dmRoot_t                 *dmRoot,
+              dmIntPortContext_t       *onePortContext
+             );
+
+osGLOBAL void
+dmInternalRemovals(
+                   dmRoot_t                 *dmRoot,
+                   dmIntPortContext_t       *onePortContext
+                   );
+osGLOBAL void
+dmDiscoveryResetProcessed(
+                          dmRoot_t                 *dmRoot,
+                          dmIntPortContext_t       *onePortContext
+                         );
+		   
+osGLOBAL void
+dmDiscoverDone(
+               dmRoot_t                 *dmRoot,
+               dmIntPortContext_t       *onePortContext,
+               bit32                    flag
+              );
+
+osGLOBAL void
+dmUpStreamDiscoverExpanderPhy(
+                              dmRoot_t              *dmRoot,
+                              dmIntPortContext_t    *onePortContext,
+                              dmExpander_t          *oneExpander,
+                              smpRespDiscover_t     *pDiscoverResp
+                             );
+
+osGLOBAL void
+dmUpStreamDiscover2ExpanderPhy(
+                              dmRoot_t              *dmRoot,
+                              dmIntPortContext_t    *onePortContext,
+                              dmExpander_t          *oneExpander,
+                              smpRespDiscover2_t    *pDiscoverResp
+                             );
+
+osGLOBAL void
+dmDownStreamDiscoverExpanderPhy(
+                                dmRoot_t              *dmRoot,
+                                dmIntPortContext_t    *onePortContext,
+                                dmExpander_t          *oneExpander,
+                                smpRespDiscover_t     *pDiscoverResp
+                               );
+osGLOBAL void
+dmDownStreamDiscover2ExpanderPhy(
+                                dmRoot_t              *dmRoot,
+                                dmIntPortContext_t    *onePortContext,
+                                dmExpander_t          *oneExpander,
+                                smpRespDiscover2_t     *pDiscoverResp
+                               );
+
+osGLOBAL void
+dmUpStreamDiscoverExpanderPhySkip(
+                                   dmRoot_t              *dmRoot,
+                                   dmIntPortContext_t    *onePortContext,
+                                   dmExpander_t          *oneExpander
+                                   );
+
+osGLOBAL void
+dmUpStreamDiscover2ExpanderPhySkip(
+                                   dmRoot_t              *dmRoot,
+                                   dmIntPortContext_t    *onePortContext,
+                                   dmExpander_t          *oneExpander
+                                   );
+
+osGLOBAL void
+dmDownStreamDiscoverExpanderPhySkip(
+                                     dmRoot_t              *dmRoot,
+                                     dmIntPortContext_t    *onePortContext,
+                                     dmExpander_t          *oneExpander
+                                     );
+osGLOBAL void
+dmDownStreamDiscover2ExpanderPhySkip(
+                                     dmRoot_t              *dmRoot,
+                                     dmIntPortContext_t    *onePortContext,
+                                     dmExpander_t          *oneExpander
+                                     );
+
+osGLOBAL void
+dmDiscoveringUndoAdd(
+                     dmRoot_t                 *dmRoot,
+                     dmIntPortContext_t       *onePortContext,
+                     dmExpander_t             *oneExpander
+                    );
+
+
+osGLOBAL void
+dmExpanderUpStreamPhyAdd(
+                         dmRoot_t              *dmRoot,
+                         dmExpander_t          *oneExpander,
+                         bit8                  phyId
+                         );
+
+osGLOBAL void
+dmExpanderDownStreamPhyAdd(
+                           dmRoot_t              *dmRoot,
+                           dmExpander_t          *oneExpander,
+                           bit8                  phyId
+                          );
+
+osGLOBAL dmDeviceData_t *
+dmPortSASDeviceFind(
+                    dmRoot_t            *dmRoot,
+                    dmIntPortContext_t  *onePortContext,
+                    bit32               sasAddrLo,
+                    bit32               sasAddrHi,
+                    dmDeviceData_t      *CurrentDeviceData		    
+                    );  
+bit32
+dmNewEXPorNot(
+              dmRoot_t              *dmRoot,
+              dmIntPortContext_t    *onePortContext,
+              dmSASSubID_t          *dmSASSubID
+             );
+
+bit32
+dmNewSASorNot(
+              dmRoot_t              *dmRoot,
+              dmIntPortContext_t    *onePortContext,
+              dmSASSubID_t          *dmSASSubID
+             );
+
+osGLOBAL dmDeviceData_t *
+dmPortSASDeviceAdd(
+                   dmRoot_t            *dmRoot,
+                   dmIntPortContext_t  *onePortContext,
+                   agsaSASIdentify_t   sasIdentify,
+                   bit32               sasInitiator,
+                   bit8                connectionRate,
+                   bit32               itNexusTimeout,
+                   bit32               firstBurstSize,
+                   bit32               deviceType,
+                   dmDeviceData_t      *oneDeviceData,
+                   dmExpander_t        *dmExpander,
+                   bit8                phyID
+                  );
+
+
+osGLOBAL dmDeviceData_t *
+dmFindRegNValid(
+                dmRoot_t             *dmRoot,
+                dmIntPortContext_t   *onePortContext,
+                dmSASSubID_t         *dmSASSubID
+               );								
+
+osGLOBAL dmExpander_t *
+dmFindConfigurableExp(
+                      dmRoot_t                  *dmRoot,
+                      dmIntPortContext_t        *onePortContext,
+                      dmExpander_t              *oneExpander
+                     );
+
+osGLOBAL bit32
+dmDuplicateConfigSASAddr(
+                         dmRoot_t                 *dmRoot,
+                         dmExpander_t             *oneExpander,
+                         bit32                    configSASAddressHi,
+                         bit32                    configSASAddressLo
+                        );
+
+
+osGLOBAL bit16
+dmFindCurrentDownStreamPhyIndex(
+                                dmRoot_t          *dmRoot,
+                                dmExpander_t      *oneExpander
+                                );
+
+
+osGLOBAL bit32
+dmFindDiscoveringExpander(
+                          dmRoot_t                  *dmRoot,
+                          dmIntPortContext_t        *onePortContext,
+                          dmExpander_t              *oneExpander
+                         );
+
+osGLOBAL void
+dmDumpAllExp(
+             dmRoot_t                  *dmRoot,
+             dmIntPortContext_t        *onePortContext,
+             dmExpander_t              *oneExpander
+            );
+
+
+osGLOBAL void
+dmDumpAllUpExp(
+               dmRoot_t                  *dmRoot,
+               dmIntPortContext_t        *onePortContext,
+               dmExpander_t              *oneExpander
+              );
+
+osGLOBAL void
+dmDumpAllFreeExp(
+                 dmRoot_t                  *dmRoot
+                );
+
+osGLOBAL void
+dmDumpAllMainExp(
+                 dmRoot_t                 *dmRoot,
+                 dmIntPortContext_t       *onePortContext
+                );
+
+osGLOBAL void
+dmDumpAllMainDevice(
+                   dmRoot_t                 *dmRoot,
+                   dmIntPortContext_t       *onePortContext
+                   );
+		
+osGLOBAL void
+dmSubReportChanges(
+                   dmRoot_t                  *dmRoot,
+                   dmIntPortContext_t        *onePortContext,
+		   dmDeviceData_t            *oneDeviceData,
+                   bit32                     flag
+                  );
+osGLOBAL void
+dmSubReportRemovals(
+                   dmRoot_t                  *dmRoot,
+                   dmIntPortContext_t        *onePortContext,
+                   dmDeviceData_t            *oneDeviceData,
+                   bit32                     flag
+                  );
+		  
+osGLOBAL void
+dmReportChanges(
+                dmRoot_t                  *dmRoot,
+                dmIntPortContext_t        *onePortContext
+               );
+
+osGLOBAL void
+dmReportRemovals(
+                 dmRoot_t                  *dmRoot,
+                 dmIntPortContext_t        *onePortContext,
+                 bit32                     flag
+                );
+
+osGLOBAL void
+dmDiscoveryDeviceCleanUp(
+                         dmRoot_t                  *dmRoot,
+                         dmIntPortContext_t        *onePortContext
+                        );
+osGLOBAL void
+dmDiscoveryExpanderCleanUp(
+                         dmRoot_t                  *dmRoot,
+                         dmIntPortContext_t        *onePortContext
+                        );
+
+osGLOBAL void
+dmResetReported(
+                dmRoot_t                  *dmRoot,
+                dmIntPortContext_t        *onePortContext
+               );
+
+osGLOBAL void
+dmDiscoveryErrorRemovals(
+                         dmRoot_t                  *dmRoot,
+                         dmIntPortContext_t        *onePortContext
+                        );
+osGLOBAL void
+dmDiscoveryInvalidateDevices(
+                             dmRoot_t                  *dmRoot,
+                             dmIntPortContext_t        *onePortContext
+                            );
+
+osGLOBAL dmDeviceData_t *
+dmAddSASToSharedcontext(
+                         dmRoot_t              *dmRoot,
+                         dmIntPortContext_t    *onePortContext,
+                         dmSASSubID_t          *dmSASSubID,
+                         dmDeviceData_t        *oneExpDeviceData,
+                         bit8                  phyID
+                        );
+osGLOBAL bit32
+dmSAS2SAS11ErrorCheck(
+                      dmRoot_t              *dmRoot,
+                      dmIntPortContext_t    *onePortContext,
+                      dmExpander_t          *topExpander,
+                      dmExpander_t          *bottomExpander,
+                      dmExpander_t          *currentExpander
+                     );
+
+osGLOBAL void
+dmUpdateMCN(
+            dmRoot_t            *dmRoot,
+            dmIntPortContext_t  *onePortContext,
+            dmDeviceData_t      *AdjacentDeviceData, /* adjacent expander */ 		    
+            dmDeviceData_t      *oneDeviceData /* current one */
+           );
+
+osGLOBAL void
+dmUpdateAllAdjacent(
+                    dmRoot_t            *dmRoot,
+                    dmIntPortContext_t  *onePortContext,
+                    dmDeviceData_t      *oneDeviceData /* current one */
+                   );
+osGLOBAL void
+dmDiscoveryResetMCN(
+                    dmRoot_t                 *dmRoot,
+                    dmIntPortContext_t       *onePortContext
+                   );
+
+osGLOBAL void
+dmDiscoveryDumpMCN(
+                    dmRoot_t                 *dmRoot,
+                    dmIntPortContext_t       *onePortContext
+                   );
+
+osGLOBAL void
+dmDiscoveryReportMCN(
+                    dmRoot_t                 *dmRoot,
+                    dmIntPortContext_t       *onePortContext
+                   );
+
+GLOBAL void dmSetDeviceInfoCB(
+                                agsaRoot_t        *agRoot,
+                                agsaContext_t     *agContext, 
+                                agsaDevHandle_t   *agDevHandle,
+                                bit32             status,
+                                bit32             option,
+                                bit32             param
+                                );
+
+/*********************************** SMP-related *******************************************************/
+osGLOBAL void 
+dmsaSMPCompleted( 
+                 agsaRoot_t            *agRoot,
+                 agsaIORequest_t       *agIORequest,
+                 bit32                 agIOStatus,
+                 bit32                 agIOInfoLen,
+                 agsaFrameHandle_t     agFrameHandle
+                 );
+		 
+osGLOBAL bit32
+dmSMPStart(
+           dmRoot_t              *dmRoot,
+           agsaRoot_t            *agRoot,
+           dmDeviceData_t        *oneDeviceData,
+           bit32                 functionCode,
+           bit8                  *pSmpBody,
+           bit32                 smpBodySize,
+           bit32                 agRequestType
+           );
+
+osGLOBAL void
+dmReportGeneralSend(
+                    dmRoot_t             *dmRoot,
+                    dmDeviceData_t       *oneDeviceData
+                    );
+
+osGLOBAL void
+dmReportGeneralRespRcvd(
+                        dmRoot_t              *dmRoot,
+                        agsaRoot_t            *agRoot,
+                        agsaIORequest_t       *agIORequest,
+                        dmDeviceData_t        *oneDeviceData,
+                        dmSMPFrameHeader_t    *frameHeader,
+                        agsaFrameHandle_t     frameHandle
+                        );
+
+osGLOBAL void
+dmReportGeneral2RespRcvd(
+                        dmRoot_t              *dmRoot,
+                        agsaRoot_t            *agRoot,
+                        agsaIORequest_t       *agIORequest,
+                        dmDeviceData_t        *oneDeviceData,
+                        dmSMPFrameHeader_t    *frameHeader,
+                        agsaFrameHandle_t     frameHandle
+                        );
+
+osGLOBAL void
+dmDiscoverSend(
+               dmRoot_t             *dmRoot,
+               dmDeviceData_t       *oneDeviceData	       
+              );
+
+osGLOBAL void
+dmDiscoverRespRcvd(
+                   dmRoot_t              *dmRoot,
+                   agsaRoot_t            *agRoot,
+                   agsaIORequest_t       *agIORequest,
+                   dmDeviceData_t        *oneDeviceData,
+                   dmSMPFrameHeader_t    *frameHeader,
+                   agsaFrameHandle_t     frameHandle
+                  );
+
+osGLOBAL void
+dmDiscover2RespRcvd(
+                   dmRoot_t              *dmRoot,
+                   agsaRoot_t            *agRoot,
+                   agsaIORequest_t       *agIORequest,
+                   dmDeviceData_t        *oneDeviceData,
+                   dmSMPFrameHeader_t    *frameHeader,
+                   agsaFrameHandle_t     frameHandle
+                  );
+
+#ifdef NOT_YET
+osGLOBAL void
+dmDiscoverList2Send(
+                    dmRoot_t             *dmRoot,
+                    dmDeviceData_t       *oneDeviceData
+                   );
+
+osGLOBAL void
+dmDiscoverList2RespRcvd(
+                        dmRoot_t              *dmRoot,
+                        agsaRoot_t            *agRoot,
+                        dmDeviceData_t        *oneDeviceData,
+                        dmSMPFrameHeader_t    *frameHeader,
+                        agsaFrameHandle_t     frameHandle
+                       );
+#endif		     
+
+osGLOBAL void
+dmReportPhySataSend(
+                    dmRoot_t             *dmRoot,
+                    dmDeviceData_t       *oneDeviceData,
+                    bit8                 phyId
+                    );
+
+osGLOBAL void
+dmReportPhySataRcvd(
+                    dmRoot_t              *dmRoot,
+                    agsaRoot_t            *agRoot,
+                    agsaIORequest_t       *agIORequest,
+                    dmDeviceData_t        *oneDeviceData,
+                    dmSMPFrameHeader_t    *frameHeader,
+                    agsaFrameHandle_t     frameHandle
+                   );
+
+osGLOBAL void
+dmReportPhySata2Rcvd(
+                    dmRoot_t              *dmRoot,
+                    agsaRoot_t            *agRoot,
+                    agsaIORequest_t       *agIORequest,
+                    dmDeviceData_t        *oneDeviceData,
+                    dmSMPFrameHeader_t    *frameHeader,
+                    agsaFrameHandle_t     frameHandle
+                   );
+
+osGLOBAL bit32
+dmRoutingEntryAdd(
+                  dmRoot_t          *dmRoot,
+                  dmExpander_t      *oneExpander,
+                  bit32             phyId,  
+                  bit32             configSASAddressHi,
+                  bit32             configSASAddressLo
+                 );
+
+osGLOBAL void
+dmConfigRoutingInfoRespRcvd(
+                            dmRoot_t              *dmRoot,
+                            agsaRoot_t            *agRoot,
+                            agsaIORequest_t       *agIORequest,
+                            dmDeviceData_t        *oneDeviceData,
+                            dmSMPFrameHeader_t    *frameHeader,
+                            agsaFrameHandle_t     frameHandle
+                           );
+						
+osGLOBAL void
+dmConfigRoutingInfo2RespRcvd(
+                            dmRoot_t              *dmRoot,
+                            agsaRoot_t            *agRoot,
+                            agsaIORequest_t       *agIORequest,
+                            dmDeviceData_t        *oneDeviceData,
+                            dmSMPFrameHeader_t    *frameHeader,
+                            agsaFrameHandle_t     frameHandle
+                           );
+						
+osGLOBAL bit32
+dmPhyControlSend(
+                 dmRoot_t             *dmRoot,
+                 dmDeviceData_t       *oneDeviceData,
+                 bit8                 phyOp,
+                 bit8                 phyID
+                 );
+
+osGLOBAL void
+dmPhyControlRespRcvd(
+                     dmRoot_t              *dmRoot,
+                     agsaRoot_t            *agRoot,
+                     agsaIORequest_t       *agIORequest,
+                     dmDeviceData_t        *oneDeviceData,
+                     dmSMPFrameHeader_t    *frameHeader,
+                     agsaFrameHandle_t     frameHandle
+                    );
+
+osGLOBAL void
+dmPhyControl2RespRcvd(
+                     dmRoot_t              *dmRoot,
+                     agsaRoot_t            *agRoot,
+                     agsaIORequest_t       *agIORequest,
+                     dmDeviceData_t        *oneDeviceData,
+                     dmSMPFrameHeader_t    *frameHeader,
+                     agsaFrameHandle_t     frameHandle
+                    );
+
+osGLOBAL void
+dmPhyControlFailureRespRcvd(
+                            dmRoot_t              *dmRoot,
+                            agsaRoot_t            *agRoot,
+                            dmDeviceData_t        *oneDeviceData,
+                            dmSMPFrameHeader_t    *frameHeader,
+                            agsaFrameHandle_t     frameHandle
+                           );
+
+osGLOBAL void
+dmHandleZoneViolation(
+                      dmRoot_t              *dmRoot,
+                      agsaRoot_t            *agRoot,
+                      agsaIORequest_t       *agIORequest,
+                      dmDeviceData_t        *oneDeviceData,
+                      dmSMPFrameHeader_t    *frameHeader,
+                      agsaFrameHandle_t     frameHandle
+                     );
+
+osGLOBAL void
+dmSMPCompleted(
+               agsaRoot_t            *agRoot,
+               agsaIORequest_t       *agIORequest,
+               bit32                 agIOStatus,
+               bit32                 agIOInfoLen,
+               agsaFrameHandle_t     agFrameHandle                   
+              );
+
+osGLOBAL void
+dmSMPAbortCB(
+             agsaRoot_t           *agRoot,
+             agsaIORequest_t      *agIORequest,
+             bit32                flag,
+             bit32                status
+             );
+	     
+osGLOBAL void                          
+dmBCTimer(
+          dmRoot_t                 *dmRoot,
+          dmIntPortContext_t       *onePortContext
+         );
+
+osGLOBAL void
+dmBCTimerCB(
+              dmRoot_t    * dmRoot_t, 
+              void        * timerData1,
+              void        * timerData2,
+              void        * timerData3
+              );
+
+/*********************************** SMP-related *******************************************************/
+osGLOBAL void
+dmDiscoverySMPTimer(dmRoot_t                 *dmRoot,
+                    dmIntPortContext_t       *onePortContext,
+                    bit32                    functionCode,
+                    dmSMPRequestBody_t       *dmSMPRequestBody
+                   );
+
+osGLOBAL void
+dmDiscoverySMPTimerCB(
+                      dmRoot_t    * dmRoot, 
+                      void        * timerData1,
+                      void        * timerData2,
+                      void        * timerData3
+                     );
+
+osGLOBAL void                          
+dmDiscoveryConfiguringTimer(dmRoot_t                 *dmRoot,
+                            dmIntPortContext_t       *onePortContext,
+                            dmDeviceData_t           *oneDeviceData
+                           );
+
+
+osGLOBAL void
+dmDiscoveryConfiguringTimerCB(
+                              dmRoot_t    * dmRoot, 
+                              void        * timerData1,
+                              void        * timerData2,
+                              void        * timerData3
+                             );
+
+osGLOBAL void                          
+dmSMPBusyTimer(dmRoot_t             *dmRoot,
+               dmIntPortContext_t   *onePortContext,
+               dmDeviceData_t       *oneDeviceData,
+               dmSMPRequestBody_t   *dmSMPRequestBody
+              );
+
+osGLOBAL void
+dmSMPBusyTimerCB(
+                 dmRoot_t    * dmRoot, 
+                 void        * timerData1,
+                 void        * timerData2,
+                 void        * timerData3
+                );
+
+osGLOBAL void                          
+dmConfigureRouteTimer(dmRoot_t                 *dmRoot,
+                      dmIntPortContext_t       *onePortContext,
+                      dmExpander_t             *oneExpander,
+                      smpRespDiscover_t        *pdmSMPDiscoverResp,
+                      smpRespDiscover2_t       *pdmSMPDiscover2Resp
+                     );
+
+osGLOBAL void
+dmConfigureRouteTimerCB(
+                        dmRoot_t    * dmRoot, 
+                        void        * timerData1,
+                        void        * timerData2,
+                        void        * timerData3
+                       );
+
+#endif                          /* __DMPROTO_H__ */
+
+

sys/dev/pms/RefTisa/discovery/dm/dmtimer.c

@@ -0,0 +1,163 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+**
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+
+#include <dev/pms/RefTisa/discovery/dm/dmdefs.h>
+#include <dev/pms/RefTisa/discovery/dm/dmtypes.h>
+#include <dev/pms/RefTisa/discovery/dm/dmproto.h>
+
+osGLOBAL void   
+dmTimerTick(dmRoot_t 		*dmRoot )
+{
+  DM_DBG6(("dmTimerTick: start\n"));
+  
+  dmProcessTimers(dmRoot);
+
+  return;
+}	  																
+				
+osGLOBAL void
+dmInitTimerRequest(
+                     dmRoot_t                *dmRoot, 
+                     dmTimerRequest_t        *timerRequest
+                     )
+{
+  timerRequest->timeout       = 0;
+  timerRequest->timerCBFunc   = agNULL;
+  timerRequest->timerData1     = agNULL;
+  timerRequest->timerData2     = agNULL;
+  timerRequest->timerData3     = agNULL;
+  DMLIST_INIT_ELEMENT((&timerRequest->timerLink));
+}
+
+osGLOBAL void
+dmSetTimerRequest(
+                  dmRoot_t            *dmRoot,
+                  dmTimerRequest_t    *timerRequest,
+                  bit32               timeout,
+                  dmTimerCBFunc_t     CBFunc,
+                  void                *timerData1,
+                  void                *timerData2,
+                  void                *timerData3
+                  )
+{
+  timerRequest->timeout     = timeout;
+  timerRequest->timerCBFunc = CBFunc;
+  timerRequest->timerData1   = timerData1;
+  timerRequest->timerData2   = timerData2;
+  timerRequest->timerData3   = timerData3;
+}
+
+osGLOBAL void
+dmAddTimer(
+           dmRoot_t            *dmRoot,
+           dmList_t            *timerListHdr, 
+           dmTimerRequest_t    *timerRequest
+          )
+{
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  DMLIST_ENQUEUE_AT_TAIL(&(timerRequest->timerLink), timerListHdr);
+  timerRequest->timerRunning = agTRUE;
+  tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+}
+
+osGLOBAL void
+dmKillTimer(
+            dmRoot_t            *dmRoot,
+            dmTimerRequest_t    *timerRequest
+           )
+{
+  tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+  timerRequest->timerRunning = agFALSE;
+  DMLIST_DEQUEUE_THIS(&(timerRequest->timerLink));
+  tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+}
+
+
+osGLOBAL void 
+dmProcessTimers(
+                dmRoot_t *dmRoot
+                )
+{
+  dmIntRoot_t               *dmIntRoot    = (dmIntRoot_t *)dmRoot->dmData;
+  dmIntContext_t            *dmAllShared = (dmIntContext_t *)&dmIntRoot->dmAllShared;
+  dmTimerRequest_t          *timerRequest_to_process = agNULL;
+  dmList_t                  *timerlist_to_process, *nexttimerlist = agNULL;
+
+  
+  timerlist_to_process = &dmAllShared->timerlist;
+  
+  timerlist_to_process = timerlist_to_process->flink;
+
+  while ((timerlist_to_process != agNULL) && (timerlist_to_process != &dmAllShared->timerlist))
+  {
+    nexttimerlist = timerlist_to_process->flink;
+    
+    tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+    timerRequest_to_process = DMLIST_OBJECT_BASE(dmTimerRequest_t, timerLink, timerlist_to_process);
+    tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+    
+    if (timerRequest_to_process == agNULL)
+    {
+      DM_DBG1(("dmProcessTimers: timerRequest_to_process is NULL! Error!!!\n"));
+      return;      
+    }
+    
+    timerRequest_to_process->timeout--;
+    
+    if (timerRequest_to_process->timeout == 0)
+    {      
+      tddmSingleThreadedEnter(dmRoot, DM_TIMER_LOCK);
+      timerRequest_to_process->timerRunning = agFALSE;
+      DMLIST_DEQUEUE_THIS(timerlist_to_process);
+      tddmSingleThreadedLeave(dmRoot, DM_TIMER_LOCK);
+      /* calling call back function */
+      (timerRequest_to_process->timerCBFunc)(dmRoot, 
+                                             timerRequest_to_process->timerData1, 
+                                             timerRequest_to_process->timerData2, 
+                                             timerRequest_to_process->timerData3 
+                                             );
+    }
+    timerlist_to_process = nexttimerlist;
+  }
+
+ return;
+}
+#endif /* FDS_ DM */
+

sys/dev/pms/RefTisa/discovery/dm/dmtypes.h

@@ -0,0 +1,428 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+#ifndef __DMTYPES_H__
+#define __DMTYPES_H__
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+
+#include <dev/pms/RefTisa/discovery/dm/dmlist.h>
+#ifdef TBD
+#include <dev/pms/RefTisa/tisa/api/tiscsi.h>
+#endif
+
+
+/* for SMP only */
+typedef void (*dmSMPCompleted_t) (
+                                    agsaRoot_t            *,
+                                    agsaIORequest_t       *,
+                                    bit32                 ,
+                                    bit32                 ,
+                                    agsaFrameHandle_t     
+                                    );
+
+
+/* timer functions ; both I and T */
+typedef void (*dmTimerCBFunc_t)(dmRoot_t *dmRoot, void *timerData1, void *timerData2, void *timerData3);
+
+
+/** \brief data structure for timer request
+ *  Timer requests are enqueued and dequeued using dmList_t
+ *  and have a callback function
+ */
+typedef struct dmTimerRequest_s {
+  /* the number of ticks */
+  bit32             timeout;
+  void              *timerData1;
+  void              *timerData2;
+  void              *timerData3;
+  dmTimerCBFunc_t   timerCBFunc;
+  dmList_t          timerLink;
+  bit32             timerRunning;
+}  dmTimerRequest_t;
+
+typedef struct dmRootOsData_s {
+  dmRoot_t  *dmRoot;            /**< Pointer back to dmRoot                 */
+  void      *dmAllShared;       /**< Pointer to dmContext_t               */
+  void      *dmIni;             /**< Pointer to SAS/SATA initiator               */
+}  dmRootOsData_t;
+
+typedef struct DMSASAddressID_s 
+{
+  bit32   sasAddressLo;     /**< HOST SAS address lower part */
+  bit32   sasAddressHi;     /**< HOST SAS address higher part */
+  bit8    phyIdentifier;    /**< PHY IDENTIFIER of the PHY */
+} DMSASAddressID_t;
+
+struct dmExpander_s;
+
+typedef struct dmDiscovery_s 
+{
+  dmList_t                   discoveringExpanderList;
+  dmList_t                   UpdiscoveringExpanderList;
+  //  tdList_t                   freeExpanderList;
+  bit32                   status;
+  DMSASAddressID_t        sasAddressIDDiscoverError;
+  agsaSATAIdentifyData_t  *pSataIdentifyData;
+  struct dmExpander_s     *RootExp; /* Root expander of discovery */
+  bit32                   NumOfUpExp;
+  bit32                   type; /* discovery type: TDSA_DISCOVERY_OPTION_FULL_START 
+                                   or TDSA_DISCOVERY_OPTION_INCREMENTAL_START*/
+  bit32                   retries;                                   
+  bit32                   configureRouteRetries; 
+  bit32                   deviceRetistrationRetries; 
+  dmTimerRequest_t        discoveryTimer;
+  dmTimerRequest_t        configureRouteTimer;
+  dmTimerRequest_t        deviceRegistrationTimer;
+  dmTimerRequest_t        BCTimer; /* Broadcast Change timer for ResetTriggerred */
+  smpRespDiscover_t       SMPDiscoverResp;
+  smpRespDiscover2_t      SMPDiscover2Resp;
+  bit32                   pendingSMP; /* the number of pending SMP for this discovery */
+  bit32                   SeenBC; /* received Broadcast change */
+  bit32                   forcedOK; /* report DiscOK when chance is missed */ 
+  dmTimerRequest_t        SMPBusyTimer; /* SMP retry timer for saSMPStart busy */
+  bit32                   SMPRetries; /* number of SMP retries when LL returns busy for saSMPStart*/
+  bit32                   ResetTriggerred; /* Hard/Link reset triggerred by discovery */
+  dmTimerRequest_t        DiscoverySMPTimer; /* discovery-related SMP application Timer */
+  /* For SAS 2 */
+  bit32                   DeferredError; /* Deferred Error for SAS 2 */
+  bit32                   ConfiguresOthers; /* exp configures others; no routing configuration */
+} dmDiscovery_t;
+
+typedef struct dmSASSubID_s
+{
+  bit32        sasAddressHi;
+  bit32        sasAddressLo;
+  bit8         initiator_ssp_stp_smp;
+  bit8         target_ssp_stp_smp;
+
+} dmSASSubID_t;
+
+struct dmDeviceData_s;
+
+typedef struct dmIntPortContext_s
+{
+  /**< current number of devices in this PortContext */
+  bit32                         Count;
+  bit32                   DiscoveryState;   
+  bit32                   DiscoveryAbortInProgress;   
+  /* passed by tiINIDiscoverTargets()
+     eg) discovery or rediscovery ....
+  */
+  bit32                   discoveryOptions;
+  /* Discovery ready is given? */ 
+  bit32                   DiscoveryRdyGiven; 
+  /* Port has received link up */
+  bit32                   SeenLinkUp;
+  /* statistics */
+  bit32                   numAvailableTargets;
+  /* flag: indicates that discovery is trigggered by tiINIDiscoverTargets */
+  bit32                   osInitiatedDiscovery;
+  
+  bit32                         id; /* for debugging only */
+  dmList_t                      FreeLink; /**< free portcontext list */
+  dmList_t                      MainLink; /**< in-use portcontext list */
+  /**< SAS address of the remote device */
+  bit32                         sasRemoteAddressHi; /**< SAS address high part */
+  bit32                         sasRemoteAddressLo; /**< SAS address low part */
+  /**< SAS ID frame of the remote device */
+  agsaSASIdentify_t             sasIDframe;
+  
+  /**< SAS address of the local device*/
+  bit32                         sasLocalAddressHi; /**< SAS address high part */
+  bit32                         sasLocalAddressLo; /**< SAS address low part */
+#ifdef TBD
+  /**< the list of PhyID belonging to this port */
+  bit8                          PhyIDList[DM_MAX_NUM_PHYS];
+#endif  
+  dmPortContext_t               *dmPortContext;
+  dmRoot_t                      *dmRoot;
+  
+#ifdef TBD  
+  /* used in tiINIDiscoverTarget() */
+  agsaRoot_t                    *agRoot;
+  agsaPortContext_t             *agPortContext;
+  /* maybe needs timers for saPhyStart() */
+
+  bit8                  nativeSATAMode; /* boolean flag: whether the port is in Native SATA mode */
+  bit8                remoteSignature[8]; /* the remote signature of the port is the port is in native SATA mode */
+#endif  
+  bit8                 directAttatchedSAS; /* boolean flag: whether the port connected directly to SAS end device*/
+  /* SAS/SATA discovery information such as discoveringExpanderList */
+  dmDiscovery_t              discovery;
+  bit32                      valid;
+  bit8                       LinkRate;
+  bit32                      RegisteredDevNums; /* registered number of devices */
+  bit32                      eventPhyID; /* used for saHwEventAck() */
+  bit32                      Transient; /* transient period between link up and link down/port recovery */
+  bit32                      RegFailed; /* Registration of expander belonging to this port failure */ 
+  
+}  dmIntPortContext_t;
+
+typedef struct dmDeviceData_s  {
+
+  dmList_t                FreeLink; /* free dev list */
+  dmList_t                MainLink; /* main(in use) dev list */
+  dmList_t                IncDisLink; /* Used for incremental Discovery only */
+  bit32                   id; /* for debugging only */
+  bit8                    DeviceType;
+  /* used in tiINIIOStart() */
+  dmRoot_t                *dmRoot;
+//  agsaDevHandle_t         *agDevHandle;
+  
+  /* for SAS; remote device */
+  //  agsaSASDeviceInfo_t     agSASDeviceInfo;
+  /* device's sas address */
+  DMSASAddressID_t        SASAddressID;
+  bit8                    initiator_ssp_stp_smp;
+  bit8                    target_ssp_stp_smp;
+  bit8                    numOfPhys;
+
+  /* SATA specific data */
+  bit8                    satSignature[8];          /* SATA device Signature*/
+
+  /**< pointer to tdsaPortcontext which the device belongs to */
+  struct dmIntPortContext_s *dmPortContext;
+  /* validity of device */
+  bit8                    valid;
+  bit8                    valid2;
+  bit8                    processed; /* used in TD discovery */
+#ifdef AGTIAPI_CTL
+  bit8                    discovered;
+#endif
+  agsaDeviceInfo_t        agDeviceInfo;
+  dmDeviceInfo_t          dmDeviceInfo;
+  agsaContext_t           agContext; /* used in saRegisterNewDevice()*/
+  /**< pointer to dmExpander if Device is expander */
+  struct dmExpander_s     *dmExpander;
+  struct dmDeviceData_s   *ExpDevice; /* Expander device which this device is attached to */
+  
+  bit8                    phyID;      /* PhyID this device is attached to SPC or expander */
+  agsaSASIdentify_t     sasIdentify; /* used only in TD discovery */
+  bit8                  connectionRate;
+//  bit8                  registered;
+  bit8                  directlyAttached;
+  bit8                  SASSpecDeviceType; /* 0 - 3; SAS_NO_DEVICE - SAS_FANOUT_EXPANDER_DEVICE */
+  bit32                 IOStart;
+  bit32                 IOResponse;
+  agsaContext_t         agDeviceResetContext; /* used in saLocalPhyControl() */
+  bit32                 TRflag; /* transport recovery flag; used only for tiINITransportRecovery */
+  bit32                 ResetCnt; /* number of reset to the device */  
+  bit32                 registered; /* registered to LL */
+  bit32                 reported; /* reproted to TDM */  
+  bit32                 MCN; /* MCN; initialized to 0; current value in discovery */  
+  bit32                 MCNDone; /* done in updating MCN */  
+  bit32                 PrevMCN; /* MCN; initialized to 0; previous value in discovery */  
+
+}  dmDeviceData_t;
+
+
+typedef struct dmExpander_s 
+{
+  /* start of dmDeviceData */
+#ifdef TBD 
+  dmList_t                FreeLink; /* free dev list */
+  dmList_t                MainLink; /* main(in use) dev list */
+#endif  
+  bit32                   id; /* for debugging only */
+  bit32                   InQID; /* Inbound queue ID */
+  bit32                   OutQID; /* Outbound queue ID */
+  bit8                    DeviceType;
+  /* used in tiINIIOStart() */
+  dmRoot_t                *dmRoot;
+  agsaDevHandle_t         *agDevHandle;
+
+  dmList_t                  linkNode; /**< the link node data structure of the expander */
+  dmList_t                  upNode; /**< the link node data structure of the expander */
+  dmDeviceData_t            *dmDevice; /**< the pointer to the device data */
+  struct dmExpander_s       *dmUpStreamExpander; /**< the pointer to the upstream expander device */
+  bit8                      hasUpStreamDevice;
+  bit8                      discoveringPhyId;
+  bit16                     routingIndex; /* maximum routing table index reported by expander */
+  bit16                     currentIndex[DM_MAX_EXPANDER_PHYS]; /* routing table index in use */
+  /*ReportPhySataSend in DM */ 
+  dmDeviceData_t            *dmDeviceToProcess;    /* on some callbacks, this is a link to the device of interest */
+  
+  bit32                     configSASAddressHi;
+  bit32                     configSASAddressLo;
+  struct dmExpander_s       *dmCurrentDownStreamExpander; 
+  bit8                      upStreamPhys[DM_MAX_EXPANDER_PHYS];
+  bit16                     numOfUpStreamPhys;
+  bit16                     currentUpStreamPhyIndex;
+  bit32                     upStreamSASAddressHi; 
+  bit32                     upStreamSASAddressLo;  
+  bit32                     underDiscovering;
+  bit32                     configRouteTable: 1;
+  bit32                     configuring: 1;
+  bit32                     configReserved: 30;
+#ifdef TBD  
+  bit32                   id; /* for debugging */
+#endif
+  struct dmExpander_s       *dmReturnginExpander;
+  bit8                      downStreamPhys[DM_MAX_EXPANDER_PHYS];
+  bit16                     numOfDownStreamPhys;
+  bit8                      currentDownStreamPhyIndex;
+  bit32                     discoverSMPAllowed; /* used only for configurable routers */
+  bit8                      routingAttribute[DM_MAX_EXPANDER_PHYS];
+  bit32                     configSASAddressHiTable[DM_MAX_DEV];
+  bit32                     configSASAddressLoTable[DM_MAX_DEV];
+  bit32                     configSASAddrTableIndex;  
+  /* for SAS 2 */  
+  bit32                     SAS2; /* supports SAS2 spec of not. The value of LONG RESPONSE 
+                                     in report general response */
+  bit32                     TTTSupported; /* Table to Table is supported */
+  bit32                     UndoDueToTTTSupported; /* flag that indicates undo exp, device, route
+                                                      configuration due to TTT */
+  
+} dmExpander_t;
+
+typedef struct dmIndirectSMPRequestBody_s {
+  dmList_t                     Link;
+  bit32                        id;
+
+}  dmIndirectSMPRequestBody_t;
+
+/*
+  should DM allocate a pool of SMP and manages it 
+  or
+  depend on ostiAllocMemory()
+*/
+typedef struct dmSMPRequestBody_s {
+  dmList_t                     Link;
+  dmSMPCompleted_t             SMPCompletionFunc;/* must be the second */
+
+#ifdef TBD    
+  tiDeviceHandle_t               *tiDevHandle;    /* not used for TD generated SMP */
+#endif  
+  agsaIORequest_t                agIORequest;
+  agsaSASRequestBody_t           agSASRequestBody;
+  agsaSATAInitiatorRequest_t     agSATARequestBody; 
+  /**< SMP response */
+  //agsaSMPFrame_t                 SMPRsp;
+  dmDeviceData_t                 *dmDevice;
+  
+#ifdef TBD
+  void                           *osMemHandle;
+  // can this be simply dmExpander_t
+  dmDeviceData_t                 *dmDevice;
+  tiIORequest_t                  *CurrentTaskTag; /* SMP is used for simulate target reset */
+#endif
+  dmRoot_t                       *dmRoot;
+//  dmExpander_t                   *dmExpander;
+  dmIntPortContext_t             *dmPortContext; /* portcontext where SMP is sent from */
+  bit8                           smpPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /* for smp retries; 
+                                                                          only for direct SMP */
+  bit32                          retries; /* number of retries */
+  /* for indirect SMP req/rsp */
+  void                           *IndirectSMP;
+  bit32                          IndirectSMPUpper32;
+  bit32                          IndirectSMPLower32;
+  /* used only when SMP is INDIRECT SMP request. On SMP completion, 
+     this is used to free up INDIRECT SMP response 
+  */
+  void                           *IndirectSMPResponse; /* dmSMPRequestBody_t */   
+
+
+
+#ifdef TBD  
+  void                           *IndirectSMPReqosMemHandle;
+  void                           *IndirectSMPReq;
+  bit32                          IndirectSMPReqLen;
+  bit32                          IndirectSMPReqUpper32;
+  bit32                          IndirectSMPReqLower32;  
+  void                           *IndirectSMPResposMemHandle;
+  void                           *IndirectSMPResp;
+  bit32                          IndirectSMPRespLen;
+  bit32                          IndirectSMPRespUpper32;
+  bit32                          IndirectSMPRespLower32;  
+#endif  
+  bit32                          id;
+  agsaContext_t                  agContext;
+}  dmSMPRequestBody_t;
+
+
+typedef struct dmIntContext_s {
+  /**< agsaRoot_t->osData points to this */
+  struct dmRootOsData_s      dmRootOsData;
+  
+  bit32               usecsPerTick;
+#ifdef TBD
+  dmRoot_t            dmRootInt;          /* for interrupt */
+  dmRoot_t            dmRootNonInt;       /* for non-interrupt */
+#endif
+
+  agsaRoot_t          *agRoot;
+  
+  /**< software-related initialization params used in saInitialize() */
+  dmSwConfig_t        SwConfig;  
+
+  /**< timers used commonly in SAS/SATA */
+  dmList_t                      timerlist;
+  /**< pointer to PortContext memory;  */
+  dmIntPortContext_t          *PortContextMem; 
+   
+  dmList_t                   FreePortContextList;
+  dmList_t                   MainPortContextList;
+  
+  /**< pointer to Device memory */
+  dmDeviceData_t             *DeviceMem;  
+  dmList_t                   FreeDeviceList;
+  dmList_t                   MainDeviceList;
+  
+  /**< pointer to Expander memory */
+  dmExpander_t               *ExpanderMem; 
+  dmList_t                   freeExpanderList;
+  dmList_t                   mainExpanderList;
+  
+  /**< pointer to SMP command memory */
+  dmSMPRequestBody_t         *SMPMem; 
+  dmList_t                   freeSMPList;
+  
+  /**< pointer to Indirect SMP request/repsonse memory */
+  bit8                       *IndirectSMPMem; 
+  bit32                      IndirectSMPUpper32;
+  bit32                      IndirectSMPLower32;
+  bit32                      itNexusTimeout;
+  bit32                      MaxRetryDiscovery;
+  bit32                      RateAdjust;
+    
+}  dmIntContext_t;
+
+typedef struct dmIntRoot_s
+{
+  /**<< common data structure for SAS/SATA */
+  dmIntContext_t          dmAllShared;
+} dmIntRoot_t;
+
+#endif                          /* __DMTYPES_H__ */
+

sys/dev/pms/RefTisa/sallsdk/api/sa_err.h

@@ -0,0 +1,244 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file sa_err.h
+ *  \brief The file defines the error code constants, defined by LL API
+ *
+ *
+ */
+/******************************************************************************/
+
+#ifndef  __SA_ERR_H__
+#define __SA_ERR_H__
+
+/************************************************************************************
+ *                                                                                  *
+ *               Error Code Constants defined for LL Layer starts                   *
+ *                                                                                  *
+ ************************************************************************************/
+
+/***********************************************************************************
+ *                    SSP/SMP/SATA IO Completion Status values
+ ***********************************************************************************/
+
+#define OSSA_IO_SUCCESS                                       0x00   /**< IO completes successfully */
+#define OSSA_IO_ABORTED                                       0x01   /**< IO aborted */
+#define OSSA_IO_OVERFLOW                                      0x02   /**< IO overflowed (SSP) */
+#define OSSA_IO_UNDERFLOW                                     0x03   /**< IO underflowed (SSP) */
+#define OSSA_IO_FAILED                                        0x04   /**< IO failed */
+#define OSSA_IO_ABORT_RESET                                   0x05   /**< IO abort because of reset */
+#define OSSA_IO_NOT_VALID                                     0x06   /**< IO not valid */
+#define OSSA_IO_NO_DEVICE                                     0x07   /**< IO is for non-existing device */
+#define OSSA_IO_ILLEGAL_PARAMETER                             0x08   /**< IO is not supported (SSP) */
+/* The following two error codes 0x09 and 0x0A are not using */
+#define OSSA_IO_LINK_FAILURE                                  0x09   /**< IO failed because of link failure (SMP) */
+#define OSSA_IO_PROG_ERROR                                    0x0A   /**< IO failed because of program error (SMP) */
+
+#define OSSA_IO_DIF_IN_ERROR                                  0x0B   /**< IO failed inbound DIF error (SSP) */
+#define OSSA_IO_DIF_OUT_ERROR                                 0x0C   /**< IO failed outbound DIF error (SSP) */
+#define OSSA_IO_ERROR_HW_TIMEOUT                              0x0D   /**< SMP request/response failed due to HW timeout  (SMP) */
+#define OSSA_IO_XFER_ERROR_BREAK                              0x0E   /**< IO aborted due to BREAK during connection */
+#define OSSA_IO_XFER_ERROR_PHY_NOT_READY                      0x0F   /**< IO aborted due to PHY NOT READY during connection*/
+#define OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED         0x10   /**< Open connection error */
+#define OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION                 0x11   /**< Open connection error */
+#define OSSA_IO_OPEN_CNX_ERROR_BREAK                          0x12   /**< Open connection error */
+#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS                  0x13   /**< Open connection error */
+#define OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION                0x14   /**< Open connection error */
+#define OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED  0x15   /**< Open connection error */
+#define OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY             0x16   /**< Open connection error */
+#define OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION              0x17   /**< Open connection error */
+/* This error code 0x18 is not used on SPCv */
+#define OSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR                  0x18   /**< Open connection error */
+#define OSSA_IO_XFER_ERROR_NAK_RECEIVED                       0x19   /**< IO aborted due to transfer error with data NAK received*/
+#define OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT                    0x1A   /**< IO aborted due to transfer error with data ACK/NAK timeout*/
+#define OSSA_IO_XFER_ERROR_PEER_ABORTED                       0x1B
+#define OSSA_IO_XFER_ERROR_RX_FRAME                           0x1C
+#define OSSA_IO_XFER_ERROR_DMA                                0x1D
+#define OSSA_IO_XFER_ERROR_CREDIT_TIMEOUT                     0x1E   /**< IO aborted due to CREDIT TIMEOUT during data transfer*/
+#define OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT                  0x1F
+#define OSSA_IO_XFER_ERROR_SATA                               0x20
+
+/* This error code 0x22 is not used on SPCv */
+#define OSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST                0x22
+#define OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE                  0x21
+#define OSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE                   0x23
+#define OSSA_IO_XFER_OPEN_RETRY_TIMEOUT                       0x24   /**< IO OPEN_RETRY_TIMEOUT */
+/* This error code 0x25 is not used on SPCv */
+#define OSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR                0x25
+#define OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE                   0x26
+#define OSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN                   0x27
+#define OSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED              0x28
+
+#define OSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT          0x30
+/* The following error code 0x31 and 0x32 are not using (obsolete) */
+#define OSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK     0x31
+#define OSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK  0x32
+
+#define OSSA_IO_XFER_ERROR_OFFSET_MISMATCH                    0x34
+#define OSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN                 0x35
+#define OSSA_IO_XFER_CMD_FRAME_ISSUED                         0x36
+#define OSSA_IO_ERROR_INTERNAL_SMP_RESOURCE                   0x37
+#define OSSA_IO_PORT_IN_RESET                                 0x38
+#define OSSA_IO_DS_NON_OPERATIONAL                            0x39
+#define OSSA_IO_DS_IN_RECOVERY                                0x3A
+#define OSSA_IO_TM_TAG_NOT_FOUND                              0x3B
+#define OSSA_IO_XFER_PIO_SETUP_ERROR                          0x3C
+#define OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR                     0x3D
+#define OSSA_IO_DS_IN_ERROR                                   0x3E
+#define OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY               0x3F
+#define OSSA_IO_ABORT_IN_PROGRESS                             0x40
+#define OSSA_IO_ABORT_DELAYED                                 0x41
+#define OSSA_IO_INVALID_LENGTH                                0x42
+#define OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT           0x43
+#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED     0x44
+#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO         0x45
+#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST          0x46
+#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE     0x47
+#define OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED  0x48
+#define OSSA_IO_DS_INVALID                                    0x49
+
+#define OSSA_IO_XFER_READ_COMPL_ERR                           0x0050
+/* WARNING: the value is not contiguous from here */
+#define OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR              0x0052
+#define OSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT               0x0053
+#define OSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR                  0x0054
+#define OSSA_MPI_IO_RQE_BUSY_FULL                             0x0055
+#define OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN                     0x0056   /* This status is only for Hitach FW */
+#define OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME               0x0057
+#define OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED                 0x0058
+
+#define OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE                  0x1004
+
+/*encrypt saSetOperator() response status */
+#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE                  0x1005
+#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR                       0x100B
+
+#ifdef SA_TESTBASE_EXTRA
+/* TestBase */
+#define OSSA_IO_HOST_BST_INVALID                              0x1005
+#endif /*  SA_TESTBASE_EXTRA */
+
+
+#define OSSA_MPI_ERR_OFFLOAD_RESOURCE_UNAVAILABLE             0x1012
+#define OSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED           0x1013
+#define OSSA_MPI_ERR_ATAPI_DEVICE_BUSY                        0x1024
+
+/* Specifies the status of the PHY_START command */
+#define OSSA_MPI_IO_SUCCESS                 0x00000000  /* PhyStart operation completed successfully */
+/* Specifies the status of the PHY_STOP command */
+#define OSSA_MPI_ERR_DEVICES_ATTACHED               0x00001046  /* All the devices in a port need to be deregistered if the PHY_STOP is for the last phy. */
+#define OSSA_MPI_ERR_INVALID_PHY_ID                 0x00001061  /* identifier specified in the PHY_START command is invalid i.e out of supported range for this product. */
+#define OSSA_MPI_ERR_PHY_ALREADY_STARTED            0x00001063  /* An attempt to start a phy which is already started.  */
+#define OSSA_MPI_ERR_PHY_NOT_STARTED                0x00001064  /* An attempt to stop a phy which is not started */
+#define OSSA_MPI_ERR_PHY_SUBOP_NOT_SUPPORTED        0x00001065  /* An attempt to use a sub operation that is not supported */
+
+#define OSSA_MPI_ERR_INVALID_ANALOG_TBL_IDX         0x00001067  /* The Analog Setup Table Index used in the PHY_START command in invalid. */
+#define OSSA_MPI_ERR_PHY_PROFILE_PAGE_NOT_SUPPORTED 0x00001068 /* Unsupported profile page code specified in the GET_PHY_PROFILE Command */
+#define OSSA_MPI_ERR_PHY_PROFILE_PAGE_NOT_FOUND     0x00001069 /* Unsupported profile page code specified in the GET_PHY_PROFILE Command */
+
+#define OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS                  0x2040
+/*
+   An encryption IO request failed due to DEK Key Tag mismatch.
+   The key tag supplied in the encryption IOMB does not match with the Key Tag in the referenced DEK Entry.
+*/
+#define OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH                0x2041
+#define OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID                 0x2042
+/*
+    An encryption I/O request failed
+    because the initial value (IV) in the unwrapped DEK blob didn't match the IV used to unwrap it.
+*/
+#define OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH                     0x2043
+/* An encryption I/O request failed due to an internal RAM ECC or interface error while unwrapping the DEK. */
+#define OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR             0x2044
+/* An encryption I/O request failed due to an internal RAM ECC or interface error while unwrapping the DEK. */
+#define OSSA_IO_XFR_ERROR_INTERNAL_RAM                        0x2045
+/*
+    An encryption I/O request failed
+    because the DEK index specified in the I/O was outside the bounds of thetotal number of entries in the host DEK table.
+*/
+#define OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS             0x2046
+#define OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE                   0x2047
+
+#define OSSA_MPI_ENC_ERR_UNSUPPORTED_OPTION                   0x2080
+#define OSSA_MPI_ENC_ERR_ID_TRANSFER_FAILURE                  0x2081
+
+#define OSSA_MPI_ENC_OPERATOR_AUTH_FAILURE                    0x2090
+#define OSSA_MPI_ENC_OPERATOR_OPERATOR_ALREADY_LOGGED_IN      0x2091
+#define OSSA_MPI_ENC_OPERATOR_ILLEGAL_PARAMETER               0x2092
+
+/* define DIF IO response error status code */
+#define OSSA_IO_XFR_ERROR_DIF_MISMATCH                        0x3000
+#define OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH        0x3001
+#define OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH          0x3002
+#define OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH                    0x3003
+#define OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR                 0x3004
+
+#define OSSA_MPI_ERR_DIF_IS_NOT_ENABLED                                   /* Indicates that saPCIeDiagExecute() is
+                                                                          *  called with DIF but DIF is not enabled.
+                                                                          */
+/* define operator management response status and error qualifier code */
+#define OPR_MGMT_OP_NOT_SUPPORTED                             0x2060
+#define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL                0x2061
+#define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND                 0x2062
+#define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH               0x2063
+#define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED             0x2064
+#define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL                  0x2022
+#define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE          0x2023
+
+/* When Status is 0x2061 */
+#define OPR_MGMT_ERR_QLFR_ILLEGAL_AUTHENTICATIONKEK_INDEX     0x1
+#define OPR_MGMT_ERR_QLFR_ILLEGAL_OPERATOR                    0x2
+#define OPR_MGMT_ERR_QLFR_ILLEGAL_KEK_FORMAT                  0x3
+#define OPR_MGMT_ERR_QLFR_WRONG_ROLE                          0x4
+
+/* When status is 0x2090 */
+/* invalid certificate: the certificate can not be unwrapped successfully by existing operators's KEKs */
+#define OPR_SET_ERR_QLFR_INVALID_CERT                         0x01
+/* role mismatch: the role from the certificate doesn't match the one inside the controller. */
+#define OPR_SET_ERR_QLFR_ROLE_MISMATCH                        0x02
+/* ID mismatch: the ID string from the certificate doesn't match the one inside the controller. */
+#define OPR_SET_ERR_QLFR_ID_MISMATCH                          0x03
+/* When status is 0x2092 */
+/* invalid OPRIDX */
+#define OPR_SET_ERR_QLFR_INVALID_OPRIDX                       0x04
+/* invalid access type */
+#define OPR_SET_ERR_QLFR_INVALID_ACCESS_TYPE                  0x05
+
+/* WARNING: This error code must always be the last number.
+ *          If you add error code, modify this code also
+ *          It is used as an index
+ */
+
+/* SAS Reconfiguration error */
+#define OSSA_CONTROLLER_NOT_IDLE                    0x1
+#define OSSA_INVALID_CONFIG_PARAM                   0x2
+
+
+/************************************************************************************
+ *                                                                                  *
+ *               Constants defined for OS Layer ends                                *
+ *                                                                                  *
+ ************************************************************************************/
+
+#endif  /*__SA_ERR_H__ */

sys/dev/pms/RefTisa/sallsdk/api/saapi.h

@@ -0,0 +1,728 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file saapi.h
+ *  \brief The file defines the declaration of tSDK APIs
+ *
+ *
+ *
+ *
+ */
+/******************************************************************************/
+
+#ifndef  __SSDKAPI_H__
+#define __SSDKAPI_H__
+
+/********************************************************************************
+ *                             SA LL Function Declaration                       *
+ ********************************************************************************/
+
+/***************************************************************************
+ * Definition of interrupt related functions start                         *
+ ***************************************************************************/
+
+
+GLOBAL bit32 FORCEINLINE saDelayedInterruptHandler(
+                              agsaRoot_t  *agRoot,
+                              bit32       interruptVectorIndex,
+                              bit32       count
+                              );
+
+GLOBAL bit32 FORCEINLINE saInterruptHandler(
+                              agsaRoot_t  *agRoot,
+                              bit32       interruptVectorIndex
+                              );
+
+GLOBAL void saSystemInterruptsActive(
+                              agsaRoot_t  *agRoot,
+                              agBOOLEAN     sysIntsActive
+                              );
+
+GLOBAL FORCEINLINE void saSystemInterruptsEnable(
+                              agsaRoot_t  *agRoot,
+                              bit32       interruptVectorIndex
+                              );
+/***************************************************************************
+ * Definition of interrupt related functions end                           *
+ ***************************************************************************/
+
+
+/***************************************************************************
+ * Definition of timer related functions start                             *
+ ***************************************************************************/
+GLOBAL void saTimerTick(agsaRoot_t  *agRoot);
+/***************************************************************************
+ * Definition of timer related functions end                               *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of initialization related functions start                    *
+ ***************************************************************************/
+GLOBAL void saGetRequirements(
+                              agsaRoot_t              *agRoot,
+                              agsaSwConfig_t          *swConfig,
+                              agsaMemoryRequirement_t *memoryRequirement,
+                              bit32                   *usecsPerTick,
+                              bit32                   *maxNumLocks
+                              );
+
+GLOBAL bit32 saInitialize(
+                          agsaRoot_t                  *agRoot,
+                          agsaMemoryRequirement_t     *memoryAllocated,
+                          agsaHwConfig_t              *hwConfig,
+                          agsaSwConfig_t              *swConfig,
+                          bit32                       usecsPerTick
+                          );
+/***************************************************************************
+ * Definition of initialization related functions end                      *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of hardware related functions start                          *
+ ***************************************************************************/
+GLOBAL void saHwReset(
+                      agsaRoot_t  *agRoot,
+                      bit32       resetType,
+                      bit32       resetParm
+                      );
+
+GLOBAL void saHwShutdown(agsaRoot_t *agRoot);
+
+/***************************************************************************
+ * Definition of hardware related functions end                            *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of phy related functions start                               *
+ ***************************************************************************/
+GLOBAL bit32 saPhyStart(
+                        agsaRoot_t          *agRoot,
+                        agsaContext_t       *agContext,
+                        bit32               queueNum,
+                        bit32               phyId,
+                        agsaPhyConfig_t     *agPhyConfig,
+                        agsaSASIdentify_t   *agSASIdentify
+                        );
+
+GLOBAL bit32 saPhyStop(
+                      agsaRoot_t            *agRoot,
+                      agsaContext_t         *agContext,
+                      bit32                 queueNum,
+                      bit32                 phyId
+                      );
+
+
+GLOBAL bit32 saLocalPhyControl(
+                      agsaRoot_t             *agRoot,
+                      agsaContext_t          *agContext,
+                      bit32                   queueNum,
+                      bit32                   phyId,
+                      bit32                   phyOperation,
+                      ossaLocalPhyControlCB_t agCB
+                      );
+
+GLOBAL bit32 saGetPhyProfile(
+                      agsaRoot_t               *agRoot,
+                      agsaContext_t            *agContext,
+                      bit32                    queueNum,
+                      bit32                    ppc,
+                      bit32                    phyID
+                      );
+
+GLOBAL bit32 saSetPhyProfile (
+                      agsaRoot_t               *agRoot,
+                      agsaContext_t            *agContext,
+                      bit32                    queueNum,
+                      bit32                    ppc,
+                      bit32                    length,
+                      void                     *buffer,
+                      bit32                    phyID
+                      );
+
+GLOBAL bit32 saHwEventAck(
+                      agsaRoot_t        *agRoot,
+                      agsaContext_t     *agContext,
+                      bit32              queueNum,
+                      agsaEventSource_t *eventSource,
+                      bit32              param0,
+                      bit32              param1
+                      );
+
+
+/***************************************************************************
+ * Definition of phy related functions end                                 *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of discovery related functions start                         *
+ ***************************************************************************/
+GLOBAL bit32 saDiscover(
+                        agsaRoot_t          *agRoot,
+                        agsaPortContext_t   *agPortContext,
+                        bit32               type,
+                        bit32               option
+                        );
+/***************************************************************************
+ * Definition of discovery related functions end                           *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of frame related functions start                             *
+ ***************************************************************************/
+GLOBAL bit32 saFrameReadBit32(
+                        agsaRoot_t          *agRoot,
+                        agsaFrameHandle_t   agFrame,
+                        bit32               frameOffset
+                        );
+
+GLOBAL void saFrameReadBlock(
+                        agsaRoot_t          *agRoot,
+                        agsaFrameHandle_t   agFrame,
+                        bit32               frameOffset,
+                        void                *frameBuffer,
+                        bit32               frameBufLen
+                        );
+/***************************************************************************
+ * Definition of frame related functions end                               *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of SATA related functions start                              *
+ ***************************************************************************/
+GLOBAL bit32 saSATAStart(
+                        agsaRoot_t                  *agRoot,
+                        agsaIORequest_t             *agIORequest,
+                        bit32                       queueNum,
+                        agsaDevHandle_t             *agDevHandle,
+                        bit32                       agRequestType,
+                        agsaSATAInitiatorRequest_t  *agSATAReq,
+                        bit8                        agTag,
+                        ossaSATACompletedCB_t       agCB
+                        );
+
+GLOBAL bit32 saSATAAbort(
+                        agsaRoot_t                  *agRoot,
+                        agsaIORequest_t             *agIORequest,
+                        bit32                       queueNum,
+                        agsaDevHandle_t             *agDevHandle,
+                        bit32                       flag,
+                        void                        *abortParam,
+                        ossaGenericAbortCB_t        agCB
+                        );
+
+/***************************************************************************
+ * Definition of SATA related functions end                                *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of SAS related functions start                               *
+ ***************************************************************************/
+
+GLOBAL bit32 saSendSMPIoctl(
+						agsaRoot_t                *agRoot,
+						agsaDevHandle_t           *agDevHandle,
+						bit32                      queueNum,
+						agsaSMPFrame_t            *pSMPFrame,  
+						ossaSMPCompletedCB_t       agCB
+						);
+
+GLOBAL bit32 saSMPStart(
+                        agsaRoot_t                *agRoot,
+                        agsaIORequest_t           *agIORequest,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle,
+                        bit32                     agRequestType,
+                        agsaSASRequestBody_t      *agRequestBody,
+                        ossaSMPCompletedCB_t      agCB
+                        );
+
+GLOBAL bit32 saSMPAbort(
+                        agsaRoot_t                *agRoot,
+                        agsaIORequest_t           *agIORequest,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle,
+                        bit32                     flag,
+                        void                      *abortParam,
+                        ossaGenericAbortCB_t      agCB
+                        );
+
+GLOBAL bit32 saSSPStart(
+                        agsaRoot_t                *agRoot,
+                        agsaIORequest_t           *agIORequest,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle,
+                        bit32                     agRequestType,
+                        agsaSASRequestBody_t      *agRequestBody,
+                        agsaIORequest_t           *agTMRequest,
+                        ossaSSPCompletedCB_t      agCB
+                        );
+
+#ifdef FAST_IO_TEST
+GLOBAL void *saFastSSPPrepare(
+                        void                 *ioHandle,
+                        agsaFastCommand_t    *fc,
+                        ossaSSPCompletedCB_t cb,
+                        void                 *cbArg);
+
+GLOBAL bit32 saFastSSPSend(void    *ioHandle);
+GLOBAL bit32 saFastSSPCancel(void  *ioHandle);
+#endif
+
+GLOBAL bit32 saSSPAbort(
+                        agsaRoot_t                *agRoot,
+                        agsaIORequest_t           *agIORequest,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle,
+                        bit32                     flag,
+                        void                      *abortParam,
+                        ossaGenericAbortCB_t      agCB
+                        );
+
+GLOBAL void saGetDifErrorDetails(
+                        agsaRoot_t                *agRoot,
+                        agsaIORequest_t           *agIORequest,
+                        agsaDifDetails_t          *difDetails
+                        );
+
+GLOBAL bit32 saRegisterEventCallback(
+                        agsaRoot_t                *agRoot,
+                        bit32                     eventSourceType,
+                        ossaGenericCB_t           callbackPtr
+                        );
+
+/***************************************************************************
+ * Definition of SAS related functions end                                 *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of Device related functions start                            *
+ ***************************************************************************/
+GLOBAL bit32 saRegisterNewDevice(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaDeviceInfo_t          *agDeviceInfo,
+                        agsaPortContext_t         *agPortContext,
+                        bit16                     hostAssignedDeviceId
+                        );
+
+GLOBAL bit32 saDeregisterDeviceHandle(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        agsaDevHandle_t           *agDevHandle,
+                        bit32                     queueNum
+                        );
+
+GLOBAL bit32 saGetDeviceHandles(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaPortContext_t         *agPortContext,
+                        bit32                     flags,
+                        agsaDevHandle_t           *agDev[],
+                        bit32                     skipCount,
+                        bit32                     maxDevs
+                        );
+
+GLOBAL bit32 saGetDeviceInfo(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     option,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle
+                        );
+
+GLOBAL bit32 saGetDeviceState(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle
+                        );
+
+GLOBAL bit32 saSetDeviceInfo(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum ,
+                        agsaDevHandle_t           *agDevHandle,
+                        bit32                     option,
+                        bit32                     param,
+                        ossaSetDeviceInfoCB_t   agCB
+                        );
+
+GLOBAL bit32 saSetDeviceState(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle,
+                        bit32                     newDeviceState
+                        );
+
+/***************************************************************************
+ * Definition of Device related functions end                              *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of Misc related functions start                              *
+ ***************************************************************************/
+GLOBAL bit32 saFwFlashUpdate(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaUpdateFwFlash_t       *flashUpdateInfo
+                        );
+
+GLOBAL bit32 saFlashExtExecute (
+                        agsaRoot_t            *agRoot,
+                        agsaContext_t         *agContext,
+                        bit32                 queueNum,
+                        agsaFlashExtExecute_t *agFlashExtExe
+                        );
+
+#ifdef SPC_ENABLE_PROFILE
+GLOBAL bit32 saFwProfile(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaFwProfile_t           *fwProfileInfo
+                        );
+#endif
+
+GLOBAL bit32 saEchoCommand(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        void                      *echoPayload
+                        );
+
+GLOBAL bit32 saGetControllerInfo(
+                        agsaRoot_t                *agRoot,
+                        agsaControllerInfo_t      *controllerInfo
+                        );
+
+GLOBAL bit32 saGetControllerStatus(
+                          agsaRoot_t              *agRoot,
+                          agsaControllerStatus_t  *controllerStatus
+                        );
+
+GLOBAL bit32 saGetControllerEventLogInfo(
+                        agsaRoot_t                 *agRoot,
+                          agsaControllerEventLog_t *eventLogInfo
+                        );
+
+GLOBAL bit32 saGpioEventSetup(
+                        agsaRoot_t                 *agRoot,
+                        agsaContext_t              *agContext,
+                        bit32                      queueNum,
+                        agsaGpioEventSetupInfo_t   *gpioEventSetupInfo
+                        );
+
+GLOBAL bit32 saGpioPinSetup(
+                        agsaRoot_t                 *agRoot,
+                        agsaContext_t              *agContext,
+                        bit32                      queueNum,
+                        agsaGpioPinSetupInfo_t     *gpioPinSetupInfo
+                        );
+
+GLOBAL bit32 saGpioRead(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum
+                        );
+
+GLOBAL bit32 saGpioWrite(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        bit32                     gpioWriteMask,
+                        bit32                     gpioWriteValue
+                        );
+
+GLOBAL bit32 saSASDiagExecute(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaSASDiagExecute_t      *diag
+                        );
+
+GLOBAL bit32 saSASDiagStartEnd(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        bit32                     phyId,
+                        bit32                     operation
+                        );
+
+GLOBAL bit32 saGetTimeStamp(
+                        agsaRoot_t    *agRoot,
+                        agsaContext_t *agContext,
+                        bit32         queueNum
+                        );
+
+GLOBAL bit32 saPortControl(
+                        agsaRoot_t        *agRoot,
+                        agsaContext_t     *agContext,
+                        bit32             queueNum,
+                        agsaPortContext_t *agPortContext,
+                        bit32             portOperation,
+                        bit32             param0,
+                        bit32             param1
+                        );
+
+GLOBAL bit32 saGetRegisterDump(
+                        agsaRoot_t        *agRoot,
+                        agsaContext_t     *agContext,
+                        bit32             queueNum,
+                        agsaRegDumpInfo_t *regDumpInfo
+                        );
+
+GLOBAL bit32 saGetForensicData(
+                        agsaRoot_t          *agRoot,
+                        agsaContext_t       *agContext,
+                        agsaForensicData_t  *forensicData
+                        );
+
+bit32 saGetIOErrorStats(
+                         agsaRoot_t        *agRoot,
+                         agsaContext_t     *agContext,
+                         bit32              flag
+                         );
+
+bit32 saGetIOEventStats(
+                         agsaRoot_t        *agRoot,
+                         agsaContext_t     *agContext,
+                         bit32              flag
+                         );
+
+GLOBAL bit32 saGetNVMDCommand(
+                        agsaRoot_t        *agRoot,
+                        agsaContext_t     *agContext,
+                        bit32             queueNum,
+                        agsaNVMDData_t    *NVMDInfo
+                        );
+
+GLOBAL bit32 saSetNVMDCommand(
+                        agsaRoot_t        *agRoot,
+                        agsaContext_t     *agContext,
+                        bit32             queueNum,
+                        agsaNVMDData_t    *NVMDInfo
+                        );
+
+GLOBAL bit32 saReconfigSASParams(
+                        agsaRoot_t        *agRoot,
+                        agsaContext_t     *agContext,
+                        bit32             queueNum ,
+                        agsaSASReconfig_t *agSASConfig
+                        );
+
+GLOBAL bit32 saSgpio(
+                agsaRoot_t              *agRoot,
+                agsaContext_t           *agContext,
+                bit32                   queueNum,
+                agsaSGpioReqResponse_t  *pSGpioReq
+                );
+
+GLOBAL bit32 saPCIeDiagExecute(
+                        agsaRoot_t             *agRoot,
+                        agsaContext_t          *agContext,
+                        bit32                   queueNum,
+                        agsaPCIeDiagExecute_t  *diag);
+
+
+GLOBAL bit32 saEncryptSelftestExecute(
+                        agsaRoot_t    *agRoot,
+                        agsaContext_t *agContext,
+                        bit32          queueNum,
+                        bit32          type,
+                        bit32          length,
+                        void          *TestDescriptor);
+
+GLOBAL bit32 saSetOperator(
+                  agsaRoot_t     *agRoot,
+                  agsaContext_t  *agContext,
+                  bit32           queueNum,
+                  bit32           flag,
+                  void           *cert);
+
+GLOBAL bit32 saGetOperator(
+                  agsaRoot_t     *agRoot,
+                  agsaContext_t  *agContext,
+                  bit32           queueNum,
+                  bit32           option,
+                  bit32           AddrHi,
+                  bit32           AddrLo);
+
+GLOBAL bit32 saOperatorManagement(
+                        agsaRoot_t           *agRoot,
+                        agsaContext_t        *agContext,
+                        bit32                 queueNum,
+                        bit32                 flag,
+                        bit8                  role,
+                        agsaID_t              *id,
+                        agsaEncryptKekBlob_t  *kblob);
+
+
+/***************************************************************************
+ * Definition of Misc. related functions end                               *
+ ***************************************************************************/
+
+GLOBAL bit32 saSetControllerConfig(
+                      agsaRoot_t        *agRoot,
+                      bit32             queueNum,
+                      bit32             modePage,
+                      bit32             length,
+                      void              *buffer,
+                      agsaContext_t     *agContext
+                      );
+
+
+GLOBAL bit32 saGetControllerConfig(
+                      agsaRoot_t        *agRoot,
+                      bit32             queueNum,
+                      bit32             modePage,
+                      bit32             flag0,
+                      bit32             flag1,
+                      agsaContext_t     *agContext
+                      );
+
+GLOBAL bit32 saEncryptDekCacheUpdate(
+                     agsaRoot_t        *agRoot,
+                     agsaContext_t     *agContext,
+                     bit32             queueNum,
+                     bit32             kekIndex,
+                     bit32             dekTableSelect,
+                     bit32             dekAddrHi,
+                     bit32             dekAddrLo,
+                     bit32             dekIndex,
+                     bit32             dekNumberOfEntries,
+                     bit32             dekBlobFormat,
+                     bit32             dekTableKeyEntrySize
+                     );
+
+GLOBAL bit32 saEncryptDekCacheInvalidate(
+                    agsaRoot_t         *agRoot,
+                    agsaContext_t      *agContext,
+                    bit32              queueNum,
+                    bit32              dekTable,
+                    bit32              dekIndex
+                    );
+
+GLOBAL bit32 saEncryptGetMode(
+                    agsaRoot_t         *agRoot,
+                    agsaContext_t      *agContext,
+                    agsaEncryptInfo_t  *encryptInfo
+                    );
+
+GLOBAL bit32 saEncryptSetMode (
+                      agsaRoot_t        *agRoot,
+                      agsaContext_t     *agContext,
+                      bit32             queueNum,
+                      agsaEncryptInfo_t *mode
+                      );
+
+GLOBAL bit32 saEncryptKekInvalidate(
+                    agsaRoot_t         *agRoot,
+                     agsaContext_t     *agContext,
+                    bit32              queueNum,
+                    bit32              kekIndex
+                    );
+
+GLOBAL bit32 saEncryptKekUpdate(
+                    agsaRoot_t         *agRoot,
+                    agsaContext_t     *agContext,
+                    bit32              queueNum,
+                    bit32              flags,
+                    bit32              newKekIndex,
+                    bit32              wrapperKekIndex,
+                    bit32              blobFormat,
+                    agsaEncryptKekBlob_t *encryptKekBlob
+                    );
+
+#ifdef HIALEAH_ENCRYPTION
+GLOBAL bit32 saEncryptHilUpdate(
+                    agsaRoot_t         *agRoot,
+                    agsaContext_t      *agContext,
+                    bit32              queueNum
+                    );
+#endif /* HIALEAH_ENCRYPTION */
+
+GLOBAL bit32 saGetDFEData(
+                          agsaRoot_t    *agRoot,
+                          agsaContext_t   *agContext,
+                          bit32     queueNum,
+                          bit32                 interface,
+                          bit32                 laneNumber,
+                          bit32                 interations,
+                          agsaSgl_t             *agSgl);
+
+
+GLOBAL bit32 saFatalInterruptHandler(
+                          agsaRoot_t  *agRoot,
+                          bit32       interruptVectorIndex
+  );
+
+
+GLOBAL bit32 saDIFEncryptionOffloadStart(
+                          agsaRoot_t         *agRoot,
+                          agsaContext_t      *agContext,
+                          bit32               queueNum,
+                          bit32               op,
+                          agsaDifEncPayload_t *agsaDifEncPayload,
+                          ossaDIFEncryptionOffloadStartCB_t agCB);
+
+
+GLOBAL bit32 saVhistCapture(
+                          agsaRoot_t    *agRoot,
+                          agsaContext_t *agContext,
+                          bit32         queueNum,
+                          bit32         Channel,
+                          bit32         NumBitLo,
+                          bit32         NumBitHi,
+                          bit32         PcieAddrLo,
+                          bit32         PcieAddrHi,
+                          bit32         ByteCount );
+
+
+GLOBAL void saCountActiveIORequests(  agsaRoot_t              *agRoot);
+
+#ifdef SA_64BIT_TIMESTAMP
+osGLOBAL bit64  osTimeStamp64(void);
+#endif /* SA_64BIT_TIMESTAMP */
+
+#ifdef SALL_API_TEST
+/***************************************************************************
+ * Definition of LL Test related API functions start                       *
+ ***************************************************************************/
+GLOBAL bit32 saGetLLCounters(
+                      agsaRoot_t          *agRoot,
+                      bit32               counters,
+                      agsaLLCountInfo_t   *LLCountInfo
+                      );
+
+GLOBAL bit32 saResetLLCounters(
+                      agsaRoot_t     *agRoot,
+                      bit32          counters
+                      );
+#endif
+
+#endif  /*__SSDKAPI_H__ */

sys/dev/pms/RefTisa/sallsdk/api/saosapi.h

@@ -0,0 +1,843 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file saosapi.h
+ *  \brief The file defines the declaration of OS APIs
+ *
+ */
+/*******************************************************************************/
+
+#ifndef  __SSDKOSAPI_H__
+#define __SSDKOSAPI_H__
+
+#ifdef LINUX
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
+
+#ifdef FORCEINLINE
+#undef FORCEINLINE
+#define FORCEINLINE
+#endif
+      
+#endif
+#endif
+
+/***************************************************************************
+ * Definition of register access related functions start                   *
+ ***************************************************************************/
+#ifndef ossaHwRegRead
+GLOBAL FORCEINLINE
+bit32 ossaHwRegRead(
+                          agsaRoot_t  *agRoot,
+                          bit32       regOffset
+                          );
+#endif
+
+#ifndef ossaHwRegWrite
+GLOBAL FORCEINLINE
+void ossaHwRegWrite(
+                          agsaRoot_t  *agRoot,
+                          bit32       regOffset,
+                          bit32       regValue
+                          );
+#endif
+
+#ifndef ossaHwRegReadExt
+GLOBAL FORCEINLINE
+bit32 ossaHwRegReadExt(
+                             agsaRoot_t  *agRoot,
+                             bit32       busBaseNumber,
+                             bit32       regOffset
+                             );
+#endif
+
+#ifndef ossaHwRegWriteExt
+GLOBAL FORCEINLINE
+void ossaHwRegWriteExt(
+                             agsaRoot_t  *agRoot,
+                             bit32       busBaseNumber,
+                             bit32       regOffset,
+                             bit32       regValue
+                             );
+#endif
+
+#ifndef ossaHwRegReadConfig32
+osGLOBAL bit32 ossaHwRegReadConfig32(
+              agsaRoot_t  *agRoot,
+              bit32       regOffset
+              );
+#endif
+
+
+/***************************************************************************
+ * Definition of register access related functions end                     *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of thread related functions start                            *
+ ***************************************************************************/
+#ifndef ossaSingleThreadedEnter
+GLOBAL FORCEINLINE void ossaSingleThreadedEnter(
+                                    agsaRoot_t  *agRoot,
+                                    bit32       syncLockId
+                                   );
+#endif
+
+#ifndef ossaSingleThreadedLeave
+GLOBAL FORCEINLINE void ossaSingleThreadedLeave(
+                                    agsaRoot_t  *agRoot,
+                                    bit32       syncLockId
+                                   );
+#endif
+
+#ifndef ossaStallThread
+GLOBAL void ossaStallThread(
+                            agsaRoot_t  *agRoot,
+                            bit32       microseconds
+                            );
+#endif
+/***************************************************************************
+ * Definition of thread related functions end                              *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of interrupt related functions start                         *
+ ***************************************************************************/
+#ifndef ossaDisableInterrupts
+#define ossaDisableInterrupts(agRoot, interruptVectorIndex) \
+do                                                          \
+{                                                           \
+  agsaLLRoot_t  *saROOT = (agsaLLRoot_t *)(agRoot->sdkData);\
+  saROOT->DisableInterrupts(agRoot, interruptVectorIndex); \
+} while(0)
+#endif
+
+#ifndef ossaReenableInterrupts
+#define ossaReenableInterrupts(agRoot, interruptVectorIndex) \
+do                                                           \
+{                                                            \
+  agsaLLRoot_t  *saROOT = (agsaLLRoot_t *)(agRoot->sdkData); \
+  saROOT->ReEnableInterrupts(agRoot, interruptVectorIndex); \
+} while(0)
+#endif
+
+/***************************************************************************
+ * Definition of interrupt related functions end                           *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of cache related functions start                             *
+ ***************************************************************************/
+#ifndef ossaCacheInvalidate
+GLOBAL FORCEINLINE void ossaCacheInvalidate(
+                                agsaRoot_t  *agRoot,
+                                void        *osMemHandle,
+                                void        *virtPtr,
+                                bit32       length
+                                );
+#endif
+
+#ifndef ossaCacheFlush
+GLOBAL FORCEINLINE void ossaCacheFlush(
+                          agsaRoot_t  *agRoot,
+                          void        *osMemHandle,
+                          void        *virtPtr,
+                          bit32       length
+                          );
+#endif
+
+#ifndef ossaCachePreFlush
+GLOBAL FORCEINLINE void ossaCachePreFlush(
+                              agsaRoot_t  *agRoot,
+                              void        *osMemHandle,
+                              void        *virtPtr,
+                              bit32       length
+                              );
+#endif
+
+/***************************************************************************
+ * Definition of cache related functions end                               *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of hardware related functions start                          *
+ ***************************************************************************/
+#ifndef ossaHwCB
+GLOBAL void ossaHwCB(
+                    agsaRoot_t        *agRoot,
+                    agsaPortContext_t *agPortContext,
+                    bit32             event,
+                    bit32             eventParm1,
+                    void              *eventParm2,
+                    void              *eventParm3
+                    );
+#endif
+
+#ifndef ossaHwEventAckCB
+GLOBAL void ossaHwEventAckCB(
+                            agsaRoot_t    *agRoot,
+                            agsaContext_t *agContext,
+                            bit32         status
+                            );
+#endif
+/***************************************************************************
+ * Definition of hardware related functions end                            *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of SATA related functions start                              *
+ ***************************************************************************/
+#ifndef ossaSATACompleted
+GLOBAL void ossaSATACompleted(
+                              agsaRoot_t        *agRoot,
+                              agsaIORequest_t   *agIORequest,
+                              bit32             agIOStatus,
+                              void              *agFirstDword,
+                              bit32             agIOInfoLen,
+                              void              *agParam
+                              );
+
+#endif
+
+#ifndef ossaSATAEvent
+GLOBAL void ossaSATAEvent(
+                        agsaRoot_t              *agRoot,
+                        agsaIORequest_t         *agIORequest,
+                        agsaPortContext_t       *agPortContext,
+                        agsaDevHandle_t         *agDevHandle,
+                        bit32                   event,
+                        bit32                   agIOInfoLen,
+                        void                    *agParam
+                        );
+#endif
+
+#ifndef ossaSATAAbortCB
+ GLOBAL void  ossaSATAAbortCB(
+                        agsaRoot_t               *agRoot,
+                        agsaIORequest_t          *agIORequest,
+                        bit32                    flag,
+                        bit32                    status
+                        );
+#endif
+
+/***************************************************************************
+ * Definition of SATA related functions end                                *
+ ***************************************************************************/
+
+
+/***************************************************************************
+ * Definition of SAS related functions start                               *
+ ***************************************************************************/
+#ifndef ossaSSPEvent
+GLOBAL void ossaSSPEvent(
+                  agsaRoot_t        *agRoot,
+                  agsaIORequest_t   *agIORequest,
+                  agsaPortContext_t *agPortContext,
+                  agsaDevHandle_t   *agDevHandle,
+                  bit32             event,
+                  bit16             sspTag,
+                  bit32             agIOInfoLen,
+                  void              *agParam
+                  );
+#endif
+
+osGLOBAL void 
+ossaSMPIoctlCompleted( 
+				 agsaRoot_t            *agRoot,
+                 agsaIORequest_t       *agIORequest,
+                 bit32                 agIOStatus,
+                 bit32                 agIOInfoLen,
+                 agsaFrameHandle_t     agFrameHandle
+                 );
+
+#ifndef ossaSMPCompleted
+GLOBAL void ossaSMPCompleted(
+                            agsaRoot_t            *agRoot,
+                            agsaIORequest_t       *agIORequest,
+                            bit32                 agIOStatus,
+                            bit32                 agIOInfoLen,
+                            agsaFrameHandle_t     agFrameHandle
+                            );
+#endif
+
+#ifndef ossaSMPReqReceived
+GLOBAL void ossaSMPReqReceived(
+                              agsaRoot_t            *agRoot,
+                              agsaDevHandle_t       *agDevHandle,
+                              agsaFrameHandle_t     agFrameHandle,
+                              bit32                 agFrameLength,
+                              bit32                 phyId
+                              );
+#endif
+
+#ifndef ossaSSPCompleted
+GLOBAL FORCEINLINE void ossaSSPCompleted(
+                            agsaRoot_t          *agRoot,
+                            agsaIORequest_t     *agIORequest,
+                            bit32               agIOStatus,
+                            bit32               agIOInfoLen,
+                            void                *agParam,
+                            bit16               sspTag,
+                            bit32               agOtherInfo
+                            );
+#endif
+
+#ifdef FAST_IO_TEST
+GLOBAL void ossaFastSSPCompleted(
+                            agsaRoot_t          *agRoot,
+                            agsaIORequest_t     *cbArg,
+                            bit32               agIOStatus,
+                            bit32               agIOInfoLen,
+                            void                *agParam,
+                            bit16               sspTag,
+                            bit32               agOtherInfo
+                            );
+#endif
+
+#ifndef ossaSSPReqReceived
+GLOBAL void ossaSSPReqReceived(
+                              agsaRoot_t        *agRoot,
+                              agsaDevHandle_t   *agDevHandle,
+                              agsaFrameHandle_t agFrameHandle,
+                              bit16             agInitiatorTag,
+                              bit32             parameter,
+                              bit32             agFrameLen
+                              );
+#endif
+
+osGLOBAL void
+ossaSSPIoctlCompleted(
+                agsaRoot_t                        *agRoot,
+                agsaIORequest_t           *agIORequest,
+                bit32                             agIOStatus,
+                bit32                             agIOInfoLen,
+                void                              *agParam,
+                bit16                             sspTag,
+                bit32                             agOtherInfo
+                );
+
+
+#ifndef ossaSSPAbortCB
+GLOBAL void ossaSSPAbortCB(
+                        agsaRoot_t              *agRoot,
+                        agsaIORequest_t         *agIORequest,
+                        bit32                   flag,
+                        bit32                   status
+                        );
+#endif
+
+#ifndef ossaSMPAbortCB
+GLOBAL void ossaSMPAbortCB(
+                        agsaRoot_t              *agRoot,
+                        agsaIORequest_t         *agIORequest,
+                        bit32                   flag,
+                        bit32                   status
+                        );
+#endif
+
+#ifndef ossaReconfigSASParamsCB
+GLOBAL void ossaReconfigSASParamsCB(
+                        agsaRoot_t        *agRoot,
+                        agsaContext_t     *agContext,
+                        bit32             status,
+                        agsaSASReconfig_t *agSASConfig
+);
+#endif
+
+/***************************************************************************
+ * Definition of SAS related functions end                                 *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of Discovery related functions start                         *
+ ***************************************************************************/
+#ifndef ossaDiscoverSataCB
+GLOBAL void ossaDiscoverSataCB(
+                              agsaRoot_t          *agRoot,
+                              agsaPortContext_t   *agPortContext,
+                              bit32               event,
+                              void                *pParm1,
+                              void                *pParm2
+                              );
+#endif
+
+#ifndef ossaDiscoverSasCB
+GLOBAL void ossaDiscoverSasCB(
+                              agsaRoot_t          *agRoot,
+                              agsaPortContext_t   *agPortContext,
+                              bit32               event,
+                              void                *pParm1,
+                              void                *pParm2
+                              );
+#endif
+
+#ifndef ossaDeviceHandleAccept
+GLOBAL bit32 ossaDeviceHandleAccept(
+                                    agsaRoot_t          *agRoot,
+                                    agsaDevHandle_t     *agDevHandle,
+                                    agsaSASDeviceInfo_t *agDeviceInfo,
+                                    agsaPortContext_t   *agPortContext,
+                                    bit32               *hostAssignedDeviceId
+                                    );
+#endif
+
+#ifndef ossaGetDeviceHandlesCB
+GLOBAL void ossaGetDeviceHandlesCB(
+                                agsaRoot_t        *agRoot,
+                                agsaContext_t     *agContext,
+                                agsaPortContext_t *agPortContext,
+                                agsaDevHandle_t   *agDev[],
+                                bit32             validDevs
+                                );
+#endif
+
+#ifndef ossaGetDeviceInfoCB
+GLOBAL void ossaGetDeviceInfoCB(
+                                agsaRoot_t        *agRoot,
+                                agsaContext_t     *agContext,
+                                agsaDevHandle_t   *agDevHandle,
+                                bit32             status,
+                                void              *agInfo
+                                );
+#endif
+
+#ifndef ossaDeviceHandleRemovedEvent
+GLOBAL void ossaDeviceHandleRemovedEvent (
+                                agsaRoot_t        *agRoot,
+                                agsaDevHandle_t   *agDevHandle,
+                                agsaPortContext_t *agPortContext
+                                );
+#endif
+
+#ifndef ossaGetDeviceStateCB
+GLOBAL void ossaGetDeviceStateCB(
+                                agsaRoot_t        *agRoot,
+                                agsaContext_t     *agContext,
+                                agsaDevHandle_t   *agDevHandle,
+                                bit32             status,
+                                bit32             deviceState
+                                );
+#endif
+
+#ifndef ossaSetDeviceInfoCB
+GLOBAL void ossaSetDeviceInfoCB(
+                                agsaRoot_t        *agRoot,
+                                agsaContext_t     *agContext,
+                                agsaDevHandle_t   *agDevHandle,
+                                bit32             status,
+                                bit32             option,
+                                bit32             param
+                                );
+#endif
+
+#ifndef ossaSetDeviceStateCB
+GLOBAL void ossaSetDeviceStateCB(
+                                agsaRoot_t        *agRoot,
+                                agsaContext_t     *agContext,
+                                agsaDevHandle_t   *agDevHandle,
+                                bit32             status,
+                                bit32             newDeviceState,
+                                bit32             previousDeviceState
+                                );
+#endif
+
+/***************************************************************************
+ * Definition of Discovery related functions end                           *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of Misc. related functions start                             *
+ ***************************************************************************/
+
+#ifndef ossaTimeStamp
+GLOBAL bit32 ossaTimeStamp(agsaRoot_t     *agRoot); 
+#endif /* ossaTimeStamp */
+
+#ifndef ossaTimeStamp64
+GLOBAL bit64 ossaTimeStamp64(agsaRoot_t     *agRoot); 
+#endif /* ossaTimeStamp64 */
+
+
+#ifndef ossaLocalPhyControlCB
+GLOBAL void ossaLocalPhyControlCB(
+                      agsaRoot_t     *agRoot,
+                      agsaContext_t  *agContext,
+                      bit32          phyId,
+                      bit32          phyOperation,
+                      bit32          status,
+                      void           *parm);
+#endif
+
+#ifndef ossaGetPhyProfileCB
+GLOBAL void   ossaGetPhyProfileCB(
+                      agsaRoot_t    *agRoot,
+                      agsaContext_t *agContext,
+                      bit32         status,
+                      bit32         ppc,
+                      bit32         phyID,
+                      void          *parm );
+#endif
+
+#ifndef ossaSetPhyProfileCB
+GLOBAL void ossaSetPhyProfileCB(
+                     agsaRoot_t    *agRoot,
+                     agsaContext_t *agContext,
+                     bit32         status,
+                     bit32         ppc,
+                     bit32         phyID,
+                     void          *parm );
+#endif
+
+#ifndef ossaFwFlashUpdateCB
+GLOBAL void ossaFwFlashUpdateCB(
+                      agsaRoot_t    *agRoot,
+                      agsaContext_t *agContext,
+                      bit32         status);
+#endif
+
+#ifndef ossaFlashExtExecuteCB
+GLOBAL void   ossaFlashExtExecuteCB(
+                      agsaRoot_t               *agRoot,
+                      agsaContext_t            *agContext,
+                      bit32                    status,
+                      bit32                    command,
+                      agsaFlashExtResponse_t  *agFlashExtRsp);
+
+#endif
+
+#ifdef SPC_ENABLE_PROFILE
+GLOBAL void ossaFwProfileCB(
+                      agsaRoot_t    *agRoot,
+                      agsaContext_t *agContext,
+                      bit32         status,
+                      bit32         len
+                      );
+
+#endif
+#ifndef ossaEchoCB
+GLOBAL void ossaEchoCB(
+                      agsaRoot_t    *agRoot,
+                      agsaContext_t *agContext,
+                      void          *echoPayload);
+#endif
+
+#ifndef ossaGpioResponseCB
+GLOBAL void ossaGpioResponseCB(
+                      agsaRoot_t               *agRoot,
+                      agsaContext_t            *agContext,
+                      bit32                    status,
+                      bit32                    gpioReadValue,
+                      agsaGpioPinSetupInfo_t   *gpioPinSetupInfo,
+                      agsaGpioEventSetupInfo_t *gpioEventSetupInfo);
+#endif
+
+#ifndef ossaGpioEvent
+GLOBAL void ossaGpioEvent(
+                      agsaRoot_t    *agRoot,
+                      bit32         gpioEvent);
+#endif
+
+#ifndef ossaSASDiagExecuteCB
+GLOBAL void ossaSASDiagExecuteCB(
+                      agsaRoot_t      *agRoot,
+                      agsaContext_t   *agContext,
+                      bit32           status,
+                      bit32           command,
+                      bit32           reportData);
+#endif
+
+#ifndef ossaSASDiagStartEndCB
+GLOBAL void ossaSASDiagStartEndCB(
+                      agsaRoot_t      *agRoot,
+                      agsaContext_t   *agContext,
+                      bit32           status);
+#endif
+
+#ifndef ossaGetTimeStampCB
+GLOBAL void ossaGetTimeStampCB(
+                      agsaRoot_t      *agRoot,
+                      agsaContext_t   *agContext,
+                      bit32           timeStampLower,
+                      bit32           timeStampUpper);
+#endif
+
+#ifndef ossaPortControlCB
+GLOBAL void ossaPortControlCB(
+                      agsaRoot_t        *agRoot,
+                      agsaContext_t     *agContext,
+                      agsaPortContext_t *agPortContext,
+                      bit32             portOperation,
+                      bit32             status);
+#endif
+
+#ifndef ossaGeneralEvent
+GLOBAL void ossaGeneralEvent(
+                      agsaRoot_t        *agRoot,
+                      bit32             status,
+                      agsaContext_t     *agContext,
+                      bit32             *msg);
+#endif
+
+#ifndef ossaGetRegisterDumpCB
+void ossaGetRegisterDumpCB(
+                      agsaRoot_t        *agRoot,
+                      agsaContext_t     *agContext,
+                      bit32             status);
+#endif
+
+GLOBAL void ossaGetForensicDataCB (
+        agsaRoot_t          *agRoot,
+        agsaContext_t       *agContext,
+        bit32                status,
+        agsaForensicData_t  *forensicData
+        );
+
+
+#ifndef ossaGetNVMDResponseCB
+GLOBAL void ossaGetNVMDResponseCB(
+                      agsaRoot_t        *agRoot,
+                      agsaContext_t     *agContext,
+                      bit32             status,
+                      bit8              indirectPayload,
+                      bit32             agInfoLen,
+                      agsaFrameHandle_t agFrameHandle );
+#endif
+
+#ifndef ossaSetNVMDResponseCB
+GLOBAL void ossaSetNVMDResponseCB(
+                      agsaRoot_t        *agRoot,
+                      agsaContext_t     *agContext,
+                      bit32             status );
+#endif
+
+#ifndef ossaQueueProcessed
+#ifdef SALLSDK_TEST_SET_OB_QUEUE
+GLOBAL void ossaQueueProcessed(agsaRoot_t *agRoot,
+                                          bit32 queue,
+                                          bit32 obpi,
+                                          bit32 obci);
+#else
+#define ossaQueueProcessed(agRoot, queue, obpi, obci)
+#endif
+#endif
+
+#ifndef ossaSGpioCB
+GLOBAL void ossaSGpioCB(
+                    agsaRoot_t              *agRoot,
+                    agsaContext_t           *agContext, 
+                    agsaSGpioReqResponse_t  *pSgpioResponse
+                    );
+#endif
+
+#ifndef ossaPCIeDiagExecuteCB
+GLOBAL void ossaPCIeDiagExecuteCB(
+            agsaRoot_t             *agRoot,
+            agsaContext_t         *agContext,
+            bit32                  status,
+            bit32                  command,
+            agsaPCIeDiagResponse_t *resp );
+#endif
+
+#ifndef ossaGetDFEDataCB
+GLOBAL void ossaGetDFEDataCB(
+                             agsaRoot_t     *agRoot,
+                             agsaContext_t  *agContext,
+                             bit32           status,
+                             bit32           agInfoLen
+                             );
+#endif
+
+#ifndef ossaVhistCaptureCB
+GLOBAL void ossaVhistCaptureCB(
+                            agsaRoot_t    *agRoot,
+                            agsaContext_t *agContext,
+                            bit32         status,
+                            bit32         len);
+#endif
+
+#ifndef ossaGetIOErrorStatsCB
+GLOBAL void ossaGetIOErrorStatsCB (
+                      agsaRoot_t               *agRoot,
+                      agsaContext_t            *agContext,
+                      bit32                     status,
+                      agsaIOErrorEventStats_t  *stats
+                      );
+#endif
+
+#ifndef ossaGetIOEventStatsCB
+GLOBAL void ossaGetIOEventStatsCB (
+                      agsaRoot_t               *agRoot,
+                      agsaContext_t            *agContext,
+                      bit32                     status,
+                      agsaIOErrorEventStats_t  *stats
+                      );
+#endif
+
+#ifndef ossaOperatorManagementCB
+GLOBAL void ossaOperatorManagementCB(
+                  agsaRoot_t    *agRoot,
+                  agsaContext_t *agContext,
+                  bit32          status,
+                  bit32          eq
+                  );
+#endif
+
+
+#ifndef ossaEncryptSelftestExecuteCB
+GLOBAL void ossaEncryptSelftestExecuteCB (
+                        agsaRoot_t    *agRoot,
+                        agsaContext_t *agContext,
+                        bit32          status,
+                        bit32          type,
+                        bit32          length,
+                        void          *TestResult
+                        );
+
+#endif
+
+#ifndef ossaGetOperatorCB
+GLOBAL void ossaGetOperatorCB(
+               agsaRoot_t    *agRoot,
+               agsaContext_t *agContext,
+               bit32          status,
+               bit32          option,
+               bit32          num,
+               bit32          role,
+               agsaID_t      *id
+               );
+
+#endif
+
+#ifndef ossaSetOperatorCB
+GLOBAL void ossaSetOperatorCB(
+              agsaRoot_t    *agRoot,
+              agsaContext_t *agContext,
+              bit32          status,
+              bit32          eq
+              );
+
+#endif
+
+#ifndef ossaDIFEncryptionOffloadStartCB
+GLOBAL void ossaDIFEncryptionOffloadStartCB(
+              agsaRoot_t    *agRoot,
+              agsaContext_t *agContext,
+              bit32          status,
+              agsaOffloadDifDetails_t *agsaOffloadDifDetails
+              );
+#endif
+
+/***************************************************************************
+ * Definition of Misc related functions end                                *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Definition of Debug related functions start                             *
+ ***************************************************************************/
+#ifndef ossaLogTrace0
+GLOBAL void ossaLogTrace0(
+                          agsaRoot_t  *agRoot,
+                          bit32       traceCode
+                          );
+#endif
+
+#ifndef ossaLogTrace1
+GLOBAL void ossaLogTrace1(
+                          agsaRoot_t  *agRoot,
+                          bit32       traceCode,
+                          bit32       value1
+                          );
+#endif
+
+#ifndef ossaLogTrace2
+GLOBAL void ossaLogTrace2(
+                          agsaRoot_t  *agRoot,
+                          bit32       traceCode,
+                          bit32       value1,
+                          bit32       value2
+                          );
+#endif
+
+#ifndef ossaLogTrace3
+GLOBAL void ossaLogTrace3(
+                          agsaRoot_t  *agRoot,
+                          bit32       traceCode,
+                          bit32       value1,
+                          bit32       value2,
+                          bit32       value3
+                          );
+#endif
+
+#ifndef ossaLogTrace4
+GLOBAL void ossaLogTrace4(
+                          agsaRoot_t  *agRoot,
+                          bit32       traceCode,
+                          bit32       value1,
+                          bit32       value2,
+                          bit32       value3,
+                          bit32       value4
+                          );
+#endif
+
+#ifndef ossaLogDebugString
+GLOBAL void ossaLogDebugString(
+                         agsaRoot_t   *agRoot,
+                         bit32        level,
+                         char         *string,
+                         void         *ptr1,
+                         void         *ptr2,
+                         bit32        value1,
+                         bit32        value2
+                         );
+#endif
+
+#ifdef SALLSDK_OS_IOMB_LOG_ENABLE
+GLOBAL void ossaLogIomb(agsaRoot_t  *agRoot,
+                        bit32        queueNum,
+                        agBOOLEAN      isInbound,
+                        void        *pMsg,
+                        bit32        msgLength);
+#else
+#define ossaLogIomb(a, b,c,d,e )
+#endif
+
+osGLOBAL void ossaPCI_TRIGGER(agsaRoot_t  *agRoot );
+
+#ifdef PERF_COUNT
+osGLOBAL void ossaEnter(agsaRoot_t *agRoot, int io);
+osGLOBAL void ossaLeave(agsaRoot_t *agRoot, int io);
+#define OSSA_INP_ENTER(root) ossaEnter(root, 0)
+#define OSSA_INP_LEAVE(root) ossaLeave(root, 0)
+#define OSSA_OUT_ENTER(root) ossaEnter(root, 1)
+#define OSSA_OUT_LEAVE(root) ossaLeave(root, 1)
+#else
+#define OSSA_INP_ENTER(root)
+#define OSSA_INP_LEAVE(root)
+#define OSSA_OUT_ENTER(root)
+#define OSSA_OUT_LEAVE(root)
+#endif
+/***************************************************************************
+ * Definition of Debug related functions end                               *
+ ***************************************************************************/
+
+#endif  /*__SSDKOSAPI_H__ */

sys/dev/pms/RefTisa/sallsdk/hda/64k/istrimg.h

@@ -0,0 +1,589 @@
+/******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+*******************************************************************************/
+
+/*******************************************************************************
+**
+**  $RCSfile:$
+**
+**  $Date: 2011-01-05 11:25:33 -0800 (Wed, 05 Jan 2011) $
+**
+**  $Revision: 106946 $
+**
+**  $Author: lindfors $
+**
+**  DESCRIPTION : This file is generated by img2c tool.
+**                Nerver try to change it manually.
+**
+*******************************************************************************/
+
+
+
+/* Version Number: 01.10.10.00 */
+
+const unsigned char istrarray[] =
+{
+	0x01,0xA5,0x5A,0x96,0x69,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+	0x08,0x00,0x00,0x06,0x01,0x01,0x40,0x40,0x00,0x40,0x00,0x40,0x04,0x00,0x01,0x00,
+	0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x01,0x01,0x24,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+};

sys/dev/pms/RefTisa/sallsdk/spc/mpi.c

@@ -0,0 +1,980 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+
+/*******************************************************************************/
+/*! \file mpi.c
+ *  \brief The file is a MPI Libraries to implement the MPI functions
+ *
+ * The file implements the MPI Library functions.
+ *
+ */
+/*******************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#ifdef siTraceFileID
+#undef siTraceFileID
+#endif
+#define siTraceFileID 'A'
+#endif
+
+#ifdef LOOPBACK_MPI
+extern int loopback;
+#endif
+/*******************************************************************************/
+
+/*******************************************************************************/
+/*******************************************************************************/
+/* FUNCTIONS                                                                   */
+/*******************************************************************************/
+/*******************************************************************************/
+/** \fn void mpiRequirementsGet(mpiConfig_t* config, mpiMemReq_t* memoryRequirement)
+ *  \brief Retrieves the MPI layer resource requirements
+ *  \param config            MPI configuration for the Host MPI Message Unit
+ *  \param memoryRequirement Returned data structure as defined by mpiMemReq_t
+ *                           that holds the different chunks of memory that are required
+ *
+ * The mpiRequirementsGet() function is used to determine the resource requirements
+ * for the SPC device interface
+ *
+ * Return: None
+ */
+/*******************************************************************************/
+void mpiRequirementsGet(mpiConfig_t* config, mpiMemReq_t* memoryRequirement)
+{
+  bit32 qIdx, numq;
+  mpiMemReq_t* memoryMap;
+  SA_DBG2(("Entering function:mpiRequirementsGet\n"));
+  SA_ASSERT((NULL != config), "config argument cannot be null");
+
+  memoryMap = memoryRequirement;
+  memoryMap->count = 0;
+
+  /* MPI Memory region 0 for MSGU(AAP1) Event Log for fw */
+  memoryMap->region[memoryMap->count].numElements = 1;
+  memoryMap->region[memoryMap->count].elementSize = sizeof(bit8) * config->mainConfig.eventLogSize;
+  memoryMap->region[memoryMap->count].totalLength = sizeof(bit8) * config->mainConfig.eventLogSize;
+  memoryMap->region[memoryMap->count].alignment = 32;
+  memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM;
+  SA_DBG2(("mpiRequirementsGet:eventLogSize region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength ));
+  memoryMap->count++;
+
+  SA_DBG2(("mpiRequirementsGet:eventLogSize region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength ));
+  /* MPI Memory region 1 for IOP Event Log for fw */
+  memoryMap->region[memoryMap->count].numElements = 1;
+  memoryMap->region[memoryMap->count].elementSize = sizeof(bit8) * config->mainConfig.IOPeventLogSize;
+  memoryMap->region[memoryMap->count].totalLength = sizeof(bit8) * config->mainConfig.IOPeventLogSize;
+  memoryMap->region[memoryMap->count].alignment = 32;
+  memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM;
+  SA_DBG2(("mpiRequirementsGet:IOPeventLogSize region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength ));
+  memoryMap->count++;
+
+  /* MPI Memory region 2 for consumer Index of inbound queues */
+  memoryMap->region[memoryMap->count].numElements = 1;
+  memoryMap->region[memoryMap->count].elementSize = sizeof(bit32) * config->numInboundQueues;
+  memoryMap->region[memoryMap->count].totalLength = sizeof(bit32) * config->numInboundQueues;
+  memoryMap->region[memoryMap->count].alignment = 4;
+  memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM;
+  SA_DBG2(("mpiRequirementsGet:numInboundQueues region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength ));
+  memoryMap->count++;
+
+  /* MPI Memory region 3 for producer Index of outbound queues */
+  memoryMap->region[memoryMap->count].numElements = 1;
+  memoryMap->region[memoryMap->count].elementSize = sizeof(bit32) * config->numOutboundQueues;
+  memoryMap->region[memoryMap->count].totalLength = sizeof(bit32) * config->numOutboundQueues;
+  memoryMap->region[memoryMap->count].alignment = 4;
+  memoryMap->region[memoryMap->count].type = AGSA_DMA_MEM;
+  SA_DBG2(("mpiRequirementsGet:numOutboundQueues region[%d] 0x%X\n",memoryMap->count,memoryMap->region[memoryMap->count].totalLength ));
+  memoryMap->count++;
+
+  /* MPI Memory regions 4, ... for the inbound queues - depends on configuration */
+  numq = 0;
+  for(qIdx = 0; qIdx < config->numInboundQueues; qIdx++)
+  {
+    if(0 != config->inboundQueues[qIdx].numElements)
+    {
+        bit32 memSize = config->inboundQueues[qIdx].numElements * config->inboundQueues[qIdx].elementSize;
+        bit32 remainder = memSize & 127;
+
+        /* Calculate the size of this queue padded to 128 bytes */
+        if (remainder > 0)
+        {
+            memSize += (128 - remainder);
+        }
+
+        if (numq == 0)
+        {
+            memoryMap->region[memoryMap->count].numElements = 1;
+            memoryMap->region[memoryMap->count].elementSize = memSize;
+            memoryMap->region[memoryMap->count].totalLength = memSize;
+            memoryMap->region[memoryMap->count].alignment = 128;
+            memoryMap->region[memoryMap->count].type = AGSA_CACHED_DMA_MEM;
+        }
+        else
+        {
+            memoryMap->region[memoryMap->count].elementSize += memSize;
+            memoryMap->region[memoryMap->count].totalLength += memSize;
+        }
+
+        numq++;
+
+        if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) ||
+            (qIdx == (bit32)(config->numInboundQueues - 1)))
+        {
+            SA_DBG2(("mpiRequirementsGet: (inboundQueues) memoryMap->region[%d].elementSize = %d\n",
+                     memoryMap->count, memoryMap->region[memoryMap->count].elementSize));
+            SA_DBG2(("mpiRequirementsGet: (inboundQueues) memoryMap->region[%d].numElements = %d\n",
+                     memoryMap->count, memoryMap->region[memoryMap->count].numElements));
+
+            memoryMap->count++;
+            numq = 0;
+        }
+    }
+  }
+
+  /* MPI Memory regions for the outbound queues - depends on configuration */
+  numq = 0;
+  for(qIdx = 0; qIdx < config->numOutboundQueues; qIdx++)
+  {
+    if(0 != config->outboundQueues[qIdx].numElements)
+    {
+        bit32 memSize = config->outboundQueues[qIdx].numElements * config->outboundQueues[qIdx].elementSize;
+        bit32 remainder = memSize & 127;
+
+        /* Calculate the size of this queue padded to 128 bytes */
+        if (remainder > 0)
+        {
+            memSize += (128 - remainder);
+        }
+
+        if (numq == 0)
+        {
+            memoryMap->region[memoryMap->count].numElements = 1;
+            memoryMap->region[memoryMap->count].elementSize = memSize;
+            memoryMap->region[memoryMap->count].totalLength = memSize;
+            memoryMap->region[memoryMap->count].alignment = 128;
+            memoryMap->region[memoryMap->count].type = AGSA_CACHED_DMA_MEM;
+        }
+        else
+        {
+            memoryMap->region[memoryMap->count].elementSize += memSize;
+            memoryMap->region[memoryMap->count].totalLength += memSize;
+        }
+
+        numq++;
+
+        if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) ||
+            (qIdx ==  (bit32)(config->numOutboundQueues - 1)))
+        {
+            SA_DBG2(("mpiRequirementsGet: (outboundQueues) memoryMap->region[%d].elementSize = %d\n",
+                     memoryMap->count, memoryMap->region[memoryMap->count].elementSize));
+            SA_DBG2(("mpiRequirementsGet: (outboundQueues) memoryMap->region[%d].numElements = %d\n",
+                     memoryMap->count, memoryMap->region[memoryMap->count].numElements));
+
+
+            memoryMap->count++;
+            numq = 0;
+        }
+    }
+  }
+
+}
+
+/*******************************************************************************/
+/** \fn mpiMsgFreeGet(mpiICQueue_t *circularQ, bit16 messageSize, void** messagePtr)
+ *  \brief Retrieves a free message buffer from an inbound queue
+ *  \param circularQ    Pointer to an inbound circular queue
+ *  \param messageSize  Requested message size in bytes - only support 64 bytes/element
+ *  \param messagePtr   Pointer to the free message buffer payload (not including message header) or NULL if no free message buffers are available
+ *
+ * This function is used to retrieve a free message buffer for the given inbound queue of at least
+ * messageSize bytes.
+ * The caller can use the returned buffer to construct the message and then call mpiMsgProduce()
+ * to deliver the message to the device message unit or mpiMsgInvalidate() if the message buffer
+ * is not going to be used
+ *
+ * Return:
+ *         AGSA_RC_SUCCESS if messagePtr contains a valid message buffer pointer
+ *         AGSA_RC_FAILURE if messageSize larger than the elementSize of queue
+ *         AGSA_RC_BUSY    if there are not free message buffers (Queue full)
+ */
+/*******************************************************************************/
+GLOBAL FORCEINLINE
+bit32
+mpiMsgFreeGet(
+  mpiICQueue_t *circularQ,
+  bit16 messageSize,
+  void** messagePtr
+  )
+{
+  bit32 offset;
+  agsaRoot_t          *agRoot=circularQ->agRoot;
+  mpiMsgHeader_t *msgHeader;
+  bit8 bcCount = 1; /* only support single buffer */
+
+  SA_DBG4(("Entering function:mpiMsgFreeGet\n"));
+  SA_ASSERT(NULL != circularQ, "circularQ cannot be null");
+  SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null");
+  SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0");
+
+  /* Checks is the requested message size can be allocated in this queue */
+  if(messageSize > circularQ->elementSize)
+  {
+    SA_DBG1(("mpiMsgFreeGet: Message Size (%d) is larger than Q element size (%d)\n",messageSize,circularQ->elementSize));
+    return AGSA_RC_FAILURE;
+  }
+
+  /* Stores the new consumer index */
+  OSSA_READ_LE_32(circularQ->agRoot, &circularQ->consumerIdx, circularQ->ciPointer, 0);
+  /* if inbound queue is full, return busy */
+  /* This queue full logic may only works for bc == 1 ( == ) */
+  /* ( pi + bc ) % size > ci not fully works for bc > 1 */
+  /* To do - support bc > 1 case and wrap around case */
+  if (((circularQ->producerIdx + bcCount) % circularQ->numElements) == circularQ->consumerIdx)
+  {
+    *messagePtr = NULL;
+    smTrace(hpDBG_VERY_LOUD,"Za", (((circularQ->producerIdx & 0xFFF) << 16) |  (circularQ->consumerIdx & 0xFFF) ));
+    /* TP:Za IQ PI CI */
+    ossaHwRegRead(agRoot, MSGU_HOST_SCRATCH_PAD_0);
+    SA_DBG1(("mpiMsgFreeGet: %d + %d == %d AGSA_RC_BUSY\n",circularQ->producerIdx,bcCount,circularQ->consumerIdx));
+
+    return AGSA_RC_BUSY;
+  }
+
+  smTrace(hpDBG_VERY_LOUD,"Zb", (((circularQ->producerIdx & 0xFFF) << 16) |  (circularQ->consumerIdx & 0xFFF) ));
+  /* TP:Zb IQ PI CI */
+
+
+  /* get memory IOMB buffer address */
+  offset = circularQ->producerIdx * circularQ->elementSize;
+  /* increment to next bcCount element */
+  circularQ->producerIdx = (circularQ->producerIdx + bcCount) % circularQ->numElements;
+
+  /* Adds that distance to the base of the region virtual address plus the message header size*/
+  msgHeader = (mpiMsgHeader_t*) (((bit8 *)(circularQ->memoryRegion.virtPtr)) + offset);
+
+  SA_DBG3(("mpiMsgFreeGet: msgHeader = %p Offset = 0x%x\n", (void *)msgHeader, offset));
+
+  /* Sets the message buffer in "allocated" state */
+  /* bc always is 1 for inbound queue */
+  /* temporarily store it in the native endian format, when the rest of the */
+  /* header is filled, this would be converted to Little Endian */
+  msgHeader->Header = (1<<24);
+  *messagePtr = ((bit8*)msgHeader) + sizeof(mpiMsgHeader_t);
+
+  return AGSA_RC_SUCCESS;
+}
+
+#ifdef LOOPBACK_MPI
+GLOBAL bit32 mpiMsgFreeGetOQ(mpiOCQueue_t *circularQ, bit16 messageSize, void** messagePtr)
+{
+  bit32 offset;
+  mpiMsgHeader_t *msgHeader;
+  bit8 bcCount = 1; /* only support single buffer */
+
+  SA_DBG4(("Entering function:mpiMsgFreeGet\n"));
+  SA_ASSERT(NULL != circularQ, "circularQ cannot be null");
+  SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null");
+  SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0");
+
+  /* Checks is the requested message size can be allocated in this queue */
+  if(messageSize > circularQ->elementSize)
+  {
+    SA_DBG1(("mpiMsgFreeGet: Message Size is not fit in\n"));
+    return AGSA_RC_FAILURE;
+  }
+
+  /* Stores the new consumer index */
+  //OSSA_READ_LE_32(circularQ->agRoot, &circularQ->consumerIdx, circularQ->ciPointer, 0);
+  /* if inbound queue is full, return busy */
+  /* This queue full logic may only works for bc == 1 ( == ) */
+  /* ( pi + bc ) % size > ci not fully works for bc > 1 */
+  /* To do - support bc > 1 case and wrap around case */
+  if (((circularQ->producerIdx + bcCount) % circularQ->numElements) == circularQ->consumerIdx)
+  {
+    *messagePtr = NULL;
+    return AGSA_RC_BUSY;
+  }
+
+  /* get memory IOMB buffer address */
+  offset = circularQ->producerIdx * circularQ->elementSize;
+  /* increment to next bcCount element */
+  circularQ->producerIdx = (circularQ->producerIdx + bcCount) % circularQ->numElements;
+
+  /* Adds that distance to the base of the region virtual address plus the message header size*/
+  msgHeader = (mpiMsgHeader_t*) (((bit8 *)(circularQ->memoryRegion.virtPtr)) + offset);
+
+  SA_DBG3(("mpiMsgFreeGet: msgHeader = %p Offset = 0x%x\n", (void *)msgHeader, offset));
+
+  /* Sets the message buffer in "allocated" state */
+  /* bc always is 1 for inbound queue */
+  /* temporarily store it in the native endian format, when the rest of the */
+  /* header is filled, this would be converted to Little Endian */
+  msgHeader->Header = (1<<24);
+  *messagePtr = ((bit8*)msgHeader) + sizeof(mpiMsgHeader_t);
+
+  return AGSA_RC_SUCCESS;
+}
+#endif
+
+/*******************************************************************************/
+/** \fn mpiMsgProduce(mpiICQueue_t *circularQ, void *messagePtr, mpiMsgCategory_t category, bit16 opCode, bit8 responseQueue)
+ *  \brief Add a header of IOMB then send to a inbound queue and update the Producer index
+ *  \param circularQ     Pointer to an inbound queue
+ *  \param messagePtr    Pointer to the message buffer payload (not including message header))
+ *  \param category      Message category (ETHERNET, FC, SAS-SATA, SCSI)
+ *  \param opCode        Message operation code
+ *  \param responseQueue If the message requires response, this paramater indicates the outbound queue for the response
+ *
+ * This function is used to sumit a message buffer, previously obtained from  mpiMsgFreeGet()
+ * function call, to the given Inbound queue
+ *
+ * Return:
+ *         AGSA_RC_SUCCESS if the message has been posted succesfully
+ */
+/*******************************************************************************/
+#ifdef FAST_IO_TEST
+GLOBAL bit32 mpiMsgPrepare(
+                       mpiICQueue_t *circularQ,
+                       void         *messagePtr,
+                       mpiMsgCategory_t category,
+                       bit16        opCode,
+                       bit8         responseQueue,
+                       bit8         hiPriority
+                       )
+{
+  mpiMsgHeader_t *msgHeader;
+  bit32          bc;
+  bit32          Header = 0;
+  bit32          hpriority = 0;
+
+  SA_DBG4(("Entering function:mpiMsgProduce\n"));
+  SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null");
+  SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null");
+  SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue"
+            " is 0");
+  SA_ASSERT(MPI_MAX_OUTBOUND_QUEUES > responseQueue, "oQueue ID is wrong");
+
+  /* Obtains the address of the entire message buffer, including the header */
+  msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr) - sizeof(mpiMsgHeader_t));
+  /* Read the BC from header, its stored in native endian format when message
+     was allocated */
+  /* intially */
+  bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK);
+  SA_DBG6(("mpiMsgProduce: msgHeader bc %d\n", bc));
+  if (circularQ->priority)
+    hpriority = 1;
+
+  /* Checks the message is in "allocated" state */
+  SA_ASSERT(0 != bc, "The message buffer is not in \"allocated\" state "
+                     "(bc == 0)");
+
+  Header = ((V_BIT << SHIFT31) | (hpriority << SHIFT30)  |
+            ((bc & BC_MASK) << SHIFT24) |
+            ((responseQueue & OBID_MASK) << SHIFT16) |
+            ((category  & CAT_MASK) << SHIFT12 ) | (opCode & OPCODE_MASK));
+
+  /* pre flush the IOMB cache line */
+  ossaCachePreFlush(circularQ->agRoot,
+                    (void *)circularQ->memoryRegion.appHandle,
+                    (void *)msgHeader, circularQ->elementSize * bc);
+  OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t,
+                   Header), Header);
+  /* flush the IOMB cache line */
+  ossaCacheFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle,
+                 (void *)msgHeader, circularQ->elementSize * bc);
+
+  MPI_DEBUG_TRACE( circularQ->qNumber,
+                  ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),
+                   MPI_DEBUG_TRACE_IBQ,
+                  (void *)msgHeader,
+                  circularQ->elementSize);
+
+  ossaLogIomb(circularQ->agRoot,
+              circularQ->qNumber,
+              TRUE,
+              (void *)msgHeader,
+              circularQ->elementSize);
+
+  return AGSA_RC_SUCCESS;
+} /* mpiMsgPrepare */
+
+GLOBAL bit32 mpiMsgProduce(
+                       mpiICQueue_t *circularQ,
+                       void         *messagePtr,
+                       mpiMsgCategory_t category,
+                       bit16        opCode,
+                       bit8         responseQueue,
+                       bit8         hiPriority
+                       )
+{
+  bit32 ret;
+
+  ret = mpiMsgPrepare(circularQ, messagePtr, category, opCode, responseQueue,
+                      hiPriority);
+  if (ret == AGSA_RC_SUCCESS)
+  {
+    /* update PI of inbound queue */
+    ossaHwRegWriteExt(circularQ->agRoot,
+                      circularQ->PIPCIBar,
+                      circularQ->PIPCIOffset,
+                      circularQ->producerIdx);
+  }
+  return ret;
+}
+
+GLOBAL void mpiIBQMsgSend(mpiICQueue_t *circularQ)
+{
+  ossaHwRegWriteExt(circularQ->agRoot,
+                    circularQ->PIPCIBar,
+                    circularQ->PIPCIOffset,
+                    circularQ->producerIdx);
+}
+#else  /* FAST_IO_TEST */
+
+GLOBAL FORCEINLINE
+bit32
+mpiMsgProduce(
+  mpiICQueue_t *circularQ,
+  void *messagePtr,
+  mpiMsgCategory_t category,
+  bit16 opCode,
+  bit8 responseQueue,
+  bit8 hiPriority
+  )
+{
+  mpiMsgHeader_t *msgHeader;
+  bit32          bc;
+  bit32          Header = 0;
+  bit32          hpriority = 0;
+
+#ifdef SA_FW_TEST_BUNCH_STARTS
+#define Need_agRootDefined 1
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+  bit32             i;
+#define Need_agRootDefined 1
+#endif /* SA_ENABLE_TRACE_FUNCTIONS */
+
+#ifdef MPI_DEBUG_TRACE_ENABLE
+#define Need_agRootDefined 1
+#endif /* MPI_DEBUG_TRACE_ENABLE */
+
+#ifdef Need_agRootDefined
+  agsaRoot_t   *agRoot=circularQ->agRoot;
+#ifdef SA_FW_TEST_BUNCH_STARTS
+   agsaLLRoot_t *saRoot = agNULL;
+  saRoot = agRoot->sdkData;
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+
+#undef Need_agRootDefined
+#endif /* Need_agRootDefined */
+
+  SA_DBG4(("Entering function:mpiMsgProduce\n"));
+  SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null");
+  SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null");
+  SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0");
+  SA_ASSERT(MPI_MAX_OUTBOUND_QUEUES > responseQueue, "oQueue ID is wrong");
+
+  /* REB Start extra trace */
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"22");
+  /* REB End extra trace */
+
+  /* Obtains the address of the entire message buffer, including the header */
+  msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr) - sizeof(mpiMsgHeader_t));
+  /* Read the BC from header, its stored in native endian format when message was allocated */
+  /* intially */
+  bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK);
+  SA_DBG6(("mpiMsgProduce: msgHeader bc %d\n", bc));
+  if (circularQ->priority)
+  {
+    hpriority = 1;
+  }
+
+  /* Checks the message is in "allocated" state */
+  SA_ASSERT(0 != bc, "The message buffer is not in \"allocated\" state (bc == 0)");
+
+  Header = ((V_BIT << SHIFT31) |
+            (hpriority << SHIFT30)  |
+            ((bc & BC_MASK) << SHIFT24) |
+            ((responseQueue & OBID_MASK) << SHIFT16) |
+            ((category  & CAT_MASK) << SHIFT12 ) |
+            (opCode & OPCODE_MASK));
+
+  /* pre flush the cache line */
+  ossaCachePreFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, circularQ->elementSize * bc);
+  OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, Header), Header);
+  /* flush the cache line for IOMB */
+  ossaCacheFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, circularQ->elementSize * bc);
+
+  MPI_DEBUG_TRACE( circularQ->qNumber,
+                  ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),
+                  MPI_DEBUG_TRACE_IBQ,
+                  (void *)msgHeader,
+                  circularQ->elementSize);
+
+  ossaLogIomb(circularQ->agRoot,
+              circularQ->qNumber,
+              TRUE,
+              (void *)msgHeader,
+              circularQ->elementSize);
+
+#if defined(SALLSDK_DEBUG)
+  MPI_IBQ_IOMB_LOG(circularQ->qNumber, (void *)msgHeader, circularQ->elementSize);
+#endif  /* SALLSDK_DEBUG */
+  /* REB Start extra trace */
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+  smTrace(hpDBG_IOMB,"M1",circularQ->qNumber);
+ /* TP:M1 circularQ->qNumber */
+  for (i=0; i<((bit32)bc*(circularQ->elementSize/4)); i++)
+  {
+      /* The -sizeof(mpiMsgHeader_t) is to account for mpiMsgProduce adding the header to the pMessage pointer */
+      smTrace(hpDBG_IOMB,"MD",*( ((bit32 *)((bit8 *)messagePtr - sizeof(mpiMsgHeader_t))) + i));
+      /* TP:MD Inbound IOMB Dword */
+  }
+#endif /* SA_ENABLE_TRACE_FUNCTIONS */
+
+  /* update PI of inbound queue */
+
+#ifdef SA_FW_TEST_BUNCH_STARTS
+  if(saRoot->BunchStarts_Enable)
+  {
+      if (circularQ->BunchStarts_QPending == 0)
+      {
+          // store tick value for 1st deferred IO only 
+          circularQ->BunchStarts_QPendingTick = saRoot->timeTick;
+      }
+      // update queue's pending count
+      circularQ->BunchStarts_QPending++;
+
+      // update global pending count
+      saRoot->BunchStarts_Pending++;
+
+      SA_DBG1(("mpiMsgProduce: BunchStarts - Global Pending %d\n", saRoot->BunchStarts_Pending));
+      SA_DBG1(("mpiMsgProduce: BunchStarts - QPending %d, Q-%d\n", circularQ->BunchStarts_QPending, circularQ->qNumber));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "22");
+
+      return AGSA_RC_SUCCESS;
+  }
+
+  saRoot->BunchStarts_Pending     = 0;
+  circularQ->BunchStarts_QPending = 0;
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+  ossaHwRegWriteExt(circularQ->agRoot,
+                    circularQ->PIPCIBar,
+                    circularQ->PIPCIOffset,
+                    circularQ->producerIdx);
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "22");
+
+  return AGSA_RC_SUCCESS;
+} /* mpiMsgProduce */
+#endif /* FAST_IO_TEST */
+
+#ifdef SA_FW_TEST_BUNCH_STARTS
+
+void mpiMsgProduceBunch(  agsaLLRoot_t  *saRoot)
+{
+  mpiICQueue_t *circularQ;
+  bit32 inq;
+
+  for(inq=0; ((inq < saRoot->QueueConfig.numInboundQueues) && saRoot->BunchStarts_Pending); inq++)
+  {
+    circularQ= &saRoot->inboundQueue[inq];
+    /* If any pending IOs present then either process if BunchStarts_Threshold
+     * IO limit reached or if the timer has popped
+     */
+    if (circularQ->BunchStarts_QPending &&
+        ((circularQ->BunchStarts_QPending >= saRoot->BunchStarts_Threshold) || 
+         ((saRoot->timeTick - circularQ->BunchStarts_QPendingTick) >= saRoot->BunchStarts_TimeoutTicks))
+       )
+    {
+      if(circularQ->qNumber != inq)
+      {
+        SA_DBG1(("mpiMsgProduceBunch:circularQ->qNumber(%d) != inq(%d)\n",circularQ->qNumber, inq));
+      }
+
+      SA_DBG1(("mpiMsgProduceBunch: IQ=%d, PI=%d\n", inq, circularQ->producerIdx));
+      SA_DBG1(("mpiMsgProduceBunch: Qpending=%d, TotPending=%d\n", circularQ->BunchStarts_QPending, saRoot->BunchStarts_Pending));
+
+      ossaHwRegWriteExt(circularQ->agRoot,
+                     circularQ->PIPCIBar,
+                     circularQ->PIPCIOffset,
+                     circularQ->producerIdx);
+
+      // update global pending count
+      saRoot->BunchStarts_Pending -= circularQ->BunchStarts_QPending;
+
+      // clear current queue's pending count after processing
+      circularQ->BunchStarts_QPending = 0;
+      circularQ->BunchStarts_QPendingTick = saRoot->timeTick;
+    }
+  }
+}
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+
+/*******************************************************************************/
+/** \fn mpiMsgConsume(mpiOCQueue_t *circularQ, void *messagePtr1,
+ *                mpiMsgCategory_t * pCategory, bit16 * pOpCode, bit8 * pBC)
+ *  \brief Get a received message
+ *  \param circularQ   Pointer to a outbound queue
+ *  \param messagePtr1 Pointer to the returned message buffer or NULL if no valid message
+ *  \param pCategory   Pointer to Message category (ETHERNET, FC, SAS-SATA, SCSI)
+ *  \param pOpCode     Pointer to Message operation code
+ *  \param pBC         Pointer to buffer count
+ *
+ * Consume a receive message in the specified outbound queue
+ *
+ * Return:
+ *         AGSA_RC_SUCCESS if the message has been retrieved succesfully
+ *         AGSA_RC_BUSY    if the circular is empty
+ */
+/*******************************************************************************/
+GLOBAL FORCEINLINE
+bit32
+mpiMsgConsume(
+  mpiOCQueue_t       *circularQ,
+  void             ** messagePtr1,
+  mpiMsgCategory_t   *pCategory,
+  bit16              *pOpCode,
+  bit8               *pBC
+  )
+{
+  mpiMsgHeader_t *msgHeader;
+  bit32          msgHeader_tmp;
+
+  SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null");
+  SA_ASSERT(NULL != messagePtr1, "messagePtr1 argument cannot be null");
+  SA_ASSERT(NULL != pCategory, "pCategory argument cannot be null");
+  SA_ASSERT(NULL != pOpCode, "pOpCode argument cannot be null");
+  SA_ASSERT(NULL != pBC, "pBC argument cannot be null");
+  SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0");
+
+  do
+  {
+    /* If there are not-yet-delivered messages ... */
+    if(circularQ->producerIdx != circularQ->consumerIdx)
+    {
+      /* Get the pointer to the circular queue buffer element */
+      msgHeader = (mpiMsgHeader_t*) ((bit8 *)(circularQ->memoryRegion.virtPtr) + circularQ->consumerIdx * circularQ->elementSize);
+
+#ifdef LOOPBACK_MPI
+      if (!loopback)
+#endif
+      /* invalidate the cache line of IOMB */
+      ossaCacheInvalidate(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, circularQ->elementSize);
+
+
+      /* read header */
+      OSSA_READ_LE_32(circularQ->agRoot, &msgHeader_tmp, msgHeader, 0);
+
+      SA_DBG4(("mpiMsgConsume: process an IOMB, header=0x%x\n", msgHeader_tmp));
+
+      SA_ASSERT(0 != (msgHeader_tmp & HEADER_BC_MASK), "The bc field in the header is 0");
+#ifdef TEST
+      /* for debugging */
+      if (0 == (msgHeader_tmp & HEADER_BC_MASK))
+      {
+        SA_DBG1(("mpiMsgConsume: CI=%d PI=%d msgHeader=%p\n", circularQ->consumerIdx, circularQ->producerIdx, (void *)msgHeader));
+        circularQ->consumerIdx = (circularQ->consumerIdx + 1) % circularQ->numElements;
+        /* update the CI of outbound queue - skip this blank IOMB, for test only */
+        ossaHwRegWriteExt(circularQ->agRoot,
+                          circularQ->CIPCIBar,
+                          circularQ->CIPCIOffset,
+                          circularQ->consumerIdx);
+        return AGSA_RC_FAILURE;
+      }
+#endif
+      /* get message pointer of valid entry */
+      if (0 != (msgHeader_tmp & HEADER_V_MASK))
+      {
+        SA_ASSERT(circularQ->consumerIdx <= circularQ->numElements, "Multi-buffer messages cannot wrap around");
+
+        if (OPC_OUB_SKIP_ENTRY != (msgHeader_tmp & OPCODE_MASK))
+        {
+          /* ... return the message payload */
+          *messagePtr1 = ((bit8*)msgHeader) + sizeof(mpiMsgHeader_t);
+          *pCategory   = (mpiMsgCategory_t)(msgHeader_tmp >> SHIFT12) & CAT_MASK;
+          *pOpCode     = (bit16)(msgHeader_tmp & OPCODE_MASK);
+          *pBC         = (bit8)((msgHeader_tmp >> SHIFT24) & BC_MASK);
+
+          /* invalidate the cache line for IOMB */
+#ifdef LOOPBACK_MPI
+          if (!loopback)
+#endif
+            ossaCacheInvalidate(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle, (void *)msgHeader, (*pBC - 1) * circularQ->elementSize);
+
+#if defined(SALLSDK_DEBUG)
+          SA_DBG3(("mpiMsgConsume: CI=%d PI=%d msgHeader=%p\n", circularQ->consumerIdx, circularQ->producerIdx, (void *)msgHeader));
+          MPI_OBQ_IOMB_LOG(circularQ->qNumber, (void *)msgHeader, circularQ->elementSize);
+#endif
+          return AGSA_RC_SUCCESS;
+        }
+        else
+        {
+          SA_DBG3(("mpiMsgConsume: SKIP_ENTRIES_IOMB BC=%d\n", (msgHeader_tmp >> SHIFT24) & BC_MASK));
+          /* Updated comsumerIdx and skip it */
+          circularQ->consumerIdx = (circularQ->consumerIdx + ((msgHeader_tmp >> SHIFT24) & BC_MASK)) % circularQ->numElements;
+          /* clean header to 0 */
+          msgHeader_tmp = 0;
+          /*ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK);*/
+
+          OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, Header), msgHeader_tmp);
+
+          /* update the CI of outbound queue */
+          ossaHwRegWriteExt(circularQ->agRoot,
+                            circularQ->CIPCIBar,
+                            circularQ->CIPCIOffset,
+                            circularQ->consumerIdx);
+          /* Update the producer index */
+          OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0);
+          /*ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK); */
+        }
+      }
+      else
+      {
+        /* V bit is not set */
+#if defined(SALLSDK_DEBUG)
+        agsaRoot_t *agRoot=circularQ->agRoot;
+        SA_DBG1(("mpiMsgConsume: V bit not set, PI=%d CI=%d msgHeader=%p\n",  circularQ->producerIdx, circularQ->consumerIdx,(void *)msgHeader));
+        SA_DBG1(("mpiMsgConsume: V bit not set, 0x%08X Q=%d  \n", msgHeader_tmp, circularQ->qNumber));
+
+        MPI_DEBUG_TRACE(MPI_DEBUG_TRACE_QNUM_ERROR + circularQ->qNumber,
+                        ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),
+                          MPI_DEBUG_TRACE_OBQ,
+                         (void *)(((bit8*)msgHeader) - sizeof(mpiMsgHeader_t)),
+                          circularQ->elementSize);
+
+        circularQ->consumerIdx = circularQ->consumerIdx % circularQ->numElements;
+        circularQ->consumerIdx ++;
+        OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t, Header), msgHeader_tmp);
+        ossaHwRegWriteExt(agRoot,
+                          circularQ->CIPCIBar,
+                          circularQ->CIPCIOffset,
+                          circularQ->consumerIdx);
+        MPI_OBQ_IOMB_LOG(circularQ->qNumber, (void *)msgHeader, circularQ->elementSize);
+#endif
+        SA_DBG1(("mpiMsgConsume: V bit is not set!!!!! HW CI=%d\n", ossaHwRegReadExt(circularQ->agRoot, circularQ->CIPCIBar, circularQ->CIPCIOffset) ));
+        SA_ASSERT(0, "V bit is not set");
+        return AGSA_RC_FAILURE;
+      }
+    }
+    else
+    {
+      /* Update the producer index from SPC */
+      OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0);
+    }
+  } while(circularQ->producerIdx != circularQ->consumerIdx); /* while we don't have any more not-yet-delivered message */
+
+#ifdef TEST
+  SA_DBG4(("mpiMsgConsume: Outbound queue is empty.\n"));
+#endif
+
+  /* report empty */
+  return AGSA_RC_BUSY;
+}
+
+/*******************************************************************************/
+/** \fn mpiMsgFreeSet(mpiOCQueue_t *circularQ, void *messagePtr)
+ *  \brief Returns a received message to the outbound queue
+ *  \param circularQ   Pointer to an outbound queue
+ *  \param messagePtr1 Pointer to the returned message buffer to free
+ *  \param messagePtr2 Pointer to the returned message buffer to free if bc > 1
+ *
+ * Returns consumed and processed message to the the specified outbounf queue
+ *
+ * Return:
+ *         AGSA_RC_SUCCESS if the message has been returned succesfully
+ */
+/*******************************************************************************/
+GLOBAL FORCEINLINE
+bit32
+mpiMsgFreeSet(
+  mpiOCQueue_t *circularQ,
+  void *messagePtr1,
+  bit8 bc
+  )
+{
+  mpiMsgHeader_t     *msgHeader;
+
+  SA_DBG4(("Entering function:mpiMsgFreeSet\n"));
+  SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null");
+  SA_ASSERT(NULL != messagePtr1, "messagePtr1 argument cannot be null");
+  SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue is 0");
+
+  /* Obtains the address of the entire message buffer, including the header */
+  msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr1) - sizeof(mpiMsgHeader_t));
+
+  if ( ((mpiMsgHeader_t*)((bit8*)circularQ->memoryRegion.virtPtr + circularQ->consumerIdx * circularQ->elementSize)) != msgHeader)
+  {
+    /* IOMB of CI points mismatch with Message Header - should never happened */
+    SA_DBG1(("mpiMsgFreeSet: Wrong CI, Q %d ConsumeIdx = %d msgHeader 0x%08x\n",circularQ->qNumber, circularQ->consumerIdx ,msgHeader->Header));
+    SA_DBG1(("mpiMsgFreeSet: msgHeader %p != %p\n", msgHeader,((mpiMsgHeader_t*)((bit8*)circularQ->memoryRegion.virtPtr + circularQ->consumerIdx * circularQ->elementSize))));
+
+#ifdef LOOPBACK_MPI
+    if (!loopback)
+#endif
+    /* Update the producer index from SPC */
+    OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0);
+#if defined(SALLSDK_DEBUG)
+    SA_DBG3(("mpiMsgFreeSet: ProducerIdx = %d\n", circularQ->producerIdx));
+#endif
+    return AGSA_RC_SUCCESS;
+  }
+
+  /* ... free the circular queue buffer elements associated with the message ... */
+  /*... by incrementing the consumer index (with wrap arround) */
+  circularQ->consumerIdx = (circularQ->consumerIdx + bc) % circularQ->numElements;
+
+  /* Invalidates this circular queue buffer element */
+
+  msgHeader->Header &= ~HEADER_V_MASK; /* Clear Valid bit to indicate IOMB consumed by host */
+  SA_ASSERT(circularQ->consumerIdx <= circularQ->numElements, "Multi-buffer messages cannot wrap arround");
+
+  /* update the CI of outbound queue */
+#ifdef LOOPBACK_MPI
+  if (!loopback)
+#endif
+  {
+  ossaHwRegWriteExt(circularQ->agRoot,
+                    circularQ->CIPCIBar,
+                    circularQ->CIPCIOffset,
+                    circularQ->consumerIdx);
+
+  /* Update the producer index from SPC */
+  OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0);
+  }
+#if defined(SALLSDK_DEBUG)
+  SA_DBG5(("mpiMsgFreeSet: CI=%d PI=%d\n", circularQ->consumerIdx, circularQ->producerIdx));
+#endif
+  return AGSA_RC_SUCCESS;
+}
+
+#ifdef TEST
+GLOBAL bit32 mpiRotateQnumber(agsaRoot_t *agRoot)
+{
+  agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+  bit32        denom;
+  bit32        ret = 0;
+
+  /* inbound queue number */
+  saRoot->IBQnumber++;
+  denom = saRoot->QueueConfig.numInboundQueues;
+  if (saRoot->IBQnumber % denom == 0) /* % Qnumber*/
+  {
+    saRoot->IBQnumber = 0;
+  }
+  SA_DBG3(("mpiRotateQnumber: IBQnumber %d\n", saRoot->IBQnumber));
+
+  /* outbound queue number */
+  saRoot->OBQnumber++;
+  denom = saRoot->QueueConfig.numOutboundQueues;
+  if (saRoot->OBQnumber % denom == 0) /* % Qnumber*/
+  {
+    saRoot->OBQnumber = 0;
+  }
+  SA_DBG3(("mpiRotateQnumber: OBQnumber %d\n", saRoot->OBQnumber));
+
+  ret = (saRoot->OBQnumber << SHIFT16) | saRoot->IBQnumber;
+  return ret;
+}
+#endif
+
+#ifdef LOOPBACK_MPI
+GLOBAL bit32 mpiMsgProduceOQ(
+                       mpiOCQueue_t *circularQ,
+                       void         *messagePtr,
+                       mpiMsgCategory_t category,
+                       bit16        opCode,
+                       bit8         responseQueue,
+                       bit8         hiPriority
+                       )
+{
+  mpiMsgHeader_t *msgHeader;
+  bit32          bc;
+  bit32          Header = 0;
+  bit32          hpriority = 0;
+
+  SA_DBG4(("Entering function:mpiMsgProduceOQ\n"));
+  SA_ASSERT(NULL != circularQ, "circularQ argument cannot be null");
+  SA_ASSERT(NULL != messagePtr, "messagePtr argument cannot be null");
+  SA_ASSERT(0 != circularQ->numElements, "The number of elements in this queue"
+            " is 0");
+  SA_ASSERT(MPI_MAX_OUTBOUND_QUEUES > responseQueue, "oQueue ID is wrong");
+
+  /* REB Start extra trace */
+  smTraceFuncEnter(hpDBG_VERY_LOUD, "2I");
+  /* REB End extra trace */
+
+  /* Obtains the address of the entire message buffer, including the header */
+  msgHeader = (mpiMsgHeader_t*)(((bit8*)messagePtr) - sizeof(mpiMsgHeader_t));
+  /* Read the BC from header, its stored in native endian format when message
+     was allocated */
+  /* intially */
+  SA_DBG4(("mpiMsgProduceOQ: msgHeader %p opcode %d pi/ci %d / %d\n", msgHeader, opCode, circularQ->producerIdx, circularQ->consumerIdx));
+  bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK);
+  SA_DBG6(("mpiMsgProduceOQ: msgHeader bc %d\n", bc));
+  if (circularQ->priority)
+    hpriority = 1;
+
+  /* Checks the message is in "allocated" state */
+  SA_ASSERT(0 != bc, "The message buffer is not in \"allocated\" state "
+                     "(bc == 0)");
+
+  Header = ((V_BIT << SHIFT31) | (hpriority << SHIFT30)  |
+            ((bc & BC_MASK) << SHIFT24) |
+            ((responseQueue & OBID_MASK) << SHIFT16) |
+            ((category  & CAT_MASK) << SHIFT12 ) | (opCode & OPCODE_MASK));
+  /* pre flush the IOMB cache line */
+  //ossaCachePreFlush(circularQ->agRoot,
+  //                  (void *)circularQ->memoryRegion.appHandle,
+  //                  (void *)msgHeader, circularQ->elementSize * bc);
+  OSSA_WRITE_LE_32(circularQ->agRoot, msgHeader, OSSA_OFFSET_OF(mpiMsgHeader_t,
+                   Header), Header);
+
+  /* flush the IOMB cache line */
+  //ossaCacheFlush(circularQ->agRoot, (void *)circularQ->memoryRegion.appHandle,
+  //               (void *)msgHeader, circularQ->elementSize * bc);
+
+  MPI_DEBUG_TRACE( circularQ->qNumber,
+                 ((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),
+                  MPI_DEBUG_TRACE_OBQ,
+                  (void *)msgHeader,
+                  circularQ->elementSize);
+
+  ossaLogIomb(circularQ->agRoot,
+              circularQ->qNumber,
+              TRUE,
+              (void *)msgHeader,
+              circularQ->elementSize);
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2I");
+  return AGSA_RC_SUCCESS;
+} /* mpiMsgProduceOQ */
+#endif
+

sys/dev/pms/RefTisa/sallsdk/spc/mpi.h

@@ -0,0 +1,476 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+
+/*******************************************************************************/
+/*! \file mpi.h
+ *  \brief The file defines the MPI constants and structures
+ *
+ * The file defines the MPI constants and structures
+ *
+ */
+/*******************************************************************************/
+
+#ifndef __MPI_H__
+#define __MPI_H__
+
+/*******************************************************************************/
+
+/*******************************************************************************/
+/* CONSTANTS                                                                   */
+/*******************************************************************************/
+/*******************************************************************************/
+#define MPI_QUEUE_PRIORITY_HIGHEST      0xFF  /**< Highest queue priority */
+#define MPI_QUEUE_PRIORITY_LOWEST       0x00  /**< Lowest queue priority */
+
+#define MPI_MAX_INBOUND_QUEUES          64     /**< Maximum number of inbound queues */
+#define MPI_MAX_OUTBOUND_QUEUES         64     /**< Maximum number of outbound queues */
+
+                                               /**< Max # of memory chunks supported */
+#define MPI_MAX_MEM_REGIONS             (MPI_MAX_INBOUND_QUEUES + MPI_MAX_OUTBOUND_QUEUES) + 4
+#define MPI_LOGSIZE                     4096  /**< default size */
+
+#define MPI_IB_NUM_MASK                 0x0000FFFF /**< Mask of Inbound Queue Number */
+#define MPI_OB_NUM_MASK                 0xFFFF0000 /**< Mask of Outbound Queue Number */
+#define MPI_OB_SHIFT                    16         /**< bits shift for outbound queue number */
+
+
+#define BAR0                            0x10
+#define BAR1                            0x14
+#define BAR2                            0x18
+#define BAR3                            0x1C
+#define BAR4                            0x20
+#define BAR5                            0x24
+
+/*******************************************************************************/
+/*******************************************************************************/
+/* ENUMERATIONS                                                                */
+/*******************************************************************************/
+
+/*******************************************************************************/
+/*******************************************************************************/
+/** \enum mpiMsgCategory_e,
+ *  \brief MPI message categories
+ */
+/*******************************************************************************/
+enum mpiMsgCategory_e
+{
+  MPI_CATEGORY_ETHERNET = 0,
+  MPI_CATEGORY_FC,
+  MPI_CATEGORY_SAS_SATA,
+  MPI_CATEGORY_SCSI
+};
+
+typedef enum mpiMsgCategory_e mpiMsgCategory_t;
+
+/*******************************************************************************/
+/*******************************************************************************/
+/* TYPES                                                                       */
+/*******************************************************************************/
+/*******************************************************************************/
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+/* DATA STRUCTURES                                                             */
+/*******************************************************************************/
+/*******************************************************************************/
+
+/*******************************************************************************/
+/** \struct mpiMem_s
+ *  \brief Structure that descibes memory regions
+ *
+ * The mpiMemoryDescriptor_t is used to describe the attributes for a memory
+ * region. Each element in the memory chunk has to be physically contiguous.
+ * Different elements in the memory chunk do not necessarily have to be
+ * contiguous to each other.
+ */
+/*******************************************************************************/
+struct mpiMem_s
+{
+  void*        virtPtr;       /**< Virtual pointer to the memory region */
+  void*        appHandle;     /**< Handle used for the application to free memory */
+  bit32        physAddrUpper; /**< Upper 32 bits of physical address */
+  bit32        physAddrLower; /**< Lower 32 bits of physical address */
+  bit32        totalLength;   /**< Total length in bytes allocated */
+  bit32        numElements;   /**< Number of elements */
+  bit32        elementSize;   /**< Size in bytes of an element */
+  bit32        alignment;     /**< Alignment in bytes needed. A value of one indicates */
+                              /**< no specific alignment requirement */
+  bit32        type;          /**< Memory type */
+  bit32        reserved;      /**< Reserved */
+};
+
+typedef struct mpiMem_s mpiMem_t;
+
+/*******************************************************************************/
+/** \struct mpiMemReq_s
+ *  \brief Describes MPI memory requirements
+ *
+ * The mpiMemRequirements_t  is used to specify the memory allocation requirement
+ * for the MPI. This is the data structure used in the mpiGetRequirements()
+ * and the mpiInitialize() function calls
+ */
+/*******************************************************************************/
+struct mpiMemReq_s
+{
+  bit32     count;                        /**< The number of element in the mpiMemory array */
+  mpiMem_t  region[MPI_MAX_MEM_REGIONS];  /**< Pointer to the array of structures that define memroy regions */
+};
+
+typedef struct mpiMemReq_s mpiMemReq_t;
+
+/*******************************************************************************/
+/** \struct mpiQCQueue_s
+ *  \brief Circular Queue descriptor
+ *
+ * This structure holds outbound circular queue attributes.
+ */
+/*******************************************************************************/
+struct mpiOCQueue_s
+{
+  bit32                     qNumber;      /**< this queue number */
+  bit32                     numElements;  /**< The total number of queue elements. A value 0 disables the queue */
+  bit32                     elementSize;  /**< The size of each queue element, in bytes */
+  bit32                     priority;     /**< The queue priority. Possible values for this field are */
+                                          /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */
+  bit32                     CIPCIBar;     /**< PCI Bar */
+  bit32                     CIPCIOffset;  /**< PCI Offset */
+  bit32                     DIntTOffset;  /**< Dynamic Interrupt Coalescing Timeout offset */
+  void*                     piPointer;    /**< pointer of PI (virtual address)*/
+  mpiMem_t                  memoryRegion; /**< Queue's memory region descriptor */
+  bit32                     producerIdx;  /**< Copy of the producer index */
+  bit32                     consumerIdx;  /**< Copy of the consumer index */
+  bit32                     pcibar;       /**< CPI Logical Bar Number */
+  agsaRoot_t                *agRoot;      /**< Pointer of LL Layer structure */
+};
+
+typedef struct mpiOCQueue_s mpiOCQueue_t;
+
+/*******************************************************************************/
+/** \struct mpiICQueue_s
+ *  \brief Circular Queue descriptor
+ *
+ * This structure holds inbound circular queue attributes.
+ */
+/*******************************************************************************/
+struct mpiICQueue_s
+{
+  bit32                     qNumber;      /**< this queue number */
+  bit32                     numElements;  /**< The total number of queue elements. A value 0 disables the queue */
+  bit32                     elementSize;  /**< The size of each queue element, in bytes */
+  bit32                     priority;     /**< The queue priority. Possible values for this field are */
+                                          /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */
+  bit32                     PIPCIBar;     /**< PCI Bar */
+  bit32                     PIPCIOffset;  /**< PCI Offset */
+  void*                     ciPointer;    /**< Pointer of CI (virtual Address) */
+  mpiMem_t                  memoryRegion; /**< Queue's memory region descriptor */
+  bit32                     producerIdx;  /**< Copy of the producer index */
+  bit32                     consumerIdx;  /**< Copy of the consumer index */
+#ifdef SA_FW_TEST_BUNCH_STARTS
+  bit32                     BunchStarts_QPending;     // un-started bunched IOs on queue
+  bit32                     BunchStarts_QPendingTick; // tick value when 1st IO is bunched 
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+  agsaRoot_t                *agRoot;      /**< Pointer of LL Layer structure */
+};
+
+typedef struct mpiICQueue_s mpiICQueue_t;
+
+struct mpiHostLLConfigDescriptor_s
+{
+  bit32 regDumpPCIBAR;
+  bit32 iQNPPD_HPPD_GEvent;                 /**< inbound Queue Process depth */
+        /* bit0-7   inbound normal priority process depth */
+        /* bit8-15  inbound high priority process depth */
+        /* bit16-23 OQ number to receive GENERAL_EVENT Notification */
+        /* bit24-31 reserved */
+  bit32 outboundHWEventPID0_3;              /**< outbound HW event for PortId 0 to 3 */
+        /* bit0-7   outbound queue number of SAS_HW event for PortId 0 */
+        /* bit8-15  outbound queue number of SAS_HW event for PortId 1 */
+        /* bit16-23 outbound queue number of SAS_HW event for PortId 2 */
+        /* bit24-31 outbound queue number of SAS_HW event for PortId 3 */
+  bit32 outboundHWEventPID4_7;              /**< outbound HW event for PortId 4 to 7 */
+        /* bit0-7   outbound queue number of SAS_HW event for PortId 4 */
+        /* bit8-15  outbound queue number of SAS_HW event for PortId 5 */
+        /* bit16-23 outbound queue number of SAS_HW event for PortId 6 */
+        /* bit24-31 outbound queue number of SAS_HW event for PortId 7 */
+  bit32 outboundNCQEventPID0_3;             /**< outbound NCQ event for PortId 0 to 3 */
+        /* bit0-7   outbound queue number of SATA_NCQ event for PortId 0 */
+        /* bit8-15  outbound queue number of SATA_NCQ event for PortId 1 */
+        /* bit16-23 outbound queue number of SATA_NCQ event for PortId 2 */
+        /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */
+  bit32 outboundNCQEventPID4_7;             /**< outbound NCQ event for PortId 4 to 7 */
+        /* bit0-7   outbound queue number of SATA_NCQ event for PortId 4 */
+        /* bit8-15  outbound queue number of SATA_NCQ event for PortId 5 */
+        /* bit16-23 outbound queue number of SATA_NCQ event for PortId 6 */
+        /* bit24-31 outbound queue number of SATA_NCQ event for PortId 7 */
+  bit32 outboundTargetITNexusEventPID0_3;   /**< outbound target ITNexus Event for PortId 0 to 3 */
+        /* bit0-7   outbound queue number of ITNexus event for PortId 0 */
+        /* bit8-15  outbound queue number of ITNexus event for PortId 1 */
+        /* bit16-23 outbound queue number of ITNexus event for PortId 2 */
+        /* bit24-31 outbound queue number of ITNexus event for PortId 3 */
+  bit32 outboundTargetITNexusEventPID4_7;   /**< outbound target ITNexus Event for PortId 4 to 7 */
+        /* bit0-7   outbound queue number of ITNexus event for PortId 4 */
+        /* bit8-15  outbound queue number of ITNexus event for PortId 5 */
+        /* bit16-23 outbound queue number of ITNexus event for PortId 6 */
+        /* bit24-31 outbound queue number of ITNexus event for PortId 7 */
+  bit32 outboundTargetSSPEventPID0_3;       /**< outbound target SSP event for PordId 0 to 3 */
+        /* bit0-7   outbound queue number of SSP event for PortId 0 */
+        /* bit8-15  outbound queue number of SSP event for PortId 1 */
+        /* bit16-23 outbound queue number of SSP event for PortId 2 */
+        /* bit24-31 outbound queue number of SSP event for PortId 3 */
+  bit32 outboundTargetSSPEventPID4_7;       /**< outbound target SSP event for PordId 4 to 7 */
+        /* bit0-7   outbound queue number of SSP event for PortId 4 */
+        /* bit8-15  outbound queue number of SSP event for PortId 5 */
+        /* bit16-23 outbound queue number of SSP event for PortId 6 */
+        /* bit24-31 outbound queue number of SSP event for PortId 7 */
+  bit32 ioAbortDelay;   /* was reserved */                 /**< io Abort delay MPI_TABLE_CHANGE */
+  bit32 custset;                          /**< custset */
+  bit32 upperEventLogAddress;               /**< Upper physical MSGU Event log address */
+  bit32 lowerEventLogAddress;               /**< Lower physical MSGU Event log address */
+  bit32 eventLogSize;                       /**< Size of MSGU Event log, 0 means log disable */
+  bit32 eventLogOption;                     /**< Option of MSGU Event log */
+        /* bit3-0 log severity, 0x0 Disable Logging */
+        /*                      0x1 Critical Error */
+        /*                      0x2 Minor Error    */
+        /*                      0x3 Warning        */
+        /*                      0x4 Information    */
+        /*                      0x5 Debugging      */
+        /*                      0x6 - 0xF Reserved */
+  bit32 upperIOPeventLogAddress;           /**< Upper physical IOP Event log address */
+  bit32 lowerIOPeventLogAddress;           /**< Lower physical IOP Event log address */
+  bit32 IOPeventLogSize;                   /**< Size of IOP Event log, 0 means log disable */
+  bit32 IOPeventLogOption;                 /**< Option of IOP Event log */
+        /* bit3-0 log severity, 0x0 Disable Logging */
+        /*                      0x1 Critical Error */
+        /*                      0x2 Minor Error    */
+        /*                      0x3 Warning        */
+        /*                      0x4 Information    */
+        /*                      0x5 Debugging      */
+        /*                      0x6 - 0xF Reserved */
+  bit32 FatalErrorInterrupt;               /**< Fatal Error Interrupt enable and vector */
+        /* bit0     Fatal Error Interrupt Enable   */
+        /* bit1     PI/CI Address                  */
+        /* bit5     enable or disable outbound coalesce   */
+        /* bit7-6  reserved */
+        /* bit15-8  Fatal Error Interrupt Vector   */
+        /* bit31-16 Reserved                       */
+  bit32 FatalErrorDumpOffset0;             /**< Fatal Error Register Dump Offset for MSGU */
+  bit32 FatalErrorDumpLength0;             /**< Fatal Error Register Dump Length for MSGU */
+  bit32 FatalErrorDumpOffset1;             /**< Fatal Error Register Dump Offset for IOP */
+  bit32 FatalErrorDumpLength1;             /**< Fatal Error Register Dump Length for IOP */
+  bit32 HDAModeFlags;                      /**< HDA Mode Flags */
+        /* bit1-0   Bootstrap pins */
+        /* bit2     Force HDA Mode bit */
+        /* bit3     HDA Firmware load method */
+  bit32 analogSetupTblOffset;              /**< Phy Calibration Table offset */
+        /* bit23-0  phy calib table offset */
+        /* bit31-24 entry size */
+  bit32 InterruptVecTblOffset;             /**< DW23 Interrupt Vector Table */
+        /* bit23-0  interrupt vector table offset */
+        /* bit31-24 entry size */
+  bit32 phyAttributeTblOffset;             /**< DW24 SAS Phy Attribute Table Offset */
+        /* bit23-0  phy attribute table offset */
+        /* bit31-24 entry size */
+  bit32 PortRecoveryTimerPortResetTimer;  /**< DW25 Port Recovery Timer and Port Reset Timer */
+  bit32 InterruptReassertionDelay;        /**< DW26 Interrupt Reassertion Delay 0:23 Reserved 24:31 */
+};
+
+typedef struct mpiHostLLConfigDescriptor_s mpiHostLLConfigDescriptor_t;
+
+/*******************************************************************************/
+/** \struct mpiInboundQueueDescriptor_s
+ *  \brief MPI inbound queue attributes
+ *
+ * The mpiInboundQueueDescriptor_t structure is used to describe an inbound queue
+ * attributes
+ */
+/*******************************************************************************/
+struct mpiInboundQueueDescriptor_s
+{
+  bit32                     numElements;     /**< The total number of queue elements. A value 0 disables the queue */
+  bit32                     elementSize;     /**< The size of each queue element, in bytes */
+  bit32                     priority;        /**< The queue priority. Possible values for this field are */
+                                              /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */
+  bit32                     PIPCIBar;        /**< PI PCIe Bar */
+  bit32                     PIOffset;        /**< PI PCI Bar Offset */
+  void*                     ciPointer;       /**< Pointer of CI (virtual Address) */
+};
+
+typedef struct mpiInboundQueueDescriptor_s mpiInboundQueueDescriptor_t;
+
+/*******************************************************************************/
+/** \struct mpiOutboundQueueDescriptor_s
+ *  \brief MPI outbound queue attributes
+ *
+ * The mpiOutboundQueueDescriptor_t structure is used to describe an outbound queue
+ * attributes
+ */
+/*******************************************************************************/
+struct mpiOutboundQueueDescriptor_s
+{
+  bit32                     numElements;        /**< The total number of queue elements. A value 0 disables the queue */
+  bit32                     elementSize;        /**< The size of each queue element, in bytes */
+  bit32                     interruptDelay;     /**< Delay in microseconds before the interrupt is asserted */
+                                                 /**< if the interrupt threshold has not been reached */
+  bit32                     interruptThreshold; /**< Number of interrupt events before the interrupt is asserted */
+                                                 /**< If set to 0, interrupts for this queue are disablec */
+  bit32                     interruptVector;    /**< Interrupt vector assigned to this queue */
+  bit32                     CIPCIBar;           /**< offset 0x14:PCI BAR for CI Offset */
+  bit32                     CIOffset;           /**< offset 0x18:Offset address for outbound queue CI */
+  bit32                     DIntTOffset;        /**< Dynamic Interrupt Coalescing Timeout offset */
+  bit32                     interruptEnable;    /**< Interrupt enable flag */
+  void*                     piPointer;          /**< pointer of PI (virtual address)*/
+};
+
+typedef struct mpiOutboundQueueDescriptor_s mpiOutboundQueueDescriptor_t;
+
+/*******************************************************************************/
+/** \struct mpiPhyCalibration_s
+ *  \brief MPI Phy Calibration Table
+ *
+ * The mpiPhyCalibration_s structure is used to set Phy Calibration
+ * attributes
+ */
+/*******************************************************************************/
+struct mpiPhyCalibration_s
+{
+  bit32   spaReg0;            /* transmitter per port configuration 1 SAS_SATA G1 */
+  bit32   spaReg1;            /* transmitter per port configuration 2 SAS_SATA G1*/
+  bit32   spaReg2;            /* transmitter per port configuration 3 SAS_SATA G1*/
+  bit32   spaReg3;            /* transmitter configuration 1 */
+  bit32   spaReg4;            /* reveiver per port configuration 1 SAS_SATA G1G2 */
+  bit32   spaReg5;            /* reveiver per port configuration 2 SAS_SATA G3 */
+  bit32   spaReg6;            /* reveiver per configuration 1 */
+  bit32   spaReg7;            /* reveiver per configuration 2 */
+  bit32   reserved[2];        /* reserved */
+};
+
+typedef struct mpiPhyCalibration_s mpiPhyCalibration_t;
+
+#define ANALOG_SETUP_ENTRY_NO              10
+#define ANALOG_SETUP_ENTRY_SIZE            10
+
+
+/*******************************************************************************/
+/** \struct mpiConfig_s
+ *  \brief MPI layer configuration parameters
+ *
+ * The mpiConfig_s structure is used as a parameter passed in
+ * mpiGetRequirements() and mpiInitialize() to describe the MPI software
+ * configuration
+ */
+/*******************************************************************************/
+struct mpiVConfig_s
+{
+  mpiHostLLConfigDescriptor_t  mainConfig;                              /**< main part of configuration table */
+  mpiInboundQueueDescriptor_t  inboundQueues[MPI_MAX_INBOUND_QUEUES];   /**< mpiQueueDescriptor structures that provide initialization */
+                                                                        /**< attributes for the inbound queues. The maximum number of */
+                                                                        /**< inbound queues is MPI_MAX_INBOUND_QUEUES */
+  mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */
+                                                                        /**< attributes for the outbound queues. The maximum number of */
+                                                                        /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */
+  agsaPhyAnalogSetupTable_t    phyAnalogConfig;
+  mpiInterruptVT_t             interruptVTable;
+  sasPhyAttribute_t            phyAttributeTable;
+  bit16   numInboundQueues;
+  bit16   numOutboundQueues;
+  bit16   maxNumInboundQueues;
+  bit16   maxNumOutboundQueues;
+  bit32   queueOption;
+};
+
+/*******************************************************************************/
+/** \struct mpiConfig_s
+ *  \brief MPI layer configuration parameters
+ *
+ * The mpiConfig_s structure is used as a parameter passed in
+ * mpiGetRequirements() and mpiInitialize() to describe the MPI software
+ * configuration
+ */
+/*******************************************************************************/
+struct mpiConfig_s
+{
+  mpiHostLLConfigDescriptor_t  mainConfig;                              /**< main part of configuration table */
+  mpiInboundQueueDescriptor_t  inboundQueues[MPI_MAX_INBOUND_QUEUES];   /**< mpiQueueDescriptor structures that provide initialization */
+                                                                        /**< attributes for the inbound queues. The maximum number of */
+                                                                        /**< inbound queues is MPI_MAX_INBOUND_QUEUES */
+  mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */
+                                                                        /**< attributes for the outbound queues. The maximum number of */
+                                                                        /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */
+  agsaPhyAnalogSetupTable_t    phyAnalogConfig;
+  bit16   numInboundQueues;
+  bit16   numOutboundQueues;
+  bit16   maxNumInboundQueues;
+  bit16   maxNumOutboundQueues;
+  bit32   queueOption;
+};
+
+typedef struct mpiConfig_s  mpiConfig_t;
+
+#define TX_PORT_CFG1_OFFSET                0x00
+#define TX_PORT_CFG2_OFFSET                0x04
+#define TX_PORT_CFG3_OFFSET                0x08
+#define TX_CFG_OFFSET                      0x0c
+#define RV_PORT_CFG1_OFFSET                0x10
+#define RV_PORT_CFG2_OFFSET                0x14
+#define RV_CFG1_OFFSET                     0x18
+#define RV_CFG2_OFFSET                     0x1c
+
+/*******************************************************************************/
+/*******************************************************************************/
+/* FUNCTIONS                                                                   */
+/*******************************************************************************/
+/*******************************************************************************/
+/*******************************************************************************/
+void      mpiRequirementsGet(mpiConfig_t *config, mpiMemReq_t *memoryRequirement);
+FORCEINLINE bit32 mpiMsgFreeGet(mpiICQueue_t *circularQ, bit16 messageSize, void** messagePtr);
+FORCEINLINE bit32 mpiMsgProduce(mpiICQueue_t *circularQ, void* messagePtr,
+                        mpiMsgCategory_t category, bit16 opCode,
+                        bit8 responseQueue, bit8 hiPriority);
+#ifdef LOOPBACK_MPI
+GLOBAL bit32 mpiMsgProduceOQ(mpiOCQueue_t *circularQ, void *messagePtr,
+                             mpiMsgCategory_t category, bit16 opCode,
+                             bit8 responseQueue, bit8 hiPriority);
+GLOBAL bit32 mpiMsgFreeGetOQ(mpiOCQueue_t *circularQ, bit16 messageSize,
+                             void** messagePtr);
+#endif
+
+#ifdef FAST_IO_TEST
+bit32     mpiMsgPrepare(mpiICQueue_t *circularQ, void* messagePtr,
+                        mpiMsgCategory_t category, bit16 opCode,
+                        bit8 responseQueue, bit8 hiPriority);
+
+bit32     mpiMsgProduceSend(mpiICQueue_t *circularQ, void* messagePtr,
+                        mpiMsgCategory_t category, bit16 opCode,
+                        bit8 responseQueue, bit8 hiPriority, int sendFl);
+GLOBAL void mpiIBQMsgSend(mpiICQueue_t *circularQ);
+#define INQ(queueNum) (bit8)(queueNum & MPI_IB_NUM_MASK)
+#define OUQ(queueNum) (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT)
+#endif
+
+FORCEINLINE bit32 mpiMsgConsume(mpiOCQueue_t *circularQ, void** messagePtr1, mpiMsgCategory_t *pCategory, bit16* pOpCode, bit8 *pBC);
+FORCEINLINE bit32 mpiMsgFreeSet(mpiOCQueue_t *circularQ, void* messagePtr1, bit8 bc);
+
+#endif /* __MPI_H__ */
+

sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.c

@@ -0,0 +1,909 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+
+/*******************************************************************************/
+/*! \file mpidebug.c
+ *  \brief The file is a MPI Libraries to implement the MPI debug and trace functions
+ *
+ * The file implements the MPI functions.
+ *
+ */
+/*******************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+#ifdef MPI_DEBUG_TRACE_ENABLE /* enable with CCBUILD_MPI_TRACE*/
+
+/*******************************************************************************/
+
+#ifdef OSLAYER_USE_HI_RES_TIMER
+unsigned __int64
+GetHiResTimeStamp(void);
+#endif /* OSLAYER_USE_HI_RES_TIMER */
+/*******************************************************************************/
+/*******************************************************************************/
+/* FUNCTIONS                                                                   */
+/*******************************************************************************/
+mpiDebugObTrace_t obTraceData;
+mpiDebugIbTrace_t ibTraceData;
+
+void mpiTraceInit(void)
+{
+
+  SA_DBG1(("mpiTraceInit:obTraceData @ %p\n",&obTraceData ));
+  SA_DBG1(("mpiTraceInit:ibTraceData @ %p\n",&ibTraceData ));
+  SA_DBG1(("mpiTraceInit: num enties %d Ib Iomb size %d Ob Iomb size %d\n",
+               MPI_DEBUG_TRACE_BUFFER_MAX,
+               MPI_DEBUG_TRACE_IB_IOMB_SIZE,
+               MPI_DEBUG_TRACE_OB_IOMB_SIZE ));
+
+  si_memset(&obTraceData, 0, sizeof(obTraceData));
+  si_memset(&ibTraceData, 0, sizeof(ibTraceData));
+}
+
+void mpiTraceAdd( bit32 q,bit32 pici,bit32 ib, void *iomb, bit32 numBytes)
+{
+  bit32                  curIdx;
+  mpiDebugIbTraceEntry_t *curIbTrace;
+  mpiDebugObTraceEntry_t *curObTrace;
+
+  mpiDebugIbTrace_t * ibTrace = &ibTraceData;
+  mpiDebugObTrace_t * obTrace = &obTraceData;
+
+  if (ib)
+  {
+    if(ibTrace->Idx >= MPI_DEBUG_TRACE_BUFFER_MAX)
+    {
+      ibTrace->Idx = 0;
+    }
+    curIdx = ibTrace->Idx;
+
+    curIbTrace = &ibTrace->Data[curIdx];
+    curIbTrace->pEntry =  iomb;
+    curIbTrace->QNum = q;
+    curIbTrace->pici = pici;
+#ifdef OSLAYER_USE_HI_RES_TIMER
+#ifdef SA_64BIT_TIMESTAMP
+  curIbTrace->Time = ossaTimeStamp64(agNULL);
+#else /* SA_64BIT_TIMESTAMP */
+  curIbTrace->Time = ossaTimeStamp(agNULL);
+#endif /* SA_64BIT_TIMESTAMP */
+#else /* OSLAYER_USE_HI_RES_TIMER */
+  curIbTrace->Time = 0;
+#endif
+    si_memcpy(curIbTrace->Iomb, iomb, MIN(numBytes, MPI_DEBUG_TRACE_IB_IOMB_SIZE));
+    ibTrace->Idx++;
+  }
+  else
+  {
+    if(obTrace->Idx >= MPI_DEBUG_TRACE_BUFFER_MAX )
+    {
+      obTrace->Idx = 0;
+    }
+    curIdx = obTrace->Idx;
+    curObTrace = &obTrace->Data[curIdx];
+    curObTrace->pEntry =  iomb;
+    curObTrace->QNum = q;
+    curObTrace->pici = pici;
+#ifdef OSLAYER_USE_HI_RES_TIMER
+#ifdef SA_64BIT_TIMESTAMP
+    curObTrace->Time = ossaTimeStamp64(agNULL);
+#else /* SA_64BIT_TIMESTAMP */
+    curObTrace->Time = ossaTimeStamp(agNULL);
+#endif /* SA_64BIT_TIMESTAMP */
+#else /* OSLAYER_USE_HI_RES_TIMER */
+    curObTrace->Time = 0;
+#endif
+    si_memcpy(curObTrace->Iomb, iomb, MIN(numBytes, MPI_DEBUG_TRACE_OB_IOMB_SIZE));
+    obTrace->Idx++;
+  }
+
+
+  return;
+}
+
+#endif /* MPI_DEBUG_TRACE_ENABLE */
+
+
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+
+/**
+ * fiEnableTracing
+ *
+ *    This fucntion is called to initialize tracing of FC layer.
+ *
+ */
+void siEnableTracing (agsaRoot_t  *agRoot)
+{
+
+  agsaLLRoot_t      *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaSwConfig_t    *swC  = &saRoot->swConfig;
+  bit32 count;
+
+  OS_ASSERT(saRoot != NULL, "");
+
+  if( saRoot->TraceBlockReInit != 0)
+  {
+    return;
+  }
+
+
+  /* Initialize tracing first */
+
+  for (count = 0; count < 10; count++)
+  {
+      saRoot->traceBuffLookup[count] = (bit8)('0' + count);
+  }
+  for (count = 0; count < 6; count++)
+  {
+      saRoot->traceBuffLookup[(bitptr)count + 10] = (bit8)('a' + count);
+  }
+
+
+  saRoot->TraceDestination = swC->TraceDestination;
+  saRoot->TraceMask = swC->TraceMask;
+  saRoot->CurrentTraceIndexWrapCount = 0;
+  saRoot->CurrentTraceIndex = 0;
+  saRoot->TraceBlockReInit = 1;
+
+
+  SA_DBG1(("siEnableTracing: \n" ));
+
+  SA_DBG1 (("      length       = %08x\n", saRoot->TraceBufferLength ));
+  SA_DBG1 (("      virt         = %p\n",   saRoot->TraceBuffer ));
+  SA_DBG1 (("    traceMask        = %08x @ %p\n", saRoot->TraceMask, &saRoot->TraceMask));
+  SA_DBG1 (("    last trace entry @ %p\n", &saRoot->CurrentTraceIndex));
+  SA_DBG1 (("    TraceWrapAround  = %x\n", saRoot->TraceMask & hpDBG_TraceBufferWrapAround ? 1 : 0));
+  SA_DBG1 (("    da %p l %x\n",saRoot->TraceBuffer ,saRoot->TraceBufferLength));
+
+#ifdef SA_PRINTOUT_IN_WINDBG
+#ifndef DBG
+  DbgPrint("siTraceEnable: \n" );
+
+  DbgPrint("      length       = %08x\n", saRoot->TraceBufferLength );
+  DbgPrint("      virt         = %p\n",   saRoot->TraceBuffer );
+  DbgPrint("    last trace entry @ %p\n", &saRoot->CurrentTraceIndex);
+  DbgPrint("    traceMask      = %08x @ %p\n", saRoot->TraceMask, &saRoot->TraceMask);
+  DbgPrint("    da %p l %x\n",saRoot->TraceBuffer ,saRoot->TraceBufferLength);
+#endif /* DBG  */
+#endif /* SA_PRINTOUT_IN_WINDBG  */
+  /*
+  ** Init trace buffer with all spaces
+  */
+  for (count = 0; count < saRoot->TraceBufferLength; count++)
+  {
+      saRoot->TraceBuffer[count] = (bit8)' ';
+  }
+
+}
+
+
+
+/**
+ * IF_DO_TRACE
+ *
+ * PURPOSE:     convenience macro for the "to output or not to output" logic
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ */
+
+#define IF_DO_TRACE                                     \
+  if ( (saRoot != NULL) &&                              \
+       (saRoot->TraceDestination & siTraceDestMask) &&  \
+       (mask & saRoot->TraceMask) )                     \
+
+
+/* #define TRACE_ENTER_LOCK  ossaSingleThreadedEnter(agRoot, LL_TRACE_LOCK); */
+/* #define TRACE_LEAVE_LOCK  ossaSingleThreadedLeave(agRoot, LL_TRACE_LOCK); */
+#define TRACE_ENTER_LOCK
+#define TRACE_LEAVE_LOCK
+/**
+ * BUFFER_WRAP_CHECK
+ *
+ * PURPOSE: Checks if the tracing buffer tracing index is too high.  If it is,
+ *          the buffer index gets reset to 0 or tracing stops..
+ */
+#define BUFFER_WRAP_CHECK                                           \
+    if( (saRoot->CurrentTraceIndex + TMP_TRACE_BUFF_SIZE)               \
+                           >= saRoot->TraceBufferLength )               \
+    {                                                                   \
+        /* Trace wrap-Around is enabled.  */                            \
+        if( saRoot->TraceMask & hpDBG_TraceBufferWrapAround )           \
+        {                                                               \
+            /* Fill the end of the buffer with spaces */                \
+            for( i = saRoot->CurrentTraceIndex;                         \
+                     i < saRoot->TraceBufferLength; i++ )               \
+            {                                                           \
+                saRoot->TraceBuffer[i] = (bit8)' ';                     \
+            }                                                           \
+            /* Wrap the current trace index back to 0.. */              \
+            saRoot->CurrentTraceIndex = 0;                              \
+            saRoot->CurrentTraceIndexWrapCount++;                       \
+        }                                                               \
+        else                                                            \
+        {                                                               \
+            /* Don't do anything -- trace buffer is filled up */        \
+            return;                                                     \
+        }                                                               \
+    }
+
+/**
+ * LOCAL_OS_LOG_DEBUG_STRING
+ *
+ * PURPOSE:     protects against a change in the api for this function
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ * Laurent Chavey   03/09/00   - changed cast of 3rd parameter to (char *)
+ */
+    #define LOCAL_OS_LOG_DEBUG_STRING(H,S)  \
+            osLogDebugString(H,hpDBG_ALWAYS,(char *)(S))
+
+/******************************************************************************
+*******************************************************************************
+**
+** copyHex
+**
+** PURPOSE:  Copies a hex version of a bit32 into a bit8 buffer
+**
+*******************************************************************************
+******************************************************************************/
+#define copyHex(bit32Val, bitSize)                                     \
+{                                                                      \
+  bit32 nibbleLen = bitSize / 4;                                       \
+  bit32 scratch = 0;                                                   \
+  for( i = 0; i < nibbleLen; i++ )                                     \
+  {                                                                    \
+    bPtr[pos++] =                                                      \
+        saRoot->traceBuffLookup[0xf & (bit32Val >> ((bitSize - 4) - (i << 2)))];  \
+    i++;                                                               \
+    bPtr[pos++] =                                                      \
+    saRoot->traceBuffLookup[0xf & (bit32Val >> ((bitSize - 4) - (i << 2)))]; \
+    /* Skip leading 0-s to save memory buffer space */                 \
+    if( !scratch                                                       \
+          && (bPtr[pos-2] == '0')                                      \
+          && (bPtr[pos-1] == '0') )                                    \
+    {                                                                  \
+      pos -= 2;                                                        \
+      continue;                                                        \
+    }                                                                  \
+    else                                                               \
+    {                                                                  \
+      scratch = 1;                                                     \
+    }                                                                  \
+  }                                                                    \
+  if( scratch == 0 )                                                   \
+  {                                                                    \
+    /* The value is 0 and nothing got put in the buffer.  Do       */  \
+    /* print at least two zeros.                                   */  \
+    bPtr[pos++] = '0';                                                 \
+    bPtr[pos++] = '0';                                                 \
+  }                                                                    \
+}
+
+
+/**
+ * TRACE_OTHER_DEST
+ *
+ * PURPOSE:  Check if any other destinations are enabled.  If yes, use them
+ *           for debug log.
+ */
+#define TRACE_OTHER_DEST                                                \
+    {                                                                   \
+    bit32 bitptrscratch;                                                \
+    if( saRoot->TraceDestination & smTraceDestDebugger )                \
+    {                                                                   \
+        bPtr[pos++] = (bit8)'\n';                                       \
+        bPtr[pos++] = (bit8)0;                                          \
+        LOCAL_OS_LOG_DEBUG_STRING(hpRoot, (char *)bPtr);                \
+    }                                                                   \
+    if( saRoot->TraceDestination & smTraceDestRegister )                \
+    {                                                                   \
+        while( (pos & 0x3) != 0x3 )                                     \
+        {                                                               \
+            bPtr[pos++] = (bit8)' ';                                    \
+        }                                                               \
+        bPtr[pos] = ' ';                                                \
+        for( i = 0; i < pos; i = i + 4 )                                \
+        {                                                               \
+            bitptrscratch =  bPtr[i+0];                                 \
+            bitptrscratch <<= 8;                                        \
+            bitptrscratch |= bPtr[i+1];                                 \
+            bitptrscratch <<= 8;                                        \
+            bitptrscratch |= bPtr[i+2];                                 \
+            bitptrscratch <<= 8;                                        \
+            bitptrscratch |= bPtr[i+3];                                 \
+            osChipRegWrite(hpRoot,                                      \
+                 FC_rFMReceivedALPA, (bit32)bitptrscratch );            \
+        }                                                               \
+    }                                                                   \
+    }
+
+
+
+/**
+ * siGetCurrentTraceIndex()
+ *
+ * PURPOSE:     Returns the current tracing index ( if tracing buffer is
+ *              used ).
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ * Tom Nalepa       02/27/03
+ *
+ * @param hpRoot
+ *
+ * @return
+ */
+GLOBAL bit32 siGetCurrentTraceIndex(agsaRoot_t  *agRoot)
+{
+    agsaLLRoot_t      *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+    return(saRoot->CurrentTraceIndex);
+}
+
+
+
+
+/**
+ * siResetTraceBuffer
+ *
+ * PURPOSE:     Sets saRoot->CurrentTraceIndex to 0.
+ *
+ * @param hpRoot
+ *
+ * @return
+ */
+GLOBAL void siResetTraceBuffer(agsaRoot_t  *agRoot)
+{
+    bit32 count;
+    agsaLLRoot_t      *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+    saRoot->CurrentTraceIndex = 0;
+
+    for ( count = 0; count < saRoot->TraceBufferLength; count++ )
+    {
+        saRoot->TraceBuffer[count] = (bit8)' ';
+    }
+}
+
+
+/**
+ * siTraceFuncEnter
+ *
+ * PURPOSE:     Format a function entry trace and post it to the appropriate
+ *              destination.
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ * siTraceFuncEnter  :    _[Xxxxx_
+ *                 fileid---^  ^------funcid
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ *
+ * @param hpRoot
+ * @param mask
+ * @param fileid
+ * @param funcid
+ *
+ * @return
+ */
+
+#define TMP_TRACE_BUFF_SIZE 32
+
+
+GLOBAL void siTraceFuncEnter( agsaRoot_t  *agRoot,
+                             bit32        mask,
+                             bit32        fileid,
+                             char       * funcid)
+{
+agsaLLRoot_t      *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+    bitptr         i;
+    bit8           tmpB[TMP_TRACE_BUFF_SIZE];
+    bit8          *bPtr;
+    bit8           pos = 0;
+
+    IF_DO_TRACE
+    {
+      TRACE_ENTER_LOCK
+      if ( saRoot->TraceDestination & smTraceDestBuffer )
+      {
+        BUFFER_WRAP_CHECK
+        bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex];
+      }
+      else
+      {
+        bPtr = tmpB;
+      }
+      bPtr[pos++] = (bit8)'[';
+
+#ifndef FC_DO_NOT_INCLUDE_FILE_NAME_TAGS_IN_ENTER_EXIT_TRACE
+        bPtr[pos++] = (bit8)fileid;
+#endif
+
+        for ( i=0; i<4; i++ )
+        {
+            if ( funcid[i] == 0 )
+            {
+                break;
+            }
+            bPtr[pos++] = (bit8)funcid[i];
+        }
+        bPtr[pos++] = ' ';
+        if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE )
+        {
+            bPtr[pos++] = '\r';
+            bPtr[pos++] = '\n';
+            saRoot->traceLineFeedCnt = 0;
+        }
+        saRoot->CurrentTraceIndex += pos;
+//        TRACE_OTHER_DEST
+    TRACE_LEAVE_LOCK
+
+    }
+    return;
+}
+
+
+/**
+ * siTraceFuncExit
+ *
+ * PURPOSE:     Format a function exit trace and post it to the appropriate
+ *              destination.
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ * siTraceFuncExit         _Xxxxx]_
+ *                 fileid---^  ^------funcid
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ *
+ * @param hpRoot
+ * @param mask
+ * @param fileid
+ * @param funcid
+ * @param exitId
+ *
+ * @return
+ */
+GLOBAL void siTraceFuncExit(   agsaRoot_t  *agRoot,  bit32   mask, char  fileid, char  * funcid, char  exitId )
+{
+    bitptr         i;
+    bit8           tmpB[TMP_TRACE_BUFF_SIZE];
+    bit8          *bPtr;
+    bit8           pos = 0;
+
+    agsaLLRoot_t      *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+
+    IF_DO_TRACE
+    {
+      TRACE_ENTER_LOCK
+      if ( saRoot->TraceDestination & smTraceDestBuffer )
+      {
+        BUFFER_WRAP_CHECK
+        bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex];
+      }
+      else
+      {
+        bPtr = tmpB;
+      }
+
+#ifndef FC_DO_NOT_INCLUDE_FILE_NAME_TAGS_IN_ENTER_EXIT_TRACE
+        bPtr[pos++] = (bit8)fileid;
+#endif
+
+        for ( i=0; i<4; i++ )
+        {
+            if ( funcid[i] == 0 )
+            {
+                break;
+            }
+            bPtr[pos++] = (bit8)funcid[i];
+        }
+        bPtr[pos++] = (bit8)exitId;
+        bPtr[pos++] = (bit8)']';
+        bPtr[pos++] = (bit8)' ';
+        if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE )
+        {
+            bPtr[pos++] = '\r';
+            bPtr[pos++] = '\n';
+            saRoot->traceLineFeedCnt = 0;
+        }
+        saRoot->CurrentTraceIndex += pos;
+//        TRACE_OTHER_DEST
+    TRACE_LEAVE_LOCK
+    }
+    return;
+}
+
+/**
+ * siTraceListRemove
+ *
+ * PURPOSE:     Adds a trace tag for an exchange that is removed from a list
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ * Tom Nalepa       12/16/02   Initial Developmet
+ *
+ * @param hpRoot
+ * @param mask
+ * @param listId
+ * @param exchangeId
+ *
+ * @return
+ */
+GLOBAL void siTraceListRemove(agsaRoot_t  *agRoot,
+                              bit32        mask,
+                              char         listId,
+                              bitptr       exchangeId)
+{
+    agsaLLRoot_t      *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+    bitptr         i;
+    bit8           tmpB[TMP_TRACE_BUFF_SIZE];
+    bit8          *bPtr;
+    bit8           pos = 0;
+
+    IF_DO_TRACE
+    {
+     TRACE_ENTER_LOCK
+        if ( saRoot->TraceDestination & smTraceDestBuffer )
+        {
+            BUFFER_WRAP_CHECK
+            bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex];
+        }
+        else
+        {
+            bPtr = tmpB;
+        }
+        bPtr[pos++] = (bit8)'<';
+        bPtr[pos++] = (bit8)listId;
+        copyHex(exchangeId, 32);
+        bPtr[pos++] = (bit8)' ';
+        if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE )
+        {
+            bPtr[pos++] = '\r';
+            bPtr[pos++] = '\n';
+            saRoot->traceLineFeedCnt = 0;
+        }
+        saRoot->CurrentTraceIndex += pos;
+//        TRACE_OTHER_DEST
+    TRACE_LEAVE_LOCK
+    }
+    return;
+}
+
+/**
+ * siTraceListAdd
+ *
+ * PURPOSE:     Adds a trace tag for an exchange that is added to a list
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ * Tom Nalepa       12/16/02   Initial Developmet
+ *
+ * @param hpRoot
+ * @param mask
+ * @param listId
+ * @param exchangeId
+ *
+ * @return
+ */
+GLOBAL void siTraceListAdd(agsaRoot_t      *agRoot,
+                           bit32        mask,
+                           char         listId,
+                           bitptr       exchangeId)
+{
+
+  agsaLLRoot_t          *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+
+    bitptr         i;
+    bit8           tmpB[TMP_TRACE_BUFF_SIZE];
+    bit8          *bPtr;
+    bit8           pos = 0;
+
+    IF_DO_TRACE
+    {
+        if ( saRoot->TraceDestination & smTraceDestBuffer )
+        {
+            BUFFER_WRAP_CHECK
+            bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex];
+        }
+        else
+        {
+            bPtr = tmpB;
+        }
+        bPtr[pos++] = (bit8)'>';
+        bPtr[pos++] = (bit8)listId;
+        copyHex(exchangeId, 32);
+        bPtr[pos++] = (bit8)' ';
+        if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE )
+        {
+            bPtr[pos++] = '\r';
+            bPtr[pos++] = '\n';
+            saRoot->traceLineFeedCnt = 0;
+        }
+        saRoot->CurrentTraceIndex += pos;
+//        TRACE_OTHER_DEST
+    }
+    return;
+}
+
+/**
+ * siTrace64
+ *
+ * PURPOSE:     Format a function parameter trace and post it to the appropriate
+ *              destination.
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ * siTrace : index is 0 for return value, 1 for first parm after "("
+ *           produces:   _nn" XXXXXXXXXX
+ *           index-----^    value--^
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ *
+ * @param hpRoot
+ * @param mask
+ * @param uId
+ * @param value
+ *
+ * @return
+ */
+GLOBAL void siTrace64(agsaRoot_t      *agRoot,
+                      bit32        mask,
+                      char       * uId,
+                      bit64        value,
+                      bit32        dataSizeInBits)
+{
+
+    agsaLLRoot_t  *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+    bitptr         i;
+    bit8           tmpB[TMP_TRACE_BUFF_SIZE];
+    bit8          *bPtr;
+    bit8           pos = 0;
+
+    IF_DO_TRACE
+    {
+        if ( saRoot->TraceDestination & smTraceDestBuffer )
+        {
+            BUFFER_WRAP_CHECK
+            bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex];
+        }
+        else
+        {
+            bPtr = tmpB;
+        }
+        bPtr[pos++] = (bit8)'"';
+        bPtr[pos++] = (bit8)uId[0];
+        bPtr[pos++] = (bit8)uId[1];
+        bPtr[pos++] = (bit8)':';
+        copyHex(value, dataSizeInBits);
+        bPtr[pos++] = (bit8)' ';
+        if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE )
+        {
+            bPtr[pos++] = '\r';
+            bPtr[pos++] = '\n';
+            saRoot->traceLineFeedCnt = 0;
+        }
+        saRoot->CurrentTraceIndex += pos;
+//        TRACE_OTHER_DEST
+    }
+    return;
+}
+
+
+
+/**
+ * siTrace
+ *
+ * PURPOSE:     Format a function parameter trace and post it to the appropriate
+ *              destination.
+ *
+ * PARAMETERS:
+ *
+ * CALLS:
+ *
+ * SIDE EFFECTS & CAVEATS:
+ *
+ * ALGORITHM:
+ *
+ * fiTrace : index is 0 for return value, 1 for first parm after "("
+ *           produces:   _nn" XXXXXXXXXX
+ *           index-----^    value--^
+ *
+ *
+ *     MODIFICATION HISTORY     ***********************
+ *
+ * ENGINEER NAME      DATE     DESCRIPTION
+ * -------------    --------   -----------
+ *
+ * @param hpRoot
+ * @param mask
+ * @param uId
+ * @param value
+ *
+ * @return
+ */
+GLOBAL void siTrace( agsaRoot_t      *agRoot,
+                    bit32        mask,
+                    char       * uId,
+                    bit32        value,
+                    bit32        dataSizeInBits)
+{
+
+   agsaLLRoot_t   *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+
+    bitptr         i;
+    bit8           tmpB[TMP_TRACE_BUFF_SIZE];
+    bit8          *bPtr;
+    bit8           pos = 0;
+
+    IF_DO_TRACE
+    {
+        if ( saRoot->TraceDestination & smTraceDestBuffer )
+        {
+            BUFFER_WRAP_CHECK
+            bPtr = &saRoot->TraceBuffer[saRoot->CurrentTraceIndex];
+        }
+        else
+        {
+            bPtr = tmpB;
+        }
+        bPtr[pos++] = (bit8)'"';
+        bPtr[pos++] = (bit8)uId[0];
+        bPtr[pos++] = (bit8)uId[1];
+        bPtr[pos++] = (bit8)':';
+        copyHex(value, dataSizeInBits);
+        bPtr[pos++] = (bit8)' ';
+        if ( saRoot->traceLineFeedCnt > FC_TRACE_LINE_SIZE )
+        {
+            bPtr[pos++] = '\r';
+            bPtr[pos++] = '\n';
+            saRoot->traceLineFeedCnt = 0;
+        }
+        saRoot->CurrentTraceIndex += pos;
+//        TRACE_OTHER_DEST
+    }
+    return;
+}
+
+
+/*Set Wrap 0 for Wrapping non zero stops when full  */
+
+
+GLOBAL void siTraceGetInfo(agsaRoot_t  *agRoot, hpTraceBufferParms_t * pBParms)
+{
+    agsaLLRoot_t  *saRoot = (agsaLLRoot_t *)agRoot->sdkData;
+
+    pBParms->TraceCompiled  =  TRUE;
+
+    pBParms->TraceWrap                  = saRoot->TraceMask & 0x80000000;
+    pBParms->CurrentTraceIndexWrapCount = saRoot->CurrentTraceIndexWrapCount;
+    pBParms->BufferSize                 = saRoot->TraceBufferLength;
+    pBParms->CurrentIndex               = saRoot->CurrentTraceIndex;
+    pBParms->pTrace                     = saRoot->TraceBuffer;
+    pBParms->pTraceIndexWrapCount       = &saRoot->CurrentTraceIndexWrapCount;
+    pBParms->pTraceMask                 = &saRoot->TraceMask;
+    pBParms->pCurrentTraceIndex         = &saRoot->CurrentTraceIndex;
+}
+/**/
+
+GLOBAL void siTraceSetMask(agsaRoot_t  *agRoot, bit32 TraceMask  )
+{
+    agsaLLRoot_t  *saRoot = (agsaLLRoot_t *)agRoot->sdkData;
+    saRoot->TraceMask = TraceMask;
+}
+
+
+
+#endif
+
+

sys/dev/pms/RefTisa/sallsdk/spc/mpidebug.h

@@ -0,0 +1,283 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+
+/*******************************************************************************/
+/*! \file mpidebug.h
+ *  \brief The file defines the debug constants and structures
+ *
+ */
+/*******************************************************************************/
+
+#ifndef __MPIDEBUG_H__
+#define __MPIDEBUG_H__
+
+/*******************************************************************************/
+#define MPI_DEBUG_TRACE_BUFFER_MAX  1024
+#define MPI_DEBUG_TRACE_OB_IOMB_SIZE   128 /* 64 */
+#define MPI_DEBUG_TRACE_IB_IOMB_SIZE   128 /* 64 */
+#define MPI_DEBUG_TRACE_IBQ   1
+#define MPI_DEBUG_TRACE_OBQ   0
+#define MPI_DEBUG_TRACE_QNUM_ERROR   100 /* Added to Qnumber to indicate error */
+
+typedef struct mpiObDebugTraceEntry_s
+{
+  bit64       Time;
+  bit32       QNum;
+  bit32       pici;
+  void *      pEntry;
+  bit32       Iomb[MPI_DEBUG_TRACE_OB_IOMB_SIZE/4];
+} mpiDebugObTraceEntry_t;
+
+typedef struct mpiIbDebugTraceEntry_s
+{
+  bit64       Time;
+  bit32       QNum;
+  bit32       pici;
+  void *      pEntry;
+  bit32       Iomb[MPI_DEBUG_TRACE_IB_IOMB_SIZE/4];
+} mpiDebugIbTraceEntry_t;
+
+typedef struct mpiIbDebugTrace_s
+{
+  bit32                 Idx;
+  bit32                 Pad;
+  mpiDebugIbTraceEntry_t  Data[MPI_DEBUG_TRACE_BUFFER_MAX];
+} mpiDebugIbTrace_t;
+
+typedef struct mpiObDebugTrace_s
+{
+  bit32                 Idx;
+  bit32                 Pad;
+  mpiDebugObTraceEntry_t  Data[MPI_DEBUG_TRACE_BUFFER_MAX];
+} mpiDebugObTrace_t;
+
+void mpiTraceInit(void);
+void mpiTraceAdd(bit32 q,bit32 pici,bit32 ib, void *iomb, bit32 numBytes);
+
+#endif /* __MPIDEBUG_H__ */
+
+
+
+
+/********************************************************************
+**  File that contains debug-specific APIs ( driver tracing etc )
+*********************************************************************/
+
+#ifndef __SPCDEBUG_H__
+#define __SPCDEBUG_H__
+
+
+/*
+** console and trace levels
+*/
+
+#define  hpDBG_ALWAYS     0x0000ffff
+#define  hpDBG_IOMB       0x00000040
+#define  hpDBG_REGISTERS  0x00000020
+#define  hpDBG_TICK_INT   0x00000010
+#define  hpDBG_SCREAM     0x00000008
+#define  hpDBG_VERY_LOUD  0x00000004
+#define  hpDBG_LOUD       0x00000002
+#define  hpDBG_ERROR      0x00000001
+#define  hpDBG_NEVER      0x00000000
+
+#define smTraceDestBuffer    0x00000001
+#define smTraceDestRegister  0x00000002
+#define smTraceDestDebugger  0x00000004
+
+
+#define siTraceDestMask     (smTraceDestBuffer    |  \
+                             smTraceDestRegister  |  \
+                             smTraceDestDebugger)
+
+/* Trace buffer will continuously  */
+/* trace and wrap-around on itself */
+/* when it reaches the end         */
+#define hpDBG_TraceBufferWrapAround   0x80000000
+/* This features enables logging of trace time       */
+/* stamps.  Only certain key routines use this       */
+/* feature because it tends to clog up the trace     */
+/* buffer.                                           */
+#define hpDBG_TraceBufferUseTimeStamp 0x40000000
+/* This features enables logging of trace sequential */
+/* stamps.  Only certain key routines use this       */
+/* feature because it tends to clog up the trace     */
+/* buffer.                                           */
+#define hpDBG_TraceBufferUseSequenceStamp 0x20000000
+
+/* Trace IDs of various state machines */
+#define fiTraceSmChip   'C'
+#define fiTraceSmPort   'P'
+#define fiTraceSmLogin  'L'
+#define fiTraceSmXchg   'X'
+#define fiTraceSmFabr   'F'
+#define fiTraceDiscFab  'D'
+#define fiTraceDiscLoop 'M'
+#define fiTraceFc2      'A'
+#define fiTraceTgtState 'S'
+#define fiTraceIniState 'I'
+
+/* Trace IDs of various queues  */
+#define fiSfsFreeList   'Z'
+#define fiSestFreeList  'W'
+#define fiOsSfsFreeList 'G'
+#define fiLgnFreeList   'K'
+#define fiPortalFreeList  'l'
+#define fiBusyList      'N'
+#define fiOsSfsAllocList     'B'
+#define fiTimerList         'V'
+#define fiSfsWaitForRspList 'I'
+#define fiLgnBusyList   'J'
+#define fiPortalBusyList  'g'
+#define fiWait4ErqList  'o'
+#define fiXchgAbortList   'U'
+#define fiXchgWaitList 'b'
+
+/* not used right now */
+#define fiSfsDeferFreeList  'q'
+#define fiDeferBusyList     'm'
+#define fiInvalidList   'X'
+#define fiInvalidatedList   'a'
+#define fiTmpXchList    'n'
+
+#define TMP_TRACE_BUFF_SIZE  32
+#define FC_TRACE_LINE_SIZE   70
+/******************************************************************************/
+/* Macro Conventions:  we are assuming that the macros will be called inside  */
+/*                     a function that already has a workable saRoot variable */
+/******************************************************************************/
+
+/******************************************************************************/
+/* fiTraceState : ==>        _!n_        _ss: XXXXXXXX       _se: XXXXXXXX    */
+/*              statemachine --^     currentstate--^    triggerevent--^       */
+/*              NOTE: shorthand forms available as macros below.              */
+/******************************************************************************/
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+
+
+void siResetTraceBuffer(agsaRoot_t  *agRoot);
+void siTraceFuncEnter(agsaRoot_t  *agRoot, bit32 mask, bit32 fileid, char *funcid);
+
+
+GLOBAL void siTraceFuncExit(   agsaRoot_t  *agRoot,  bit32   mask, char  fileid, char  * funcid, char  exitId );
+
+
+void siTrace(agsaRoot_t  *agRoot, bit32 mask, char *uId, bit32 value, bit32 dataSizeInBits);
+void siTrace64(agsaRoot_t  *agRoot, bit32 mask, char *uId, bit64 value, bit32 dataSizeInBits);
+bit32 siGetCurrentTraceIndex(agsaRoot_t  *agRoot);
+void siTraceListRemove(agsaRoot_t  *agRoot, bit32 mask, char listId, bitptr exchangeId);
+void siTraceListAdd(agsaRoot_t  *agRoot, bit32 mask, char listId, bitptr exchangeId);
+void siTraceState(agsaRoot_t  *agRoot, bit32 mask, bit32 statemachine, bit32 currentstate, bit32 triggerevent);
+
+#define smTraceState(L,S,C,T)     siTraceState(agRoot,L,S,C,T)
+#define smTraceChipState(L,C,T)   siTraceState(agRoot,L,fiTraceSmChip,C,T)
+#define smTraceFabricState(L,C,T) siTraceState(agRoot,L,fiTraceSmFabr,C,T)
+#define smTracePortState(L,C,T)   siTraceState(agRoot,L,fiTraceSmPort,C,T)
+#define smTraceLoginState(L,C,T)  siTraceState(agRoot,L,fiTraceSmLogin,C,T)
+#define smTraceXchgState(L,C,T)   siTraceState(agRoot,L,fiTraceSmXchg,C,T)
+#define smTraceDiscFabState(L,C,T)    siTraceState(agRoot,L,fiTraceDiscFab,C,T)
+#define smTraceDiscLoopState(L,C,T)   siTraceState(agRoot,L,fiTraceDiscLoop,C,T)
+#define smTraceFc2State(L,C,T)    siTraceState(agRoot,L,fiTraceFc2,C,T)
+#define smTraceScsiTgtState(L,C,T)    siTraceState(agRoot,L,fiTraceTgtState,C,T)
+#define smTraceScsiIniState(L,C,T)    siTraceState(agRoot,L,fiTraceIniState,C,T)
+
+#define smResetTraceBuffer(L)   siResetTraceBuffer(L)
+#define smTraceFuncEnter(L,I)  siTraceFuncEnter(agRoot,L,siTraceFileID,I)
+#define smTraceFuncExit(L,S,I)  siTraceFuncExit(agRoot,L,siTraceFileID,I,S)
+#define smGetCurrentTraceIndex(L)   siGetCurrentTraceIndex(L)
+#define smTraceListRemove(R,L,I,V)   siTraceListRemove(R,L,I,V)
+#define smTraceListAdd(R,L,I,V)   siTraceListAdd(R,L,I,V)
+
+#define smTrace(L,I,V)                                        \
+    /*lint -e506 */                                           \
+    /*lint -e774 */                                           \
+    if (sizeof(V) == 8) {siTrace64(agRoot,L,I,(bit64)V,64);}  \
+    else {siTrace(agRoot,L,I,(bit32)V,32);}                   \
+    /*lint +e506 */                                           \
+    /*lint +e774 */
+
+
+#else
+
+#define siTraceState(agRoot,L,fiTraceSmXchg,C,T)
+
+#define smTraceState(L,S,C,T)
+#define smTraceChipState(L,C,T)
+#define smTraceFabricState(L,C,T)
+#define smTracePortState(L,C,T)
+#define smTraceLoginState(L,C,T)
+#define smTraceXchgState(L,C,T)
+#define smTraceDiscFabState(L,C,T)
+#define smTraceDiscLoopState(L,C,T)
+#define smTraceFc2State(L,C,T)
+#define smTraceScsiTgtState(L,C,T)
+#define smTraceScsiIniState(L,C,T)
+
+#define smResetTraceBuffer(agRoot)
+#define smTraceFuncEnter(L,I)
+#define smTraceFuncExit(L,S,I)
+#define smGetCurrentTraceIndex(L)
+#define smTraceListRemove(L,I,V)
+#define smTraceListAdd(L,I,V)
+
+#define smTrace(L,I,V)
+
+#endif
+
+struct hpTraceBufferParms_s {
+  bit32 TraceCompiled;
+  bit32 BufferSize;
+  bit32 CurrentTraceIndexWrapCount;
+  bit32 CurrentIndex;
+  bit32 TraceWrap;
+  bit8  * pTrace;
+  bit32 * pCurrentTraceIndex;
+  bit32 * pTraceIndexWrapCount;
+  bit32 * pTraceMask;
+};
+typedef struct hpTraceBufferParms_s
+               hpTraceBufferParms_t;
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+
+GLOBAL void siTraceGetInfo(agsaRoot_t  *agRoot, hpTraceBufferParms_t * pBParms);
+
+#define smTraceGetInfo(R,P)  siTraceGetInfo(R,P)
+#else
+#define smTraceGetInfo(R,P)
+#endif
+
+
+void siEnableTracing ( agsaRoot_t  *agRoot );
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+
+GLOBAL void siTraceSetMask(agsaRoot_t  *agRoot, bit32 TraceMask  );
+
+#define smTraceSetMask(R,P)  siTraceSetMask(R,P)
+#else
+#define smTraceSetMask(R,P)
+#endif /* SA_ENABLE_TRACE_FUNCTIONS */
+
+#endif /* #ifndef __SPCDEBUG_H__ */
+

sys/dev/pms/RefTisa/sallsdk/spc/sadefs.h

@@ -0,0 +1,320 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file  sadefs.h
+ *  \brief The file defines the constants used by LL layer
+ */
+
+/*******************************************************************************/
+
+#ifndef  __SADEFS_H__
+
+#define __SADEFS_H__
+
+#define SA_LL_IBQ_PROTECT
+
+#define AGSA_MAX_VALID_PORTS                      AGSA_MAX_VALID_PHYS     /**< defines the maximum number of ports */
+
+#define NUM_TIMERS                                2                       /**< defines the maximum number of timers */
+#define SA_USECS_PER_TICK                         1000000                 /**< defines the heart beat of the LL layer 1us */
+#define MAX_ACTIVE_IO_REQUESTS                    4096                    /**< Maximum Active IO Requests */
+#define SMP_RESPONSE_FRAMES                       AGSA_MAX_VALID_PHYS     /**< SMP Response Frame Buffer */
+#define MAX_NUM_VECTOR                            64                      /**< Maximum Number of Interrupt Vectors */
+#define REGISTER_DUMP_BUFF_SIZE                   0x4000                  /**< Maximum Fatal Error Register Dump Buffer Size */
+#define KBYTES                                    1024
+
+/* number of IQ/OQ */
+#define IQ_NUM_32                                 32
+#define OQ_NUM_32                                 32
+
+/* default value of Inbound/Outbound element size */
+#define INBOUND_DEPTH_SIZE                        512
+#define OUTBOUND_DEPTH_SIZE                       512
+
+/* Priority of Queue */
+#define MPI_QUEUE_NORMAL                          0
+#define MPI_QUEUE_PRIORITY                        1
+
+/* size of IOMB - multiple with 32 bytes */
+#define IOMB_SIZE64                               64
+#define IOMB_SIZE96                               96
+#define IOMB_SIZE128                              128
+#define IOMB_SIZE256                              256
+
+/* DIR bit of IOMB for SSP read/write command */
+#define DIR_NODATA                                0x000
+#define DIR_READ                                  0x100
+#define DIR_WRITE                                 0x200
+
+/* TLR bits mask */
+#define TLR_MASK                                  0x00000003
+/* port and phy Id bits Mask */
+
+
+#define PORTID_MASK                               0x0000000F
+#define PORTID_V_MASK                             0x000000FF
+#define PHYID_MASK                                0x0000000F
+#define PHYID_V_MASK                              0x000000FF
+#define PORT_STATE_MASK                           0x0000000F
+#define PHY_IN_PORT_MASK                          0x000000F0
+
+#define SM_PHYID_MASK   (smIS_SPC(agRoot) ? PHYID_MASK  : PHYID_V_MASK )
+#define SM_PORTID_MASK  (smIS_SPC(agRoot) ? PORTID_MASK : PORTID_V_MASK )
+
+/* the index for memory requirement, must be continious */
+#define LLROOT_MEM_INDEX                          0              /**< the index of root memory */
+#define DEVICELINK_MEM_INDEX         (LLROOT_MEM_INDEX + 1)      /**< the index of device descriptors memory */
+#define IOREQLINK_MEM_INDEX          (DEVICELINK_MEM_INDEX+1)    /**< the index of IO requests memory */
+
+#ifdef SA_ENABLE_HDA_FUNCTIONS
+#define  HDA_DMA_BUFFER              (IOREQLINK_MEM_INDEX+1)     /** HDA Buffer */
+#else  /* SA_ENABLE_HDA_FUNCTIONS */
+#define  HDA_DMA_BUFFER              (IOREQLINK_MEM_INDEX)       /** HDA Buffer */
+#endif /* SA_ENABLE_HDA_FUNCTIONS */
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#define  LL_FUNCTION_TRACE              (HDA_DMA_BUFFER+1)      /**TraceLog */
+#else /* SA_ENABLE_TRACE_FUNCTIONS */
+#define  LL_FUNCTION_TRACE               HDA_DMA_BUFFER         /**TraceLog */
+#endif /* END SA_ENABLE_TRACE_FUNCTIONS */
+
+#define TIMERLINK_MEM_INDEX              (LL_FUNCTION_TRACE+1)   /**< the index of timers memory */
+
+#ifdef FAST_IO_TEST
+#define LL_FAST_IO                        (TIMERLINK_MEM_INDEX+1)
+#define MPI_IBQ_OBQ_INDEX                    (LL_FAST_IO + 1)
+
+#else /* FAST_IO_TEST */
+
+#define LL_FAST_IO                         TIMERLINK_MEM_INDEX
+#define MPI_IBQ_OBQ_INDEX                     (LL_FAST_IO + 1)
+#endif /* FAST_IO_TEST */
+
+#define MPI_MEM_INDEX                             (MPI_IBQ_OBQ_INDEX - LLROOT_MEM_INDEX)
+
+#define MPI_EVENTLOG_INDEX                        0
+#define MPI_IOP_EVENTLOG_INDEX                    1
+#define MPI_CI_INDEX                              2
+/* The following is a reference index */
+#define MPI_PI_INDEX                              (MPI_CI_INDEX + 1)
+#define MPI_IBQ_INDEX                             (MPI_PI_INDEX + 1)
+#define MPI_OBQ_INDEX                             (MPI_IBQ_INDEX + MPI_MAX_INBOUND_QUEUES)
+
+#define TOTAL_MPI_MEM_CHUNKS                      (MPI_MAX_INBOUND_QUEUES * 2) + MPI_IBQ_INDEX
+
+
+#define LL_DEVICE_LOCK 0
+#define LL_PORT_LOCK          (LL_DEVICE_LOCK+1)
+#define LL_TIMER_LOCK         (LL_PORT_LOCK+1)
+#define LL_IOREQ_LOCKEQ_LOCK  (LL_TIMER_LOCK+1)
+
+#ifdef FAST_IO_TEST
+#define LL_FAST_IO_LOCK       (LL_IOREQ_LOCKEQ_LOCK+1)
+#else /* FAST_IO_TEST   */
+#define LL_FAST_IO_LOCK       (LL_IOREQ_LOCKEQ_LOCK)
+#endif /* FAST_IO_TEST   */
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#define LL_TRACE_LOCK       (LL_FAST_IO_LOCK+1)
+#else /* SA_ENABLE_TRACE_FUNCTIONS   */
+#define LL_TRACE_LOCK       (LL_FAST_IO_LOCK)
+#endif /* SA_ENABLE_TRACE_FUNCTIONS   */
+
+#ifdef  MPI_DEBUG_TRACE_ENABLE
+#define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK+1)
+#else /* MPI_DEBUG_TRACE_ENABLE */
+#define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK)
+#endif /* MPI_DEBUG_TRACE_ENABLE */
+
+#define LL_IOREQ_OBQ_LOCK     (LL_IOMB_TRACE_LOCK+1)
+
+#define LL_IOREQ_IBQ_LOCK      (LL_IOREQ_OBQ_LOCK +1)
+#define LL_IOREQ_IBQ_LOCK_PARM (LL_IOREQ_OBQ_LOCK + queueConfig->numOutboundQueues  +1)
+#define LL_IOREQ_IBQ0_LOCK     (LL_IOREQ_OBQ_LOCK + saRoot->QueueConfig.numOutboundQueues  +1)
+
+
+
+/* define phy states */
+#define PHY_STOPPED                               0x00000000              /**< flag indicates phy stopped */
+#define PHY_UP                                    0x00000001              /**< flag indicates phy up */
+#define PHY_DOWN                                  0x00000002              /**< flag indicates phy down */
+
+/* define port states */
+#define PORT_NORMAL                               0x0000
+#define PORT_INVALIDATING                         0x0002
+
+/* define chip status */
+#define CHIP_NORMAL                               0x0000
+#define CHIP_SHUTDOWN                             0x0001
+#define CHIP_RESETTING                            0x0002
+#define CHIP_RESET_FW                             0x0004
+#define CHIP_FATAL_ERROR                          0x0008
+
+/* define device types */
+#define SAS_SATA_UNKNOWN_DEVICE                   0xFF       /**< SAS SATA unknown device type */
+
+#define STP_DEVICE                                0x00       /**< SATA device behind an expander */
+#define SSP_SMP_DEVICE                            0x01       /**< SSP or SMP device type */
+#define DIRECT_SATA_DEVICE                        0x02       /**< SATA direct device type */
+
+/* SATA */
+#define SATA_FIS_MASK                             0x00000001
+#define MAX_SATARESP_SUPPORT_BYTES                44
+
+#define MARK_OFF                                  0xFFFFFFFF
+#define PORT_MARK_OFF                             0xFFFFFFFF
+#define NO_FATAL_ERROR_VECTOR                     0xFFFFFFFF
+
+#define SATA_PROTOCOL_RSRT_ASSERT                 0x01
+#define SATA_PROTOCOL_RSRT_DEASSERT               0x02
+#define SATA_NON_DATA_PROTOCOL                    0x0d
+#define SATA_PIO_READ_PROTOCOL                    0x0e
+#define SATA_DMA_READ_PROTOCOL                    0x0f
+#define SATA_FPDMA_READ_PROTOCOL                  0x10
+#define SATA_PIO_WRITE_PROTOCOL                   0x11
+#define SATA_DMA_WRITE_PROTOCOL                   0x12
+#define SATA_FPDMA_WRITE_PROTOCOL                 0x13
+#define SATA_DEVICE_RESET_PROTOCOL                0x14
+
+/* Definition for bit shift */
+#define SHIFT0                                    0
+#define SHIFT1                                    1
+#define SHIFT2                                    2
+#define SHIFT3                                    3
+#define SHIFT4                                    4
+#define SHIFT5                                    5
+#define SHIFT6                                    6
+#define SHIFT7                                    7
+#define SHIFT8                                    8
+#define SHIFT9                                    9
+#define SHIFT10                                   10
+#define SHIFT11                                   11
+#define SHIFT12                                   12
+#define SHIFT13                                   13
+#define SHIFT14                                   14
+#define SHIFT15                                   15
+#define SHIFT16                                   16
+#define SHIFT17                                   17
+#define SHIFT18                                   18
+#define SHIFT19                                   19
+#define SHIFT20                                   20
+#define SHIFT21                                   21
+#define SHIFT22                                   22
+#define SHIFT23                                   23
+#define SHIFT24                                   24
+#define SHIFT25                                   25
+#define SHIFT26                                   26
+#define SHIFT27                                   27
+#define SHIFT28                                   28
+#define SHIFT29                                   29
+#define SHIFT30                                   30
+#define SHIFT31                                   31
+
+/* These flags used for saSSPAbort(), saSATAAbort() */
+#define ABORT_MASK                                0x3
+#define ABORT_SINGLE                              0x0
+#define ABORT_SCOPE                               0x3 /* bits 0-1*/
+#define ABORT_ALL                                 0x1
+#define ABORT_TSDK_QUARANTINE                     0x4
+#define ABORT_QUARANTINE_SPC                      0x4
+#define ABORT_QUARANTINE_SPCV                     0x8
+
+/* These flags used for saGetRegDump() */
+#define REG_DUMP_NUM0                             0x0
+#define REG_DUMP_NUM1                             0x1
+#define REG_DUMP_NONFLASH                         0x0
+#define REG_DUMP_FLASH                            0x1
+
+/* MSIX Interupts */
+#define MSIX_TABLE_OFFSET                         0x2000
+#define MSIX_TABLE_ELEMENT_SIZE                   0x10
+#define MSIX_INTERRUPT_CONTROL_OFFSET             0xC
+#define MSIX_TABLE_BASE                   (MSIX_TABLE_OFFSET+MSIX_INTERRUPT_CONTROL_OFFSET)
+#define MSIX_INTERRUPT_DISABLE                    0x1
+#define MSIX_INTERRUPT_ENABLE                     0x0
+
+#define MAX_QUEUE_EACH_MEM                        8
+
+#define NUM_MEM_CHUNKS(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q/rem+1) : (bit32)(Q/rem))
+#define NUM_QUEUES_IN_MEM(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q%rem) : (bit32)(MAX_QUEUE_EACH_MEM))
+
+#define MAX_DEV_BITS                              0xFFFF0000
+#define PHY_COUNT_BITS                            0x01f80000
+#define Q_SUPPORT_BITS                            0x0007ffff
+#define SAS_SPEC_BITS                             0xfe000000
+#define HP_SUPPORT_BIT                            0x00010000
+#define INT_COL_BIT                               0x00040000
+#define INT_DELAY_BITS                            0xFFFF
+#define INT_THR_BITS                              0xFF
+#define INT_VEC_BITS                              0xFF
+
+#define AUTO_HARD_RESET_DEREG_FLAG                0x00000001
+#define AUTO_FW_CLEANUP_DEREG_FLAG                0x00000002
+
+#define BYTE_MASK                                 0xff
+
+#define INT_OPTION                                0x7FFF
+#define SMP_TO_DEFAULT                            100
+#define ITL_TO_DEFAULT                            0xFFFF
+
+
+/*
+agsaHwConfig_s  hwOption
+*/
+#define HW_CFG_PICI_EFFECTIVE_ADDRESS             0x1
+
+/* SPC or SPCv ven dev Id */
+
+#define SUBID_SPC                                 0x00000000
+#define SUBID_SPCV                                0x56781234
+
+#define VEN_DEV_SPC                               0x80010000
+#define VEN_DEV_HIL                               0x80810000
+
+#define VEN_DEV_SPCV                              0x80080000
+#define VEN_DEV_SPCVE                             0x80090000
+#define VEN_DEV_SPCVP                             0x80180000
+#define VEN_DEV_SPCVEP                            0x80190000
+
+#define VEN_DEV_SPC12V                            0x80700000
+#define VEN_DEV_SPC12VE                           0x80710000
+#define VEN_DEV_SPC12VP                           0x80720000
+#define VEN_DEV_SPC12VEP                          0x80730000
+#define VEN_DEV_9015                              0x90150000
+#define VEN_DEV_9060                              0x90600000
+
+#define VEN_DEV_ADAPVEP                           0x80890000
+#define VEN_DEV_ADAPVP                            0x80880000
+
+
+#define VEN_DEV_SFC                               0x80250000
+
+/*DelRay PCIid */
+#define VEN_DEV_SPC12ADP                          0x80740000 /* 8 ports */
+#define VEN_DEV_SPC12ADPE                         0x80750000 /* 8 ports encrypt */
+#define VEN_DEV_SPC12ADPP                         0x80760000 /* 16 ports  */
+#define VEN_DEV_SPC12ADPEP                        0x80770000 /* 16 ports encrypt */
+#define VEN_DEV_SPC12SATA                         0x80060000 /* SATA HBA */
+
+#endif  /*__SADEFS_H__ */

sys/dev/pms/RefTisa/sallsdk/spc/sadisc.c

@@ -0,0 +1,864 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/*! \file sadisc.c
+ *  \brief The file implements the functions to do SAS/SATA discovery
+ */
+
+/******************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#ifdef siTraceFileID
+#undef siTraceFileID
+#endif
+#define siTraceFileID 'C'
+#endif
+
+/******************************************************************************/
+/*! \brief Start/Abort SAS/SATA discovery
+ *
+ *  Start/Abort SAS/SATA discovery
+ *
+ *  \param agRoot         Handles for this instance of SAS/SATA hardware
+ *  \param agPortContext  Pointer to this instance of port context
+ *  \param type           Specifies the type(s) of discovery operation to start or cancel
+ *  \param option         Specified the discovery option
+ *
+ *  \return If discovery is started/aborted successfully
+ *          - \e AGSA_RC_SUCCESS discovery is started/aborted successfully
+ *          - \e AGSA_RC_FAILURE discovery is not started/aborted successfully
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saDiscover(
+  agsaRoot_t        *agRoot,
+  agsaPortContext_t *agPortContext,
+  bit32             type,
+  bit32             option
+  )
+{
+  /* Currently not supported */
+  return AGSA_RC_FAILURE;
+}
+
+/******************************************************************************/
+/*! \brief Function for target to remove stale initiator device handle
+ *
+ *  function is called to ask the LL layer to remove all LL layer and SPC firmware
+ *  internal resources associated with a device handle
+ *
+ *  \param agRoot       Handles for this instance of SAS/SATA hardware
+ *  \param agDevHandle  Handle of the device that this I/O request will be made on
+ *
+ *  \return If the device handle is removed successfully
+ *          - \e AGSA_RC_SUCCESS the device handle is removed successfully
+ *          - \e AGSA_RC_BUSY the device is busy, cannot be removed now
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saDeregisterDeviceHandle(
+  agsaRoot_t      *agRoot,
+  agsaContext_t   *agContext,
+  agsaDevHandle_t *agDevHandle,
+  bit32           queueNum
+  )
+{
+  agsaLLRoot_t          *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+  agsaDeviceDesc_t      *pDevice;
+  agsaPort_t            *pPort;
+  bit32                 ret = AGSA_RC_SUCCESS;
+  bit32                 deviceid, portid;
+  bit32                 deviceIdx;
+
+  OS_ASSERT(agDevHandle != agNULL, "saDeregisterDeviceHandle agDevHandle is NULL");
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD, "za");
+
+  if(agNULL == agDevHandle)
+  {
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "za");
+    return AGSA_RC_FAILURE;
+  }
+
+  pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+
+  OS_ASSERT(pDevice != agNULL, "saDeregisterDeviceHandle pDevice is NULL");
+  if(pDevice == agNULL)
+  {
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "za");
+    return AGSA_RC_FAILURE;
+  }
+
+  /* find device id */
+  deviceid = pDevice->DeviceMapIndex;
+  deviceIdx = deviceid & DEVICE_ID_BITS;
+  OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES");
+  pPort = pDevice->pPort;
+  /* find port id */
+  portid = pPort->portId;
+
+  SA_DBG3(("saDeregisterDeviceHandle: start DeviceHandle %p\n", agDevHandle));
+  SA_DBG1(("saDeregisterDeviceHandle: deviceId 0x%x Device Context %p\n", deviceid, pDevice));
+
+  if ((deviceid != saRoot->DeviceMap[deviceIdx].DeviceIdFromFW) ||
+     (pDevice != saRoot->DeviceMap[deviceIdx].DeviceHandle))
+  {
+    SA_DBG1(("saDeregisterDeviceHandle: Not match failure\n"));
+    ret = AGSA_RC_FAILURE;
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "za");
+    return ret;
+  }
+
+  /* Build IOMB and send it to SPC */
+  ret = mpiDeregDevHandleCmd(agRoot, agContext, pDevice, deviceid, portid, queueNum);
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "za");
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Function for target to remove stale initiator device handle
+ *
+ *  function is called to ask the LL layer to remove all LL layer internal resources
+ *  associated with a device handle
+ *
+ *  \param agRoot       Handles for this instance of SAS/SATA hardware
+ *  \param agDevHandle  Handle of the device that this I/O request will be made on
+ *
+ *  \return If the device handle is removed successfully
+ *          - \e AGSA_RC_SUCCESS the device handle is removed successfully
+ *          - \e AGSA_RC_BUSY the device is busy, cannot be removed now
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 siRemoveDevHandle(
+  agsaRoot_t      *agRoot,
+  agsaDevHandle_t *agDevHandle
+  )
+{
+  agsaDeviceDesc_t      *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+  agsaPort_t            *pPort;
+  bit32                 ret = AGSA_RC_SUCCESS;
+
+  OS_ASSERT(pDevice != agNULL, "siRemoveDevHandle is NULL");
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"zb");
+
+  if (pDevice == agNULL)
+  {
+    SA_DBG1(("siRemoveDevHandle: pDevice is NULL \n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zb");
+    return AGSA_RC_FAILURE;
+  }
+
+  /* If it's to remove an initiator device handle */
+  if ( &(pDevice->initiatorDevHandle) == agDevHandle )
+  {
+    (pDevice->initiatorDevHandle).sdkData = agNULL;
+  }
+  /* If it's to remove an target device handle */
+  else if ( &(pDevice->targetDevHandle) == agDevHandle )
+  {
+    (pDevice->targetDevHandle).sdkData = agNULL;
+  }
+  else
+  {
+    SA_ASSERT(agFALSE, "");
+  }
+
+  /* remove the device descriptor if it doesn't have either initiator handle and target handle */
+  if ( (agNULL == (pDevice->initiatorDevHandle).sdkData)
+      && (agNULL == (pDevice->targetDevHandle).sdkData) )
+  {
+    /* Find the port of the device */
+    pPort = pDevice->pPort;
+
+    /* remove the device descriptor free discover list */
+    switch ( pDevice->deviceType )
+    {
+      case STP_DEVICE: /* fall through */
+      case SSP_SMP_DEVICE:
+      case DIRECT_SATA_DEVICE:
+      {
+        SA_DBG3(("siRemoveDevHandle: remove device context %p\n", pDevice));
+        siPortDeviceRemove(agRoot, pPort, pDevice, agTRUE);
+        break;
+      }
+      default:
+      {
+        SA_DBG1(("siRemoveDevHandle: switch. Not calling siPortDeviceRemove %d\n", pDevice->deviceType));
+        break;
+      }
+    }
+  }
+  else
+  {
+    SA_DBG1(("siRemoveDevHandle: else. Not caling siPortDeviceRemove\n"));
+  }
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zb");
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Get Device Handles from a specific local port
+ *
+ *  Get a Device Handles
+ *
+ *  \param agRoot         Handles for this instance of SAS/SATA hardware
+ *  \param agsaContext    Pointer to this API context
+ *  \param agPortContext  Pointer to this instance of port context
+ *  \param flags          Device flags
+ *  \param agDev[]        Pointer of array of device handles
+ *  \param MaxDevs        Specified Maximum number of Device Handles
+ *
+ *  \return If GetDeviceHandles is successfully or failure
+ *          - \e AGSA_RC_SUCCESS GetDeviceHandles is successfully
+ *          - \e AGSA_RC_FAILURE GetDeviceHandles is not successfully
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saGetDeviceHandles(
+  agsaRoot_t        *agRoot,
+  agsaContext_t     *agContext,
+  bit32             queueNum,
+  agsaPortContext_t *agPortContext,
+  bit32             flags,
+  agsaDevHandle_t   *agDev[],
+  bit32             skipCount,
+  bit32             MaxDevs
+  )
+{
+  agsaLLRoot_t      *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+  agsaPort_t        *pPort = (agsaPort_t *) (agPortContext->sdkData);
+  bit32             portIndex, i;
+  bit32             ret = AGSA_RC_SUCCESS;
+
+  OS_ASSERT(pPort != agNULL, "saGetDeviceHandles is NULL");
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"zc");
+
+  if (pPort == agNULL)
+  {
+    SA_DBG1(("saGetDeviceHandles: pPort is NULL \n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zc");
+    return AGSA_RC_FAILURE;
+  }
+
+  SA_DBG1(("saGetDeviceHandles: start portId %d\n", pPort->portId));
+
+  /* save the device handles arrary pointer */
+  for (i = 0; i < MaxDevs; i ++)
+  {
+    saRoot->DeviceHandle[i] = agDev[i];
+  }
+
+  /* send GET_DEVICE_HANDLE IOMB to SPC */
+  portIndex = pPort->portId;
+  mpiGetDeviceHandleCmd(agRoot, agContext, portIndex, flags, MaxDevs, queueNum, skipCount);
+
+  /* return */
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zc");
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Register New Device from a specific local port
+ *
+ *  Register New Device API
+ *
+ *  \param agRoot         Handles for this instance of SAS/SATA hardware
+ *  \param agContext      Pointer to this API context
+ *  \param agDeviceInfo   Pointer to this instance of device info
+ *  \param agPortContext  Pointer to this instance of port context
+ *
+ *  \return If discovery is started/aborted successfully
+ *          - \e AGSA_RC_SUCCESS discovery is started/aborted successfully
+ *          - \e AGSA_RC_FAILURE discovery is not started/aborted successfully
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saRegisterNewDevice(
+  agsaRoot_t            *agRoot,
+  agsaContext_t         *agContext,
+  bit32                 queueNum,
+  agsaDeviceInfo_t      *agDeviceInfo,
+  agsaPortContext_t     *agPortContext,
+  bit16                 hostAssignedDeviceId
+  )
+{
+  bit32               ret = AGSA_RC_SUCCESS;
+  agsaRegDevCmd_t     payload;
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+  agsaIORequestDesc_t *pRequest;
+  agsaPort_t          *pPort = (agsaPort_t *) (agPortContext->sdkData);
+  agsaSASIdentify_t   remoteIdentify;
+  bit32               i, phyId, sDTypeRate;
+  agsaDeviceDesc_t    *pDevice = agNULL;
+
+  OS_ASSERT(pPort != agNULL, "saRegisterNewDevice is NULL");
+  OS_ASSERT(saRoot != agNULL, "saRoot is NULL");
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"zd");
+
+  if(saRoot == agNULL)
+  {
+    SA_DBG1(("saRegisterNewDevice: saRoot == agNULL\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zd");
+    return(AGSA_RC_FAILURE);
+  }
+
+  if (pPort == agNULL)
+  {
+    SA_DBG1(("saRegisterNewDevice: pPort is NULL \n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zd");
+    return AGSA_RC_FAILURE;
+  }
+
+  SA_DBG2(("saRegisterNewDevice: start portId %d Port Context %p\n", pPort->portId, agPortContext));
+
+  SA_DBG2(("saRegisterNewDevice: smpTimeout 0x%x\n", agDeviceInfo->smpTimeout));
+  SA_DBG2(("saRegisterNewDevice: it_NexusTimeout 0x%x\n", agDeviceInfo->it_NexusTimeout));
+  SA_DBG2(("saRegisterNewDevice: firstBurstSize 0x%x\n", agDeviceInfo->firstBurstSize));
+  SA_DBG2(("saRegisterNewDevice: devType_S_Rate 0x%x\n", agDeviceInfo->devType_S_Rate));
+  SA_DBG2(("saRegisterNewDevice: flag 0x%x\n", agDeviceInfo->flag));
+  SA_DBG2(("saRegisterNewDevice: hostAssignedDeviceId  0x%x\n",hostAssignedDeviceId ));
+  SA_DBG2(("saRegisterNewDevice: Addr 0x%02x%02x%02x%02x 0x%02x%02x%02x%02x\n",
+          agDeviceInfo->sasAddressHi[0],agDeviceInfo->sasAddressHi[1],agDeviceInfo->sasAddressHi[2],agDeviceInfo->sasAddressHi[3],
+          agDeviceInfo->sasAddressLo[0],agDeviceInfo->sasAddressLo[1],agDeviceInfo->sasAddressLo[2],agDeviceInfo->sasAddressLo[3] ));
+
+  agDeviceInfo->devType_S_Rate &= DEV_LINK_RATE;
+
+  /*
+    Using agsaDeviceInfo_t, fill in only sas address and device type
+    of identify address frame
+  */
+  si_memset(&remoteIdentify, 0, sizeof(agsaSASIdentify_t));
+  for (i=0;i<4;i++)
+  {
+    remoteIdentify.sasAddressHi[i] = agDeviceInfo->sasAddressHi[i];
+    remoteIdentify.sasAddressLo[i] = agDeviceInfo->sasAddressLo[i];
+  }
+  remoteIdentify.deviceType_addressFrameType = (bit8)(agDeviceInfo->devType_S_Rate & 0xC0);
+
+  /* Get request from free IORequests */
+  ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+  pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests));
+
+  /* If no LL Control request entry available */
+  if ( agNULL == pRequest )
+  {
+    pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); /**/
+    if(agNULL != pRequest)
+    {
+      saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
+      SA_DBG1(("saRegisterNewDevice, using saRoot->freeReservedRequests\n"));
+    }
+    else
+    {
+      SA_DBG1(("saRegisterNewDevice, No request from free list Not using saRoot->freeReservedRequests\n"));
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zd");
+      return AGSA_RC_BUSY;
+    }
+  }
+  else
+  {
+    /* If LL Control request entry avaliable */
+    saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode));
+  }
+
+  saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag;
+  saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest;
+  saRoot->IOMap[pRequest->HTag].agContext = agContext;
+  pRequest->valid = agTRUE;
+
+  ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+  /* checking bit5 for SATA direct device */
+  if (!(agDeviceInfo->devType_S_Rate & 0x20))
+  {
+    /* SAS device */
+    /* Add SAS device to the device list */
+    pDevice = siPortSASDeviceAdd(agRoot,
+                       pPort,
+                       remoteIdentify,
+                       agFALSE,
+                       agDeviceInfo->smpTimeout,
+                       agDeviceInfo->it_NexusTimeout,
+                       agDeviceInfo->firstBurstSize,
+                       agDeviceInfo->devType_S_Rate,
+                       (agDeviceInfo->flag & DEV_INFO_MASK));
+   }
+   else
+   {
+    /* SATA device */
+    /* Add SATA device to the device list */
+    pDevice = siPortSATADeviceAdd(agRoot,
+                                  pPort,
+                                  agNULL,
+                                  agNULL, /* no signature */
+                                  agFALSE,
+                                  0,
+                                  agDeviceInfo->smpTimeout,
+                                  agDeviceInfo->it_NexusTimeout,
+                                  agDeviceInfo->firstBurstSize,
+                                  agDeviceInfo->devType_S_Rate,
+                                  (agDeviceInfo->flag & DEV_INFO_MASK));
+    }
+
+    SA_DBG1(("saRegisterNewDevice: Device Context %p, TypeRate 0x%x\n", pDevice, agDeviceInfo->devType_S_Rate));
+
+    pRequest->pDevice = pDevice;
+
+    /* adjust the flag bit to build the IOMB; use only bit0 and 1 */
+    sDTypeRate = agDeviceInfo->devType_S_Rate << SHIFT24;
+    sDTypeRate |= (agDeviceInfo->flag & 0x01);
+    /* set AWT flag */
+    sDTypeRate |= (agDeviceInfo->flag & 0x02) << 1;
+
+    /* If the host assigned device ID is used, then set the HA bit. */
+    if ( hostAssignedDeviceId != 0 )
+    {
+      sDTypeRate |= 2;
+      SA_DBG3(("saRegisterNewDevice:hostAssignedDeviceId 0x%x sDTypeRate 0x%x\n",hostAssignedDeviceId,sDTypeRate ));
+    }
+
+    /* Add the MCN field */
+
+    sDTypeRate |= ((agDeviceInfo->flag >> DEV_INFO_MCN_SHIFT) & 0xf) << 4;
+
+    /* Add the IR field */
+    sDTypeRate |= ((agDeviceInfo->flag >> DEV_INFO_IR_SHIFT) & 0x1) <<  3;
+
+    /* Add the ATAPI protocol flag */
+    sDTypeRate |= ((agDeviceInfo->flag & ATAPI_DEVICE_FLAG) << SHIFT9 );
+
+    /* Add the AWT  flag */
+    sDTypeRate |= (agDeviceInfo->flag & AWT_DEVICE_FLAG) ? (1 << SHIFT2) : 0;
+
+    /* Add the XFER_READY flag  */
+    sDTypeRate |= (agDeviceInfo->flag & XFER_RDY_PRIORTY_DEVICE_FLAG) ? (1 << SHIFT31) : 0;
+    if(agDeviceInfo->flag & XFER_RDY_PRIORTY_DEVICE_FLAG)
+    {
+      SA_DBG1(("saRegisterNewDevice: sflag XFER_RDY_PRIORTY_DEVICE_FLAG sDTypeRate 0x%x\n",sDTypeRate ));
+    }
+#ifdef CCFLAG_FORCE_AWT_ON
+    sDTypeRate |= (1 << SHIFT2);
+    SA_DBG1(("saRegisterNewDevice: Force AWT_DEVICE_FLAG sDTypeRate 0x%x\n",sDTypeRate ));
+#endif /* CCFLAG_FORCE_AWT_ON */
+
+    /* create payload for IOMB */
+    si_memset(&payload, 0, sizeof(agsaRegDevCmd_t));
+
+    SA_DBG2(("saRegisterNewDevice,flag 0x%08X\n",agDeviceInfo->flag));
+    if ((agDeviceInfo->devType_S_Rate & 0x30) == 0x20)
+    {
+      if(smIS_SPC(agRoot))
+      {
+        /* direct SATA device */
+        phyId = (agDeviceInfo->flag & 0xF0);
+      }
+      else
+      {
+        phyId = (agDeviceInfo->flag & 0xF0) << SHIFT4;
+      }
+    }
+    else
+    {
+      phyId = 0;
+    }
+
+    smTrace(hpDBG_VERY_LOUD,"QQ",phyId);
+    /* TP:QQ phyId */
+    smTrace(hpDBG_VERY_LOUD,"QR",pPort->portId);
+    /* TP:QR portId */
+    smTrace(hpDBG_VERY_LOUD,"QS",sDTypeRate);
+    /* TP:QS sDTypeRate */
+    smTrace(hpDBG_VERY_LOUD,"QT",agDeviceInfo->it_NexusTimeout);
+    /* TP:QT agDeviceInfo->it_NexusTimeout */
+
+    OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, phyIdportId), (bit32)(pPort->portId & PORTID_MASK) | phyId);
+    OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, dTypeLRateAwtHa), sDTypeRate);
+    OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, ITNexusTimeOut), (agDeviceInfo->it_NexusTimeout));
+
+    smTrace(hpDBG_VERY_LOUD,"QT",(bit32)(pPort->portId & PORTID_MASK) | phyId);
+    /* TP:QT phyIdportId */
+    /* no conversion is needed since SAS address is in BE format */
+    payload.sasAddrHi = *(bit32*)agDeviceInfo->sasAddressHi;
+    payload.sasAddrLo = *(bit32*)agDeviceInfo->sasAddressLo;
+
+    OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, tag), pRequest->HTag);
+    OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaRegDevCmd_t, DeviceId), ((bit32)hostAssignedDeviceId) << 16);
+
+    if(smIS_SPC(agRoot))
+    {
+      ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SPC_REG_DEV, IOMB_SIZE64, queueNum);
+    }
+    else
+    {
+      ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_REG_DEV, IOMB_SIZE64, queueNum);
+    }
+
+    if (AGSA_RC_SUCCESS != ret)
+    {
+      /* return the request to free pool */
+      ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      /* remove the request from IOMap */
+      saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF;
+      saRoot->IOMap[pRequest->HTag].IORequest = agNULL;
+      saRoot->IOMap[pRequest->HTag].agContext = agNULL;
+      pRequest->valid = agFALSE;
+
+      if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT)
+      {
+        SA_DBG1(("saRegisterNewDevice: saving pRequest (%p) for later use\n", pRequest));
+        saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
+      }
+      else
+      {
+        /* return the request to free pool */
+        saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+      }
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      SA_DBG1(("saRegisterNewDevice, sending IOMB failed\n" ));
+    }
+    SA_DBG3(("saRegisterNewDevice: end\n"));
+
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "zd");
+    return ret;
+}
+
+/******************************************************************************/
+/*! \brief Register a callback for a specific event
+ *
+ *  Register a callback for a Event API
+ *
+ *  \param agRoot          Handles for this instance of SAS/SATA hardware
+ *  \param eventSourceType Event Type
+ *  \param callbackPtr     Function pointer to OS layer
+ *
+ *  \return
+ *          - \e AGSA_RC_SUCCESS
+ *          - \e AGSA_RC_FAILURE
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saRegisterEventCallback(
+                        agsaRoot_t                *agRoot,
+                        bit32                     eventSourceType,
+                        ossaGenericCB_t           callbackPtr
+                        )
+{
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  bit32               ret = AGSA_RC_FAILURE;
+
+  SA_DBG3(("saRegisterEventCallback: start\n"));
+  switch (eventSourceType)
+  {
+    case OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED:
+      saRoot->DeviceRegistrationCB =  (ossaDeviceRegistrationCB_t)callbackPtr;
+      ret = AGSA_RC_SUCCESS;
+      break;
+    case OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED:
+      saRoot->DeviceDeregistrationCB = (ossaDeregisterDeviceHandleCB_t) callbackPtr;
+      ret = AGSA_RC_SUCCESS;
+      break;
+    default:
+      SA_DBG1(("saRegisterEventCallback: not allowed case %d\n", eventSourceType));
+      ret = AGSA_RC_FAILURE;
+      break;
+  }
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Get Device Information
+ *
+ *  Get SAS/SATA device information API
+ *
+ *  \param agRoot          Handles for this instance of SAS/SATA hardware
+ *  \param option          device general information or extended information
+ *  \param agDevHandle     Pointer of device handle
+ *
+ *  \return
+ *          - \e AGSA_RC_SUCCESS
+ *          - \e AGSA_RC_FAILURE
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saGetDeviceInfo(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     option,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle
+                        )
+{
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaDeviceDesc_t    *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+  bit32               deviceid;
+  bit32               ret = AGSA_RC_FAILURE;
+
+  OS_ASSERT(pDevice != agNULL, "saGetDeviceInfo is NULL");
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"ze");
+
+  if (pDevice == agNULL)
+  {
+    SA_DBG1(("saGetDeviceInfo: pDevice is NULL \n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "ze");
+    return AGSA_RC_FAILURE;
+  }
+
+  /* Get deviceid */
+  deviceid = pDevice->DeviceMapIndex;
+  SA_DBG3(("saGetDeviceInfo: start pDevice %p, deviceId %d\n", pDevice, deviceid));
+
+  /* verify the agDeviceHandle with the one in the deviceMap */
+  if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) ||
+     (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle))
+  {
+    SA_DBG1(("saGetDeviceInfo: Not match failure or device not exist\n"));
+    ret = AGSA_RC_FAILURE;
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "ze");
+    return ret;
+  }
+
+  /* send IOMB to the SPC */
+  ret = mpiGetDeviceInfoCmd(agRoot, agContext, deviceid, option, queueNum);
+
+  SA_DBG3(("saGetDeviceInfo: end\n"));
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "ze");
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Set Device Information
+ *
+ *  Set SAS/SATA device information API
+ *
+ *  \param agRoot          Handles for this instance of SAS/SATA hardware
+ *  \param agContext       Pointer to this API context
+ *  \param queueNum        IQ/OQ number
+ *  \param agDevHandle     Pointer of device handle
+ *  \param option          device general information or extended information
+ *  \param param           Parameter of Set Device Infomation
+ *
+ *  \return
+ *          - \e AGSA_RC_SUCCESS
+ *          - \e AGSA_RC_FAILURE
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saSetDeviceInfo(
+                        agsaRoot_t            *agRoot,
+                        agsaContext_t         *agContext,
+                        bit32                 queueNum,
+                        agsaDevHandle_t       *agDevHandle,
+                        bit32                  option,
+                        bit32                  param,
+                        ossaSetDeviceInfoCB_t  agCB
+                        )
+{
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaDeviceDesc_t    *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+  bit32               deviceid;
+  bit32               ret = AGSA_RC_FAILURE;
+
+  OS_ASSERT(pDevice != agNULL, "saSetDeviceInfo is NULL");
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"zf");
+
+  SA_DBG2(("saSetDeviceInfo: start pDevice %p, option=0x%x param=0x0%x\n", pDevice, option, param));
+  if(agNULL ==  pDevice )
+  {
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zf");
+    return ret;
+  }
+
+
+  /* Get deviceid */
+  deviceid = pDevice->DeviceMapIndex;
+  pDevice->option = option;
+  pDevice->param = param;
+
+  SA_DBG3(("saSetDeviceInfo: deviceId %d\n", deviceid));
+
+  /* verify the agDeviceHandle with the one in the deviceMap */
+  if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) ||
+     (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle))
+  {
+    SA_DBG1(("saSetDeviceInfo: Not match failure or device not exist\n"));
+    ret = AGSA_RC_FAILURE;
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zf");
+    return ret;
+  }
+
+  /* send IOMB to the SPC */
+  ret = mpiSetDeviceInfoCmd(agRoot, agContext, deviceid, option, queueNum, param, agCB);
+
+  SA_DBG3(("saSetDeviceInfo: end\n"));
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zf");
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Get Device State
+ *
+ *  Get SAS/SATA device state API
+ *
+ *  \param agRoot          Handles for this instance of SAS/SATA hardware
+ *  \param agContext       Pointer to this API context
+ *  \param queueNum        IQ/OQ number
+ *  \param agDevHandle     Pointer of device handler
+ *
+ *  \return
+ *          - \e AGSA_RC_SUCCESS
+ *          - \e AGSA_RC_FAILURE
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saGetDeviceState(
+                        agsaRoot_t                *agRoot,
+                        agsaContext_t             *agContext,
+                        bit32                     queueNum,
+                        agsaDevHandle_t           *agDevHandle
+                        )
+{
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaDeviceDesc_t    *pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+  bit32               deviceid;
+  bit32               ret = AGSA_RC_FAILURE;
+
+  OS_ASSERT(pDevice != agNULL, "saGetDeviceState is NULL");
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"zg");
+
+  if (pDevice == agNULL)
+  {
+    SA_DBG1(("saGetDeviceState: pDevice is NULL \n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zg");
+    return AGSA_RC_FAILURE;
+  }
+
+  SA_DBG3(("saGetDeviceState: start pDevice %p\n", pDevice));
+
+  /* Get deviceid */
+  deviceid = pDevice->DeviceMapIndex;
+
+  /* verify the agDeviceHandle with the one in the deviceMap */
+  if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) ||
+     (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle))
+  {
+    SA_DBG1(("saGetDeviceState: Not match failure or device not exist\n"));
+    ret = AGSA_RC_FAILURE;
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zg");
+    return ret;
+  }
+
+  /* send IOMB to the SPC */
+  ret = mpiGetDeviceStateCmd(agRoot, agContext, deviceid, queueNum);
+
+  SA_DBG3(("saGetDeviceState: end\n"));
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zg");
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Set Device State
+ *
+ *  Set SAS/SATA device state API
+ *
+ *  \param agRoot          Handles for this instance of SAS/SATA hardware
+ *  \param agContext       Pointer to this API context
+ *  \param queueNum        IQ/OQ number
+ *  \param agDevHandle     Pointer of device handler
+ *  \param newDeviceState  new device state
+ *
+ *  \return
+ *          - \e AGSA_RC_SUCCESS
+ *          - \e AGSA_RC_FAILURE
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saSetDeviceState(
+                        agsaRoot_t      *agRoot,
+                        agsaContext_t   *agContext,
+                        bit32           queueNum,
+                        agsaDevHandle_t *agDevHandle,
+                        bit32            newDeviceState
+                        )
+{
+  agsaLLRoot_t        *saRoot;
+  agsaDeviceDesc_t    *pDevice;
+  bit32               deviceid;
+  bit32               ret = AGSA_RC_FAILURE;
+
+  saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  OS_ASSERT(saRoot != agNULL, "saSetDeviceState saRoot");
+
+  if(saRoot == agNULL )
+  {
+    SA_DBG1(("saSetDeviceState: saRoot is NULL\n"));
+    return ret;
+  }
+
+  OS_ASSERT(agDevHandle != agNULL, "saSetDeviceState agDevHandle  is NULL");
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"zh");
+
+  if(agDevHandle == agNULL )
+  {
+    SA_DBG1(("saSetDeviceState: agDevHandle is NULL\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zh");
+    return ret;
+  }
+
+  pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+
+  OS_ASSERT(pDevice != agNULL, "saSetDeviceState pDevice is NULL");
+
+  SA_DBG3(("saSetDeviceState: start pDevice %p\n", pDevice));
+
+  if(pDevice == agNULL )
+  {
+    SA_DBG1(("saSetDeviceState: pDevice is NULL\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "zh");
+    return ret;
+  }
+  /* Get deviceid */
+  deviceid = pDevice->DeviceMapIndex;
+
+  /* verify the agDeviceHandle with the one in the deviceMap */
+  if ((deviceid != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceIdFromFW) ||
+     (pDevice != saRoot->DeviceMap[deviceid & DEVICE_ID_BITS].DeviceHandle))
+  {
+    SA_DBG1(("saSetDeviceState: Not match failure or device not exist\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "zh");
+    return ret;
+  }
+
+  /* send IOMB to the SPC */
+  ret = mpiSetDeviceStateCmd(agRoot, agContext, deviceid, newDeviceState, queueNum);
+
+  SA_DBG3(("saSetDeviceState: end\n"));
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "zh");
+  return ret;
+}

sys/dev/pms/RefTisa/sallsdk/spc/saframe.c

@@ -0,0 +1,125 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/*! \file saframe.c
+ *  \brief The file implements the functions to read frame content
+ */
+
+
+/******************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#ifdef siTraceFileID
+#undef siTraceFileID
+#endif
+#define siTraceFileID 'D'
+#endif
+
+/******************************************************************************/
+/*! \brief Read 32 bits from a frame
+ *
+ *  Read 32 bits from a frame
+ *
+ *  \param agRoot       Handles for this instance of SAS/SATA LLL
+ *  \param agFrame      The frame handler
+ *  \param frameOffset  Offset in bytes from the beginning of valid frame bytes or IU
+                        to the 32-bit value to read
+ *
+ *  \return The read value
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saFrameReadBit32(
+  agsaRoot_t          *agRoot,
+  agsaFrameHandle_t   agFrame,
+  bit32               frameOffset
+  )
+{
+  bit8                    *payloadAddr;
+  bit32                   value = 0;
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD, "zr");
+
+  if ( agNULL != agFrame )
+  {
+    /* Find the address of the payload */
+    payloadAddr = (bit8 *)(agFrame) + frameOffset;
+
+    /* read one DW Data */
+    value = *(bit32 *)payloadAddr;
+  }
+
+
+  /* (5) return value */
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zr");
+  return value;
+}
+
+/******************************************************************************/
+/*! \brief Read a block from a frame
+ *
+ *  Read a block from a frame
+ *
+ *  \param agRoot         Handles for this instance of SAS/SATA LLL
+ *  \param agFrame        The frame handler
+ *  \param frameOffset    The offset of the frame to start read
+ *  \param frameBuffer    The pointer to the destination of data read from the frame
+ *  \param frameBufLen    Number of bytes to read from the frame
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+GLOBAL void saFrameReadBlock (
+  agsaRoot_t          *agRoot,
+  agsaFrameHandle_t   agFrame,
+  bit32               frameOffset,
+  void                *frameBuffer,
+  bit32               frameBufLen
+  )
+{
+  bit8                    *payloadAddr;
+  bit32                   i;
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD, "zi");
+
+  /* Sanity check */
+  SA_ASSERT(frameBufLen < 4096, "saFrameReadBlock read more than 4k");
+
+  if ( agNULL != agFrame )
+  {
+    /* Find the address of the payload */
+    payloadAddr = (bit8 *)(agFrame) + frameOffset;
+    /* Copy the frame data to the destination frame buffer */
+    for ( i = 0; i < frameBufLen; i ++ )
+    {
+      *(bit8 *)((bit8 *)frameBuffer + i) = *(bit8 *)(payloadAddr + i);
+    }
+  }
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "zi");
+}
+

sys/dev/pms/RefTisa/sallsdk/spc/saglobal.h

@@ -0,0 +1,56 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file saglobal.h
+ *  \brief This file defines global types
+ */
+
+/*******************************************************************************/
+
+#ifndef __SAGLOBAL_H__
+#define __SAGLOBAL_H__
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/tisa/sassata/common/ossa.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/sallist.h>
+#include <dev/pms/RefTisa/sallsdk/spc/sadefs.h>
+#include <dev/pms/RefTisa/sallsdk/spc/sampidefs.h>
+#include <dev/pms/RefTisa/sallsdk/api/sa_err.h>
+#include <dev/pms/RefTisa/sallsdk/api/sa_spec.h>
+#include <dev/pms/RefTisa/sallsdk/spc/sahwreg.h>
+#include <dev/pms/RefTisa/sallsdk/spc/samacro.h>
+#include <dev/pms/RefTisa/sallsdk/spc/spcdefs.h>
+#include <dev/pms/RefTisa/sallsdk/spc/mpi.h>
+#include <dev/pms/RefTisa/sallsdk/spc/satypes.h>
+#include <dev/pms/RefTisa/sallsdk/spc/saproto.h>
+#include <dev/pms/RefTisa/sallsdk/spc/mpidebug.h>
+
+#endif /* __SAGLOBAL_H__ */

sys/dev/pms/RefTisa/sallsdk/spc/sahwreg.h

@@ -0,0 +1,709 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file sahwreg.h
+ *  \brief The file defines the register offset of hardware
+ */
+/******************************************************************************/
+#ifndef  __SAHWREG_H__
+
+#define __SAHWREG_H__
+
+/* #define MSGU_ACCESS_VIA_XCBI  */ /* Defined in build script now */
+
+/* Message Unit Registers - BAR0(0x10), BAR0(win) */
+#ifdef SPC_I2O_ENABLE
+/* i2o=1 space register offsets - MU_I2O_ENABLE */
+/* Currently FPGA use these offset */
+#define MSGU_IBDB_SET                            0x20
+#define MSGU_HOST_INT_STATUS                     0x30
+#define MSGU_HOST_INT_MASK                       0x34
+#define MSGU_IOPIB_INT_STATUS                    0x40
+#define MSGU_IOPIB_INT_MASK                      0x44
+#define MSGU_IBDB_CLEAR                          0x70
+#define MSGU_MSGU_CONTROL                        0x74
+#define MSGU_ODR                                 0x9C
+#define MSGU_ODCR                                0xA0
+#define MSGU_SCRATCH_PAD_0                       0xB0
+#define MSGU_SCRATCH_PAD_1                       0xB4
+#define MSGU_SCRATCH_PAD_2                       0xB8
+#define MSGU_SCRATCH_PAD_3                       0xBC
+#else
+/* i2o=0 space register offsets - ~MU_I2O_ENABLE */
+#define MSGU_IBDB_SET                            0x04  /* RevA - Write only, RevB - Read/Write */
+#define MSGU_HOST_INT_STATUS                     0x08
+#define MSGU_HOST_INT_MASK                       0x0C
+#define MSGU_IOPIB_INT_STATUS                    0x18
+#define MSGU_IOPIB_INT_MASK                      0x1C
+#define MSGU_IBDB_CLEAR                          0x20  /* RevB - Host not use */
+#define MSGU_MSGU_CONTROL                        0x24
+#define MSGU_ODR                                 0x3C  /* RevB */
+#define MSGU_ODCR                                0x40  /* RevB */
+#define MSGU_SCRATCH_PAD_0                       0x44
+#define MSGU_SCRATCH_PAD_1                       0x48
+#define MSGU_SCRATCH_PAD_2                       0x4C
+#define MSGU_SCRATCH_PAD_3                       0x50
+#define MSGU_HOST_SCRATCH_PAD_0                  0x54
+#define MSGU_HOST_SCRATCH_PAD_1                  0x58
+#define MSGU_HOST_SCRATCH_PAD_2                  0x5C
+#define MSGU_HOST_SCRATCH_PAD_3                  0x60
+#define MSGU_HOST_SCRATCH_PAD_4                  0x64
+#define MSGU_HOST_SCRATCH_PAD_5                  0x68
+#define MSGU_HOST_SCRATCH_PAD_6                  0x6C
+#define MSGU_HOST_SCRATCH_PAD_7                  0x70
+#define MSGU_ODMR                                0x74  /* RevB */
+#endif
+
+
+
+
+/*
+Table 215   Messaging Unit Address Map
+Offset (Hex) Name Access Internal Offset Internal Name Comment
+*/
+
+#define V_Inbound_Doorbell_Set_Register          0x00    /* Host R/W Local INT 0x0 MSGU - Inbound Doorbell Set */
+#define V_Inbound_Doorbell_Set_RegisterU         0x04    /* Host R/W Local INT 0x4 MSGU - Inbound Doorbell Set */
+#define V_Inbound_Doorbell_Clear_Register        0x08    /* Host No access Local  W, R all 0s 0x8 MSGU - Inbound Doorbell Clear */
+#define V_Inbound_Doorbell_Clear_RegisterU       0x0C    /* Host No access Local  W, R all 0s 0xC MSGU - Inbound Doorbell Clear */
+#define V_Inbound_Doorbell_Mask_Set_Register     0x10    /* Host RO Local R/W 0x10 MSGU - Inbound Doorbell Mask Set New in SPCv */
+#define V_Inbound_Doorbell_Mask_Set_RegisterU    0x14    /* Host RO Local R/W 0x14 MSGU - Inbound Doorbell Mask Set New in SPCv */
+#define V_Inbound_Doorbell_Mask_Clear_Register   0x18    /* Host RO Local W, R all 0s 0x18 MSGU - Inbound Doorbell Mask Clear New in SPCv */
+#define V_Inbound_Doorbell_Mask_Clear_RegisterU  0x1C    /* Host RO Local W, R all 0s 0x1C MSGU - Inbound Doorbell Mask Clear New in SPCv */
+#define V_Outbound_Doorbell_Set_Register         0x20    /* Host RO Local R/W 0x20 MSGU - Outbound Doorbell Set */
+#define V_Outbound_Doorbell_Set_RegisterU        0x24    /* Host RO Local R/W 0x24 MSGU - Outbound Doorbell Set */
+#define V_Outbound_Doorbell_Clear_Register       0x28    /* Host W, R all 0s Local  RO 0x28 MSGU - Outbound Doorbell Clear */
+#define V_Outbound_Doorbell_Clear_RegisterU      0x2C    /* Host W, R all 0s Local  RO 0x2C MSGU - Outbound Doorbell Clear */
+#define V_Outbound_Doorbell_Mask_Set_Register    0x30    /* Host RW  Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */
+#define V_Outbound_Doorbell_Mask_Set_RegisterU   0x34    /* Host RW  Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */
+#define V_Outbound_Doorbell_Mask_Clear_Register  0x38    /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */
+#define V_Outbound_Doorbell_Mask_Clear_RegisterU 0x3C    /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */
+/* 0x40 Reserved  R all 0s */
+#define V_Scratchpad_0_Register                 0x44    /* Host RO Local R/W 0x120 MSGU - Scratchpad 0 */
+#define V_Scratchpad_1_Register                 0x48    /* Host RO Local R/W 0x128 MSGU - Scratchpad 1 */
+#define V_Scratchpad_2_Register                 0x4C    /* Host RO Local R/W 0x130 MSGU - Scratchpad 2 */
+#define V_Scratchpad_3_Register                 0x50    /* Host RO Local R/W 0x138 MSGU - Scratchpad 3 */
+#define V_Host_Scratchpad_0_Register            0x54    /* Host RW Local RO 0x140 MSGU - Scratchpad 4 */
+#define V_Host_Scratchpad_1_Register            0x58    /* Host RW Local RO 0x148 MSGU - Scratchpad 5 */
+#define V_Host_Scratchpad_2_Register            0x5C    /* Host RW Local RO 0x150 MSGU - Scratchpad 6 */
+#define V_Host_Scratchpad_3_Register            0x60    /* Host RW Local RO 0x158 MSGU - Scratchpad 7 */
+#define V_Host_Scratchpad_4_Register            0x64    /* Host RW Local R/W 0x160 MSGU - Scratchpad 8 */
+#define V_Host_Scratchpad_5_Register            0x68    /* Host RW Local R/W 0x168 MSGU - Scratchpad 9 */
+#define V_Scratchpad_Rsvd_0_Register            0x6C    /* Host RW Local R/W 0x170 MSGU - Scratchpad 10 */
+#define V_Scratchpad_Rsvd_1_Register            0x70    /* Host RW Local R/W 0x178 MSGU - Scratchpad 11 */
+/* 0x74 - 0xFF Reserved R all 0s */
+#define V_Outbound_Queue_Consumer_Indices_Base  0x100  /*  typical value real offset is read from table to 0x1FF Host RW Local RO 0x1F100 – 0x1F1FF In DQ storage area*/
+#define V_Inbound_Queue_Producer_Indices        0x200  /*  typical value real offset is read from table to 0x3FF Host RW Local RO 0x1F200 – 0x1F3FF In DQ storage area, also mapped as WSM*/
+/*
+               SPC_V                                                 SPC
+     Bar     Name                                 Offset     Bar     Name                    Offset
+  PCIBAR0, V_Inbound_Doorbell_Set_Register,         0x00   PCIBAR0, MSGU_IBDB_SET,            0x04
+  PCIBAR0, V_Inbound_Doorbell_Clear_Register,       0x08       NA
+  PCIBAR0, V_Inbound_Doorbell_Mask_Set_Register,    0x10       NA
+  PCIBAR0, V_Inbound_Doorbell_Mask_Clear_Register,  0x18       NA
+  PCIBAR0, V_Outbound_Doorbell_Set_Register,        0x20   PCIBAR0, MSGU_ODR,                 0x3C
+  PCIBAR0, V_Outbound_Doorbell_Clear_Register,      0x28   PCIBAR0, MSGU_ODCR,                0x40
+  PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register,   0x30   PCIBAR0, MSGU_ODMR,                0x74
+  PCIBAR0, V_Outbound_Doorbell_Mask_Clear_Register, 0x38       NA
+  PCIBAR0, V_Scratchpad_0_Register,                 0x44   PCIBAR0, MSGU_SCRATCH_PAD_0,       0x44
+  PCIBAR0, V_Scratchpad_1_Register,                 0x48   PCIBAR0, MSGU_SCRATCH_PAD_1,       0x48
+  PCIBAR0, V_Scratchpad_2_Register,                 0x4C   PCIBAR0, MSGU_SCRATCH_PAD_2,       0x4C
+  PCIBAR0, V_Scratchpad_3_Register,                 0x50   PCIBAR0, MSGU_SCRATCH_PAD_3,       0x50
+  PCIBAR0, V_Host_Scratchpad_0_Register,            0x54   PCIBAR0, MSGU_HOST_SCRATCH_PAD_0,  0x54
+  PCIBAR0, V_Host_Scratchpad_1_Register,            0x58   PCIBAR0, MSGU_HOST_SCRATCH_PAD_1,  0x58
+  PCIBAR0, V_Host_Scratchpad_2_Register,            0x5C   PCIBAR0, MSGU_HOST_SCRATCH_PAD_2,  0x5C
+  PCIBAR0, V_Host_Scratchpad_3_Register,            0x60   PCIBAR0, MSGU_HOST_SCRATCH_PAD_3,  0x60
+
+*/
+
+
+#define V_RamEccDbErr               0x00000018
+#define V_SoftResetRegister        0x1000
+#define V_MEMBASE_II_ShiftRegister 0x1010
+
+#define V_GsmConfigReset                0
+#define V_GsmReadAddrParityCheck    0x38
+#define V_GsmWriteAddrParityCheck   0x40
+#define V_GsmWriteDataParityCheck   0x48
+#define V_GsmReadAddrParityIndic    0x58
+#define V_GsmWriteAddrParityIndic   0x60
+#define V_GsmWriteDataParityIndic   0x68
+
+
+#define SPCv_Reset_Reserved             0xFFFFFF3C
+#define SPCv_Reset_Read_Mask                  0xC0
+#define SPCv_Reset_Read_NoReset               0x0
+#define SPCv_Reset_Read_NormalResetOccurred   0x40
+#define SPCv_Reset_Read_SoftResetHDAOccurred  0x80
+#define SPCv_Reset_Read_ChipResetOccurred     0xC0
+
+
+#define SPCv_Reset_Write_NormalReset      0x1
+#define SPCv_Reset_Write_SoftResetHDA     0x2
+#define SPCv_Reset_Write_ChipReset        0x3
+
+/* [31:8] Reserved -- Reserved Host R / Local R/W */
+
+/* Indicator that a controller soft reset has occurred.
+The bootloader sets this field when a soft reset occurs. Host is read only.
+[7:6]
+b00: No soft reset occurred. Device reset value.
+b01: Normal soft reset occurred.
+b10: Soft reset HDA mode occurred.
+b11: Chip reset occurred.
+Soft Reset Occurred SFT_RST_OCR
+[5:2] Reserved -- Reserved b0000 Reserved
+Host R/W / Local R
+The controller soft reset type that is required by the host side. The host sets this field and the bootloader clears it.
+b00: Ready for soft reset / normal status.
+b01: Normal soft reset.
+b10: Soft reset HDA mode.
+b11: Chip reset.
+Soft Reset Requested
+SFT_RST_RQST
+[1:0]
+ */
+
+
+
+
+/***** RevB - ODAR - Outbound DoorBell Auto-Clearing Register
+              ICT  - Interrupt Coalescing Timer Register
+              ICC  - Interrupt Coalescing Control Register
+            - BAR2(0x18), BAR1(win) *****/
+/****************** 64 KB BAR *****************/
+#define SPC_ODAR                                 0x00335C
+#define SPC_ICTIMER                              0x0033C0
+#define SPC_ICCONTROL                            0x0033C4
+
+/* BAR2(0x18), BAR1(win) */
+#define MSGU_XCBI_IBDB_REG                       0x003034 /* PCIE - Message Unit Inbound Doorbell register */
+#define MSGU_XCBI_OBDB_REG                       0x003354 /* PCIE - Message Unit Outbound Doorbell Interrupt Register */
+#define MSGU_XCBI_OBDB_MASK                      0x003358 /* PCIE - Message Unit Outbound Doorbell Interrupt Mask Register */
+#define MSGU_XCBI_OBDB_CLEAR                     0x00303C /* PCIE - Message Unit Outbound Doorbell Interrupt Clear Register */
+
+/* RB6 offset */
+#define SPC_RB6_OFFSET                           0x80C0
+
+#define RB6_MAGIC_NUMBER_RST                     0x1234   /* Magic number of soft reset for RB6 */
+
+#ifdef MSGU_ACCESS_VIA_XCBI
+#define MSGU_READ_IDR  ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_IBDB_REG)
+#define MSGU_READ_ODMR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_MASK)
+#define MSGU_READ_ODR  ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_REG)
+#define MSGU_READ_ODCR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_CLEAR)
+#else
+#define MSGU_READ_IDR  siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET)
+#define MSGU_READ_ODMR siHalRegReadExt(agRoot, GEN_MSGU_ODMR,     MSGU_ODMR)
+#define MSGU_READ_ODR  siHalRegReadExt(agRoot, GEN_MSGU_ODR,      MSGU_ODR)
+#define MSGU_READ_ODCR siHalRegReadExt(agRoot, GEN_MSGU_ODCR,     MSGU_ODCR)
+#endif
+
+/* bit definition for ODMR register */
+#define ODMR_MASK_ALL                            0xFFFFFFFF   /* mask all interrupt vector */
+#define ODMR_CLEAR_ALL                           0            /* clear all interrupt vector */
+/* bit definition for ODMR register */
+#define ODCR_CLEAR_ALL                           0xFFFFFFFF   /* mask all interrupt vector */
+
+/* bit definition for Inbound Doorbell register */
+#define IBDB_IBQ_UNFREEZE                        0x08         /* Inbound doorbell bit3 */
+#define IBDB_IBQ_FREEZE                          0x04         /* Inbound doorbell bit2 */
+#define IBDB_CFG_TABLE_RESET                     0x02         /* Inbound doorbell bit1 */
+#define IBDB_CFG_TABLE_UPDATE                    0x01         /* Inbound doorbell bit0 */
+
+#define IBDB_MPIIU                               0x08         /* Inbound doorbell bit3 - Unfreeze */
+#define IBDB_MPIIF                               0x04         /* Inbound doorbell bit2 - Freeze */
+#define IBDB_MPICT                               0x02         /* Inbound doorbell bit1 - Termination */
+#define IBDB_MPIINI                              0x01         /* Inbound doorbell bit0 - Initialization */
+
+/* bit mask definition for Scratch Pad0 register */
+#define SCRATCH_PAD0_BAR_MASK                    0xFC000000   /* bit31-26 - mask bar */
+#define SCRATCH_PAD0_OFFSET_MASK                 0x03FFFFFF   /* bit25-0  - offset mask */
+#define SCRATCH_PAD0_AAPERR_MASK                 0xFFFFFFFF   /* if AAP error state */
+
+/* state definition for Scratch Pad1 register */
+#define SCRATCH_PAD1_POR                         0x00         /* power on reset state */
+#define SCRATCH_PAD1_SFR                         0x01         /* soft reset state */
+#define SCRATCH_PAD1_ERR                         0x02         /* error state */
+#define SCRATCH_PAD1_RDY                         0x03         /* ready state */
+#define SCRATCH_PAD1_RST                         0x04         /* soft reset toggle flag */
+#define SCRATCH_PAD1_AAP1RDY_RST                 0x08         /* AAP1 ready for soft reset */
+#define SCRATCH_PAD1_STATE_MASK                  0xFFFFFFF0   /* ScratchPad1 Mask other bits 31:4, bit1-0 State */
+#define SCRATCH_PAD1_RESERVED                    0x000000F0   /* Scratch Pad1 Reserved bit 4 to 7 */
+
+
+
+#define SCRATCH_PAD1_V_RAAE_MASK                 0x00000003   /* 0 1 also  ready */
+#define SCRATCH_PAD1_V_RAAE_ERR                  0x00000002   /* 1 */
+#define SCRATCH_PAD1_V_ILA_MASK                  0x0000000C   /* 2 3 also  ready */
+#define SCRATCH_PAD1_V_ILA_ERR                   0x00000008   /* 3  */
+#define SCRATCH_PAD1_V_BOOTSTATE_MASK            0x00000070   /* 456 */
+#define SCRATCH_PAD1_V_BOOTSTATE_SUCESS          0x00000000   /* Load successful */
+#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM     0x00000010   /* HDA Mode SEEPROM Setting */
+#define SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP   0x00000020   /* HDA Mode BootStrap Setting */
+#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET   0x00000030   /* HDA Mode Soft Reset */
+#define SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR      0x00000040   /* HDA Mode due to critical error */
+#define SCRATCH_PAD1_V_BOOTSTATE_R1              0x00000050   /* Reserved */
+#define SCRATCH_PAD1_V_BOOTSTATE_R2              0x00000060   /* Reserved */
+#define SCRATCH_PAD1_V_BOOTSTATE_FATAL           0x00000070   /* Fatal Error  Boot process halted */
+
+
+#define SCRATCH_PAD1_V_ILA_IMAGE                 0x00000080   /* 7 */
+#define SCRATCH_PAD1_V_FW_IMAGE                  0x00000100   /* 8 */
+#define SCRATCH_PAD1_V_BIT9_RESERVED             0x00000200   /* 9 */
+#define SCRATCH_PAD1_V_IOP0_MASK                 0x00000C00   /* 10 11 also ready  */
+#define SCRATCH_PAD1_V_IOP0_ERR                  0x00000800   /* 11   */
+#define SCRATCH_PAD1_V_IOP1_MASK                 0x00003000   /* 12 13 also ready */
+#define SCRATCH_PAD1_V_IOP1_ERR                  0x00002000   /* 13  */
+#define SCRATCH_PAD1_V_RESERVED                  0xFFFFC000   /* 14-31  */
+
+#define SCRATCH_PAD1_V_READY                    ( SCRATCH_PAD1_V_RAAE_MASK | SCRATCH_PAD1_V_ILA_MASK | SCRATCH_PAD1_V_IOP0_MASK ) /*  */
+#define SCRATCH_PAD1_V_ERROR                    ( SCRATCH_PAD1_V_RAAE_ERR  | SCRATCH_PAD1_V_ILA_ERR  | SCRATCH_PAD1_V_IOP0_ERR  | SCRATCH_PAD1_V_IOP1_ERR  )  /* Scratch Pad1 13 11 3 1 */
+
+#define SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1)  ((((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_MASK) ?  0: \
+                                                      (((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_ERR ) ?  SCRATCH_PAD1_V_ILA_ERR : 0 )
+
+#define SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_MASK) ?  0: \
+                                                      (((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_ERR)  ?  SCRATCH_PAD1_V_RAAE_ERR : 0 )
+
+#define SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_MASK) ?  0: \
+                                                      (((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_ERR)  ?  SCRATCH_PAD1_V_IOP0_ERR : 0 )
+
+#define SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_MASK) ?  0: \
+                                                      (((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_ERR)  ?  SCRATCH_PAD1_V_IOP1_ERR : 0 )
+
+#define SCRATCH_PAD1_V_ERROR_STATE(ScratchPad1) ( SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1)  | \
+                                                  SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) | \
+                                                  SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) | \
+                                                  SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) )
+
+#define SCRATCH_PAD1_V_BOOTLDR_ERROR             0x00000070   /* Scratch Pad1 (6 5 4) */
+
+
+/* error bit definition */
+#define SCRATCH_PAD1_BDMA_ERR                    0x80000000   /* bit31 */
+#define SCRATCH_PAD1_GSM_ERR                     0x40000000   /* bit30 */
+#define SCRATCH_PAD1_MBIC1_ERR                   0x20000000   /* bit29 */
+#define SCRATCH_PAD1_MBIC1_SET0_ERR              0x10000000   /* bit28 */
+#define SCRATCH_PAD1_MBIC1_SET1_ERR              0x08000000   /* bit27 */
+#define SCRATCH_PAD1_PMIC1_ERR                   0x04000000   /* bit26 */
+#define SCRATCH_PAD1_PMIC2_ERR                   0x02000000   /* bit25 */
+#define SCRATCH_PAD1_PMIC_EVENT_ERR              0x01000000   /* bit24 */
+#define SCRATCH_PAD1_OSSP_ERR                    0x00800000   /* bit23 */
+#define SCRATCH_PAD1_SSPA_ERR                    0x00400000   /* bit22 */
+#define SCRATCH_PAD1_SSPL_ERR                    0x00200000   /* bit21 */
+#define SCRATCH_PAD1_HSST_ERR                    0x00100000   /* bit20 */
+#define SCRATCH_PAD1_PCS_ERR                     0x00080000   /* bit19 */
+#define SCRATCH_PAD1_FW_INIT_ERR                 0x00008000   /* bit15 */
+#define SCRATCH_PAD1_FW_ASRT_ERR                 0x00004000   /* bit14 */
+#define SCRATCH_PAD1_FW_WDG_ERR                  0x00002000   /* bit13 */
+#define SCRATCH_PAD1_AAP_ERROR_STATE             0x00000002   /* bit1 */
+#define SCRATCH_PAD1_AAP_READY                   0x00000003   /* bit1 & bit0 */
+
+
+/* state definition for Scratch Pad2 register */
+#define SCRATCH_PAD2_POR                         0x00         /* power on state */
+#define SCRATCH_PAD2_SFR                         0x01         /* soft reset state */
+#define SCRATCH_PAD2_ERR                         0x02         /* error state */
+#define SCRATCH_PAD2_RDY                         0x03         /* ready state */
+#define SCRATCH_PAD2_FWRDY_RST                   0x04         /* FW ready for soft reset rdy flag */
+#define SCRATCH_PAD2_IOPRDY_RST                  0x08         /* IOP ready for soft reset */
+#define SCRATCH_PAD2_STATE_MASK                  0xFFFFFFF0   /* ScratchPad 2 Mask for other bits 31:4, bit1-0 State*/
+#define SCRATCH_PAD2_RESERVED                    0x000000F0   /* Scratch Pad1 Reserved bit 4 to 7 */
+
+/* error bit definition */
+#define SCRATCH_PAD2_BDMA_ERR                    0x80000000   /* bit31 */
+#define SCRATCH_PAD2_GSM_ERR                     0x40000000   /* bit30 */
+#define SCRATCH_PAD2_MBIC3_ERR                   0x20000000   /* bit29 */
+#define SCRATCH_PAD2_MBIC3_SET0_ERR              0x10000000   /* bit28 */
+#define SCRATCH_PAD2_MBIC3_SET1_ERR              0x08000000   /* bit27 */
+#define SCRATCH_PAD2_PMIC1_ERR                   0x04000000   /* bit26 */
+#define SCRATCH_PAD2_PMIC2_ERR                   0x02000000   /* bit25 */
+#define SCRATCH_PAD2_PMIC_EVENT_ERR              0x01000000   /* bit24 */
+#define SCRATCH_PAD2_OSSP_ERR                    0x00800000   /* bit23 */
+#define SCRATCH_PAD2_SSPA_ERR                    0x00400000   /* bit22 */
+#define SCRATCH_PAD2_SSPL_ERR                    0x00200000   /* bit21 */
+#define SCRATCH_PAD2_HSST_ERR                    0x00100000   /* bit20 */
+#define SCRATCH_PAD2_PCS_ERR                     0x00080000   /* bit19 */
+
+#define SCRATCH_PAD2_FW_BOOT_ROM_ERROR           0x00010000   /* bit16 */
+#define SCRATCH_PAD2_FW_ILA_ERR                  0x00008000   /* bit15 */
+#define SCRATCH_PAD2_FW_FLM_ERR                  0x00004000   /* bit14 */
+#define SCRATCH_PAD2_FW_FW_ASRT_ERR              0x00002000   /* bit13 */
+#define SCRATCH_PAD2_FW_HW_WDG_ERR               0x00001000   /* bit12 */
+#define SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR        0x00000800   /* bit11 */
+#define SCRATCH_PAD2_FW_UNDTMN_ERR               0x00000400   /* bit10 */
+#define SCRATCH_PAD2_FW_HW_FATAL_ERR             0x00000200   /* bit9 */
+#define SCRATCH_PAD2_FW_HW_NON_FATAL_ERR         0x00000100   /* bit8 */
+#define SCRATCH_PAD2_FW_HW_MASK                  0x000000FF
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR                     0x00
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR                     0x01
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR                   0x02
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR                   0x03
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR                   0x04
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR                   0x05
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR                     0x06
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR               0x08
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR                 0x0C
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR                    0x0E
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR                    0x0F
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR                    0x10
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR                 0x13
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR                  0x14
+#define SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0xFF
+
+
+
+#define SCRATCH_PAD_ERROR_MASK                   0xFFFFFF00   /* Error mask bits 31:8 */
+#define SCRATCH_PAD_STATE_MASK                   0x00000003   /* State Mask bits 1:0 */
+
+#define SPCV_RAAE_STATE_MASK                          0x3
+#define SPCV_IOP0_STATE_MASK                          ((1 << 10) | (1 << 11))
+#define SPCV_IOP1_STATE_MASK                          ((1 << 12) | (1 << 13))
+#define SPCV_ERROR_VALUE                              0x2
+
+
+#define SCRATCH_PAD3_FW_IMAGE_MASK               0x0000000F   /* SPC 8x6G boots from Image */
+#define SCRATCH_PAD3_FW_IMAGE_FLAG_VALID         0x00000008   /* Image flag is valid */
+#define SCRATCH_PAD3_FW_IMAGE_B_VALID            0x00000004   /* Image B is valid */
+#define SCRATCH_PAD3_FW_IMAGE_A_VALID            0x00000002   /* Image A is valid */
+#define SCRATCH_PAD3_FW_IMAGE_B_ACTIVE           0x00000001   /* Image B is active */
+
+
+#define SCRATCH_PAD3_V_            0x00000001   /* Image B is valid */
+
+#define SCRATCH_PAD3_V_ENC_DISABLED              0x00000000   /*  */
+#define SCRATCH_PAD3_V_ENC_DIS_ERR               0x00000001   /*  */
+#define SCRATCH_PAD3_V_ENC_ENA_ERR               0x00000002   /*  */
+#define SCRATCH_PAD3_V_ENC_READY                 0x00000003   /*  */
+#define SCRATCH_PAD3_V_ENC_MASK    SCRATCH_PAD3_V_ENC_READY   /*  */
+
+#define SCRATCH_PAD3_V_AUT                        0x00000008    /* AUT Operator authentication*/
+#define SCRATCH_PAD3_V_ARF                        0x00000004    /* ARF factory mode. */
+
+#define SCRATCH_PAD3_V_XTS_ENABLED               (1 << SHIFT14) /*  */
+#define SCRATCH_PAD3_V_SMA_ENABLED               (1 << SHIFT4 ) /*  */
+#define SCRATCH_PAD3_V_SMB_ENABLED               (1 << SHIFT5 ) /*  */
+#define SCRATCH_PAD3_V_SMF_ENABLED               0 /*  */
+#define SCRATCH_PAD3_V_SM_MASK                   0x000000F0    /*  */
+#define SCRATCH_PAD3_V_ERR_CODE                  0x00FF0000    /*  */
+
+
+/* Dynamic map through Bar4 - 0x00700000 */
+#define GSM_CONFIG_RESET                         0x00000000
+#define RAM_ECC_DB_ERR                           0x00000018
+#define GSM_READ_ADDR_PARITY_INDIC               0x00000058
+#define GSM_WRITE_ADDR_PARITY_INDIC              0x00000060
+#define GSM_WRITE_DATA_PARITY_INDIC              0x00000068
+#define GSM_READ_ADDR_PARITY_CHECK               0x00000038
+#define GSM_WRITE_ADDR_PARITY_CHECK              0x00000040
+#define GSM_WRITE_DATA_PARITY_CHECK              0x00000048
+
+/* signature defintion for host scratch pad0 register */
+#define SPC_SOFT_RESET_SIGNATURE                 0x252acbcd   /* Signature for Soft Reset */
+#define SPC_HDASOFT_RESET_SIGNATURE              0xa5aa27d7   /* Signature for HDA Soft Reset without PCIe resetting */
+
+/**** SPC Top-level Registers definition for Soft Reset/HDA mode ****/
+/****************** 64 KB BAR *****************/
+/* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
+#define SPC_REG_RESET                            0x000000   /* reset register */
+#define SPC_REG_DEVICE_LCLK                      0x000058   /* Device LCLK generation register */
+
+#define SPC_READ_RESET_REG siHalRegReadExt(agRoot, GEN_SPC_REG_RESET, SPC_REG_RESET)
+
+#define SPC_WRITE_RESET_REG(value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, value);
+/* NMI register - BAR4(0x20), BAR2(win) 0x060000/0x070000 */
+//#define MBIC_RAW_NMI_STAT_VPE0_IOP               0x0004C8 not used anymore
+//#define MBIC_RAW_NMI_STAT_VPE0_AAP1              0x0104C8 not used anymore
+#define MBIC_NMI_ENABLE_VPE0_IOP                 0x000418
+#define MBIC_NMI_ENABLE_VPE0_AAP1                0x000418
+
+/* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
+#define PCIE_EVENT_INTERRUPT_ENABLE              0x003040
+#define PCIE_EVENT_INTERRUPT                     0x003044
+#define PCIE_ERROR_INTERRUPT_ENABLE              0x003048
+#define PCIE_ERROR_INTERRUPT                     0x00304C
+
+/* PCIe Message Unit Configuration Registers offset - BAR2(0x18), BAR1(win) 0x010000 */
+#define SPC_REG_MSGU_CONFIG                      0x003018
+#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE       0x00000010
+
+/* bit difination for SPC_RESET register */
+#define   SPC_REG_RESET_OSSP                     0x00000001
+#define   SPC_REG_RESET_RAAE                     0x00000002
+#define   SPC_REG_RESET_PCS_SPBC                 0x00000004
+#define   SPC_REG_RESET_PCS_IOP_SS               0x00000008
+#define   SPC_REG_RESET_PCS_AAP1_SS              0x00000010
+#define   SPC_REG_RESET_PCS_AAP2_SS              0x00000020
+#define   SPC_REG_RESET_PCS_LM                   0x00000040
+#define   SPC_REG_RESET_PCS                      0x00000080
+#define   SPC_REG_RESET_GSM                      0x00000100
+#define   SPC_REG_RESET_DDR2                     0x00010000
+#define   SPC_REG_RESET_BDMA_CORE                0x00020000
+#define   SPC_REG_RESET_BDMA_SXCBI               0x00040000
+#define   SPC_REG_RESET_PCIE_AL_SXCBI            0x00080000
+#define   SPC_REG_RESET_PCIE_PWR                 0x00100000
+#define   SPC_REG_RESET_PCIE_SFT                 0x00200000
+#define   SPC_REG_RESET_PCS_SXCBI                0x00400000
+#define   SPC_REG_RESET_LMS_SXCBI                0x00800000
+#define   SPC_REG_RESET_PMIC_SXCBI               0x01000000
+#define   SPC_REG_RESET_PMIC_CORE                0x02000000
+#define   SPC_REG_RESET_PCIE_PC_SXCBI            0x04000000
+#define   SPC_REG_RESET_DEVICE                   0x80000000
+
+/* bit definition for SPC Device Revision register - BAR1 */
+#define SPC_REG_DEVICE_REV                       0x000024
+#define SPC_REG_DEVICE_REV_MASK                  0x0000000F
+
+
+/* bit definition for SPC_REG_TOP_DEVICE_ID  - BAR2 */
+#define SPC_REG_TOP_DEVICE_ID                    0x20
+#define SPC_TOP_DEVICE_ID                        0x8001
+
+#define SPC_REG_TOP_BOOT_STRAP                   0x8
+#define SPC_TOP_BOOT_STRAP                       0x02C0A682
+
+
+/* For PHY Error */
+#define COUNT_OFFSET                             0x4000
+#define LCLK_CLEAR                               0x2
+#define LCLK                                     0x1
+#define CNTL_OFFSET                              0x100
+#define L0_LCLK_CLEAR                            0x2
+#define L0_LCLK                                  0x1
+#define DEVICE_LCLK_CLEAR                        0x40
+
+/****************** 64 KB BAR *****************/
+/* PHY Error Count Registers - BAR4(0x20), BAR2(win) (need dynamic mapping) */
+#define SPC_SSPL_COUNTER_CNTL                    0x001030
+#define SPC_INVALID_DW_COUNT                     0x001034
+#define SPC_RUN_DISP_ERROR_COUNT                 0x001038
+#define SPC_CODE_VIOLATION_COUNT                 0x00103C
+#define SPC_LOSS_DW_SYNC_COUNT                   0x001040
+#define SPC_PHY_RESET_PROBLEM_COUNT              0x001044
+#define SPC_READ_DEV_REV ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_REV);
+
+#define SPC_READ_COUNTER_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId))
+#define SPC_WRITE_COUNTER_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId), value)
+#define SPC_READ_INV_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_INVALID_DW_COUNT + (COUNT_OFFSET * phyId))
+#define SPC_READ_DISP_ERR_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_RUN_DISP_ERROR_COUNT + (COUNT_OFFSET * phyId))
+#define SPC_READ_CODE_VIO_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_CODE_VIOLATION_COUNT + (COUNT_OFFSET * phyId))
+#define SPC_READ_LOSS_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_LOSS_DW_SYNC_COUNT + (COUNT_OFFSET * phyId))
+#define SPC_READ_PHY_RESET_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_PHY_RESET_PROBLEM_COUNT + (COUNT_OFFSET * phyId))
+/* PHY Error Count Control Registers - BAR2(0x18), BAR1(win) */
+#define SPC_L0_ERR_CNT_CNTL                      0x0041B0
+#define SPC_READ_L0ERR_CNT_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId))
+#define SPC_WRITE_L0ERR_CNT_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId), value)
+
+/* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
+#define SPC_IBW_AXI_TRANSLATION_LOW              0x003258
+
+/* HDA mode definitions */
+/* 256KB */
+#define HDA_CMD_OFFSET256K                       0x0003FFC0
+#define HDA_RSP_OFFSET256K                       0x0003FFE0
+
+/* 512KB */
+#define HDA_CMD_OFFSET512K                       0x0007FFC0
+#define HDA_RSP_OFFSET512K                       0x0007FFE0
+
+/* 768KB */
+#define HDA_CMD_OFFSET768K                       0x000BFFC0
+#define HDA_RSP_OFFSET768K                       0x000BFFE0
+
+/* 1024KB - by default */
+#define HDA_CMD_OFFSET1MB                        0x0000FEC0
+#define HDA_RSP_OFFSET1MB                        0x0000FEE0
+
+
+
+/*  Table 27 Boot ROM HDA Protocol Command Format */
+typedef struct spcv_hda_cmd_s {
+/*  Offset Byte 3 Byte 2 Byte 1 Byte 0 */
+  bit32 cmdparm_0;            /*  0 Command Parameter 0 */
+  bit32 cmdparm_1;            /*  4 Command Parameter 1 */
+  bit32 cmdparm_2;            /*  8 Command Parameter 2 */
+  bit32 cmdparm_3;            /*  12 Command Parameter 3 */
+  bit32 cmdparm_4;            /*  16 Command Parameter 4 */
+  bit32 cmdparm_5;            /*  20 Command Parameter 5 */
+  bit32 cmdparm_6;            /*  24 Command Parameter 6 */
+  bit32 C_PA_SEQ_ID_CMD_CODE; /*  28 C_PA SEQ_ID CMD_CODE */
+} spcv_hda_cmd_t;
+
+/* Table 28 Boot ROM HDA Protocol Response Format  */
+typedef struct spcv_hda_rsp_s {
+/*  Offset Byte 3 Byte 2 Byte 1 Byte 0 */
+  bit32 cmdparm_0;            /*  0 Command Parameter 0 */
+  bit32 cmdparm_1;            /*  4 Command Parameter 1 */
+  bit32 cmdparm_2;            /*  8 Command Parameter 2 */
+  bit32 cmdparm_3;            /*  12 Command Parameter 3 */
+  bit32 cmdparm_4;            /*  16 Command Parameter 4 */
+  bit32 cmdparm_5;            /*  20 Command Parameter 5 */
+  bit32 cmdparm_6;            /*  24 Command Parameter 6 */
+  bit32 R_PA_SEQ_ID_RSP_CODE; /*  28 C_PA SEQ_ID CMD_CODE */
+} spcv_hda_rsp_t;
+
+#define SPC_V_HDA_COMMAND_OFFSET  0x000042c0
+#define SPC_V_HDA_RESPONSE_OFFSET 0x000042e0
+
+
+#define HDA_C_PA_OFFSET                          0x1F
+#define HDA_SEQ_ID_OFFSET                        0x1E
+#define HDA_PAR_LEN_OFFSET                       0x04
+#define HDA_CMD_CODE_OFFSET                      0x1C
+#define HDA_RSP_CODE_OFFSET                      0x1C
+#define SM_HDA_RSP_OFFSET1MB_PLUS_HDA_RSP_CODE_OFFSET    (HDA_RSP_OFFSET1MB + HDA_RSP_CODE_OFFSET)
+
+/* commands */
+#define SPC_V_HDAC_PA                         0xCB
+#define SPC_V_HDAC_BUF_INFO                   0x0001
+#define SPC_V_HDAC_EXEC                       0x0002
+#define SPC_V_HDAC_RESET                      0x0003
+#define SPC_V_HDAC_DMA                        0x0004
+
+#define SPC_V_HDAC_PA_MASK                    0xFF000000
+#define SPC_V_HDAC_SEQID_MASK                 0x00FF0000
+#define SPC_V_HDAC_CMDCODE_MASK               0x0000FFFF
+
+/* responses */
+#define SPC_V_HDAR_PA                         0xDB
+#define SPC_V_HDAR_BUF_INFO                   0x8001
+#define SPC_V_HDAR_IDLE                       0x8002
+#define SPC_V_HDAR_BAD_IMG                    0x8003
+#define SPC_V_HDAR_BAD_CMD                    0x8004
+#define SPC_V_HDAR_INTL_ERR                   0x8005
+#define SPC_V_HDAR_EXEC                       0x8006
+
+#define SPC_V_HDAR_PA_MASK                    0xFF000000
+#define SPC_V_HDAR_SEQID_MASK                 0x00FF0000
+#define SPC_V_HDAR_RSPCODE_MASK               0x0000FFFF
+
+#define ILAHDA_RAAE_IMG_GET                   0x11
+#define ILAHDA_IOP_IMG_GET                    0x10
+
+#define ILAHDAC_RAAE_IMG_DONE                 0x81
+
+
+#define HDA_AES_DIF_FUNC                      0xFEDFAE1F
+
+
+/* Set MSGU Mapping Registers in BAR0 */
+#define PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE        0x00000001
+#define PMIC_MU_CFG_1_BITMSK_MU_IO_WIR           0x0000000C
+#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE       0x00000010
+#define PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET       0xFFFFFC00
+
+/* PMIC Init */
+#define MU_MEM_OFFSET                            0x0
+#define MSGU_MU_IO_WIR                           0x8            /* Window 0 */
+
+#define BOOTTLOADERHDA_IDLE                      0x8002
+#define HDAR_BAD_IMG                             0x8003
+#define HDAR_BAD_CMD                             0x8004
+#define HDAR_EXEC                                0x8006
+
+#define CEILING(X, rem) ((((bit32)X % rem) > 0) ? (bit32)(X/rem+1) : (bit32)(X/rem))
+
+#define GSMSM_AXI_LOWERADDR                      0x00400000
+#define SHIFT_MASK                               0xFFFF0000
+#define OFFSET_MASK                              0x0000FFFF
+#define SIZE_64KB                                0x00010000
+#define ILA_ISTR_ADDROFFSETHDA                   0x0007E000
+#define HDA_STATUS_BITS                          0x0000FFFF
+
+/* Scratchpad Reg: bit[31]: 1-CMDFlag 0-RSPFlag; bit[30,24]:CMD/RSP; bit[23,0]:Offset/Size - Shared with the host driver */
+/* ILA: Mandatory response / state codes in MSGU Scratchpad 0 */
+#define ILAHDA_IOP_IMG_GET                       0x10
+#define ILAHDA_AAP1_IMG_GET                      0x11
+#define ILAHDA_AAP2_IMG_GET                      0x12
+#define ILAHDA_EXITGOOD                          0x1F
+
+/* HOST: Mandatory command codes in Host Scratchpad 3 */
+#define ILAHDAC_IOP_IMG_DONE                     0x00000080
+#define ILAHDAC_AAP1_IMG_DONE                    0x00000081
+#define ILAHDAC_AAP2_IMG_DONE                    0x00000082
+#define ILAHDAC_ISTR_IMG_DONE                    0x00000083
+#define ILAHDAC_GOTOHDA                          0x000000ff
+
+#define HDA_ISTR_DONE                            (bit32)(ILAHDAC_ISTR_IMG_DONE << 24)
+#define HDA_AAP1_DONE                            (bit32)(ILAHDAC_AAP1_IMG_DONE << 24)
+#define HDA_IOP_DONE                             (bit32)(ILAHDAC_IOP_IMG_DONE << 24)
+
+#define RB6_ACCESS_REG                           0x6A0000
+#define HDAC_EXEC_CMD                            0x0002
+#define HDA_C_PA                                 0xcb
+#define HDA_SEQ_ID_BITS                          0x00ff0000
+#define HDA_GSM_OFFSET_BITS                      0x00FFFFFF
+#define MBIC_AAP1_ADDR_BASE                      0x060000
+#define MBIC_GSM_SM_BASE                         0x04F0000
+#define MBIC_IOP_ADDR_BASE                       0x070000
+#define GSM_ADDR_BASE                            0x0700000
+#define SPC_TOP_LEVEL_ADDR_BASE                  0x000000
+#define GSM_CONFIG_RESET_VALUE                   0x00003b00
+#define GPIO_ADDR_BASE                           0x00090000
+#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET            0x0000010c
+
+
+/* Scratchpad registers for fatal errors */
+#define SA_FATAL_ERROR_SP1_AAP1_ERR_MASK        0x3
+#define SA_FATAL_ERROR_SP2_IOP_ERR_MASK         0x3
+#define SA_FATAL_ERROR_FATAL_ERROR              0x2
+
+/* PCIe Analyzer trigger */
+#define PCIE_TRIGGER_ON_REGISTER_READ          V_Host_Scratchpad_2_Register    /* PCI trigger on this offset */
+
+#define PCI_TRIGGER_INIT_TEST                 1 /* Setting adjustable paramater PciTrigger to match this value */
+#define PCI_TRIGGER_OFFSET_MISMATCH           2 /* Setting adjustable paramater PciTrigger to match this value */
+#define PCI_TRIGGER_COAL_IOMB_ERROR           4 /* Setting adjustable paramater PciTrigger to match this value */
+#define PCI_TRIGGER_COAL_INVALID              8 /* Setting adjustable paramater PciTrigger to match this value */
+
+
+
+
+/*                                                                   */
+
+enum spc_spcv_offsetmap_e
+{
+  GEN_MSGU_IBDB_SET=0,
+  GEN_MSGU_ODR,
+  GEN_MSGU_ODCR,
+  GEN_MSGU_SCRATCH_PAD_0,
+  GEN_MSGU_SCRATCH_PAD_1,
+  GEN_MSGU_SCRATCH_PAD_2,
+  GEN_MSGU_SCRATCH_PAD_3,
+  GEN_MSGU_HOST_SCRATCH_PAD_0,
+  GEN_MSGU_HOST_SCRATCH_PAD_1,
+  GEN_MSGU_HOST_SCRATCH_PAD_2,
+  GEN_MSGU_HOST_SCRATCH_PAD_3,
+  GEN_MSGU_ODMR,
+  GEN_PCIE_TRIGGER,
+  GEN_SPC_REG_RESET,
+};
+
+
+#endif  /*__SAHWREG_H__ */
+
+
+
+

sys/dev/pms/RefTisa/sallsdk/spc/sallist.h

@@ -0,0 +1,443 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file sallist.h
+ *  \brief The file contains link list manipulation helper routines
+ *
+ */
+/*******************************************************************************/
+
+#ifndef __SALLIST_H__
+#define __SALLIST_H__
+
+
+/********************************************************************
+*********************************************************************
+**   DATA STRUCTURES
+********************************************************************/
+
+/** \brief Structure of Link Data
+ *
+ *  link data, need to be included at the start (offset 0)
+ *  of any strutures that are to be stored in the link list
+ *
+ */
+typedef struct _SALINK
+{
+  struct _SALINK *pNext;
+  struct _SALINK *pPrev;
+
+  /*
+  ** for assertion purpose only
+  */
+  struct _SALINK * pHead;     /* track the link list the link is a member of */
+
+} SALINK, * PSALINK;
+
+/** \brief Structure of Link List
+ *
+ * link list basic pointers
+ *
+ */
+typedef struct _SALINK_LIST
+{
+  PSALINK pHead;
+  bit32   Count;
+
+  SALINK  Head; /* allways one link to speed up insert and delete */
+
+} SALINK_LIST, * PSALINK_LIST;
+
+
+/********************************************************************
+*********************************************************************
+** MACROS
+********************************************************************/
+
+/*! \def saLlistInitialize(pList)
+* \brief saLlistInitialize macro
+*
+* use to initialize a Link List
+*/
+/*******************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistInitialize
+**
+** PURPOSE:     Initialize a link list.
+**
+** PARAMETERS:  PSALINK_LIST  OUT - Link list definition.
+**
+** SIDE EFFECTS & CAVEATS:
+**
+** ALGORITHM:
+**
+********************************************************************************/
+/*lint -emacro(613,saLlistInitialize) */
+
+#define saLlistInitialize(pList) {(pList)->pHead        = &((pList)->Head); \
+                                  (pList)->pHead->pNext = (pList)->pHead;   \
+                                  (pList)->pHead->pPrev = (pList)->pHead;   \
+                                  (pList)->Count        = 0;                \
+                                 }
+
+#define saLlistIOInitialize(pList){(pList)->pHead        = &((pList)->Head); \
+                                  (pList)->pHead->pNext = (pList)->pHead;   \
+                                  (pList)->pHead->pPrev = (pList)->pHead;   \
+                                  (pList)->Count        = 0;                \
+                                 }
+/*! \def saLlinkInitialize(pLink)
+* \brief saLlinkInitialize macro
+*
+* use to initialize a Link
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlinkInitialize
+**
+** PURPOSE:     Initialize a link.
+**              This function should be used to initialize a new link before it
+**              is used in the linked list. This will initialize the link so
+**              the assertion will work
+**
+** PARAMETERS:  PSALINK      IN  - Link to be initialized.
+**
+** SIDE EFFECTS & CAVEATS:
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+
+/*lint -emacro(613,saLlinkInitialize) */
+
+#define saLlinkInitialize(pLink) { (pLink)->pHead = agNULL;    \
+                                   (pLink)->pNext = agNULL;    \
+                                   (pLink)->pPrev = agNULL;    \
+                                 }
+
+#define saLlinkIOInitialize(pLink) { (pLink)->pHead = agNULL;    \
+                                   (pLink)->pNext = agNULL;    \
+                                   (pLink)->pPrev = agNULL;    \
+                                 }
+/*! \def saLlistAdd(pList, pLink)
+* \brief saLlistAdd macro
+*
+* use to add a link to the tail of list
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistAdd
+**
+** PURPOSE:     add a link at the tail of the list
+**
+** PARAMETERS:  PSALINK_LIST OUT - Link list definition.
+**              PSALINK      IN  - Link to be inserted.
+**
+** SIDE EFFECTS & CAVEATS:
+**   !!! assumes that fcllistInitialize has been called on the linklist
+**   !!! if not, this function behavior is un-predictable
+**
+**   The OS_ASSERT() is an assignment for debug code only
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+
+/*lint -emacro(506,saLlistAdd) */
+/*lint -emacro(613,saLlistAdd) */
+/*lint -emacro(666,saLlistAdd) */
+/*lint -emacro(720,saLlistAdd) */
+
+#define saLlistAdd(pList, pLink) {                                          \
+                             (pLink)->pNext        = (pList)->pHead;        \
+                             (pLink)->pPrev        = (pList)->pHead->pPrev; \
+                             (pLink)->pPrev->pNext = (pLink);               \
+                             (pList)->pHead->pPrev = (pLink);               \
+                             (pList)->Count ++;                             \
+                             (pLink)->pHead = (pList)->pHead;               \
+                             }
+
+#define saLlistIOAdd(pList, pLink) {                                        \
+                             (pLink)->pNext        = (pList)->pHead;        \
+                             (pLink)->pPrev        = (pList)->pHead->pPrev; \
+                             (pLink)->pPrev->pNext = (pLink);               \
+                             (pList)->pHead->pPrev = (pLink);               \
+                             (pList)->Count ++;                             \
+                             (pLink)->pHead = (pList)->pHead;               \
+                             }
+
+/*! \def saLlistInsert(pList, pLink, pNew)
+* \brief saLlistInsert macro
+*
+* use to insert a link preceding the given one
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistInsert
+**
+** PURPOSE:     insert a link preceding the given one
+**
+** PARAMETERS:  PSALINK_LIST OUT - Link list definition.
+**              PSALINK      IN  - Link to be inserted after.
+**              PSALINK      IN  - Link to be inserted.
+**
+** SIDE EFFECTS & CAVEATS:
+**   !!! assumes that fcllistInitialize has been called on the linklist
+**   !!! if not, this function behavior is un-predictable
+**
+**   The OS_ASSERT() is an assignment for debug code only
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+
+/*lint -emacro(506,saLlistInsert) */
+/*lint -emacro(613,saLlistInsert) */
+/*lint -emacro(666,saLlistInsert) */
+/*lint -emacro(720,saLlistInsert) */
+
+#define saLlistInsert(pList, pLink, pNew) {                                 \
+                                 (pNew)->pNext        = (pLink);            \
+                                 (pNew)->pPrev        = (pLink)->pPrev;     \
+                                 (pNew)->pPrev->pNext = (pNew);             \
+                                 (pLink)->pPrev       = (pNew);             \
+                                 (pList)->Count ++;                         \
+                                 (pNew)->pHead = (pList)->pHead;            \
+                                 }
+
+/*! \def saLlistRemove(pList, pLink)
+* \brief saLlistRemove macro
+*
+* use to remove the link from the list
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistRemove
+**
+** PURPOSE:     remove the link from the list.
+**
+** PARAMETERS:  PSALINK_LIST OUT  - Link list definition.
+**              PSALINK      IN   - Link to delet from list
+**
+** SIDE EFFECTS & CAVEATS:
+**   !!! assumes that fcllistInitialize has been called on the linklist
+**   !!! if not, this function behavior is un-predictable
+**
+**   !!! No validation is made on the list or the validity of the link
+**   !!! the caller must make sure that the link is in the list
+**
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+
+/*lint -emacro(506,saLlistRemove) */
+/*lint -emacro(613,saLlistRemove) */
+/*lint -emacro(666,saLlistRemove) */
+/*lint -emacro(720,saLlistRemove) */
+
+#define saLlistRemove(pList, pLink) {                                   \
+                           (pLink)->pPrev->pNext = (pLink)->pNext;      \
+                           (pLink)->pNext->pPrev = (pLink)->pPrev;      \
+                           (pLink)->pHead = agNULL;                     \
+                           (pList)->Count --;                           \
+                           }
+
+#define saLlistIORemove(pList, pLink) {                                 \
+                           (pLink)->pPrev->pNext = (pLink)->pNext;      \
+                           (pLink)->pNext->pPrev = (pLink)->pPrev;      \
+                           (pLink)->pHead = agNULL;                     \
+                           (pList)->Count --;                           \
+                           }
+/*! \def saLlistGetHead(pList)
+* \brief saLlistGetHead macro
+*
+* use to get the link following the head link
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistGetHead
+**
+** PURPOSE:     get the link following the head link.
+**
+** PARAMETERS:  PSALINK_LIST  OUT - Link list definition.
+**              RETURNS - PSALINK   the link following the head
+**                                  agNULL if the following link is the head
+**
+** SIDE EFFECTS & CAVEATS:
+**   !!! assumes that fcllistInitialize has been called on the linklist
+**   !!! if not, this function behavior is un-predictable
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+#define saLlistGetHead(pList) saLlistGetNext(pList,(pList)->pHead)
+
+#define saLlistIOGetHead(pList) saLlistGetNext(pList,(pList)->pHead)
+
+/*! \def saLlistGetTail(pList)
+* \brief saLlistGetTail macro
+*
+* use to get the link preceding the tail link
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistGetTail
+**
+** PURPOSE:     get the link preceding the tail link.
+**
+** PARAMETERS:  PSALINK_LIST  OUT - Link list definition.
+**              RETURNS - PSALINK   the link preceding the head
+**                                  agNULL if the preceding link is the head
+**
+** SIDE EFFECTS & CAVEATS:
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+#define saLlistGetTail(pList) saLlistGetPrev((pList), (pList)->pHead)
+
+/*! \def saLlistGetCount(pList)
+* \brief saLlistGetCount macro
+*
+* use to get the number of links in the list excluding head and tail
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistGetCount
+**
+** PURPOSE:     get the number of links in the list excluding head and tail.
+**
+** PARAMETERS:  PSALINK_LIST  OUT - Link list definition.
+**
+** SIDE EFFECTS & CAVEATS:
+**   !!! assumes that fcllistInitialize has been called on the linklist
+**   !!! if not, this function behavior is un-predictable
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+
+/*lint -emacro(613,saLlistGetCount) */
+/*lint -emacro(666,saLlistGetCount) */
+
+#define saLlistGetCount(pList) ((pList)->Count)
+
+#define saLlistIOGetCount(pList) ((pList)->Count)
+
+/*! \def saLlistGetNext(pList, pLink)
+* \brief saLlistGetNext macro
+*
+* use to get the next link in the list
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistGetNext
+**
+** PURPOSE:     get the next link in the list. (one toward tail)
+**
+** PARAMETERS:  PSALINK_LIST  OUT - Link list definition.
+**              PSALINK       IN  - Link to get next to
+**
+**           return PLINK  - points to next link
+**                           agNULL if next link is head
+**
+** SIDE EFFECTS & CAVEATS:
+**   !!! assumes that fcllistInitialize has been called on the linklist
+**   !!! if not, this function behavior is un-predictable
+**
+**   !!! No validation is made on the list or the validity of the link
+**   !!! the caller must make sure that the link is in the list
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+
+/*lint -emacro(613,saLlistGetNext) */
+
+#define saLlistGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ?  \
+                                      agNULL : (pLink)->pNext)
+
+#define saLlistIOGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ?  \
+                                        agNULL : (pLink)->pNext)
+
+/*! \def saLlistGetPrev(pList, pLink)
+* \brief saLlistGetPrev macro
+*
+* use to get the previous link in the list
+*/
+/********************************************************************************
+********************************************************************************
+**
+** MODULE NAME: saLlistGetPrev
+**
+** PURPOSE:     get the previous link in the list. (one toward head)
+**
+** PARAMETERS:  PSALINK_LIST  OUT - Link list definition.
+**              PSALINK       IN  - Link to get prev to
+**
+**           return PLINK  - points to previous link
+**                           agNULL if previous link is head
+**
+** SIDE EFFECTS & CAVEATS:
+**   !!! assumes that fcllistInitialize has been called on the linklist
+**   !!! if not, this function behavior is un-predictable
+**
+**   !!! No validation is made on the list or the validity of the link
+**   !!! the caller must make sure that the link is in the list
+**
+** ALGORITHM:
+**
+********************************************************************************
+*******************************************************************************/
+
+/*lint -emacro(613,saLlistGetPrev) */
+
+#define saLlistGetPrev(pList, pLink) (((pLink)->pPrev == (pList)->pHead) ?  \
+                                      agNULL : (pLink)->pPrev)
+
+
+
+#define agObjectBase(baseType,fieldName,fieldPtr) \
+            (void * ) fieldPtr == (void *) 0 ? (baseType *) 0 : \
+            ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName)))))
+
+
+#endif /* #ifndef __SALLIST_H__*/

sys/dev/pms/RefTisa/sallsdk/spc/samacro.h

@@ -0,0 +1,301 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+
+/*! \file samacro.h
+ *  \brief The file defines macros used in LL sTSDK
+ */
+
+/*******************************************************************************/
+
+#ifndef __SAMACRO_H__
+#define __SAMACRO_H__
+
+#if defined(SALLSDK_DEBUG)
+#define MPI_IBQ_IOMB_LOG_ENABLE
+#define MPI_OBQ_IOMB_LOG_ENABLE
+#endif
+
+/*! \def MIN(a,b)
+* \brief MIN macro
+*
+* use to find MIN of two values
+*/
+#ifndef MIN
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#endif
+
+/*! \def MAX(a,b)
+* \brief MAX macro
+*
+* use to find MAX of two values
+*/
+#ifndef MAX
+#define MAX(a,b) ((a) < (b) ? (b) : (a))
+#endif
+
+/*************************************************************************************************
+ *                      define Phy status macros                                                 *
+ *************************************************************************************************/
+/*! \def PHY_STATUS_SET(pPhy, value)
+* \brief PHY_STATUS_SET macro
+*
+* use to set phy status
+*/
+#define PHY_STATUS_SET(pPhy, value)  ((pPhy)->status = (((pPhy)->status & 0xFFFF0000) | (value)))
+
+/*! \def PHY_STATUS_CHECK(pPhy, value)
+* \brief PHY_STATUS_CHECK macro
+*
+* use to check phy status
+*/
+#define PHY_STATUS_CHECK(pPhy, value)  ( ((pPhy)->status & 0x0000FFFF) == (value) )
+
+
+/************************************************************************************
+ *                        define CBUFFER operation macros                           *
+ ************************************************************************************/
+/*! \def AGSAMEM_ELEMENT_READ(pMem, index)
+* \brief AGSAMEM_ELEMENT_READ macro
+*
+* use to read an element of a memory array
+*/
+#define AGSAMEM_ELEMENT_READ(pMem, index) (((bit8 *)(pMem)->virtPtr) + (pMem)->singleElementLength * (index))
+
+/************************************************************************************
+ *                        define Chip ID macro                                      *
+ ************************************************************************************/
+
+#define SA_TREAT_SFC_AS_SPC
+
+#ifdef SA_TREAT_SFC_AS_SPC
+#define SA_SFC_AS_SPC 1
+#define SA_SFC_AS_SPCV 0
+#else /* TREAT_SFC_AS_SPCv */
+#define SA_SFC_AS_SPC 0
+#define SA_SFC_AS_SPCV 1
+#endif /* SA_TREAT_SFC_AS_SPC */
+
+#define IS_SDKDATA(agr) (((agr)->sdkData != agNULL ) ? 1 : 0) /* returns true if sdkdata is available */
+
+#define smIsCfgSpcREV_A(agr)    (8  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */
+#define smIsCfgSpcREV_B(agr)    (4  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */
+#define smIsCfgSpcREV_C(agr)    (5  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */
+
+#define smIsCfgVREV_A(agr)    (4  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */
+#define smIsCfgVREV_B(agr)    (5  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */
+#define smIsCfgVREV_C(agr)    (6  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */
+
+#define smIsCfg8001(agr)   (VEN_DEV_SPC   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPC */
+#define smIsCfg8081(agr)   (VEN_DEV_HIL   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000 ) ? 1 : 0) /* returns true config space read is Hialeah */
+
+#define smIsCfg_V8025(agr) (VEN_DEV_SFC   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SFC  */
+
+#define smIsCfg_V8008(agr) (VEN_DEV_SPCV  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
+#define smIsCfg_V8009(agr) (VEN_DEV_SPCVE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
+#define smIsCfg_V8018(agr) (VEN_DEV_SPCVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
+#define smIsCfg_V8019(agr) (VEN_DEV_SPCVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
+
+#define smIsCfg_V8088(agr) (VEN_DEV_ADAPVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */
+#define smIsCfg_V8089(agr) (VEN_DEV_ADAPVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */
+
+#define smIsCfg_V8070(agr) (VEN_DEV_SPC12V  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
+#define smIsCfg_V8071(agr) (VEN_DEV_SPC12VE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
+#define smIsCfg_V8072(agr) (VEN_DEV_SPC12VP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
+#define smIsCfg_V8073(agr) (VEN_DEV_SPC12VEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
+
+#define smIsCfg_V8074(agr) (VEN_DEV_SPC12ADP   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
+#define smIsCfg_V8075(agr) (VEN_DEV_SPC12ADPE  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
+#define smIsCfg_V8076(agr) (VEN_DEV_SPC12ADPP  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
+#define smIsCfg_V8077(agr) (VEN_DEV_SPC12ADPEP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
+#define smIsCfg_V8006(agr) (VEN_DEV_SPC12SATA  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
+#define smIsCfg_V9015(agr) (VEN_DEV_9015 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
+#define smIsCfg_V9060(agr) (VEN_DEV_9060 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
+
+#define smIsCfg_SPC_ANY(agr) ((smIsCfg8001((agr))    == 1) ? 1 : \
+                              (smIsCfg8081((agr))    == 1) ? 1 : \
+                              (smIsCfg_V8025((agr)) == 1) ? SA_SFC_AS_SPC : 0)
+
+#define smIS_SPCV8008(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCV )  ? 1 : 0) : smIsCfg_V8008((agr)))
+#define smIS_SPCV8009(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVE)  ? 1 : 0) : smIsCfg_V8009((agr)))
+#define smIS_SPCV8018(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVP)  ? 1 : 0) : smIsCfg_V8018((agr)))
+#define smIS_SPCV8019(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVEP) ? 1 : 0) : smIsCfg_V8019((agr)))
+#define smIS_ADAP8088(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVP) ? 1 : 0) : smIsCfg_V8088((agr)))
+#define smIS_ADAP8089(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVEP)? 1 : 0): smIsCfg_V8089((agr)))
+
+#define smIS_SPCV8070(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12V ) ? 1 : 0) : smIsCfg_V8070((agr)))
+#define smIS_SPCV8071(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VE) ? 1 : 0) : smIsCfg_V8071((agr)))
+#define smIS_SPCV8072(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VP) ? 1 : 0) : smIsCfg_V8072((agr)))
+#define smIS_SPCV8073(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VEP)? 1 : 0) : smIsCfg_V8073((agr)))
+
+#define smIS_SPCV8074(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADP ) ? 1 : 0) : smIsCfg_V8074((agr)))
+#define smIS_SPCV8075(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPE) ? 1 : 0) : smIsCfg_V8075((agr)))
+#define smIS_SPCV8076(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPP) ? 1 : 0) : smIsCfg_V8076((agr)))
+#define smIS_SPCV8077(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPEP)? 1 : 0) : smIsCfg_V8077((agr)))
+#define smIS_SPCV8006(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12SATA) ? 1 : 0) : smIsCfg_V8006((agr)))
+#define smIS_SPCV9015(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9015)    ? 1 : 0) : smIsCfg_V9015((agr)))
+#define smIS_SPCV9060(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9060)    ? 1 : 0) : smIsCfg_V9060((agr)))
+
+#define smIS_SPCV8025(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC  ) ? 1 : 0) : smIsCfg_V8025((agr)))
+
+#define smIS_SFC(agr)      (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC  ) ? 1 : 0) : smIsCfg_V8025((agr)))
+#define smIS_spc8001(agr)  (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC  ) ? 1 : 0) : smIsCfg8001((agr)))
+#define smIS_spc8081(agr)  (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_HIL  ) ? 1 : 0) : smIsCfg8081((agr)))
+
+
+
+#define smIS_SFC_AS_SPC(agr) ((smIS_SFC((agr)) == 1) ? SA_SFC_AS_SPC : 0 )
+
+#define smIS_SFC_AS_V(agr)   ((smIS_SFC((agr)) == 1 )? SA_SFC_AS_SPCV : 0 )
+
+/* Use 64 bit interrupts for SPCv, before getting saroot. Once saroot available only use 64bit when needed */
+#define smIS64bInt(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->Use64bit) ? 1 : 0)  : smIS_SPCV(agr))
+
+#define WHATTABLE(agr)                                                         \
+(                                                                               \
+IS_SDKDATA((agr)) ?                                                               \
+  (smIS_SPC((agr))  ? &SPCTable[0]  : (smIS_SPCV((agr)) ? &SPC_V_Table[0] : agNULL ) )  \
+:                                                                               \
+  (smIsCfg_SPC_ANY((agr)) ? &SPCTable[0] : (smIsCfg_V_ANY((agr)) ? &SPC_V_Table[0] : agNULL ) ) \
+) \
+
+#if defined(SALLSDK_DEBUG)
+/*
+* for debugging purposes.
+*/
+extern bit32 gLLDebugLevel;
+
+#define SA_DBG0(format) ossaLogDebugString(gLLDebugLevel, 0, format)
+#define SA_DBG1(format) ossaLogDebugString(gLLDebugLevel, 1, format)
+#define SA_DBG2(format) ossaLogDebugString(gLLDebugLevel, 2, format)
+#define SA_DBG3(format) ossaLogDebugString(gLLDebugLevel, 3, format)
+#define SA_DBG4(format) ossaLogDebugString(gLLDebugLevel, 4, format)
+#define SA_DBG5(format) ossaLogDebugString(gLLDebugLevel, 5, format)
+#define SA_DBG6(format) ossaLogDebugString(gLLDebugLevel, 6, format)
+
+#else
+
+#define SA_DBG0(format)
+#define SA_DBG1(format)
+#define SA_DBG2(format)
+#define SA_DBG3(format)
+#define SA_DBG4(format)
+#define SA_DBG5(format)
+#define SA_DBG6(format)
+
+#endif
+
+#define SA_ASSERT OS_ASSERT
+
+typedef enum siPrintType_e
+{
+  SA_8,
+  SA_16,
+  SA_32
+} siPrintType;
+
+#if defined(SALLSDK_DEBUG)
+#define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength) siPrintBuffer(lDebugLevel,lWidth,pHeader,pBuffer,lLength)
+#else
+#define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength)
+#endif
+
+#ifdef SALLSDK_DEBUG
+
+#define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody) siDumpSSPStartIu(agDevHandle,agRequestType,agRequestBody)
+
+#else
+
+#define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody)
+
+#endif
+
+#ifdef MPI_DEBUG_TRACE_ENABLE
+#define MPI_DEBUG_TRACE_ENTER_LOCK  ossaSingleThreadedEnter(agRoot, LL_IOMB_TRACE_LOCK);
+#define MPI_DEBUG_TRACE_LEAVE_LOCK  ossaSingleThreadedLeave(agRoot, LL_IOMB_TRACE_LOCK);
+
+#define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count) \
+  MPI_DEBUG_TRACE_ENTER_LOCK \
+ mpiTraceAdd( (queue), (pici),(ib), (iomb), (count)); \
+  MPI_DEBUG_TRACE_LEAVE_LOCK
+#else
+#define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count)
+#endif /* MPI_DEBUG_TRACE_ENABLE */
+
+#ifdef MPI_IBQ_IOMB_LOG_ENABLE
+#define MPI_IBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \
+do \
+{ \
+  bit32 i; \
+  SA_DBG3(("\n")); \
+  SA_DBG3(("mpiMsgProduce: IBQ %d\n", (qNumber))); \
+  for (i = 0; i < msgLength/16; i++) \
+  { \
+    SA_DBG3(("Inb: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \
+           *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \
+           *((bit32 *)msgHeader+(i*4)+3))); \
+  } \
+} while(0)
+#endif
+#ifdef MPI_OBQ_IOMB_LOG_ENABLE
+#define MPI_OBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \
+do \
+{ \
+  bit32 i; \
+  SA_DBG3(("\n")); \
+  SA_DBG3(("mpiMsgConsume: OBQ %d\n", qNumber)); \
+  for (i = 0; i < msgLength/16; i++) \
+  { \
+    SA_DBG3(("Out: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \
+           *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \
+           *((bit32 *)msgHeader+(i*4)+3))); \
+  } \
+} while(0)
+#endif
+
+
+/************************************************************************************
+ *                        Wait X Second                                             *
+ ************************************************************************************/
+
+#define WAIT_SECONDS(x) ((x) * 1000 * 1000 )
+#define ONE_HUNDRED_MILLISECS (100 * 1000)   /* 100,000 microseconds  */
+
+#define WAIT_INCREMENT_DEFAULT  1000
+#define WAIT_INCREMENT  (IS_SDKDATA(agRoot) ? ( ((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs ) : WAIT_INCREMENT_DEFAULT )
+// (((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs)
+
+
+#define MAKE_MODULO(a,b)  (((a) % (b)) ? ((a) - ((a) % (b))) : (a))
+
+
+#define HDA_STEP_2  1
+#define HDA_STEP_3  1
+#define HDA_STEP_4  1
+#define HDA_STEP_5  1
+#define HDA_STEP_6  1
+#define HDA_STEP_7  1
+#define HDA_STEP_8  1
+
+#endif /* __SAMACRO_H__ */

sys/dev/pms/RefTisa/sallsdk/spc/saproto.h

@@ -0,0 +1,947 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file saproto.h
+ *  \brief The file defines the function delcaration for internal used function
+ *
+ */
+/******************************************************************************/
+
+#ifndef  __SAPROTO_H__
+
+#define __SAPROTO_H__
+
+/* function declaration */
+/*** SATIMER.C ***/
+GLOBAL agsaTimerDesc_t *siTimerAdd(
+                                  agsaRoot_t      *agRoot,
+                                  bit32           timeout,
+                                  agsaCallback_t  pfnTimeout,
+                                  bit32           Event,
+                                  void *          pParm
+                                  );
+
+GLOBAL void siTimerRemove(
+                          agsaRoot_t      *agRoot,
+                          agsaTimerDesc_t *pTimer
+                          );
+
+GLOBAL void siTimerRemoveAll(agsaRoot_t   *agRoot);
+
+/*** SAINIT.C ***/
+GLOBAL bit32 siConfiguration(agsaRoot_t    *agRoot,
+                            mpiConfig_t    *mpiConfig,
+                            agsaHwConfig_t *hwConfig,
+                            agsaSwConfig_t *swConfig
+                            );
+
+GLOBAL bit32 mpiInitialize(agsaRoot_t  *agRoot,
+                           mpiMemReq_t *memoryAllocated,
+                           mpiConfig_t *config
+                           );
+
+GLOBAL bit32 mpiWaitForConfigTable(agsaRoot_t *agRoot,
+                                   spc_configMainDescriptor_t *config
+                                   );
+
+GLOBAL void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot,
+                                     spc_inboundQueueDescriptor_t *inQueueCfg,
+                                     bit32 QueueTableOffset,
+                                     bit8 pcibar
+                                     );
+
+GLOBAL void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot,
+                                     spc_outboundQueueDescriptor_t *outQueueCfg,
+                                     bit32 QueueTableOffset,
+                                     bit8 pcibar
+                                     );
+GLOBAL void mpiUpdateFatalErrorTable(agsaRoot_t             *agRoot, 
+                              bit32                         FerrTableOffset,
+                              bit32                         lowerBaseAddress,
+                              bit32                         upperBaseAddress,
+                              bit32                         length,
+                              bit8                          pcibar);
+
+GLOBAL bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot,
+                               bit32 pciBar
+                               );
+
+GLOBAL bit32 mpiUnInitConfigTable(agsaRoot_t *agRoot);
+
+GLOBAL void mpiReadGSTable(agsaRoot_t             *agRoot,
+                         spc_GSTableDescriptor_t  *mpiGSTable);
+
+GLOBAL void siInitResources(agsaRoot_t              *agRoot,
+                            agsaMemoryRequirement_t *memoryAllocated,
+                            agsaHwConfig_t          *hwConfig,
+                            agsaSwConfig_t          *swConfig,
+                            bit32                   usecsPerTick);
+
+GLOBAL void mpiReadCALTable(agsaRoot_t      *agRoot,
+                            spc_SPASTable_t *mpiCALTable,
+                            bit32           index);
+
+GLOBAL void mpiWriteCALTable(agsaRoot_t     *agRoot,
+                            spc_SPASTable_t *mpiCALTable,
+                            bit32           index);
+
+GLOBAL void mpiWriteCALAll(agsaRoot_t     *agRoot,
+                           agsaPhyAnalogSetupTable_t *mpiCALTable);
+
+GLOBAL void mpiWrIntVecTable(agsaRoot_t *agRoot,
+                            mpiConfig_t* config
+                            );
+
+GLOBAL void mpiWrAnalogSetupTable(agsaRoot_t *agRoot,
+                            mpiConfig_t      *config
+                            );
+
+
+GLOBAL void mpiWrPhyAttrbTable(agsaRoot_t *agRoot,
+                            sasPhyAttribute_t *phyAttrib
+                            );
+
+/*** SAPHY.C ***/
+GLOBAL bit32 siPhyStopCB(
+                      agsaRoot_t    *agRoot,
+                      bit32         phyId,
+                      bit32         status,
+                      agsaContext_t *agContext,
+                      bit32         portId,
+                      bit32         npipps
+                      );
+
+/*** SAPORT.C ***/
+GLOBAL void siPortInvalid(
+                          agsaRoot_t  *agRoot,
+                          agsaPort_t  *pPort
+                          );
+
+GLOBAL agsaDeviceDesc_t *siPortSASDeviceAdd(
+                                    agsaRoot_t        *agRoot,
+                                    agsaPort_t        *pPort,
+                                    agsaSASIdentify_t sasIdentify,
+                                    bit32             sasInitiator,
+                                    bit32             smpTimeout,
+                                    bit32             itNexusTimeout,
+                                    bit32             firstBurstSize,
+                                    bit8              dTypeSRate,
+                                    bit32              flag
+                                    );
+
+GLOBAL void siPortDeviceRemove(
+                              agsaRoot_t        *agRoot,
+                              agsaPort_t        *pPort,
+                              agsaDeviceDesc_t  *pDevice,
+                              bit32             unmap
+                              );
+
+GLOBAL agsaDeviceDesc_t *siPortSATADeviceAdd(
+                                              agsaRoot_t              *agRoot,
+                                              agsaPort_t              *pPort,
+                                              agsaDeviceDesc_t        *pSTPBridge,
+                                              bit8                    *pSignature,
+                                              bit8                    pm,
+                                              bit8                    pmField,
+                                              bit32                   smpReqTimeout,
+                                              bit32                   itNexusTimeout,
+                                              bit32                   firstBurstSize,
+                                              bit8                    dTypeSRate,
+                                              bit32                   flag
+                                              );
+
+GLOBAL void siPortDeviceListRemove(
+                              agsaRoot_t        *agRoot,
+                              agsaPort_t        *pPort,
+                              agsaDeviceDesc_t  *pDevice
+                              );
+
+/*** SASATA.C ***/
+GLOBAL void siSATASignatureCpy(
+                                bit8  *pDstSignature,
+                                bit8  *pSrcSignature
+                                );
+
+/*** SASSP.C ***/
+
+/*** SAHW.C ***/
+#ifdef SA_ENABLE_HDA_FUNCTIONS
+GLOBAL bit32 siHDAMode(
+                      agsaRoot_t  *agRoot,
+                      bit32       HDAMode,
+                      agsaFwImg_t *userFwImg
+                      );
+
+GLOBAL bit32 siHDAMode_V(
+                      agsaRoot_t  *agRoot,
+                      bit32       HDAMode,
+                      agsaFwImg_t *userFwImg
+                      );
+
+#endif
+
+GLOBAL bit32 siBar4Shift(
+  agsaRoot_t  *agRoot,
+  bit32       shiftValue
+  );
+
+
+GLOBAL bit32 siSoftReset(
+                       agsaRoot_t  *agRoot,
+                       bit32       signature
+                       );
+
+GLOBAL bit32 siSpcSoftReset(
+                       agsaRoot_t  *agRoot,
+                       bit32       signature
+                       );
+
+GLOBAL void siChipReset(
+                       agsaRoot_t  *agRoot
+                       );
+
+
+GLOBAL bit32 siChipResetV(
+                       agsaRoot_t  *agRoot,
+                       bit32       signature
+                       );
+
+GLOBAL void siChipResetSpc(
+                      agsaRoot_t  *agRoot
+                      );
+
+
+/*** SAUTIL.C ***/
+GLOBAL void siPrintBuffer(
+                          bit32                 debugLevel,
+                          siPrintType           type,
+                          char                  *header,
+                          void                  *a,
+                          bit32                 length
+                          );
+int siIsHexDigit(char a);
+GLOBAL FORCEINLINE void* si_memcpy(void *dst, void *src, bit32 count);
+GLOBAL FORCEINLINE void* si_memset(void *s, int c, bit32 n);
+
+GLOBAL void siDumpActiveIORequests(
+                          agsaRoot_t              *agRoot,
+                          bit32                   count);
+
+
+GLOBAL void siClearActiveIORequests(   agsaRoot_t  *agRoot);
+
+GLOBAL void siCountActiveIORequestsOnDevice( agsaRoot_t *agRoot,  bit32      device );
+GLOBAL void siClearActiveIORequestsOnDevice( agsaRoot_t *agRoot,  bit32      device );
+
+
+
+/*** SAINT.C ***/
+GLOBAL void siEventPhyUpRcvd(
+                             agsaRoot_t  *agRoot,
+                             bit32       phyId,
+                             agsaSASIdentify_t *agSASIdentify,
+                             bit32       portId,
+                             bit32       npipps,
+                             bit8        linkRate
+                             );
+
+GLOBAL void siEventSATASignatureRcvd(
+                                    agsaRoot_t    *agRoot,
+                                    bit32         phyId,
+                                    void          *pMsg,
+                                    bit32         portId,
+                                    bit32         npipps,
+                                    bit8          linkRate
+                                    );
+
+GLOBAL FORCEINLINE void siIODone(
+                     agsaRoot_t          *agRoot,
+                     agsaIORequestDesc_t *pRequest,
+                     bit32               status,
+                     bit32               sspTag
+                     );
+
+GLOBAL void siAbnormal(
+                       agsaRoot_t          *agRoot,
+                       agsaIORequestDesc_t *pRequest,
+                       bit32               status,
+                       bit32               param,
+                       bit32               sspTag
+                       );
+
+GLOBAL void siDifAbnormal(
+                         agsaRoot_t          *agRoot,
+                         agsaIORequestDesc_t *pRequest,
+                         bit32               status,
+                         bit32               param,
+                         bit32               sspTag,
+                         bit32               *pMsg1
+                         );
+
+GLOBAL void siEventSSPResponseWtDataRcvd(
+                                        agsaRoot_t                *agRoot,
+                                        agsaIORequestDesc_t       *pRequest,
+                                        agsaSSPResponseInfoUnit_t *pRespIU,
+                                        bit32                     param,
+                                        bit32                     sspTag
+                                        );
+
+GLOBAL void siSMPRespRcvd(
+                          agsaRoot_t              *agRoot,
+                          agsaSMPCompletionRsp_t  *pIomb,
+                          bit32                   payloadSize,
+                          bit32                   tag
+                          );
+
+GLOBAL void siEventSATAResponseWtDataRcvd(
+                                          agsaRoot_t          *agRoot,
+                                          agsaIORequestDesc_t *pRequest,
+                                          bit32               *agFirstDword,
+                                          bit32               *pResp,
+                                          bit32               lengthResp
+                                          );
+
+/*** SADISC.C ***/
+GLOBAL bit32 siRemoveDevHandle(
+                              agsaRoot_t      *agRoot,
+                              agsaDevHandle_t *agDevHandle
+                              );
+
+/*** SAMPIRSP.C ***/
+GLOBAL FORCEINLINE bit32 mpiParseOBIomb(
+                            agsaRoot_t            *agRoot,
+                            bit32                 *pMsg1,
+                            mpiMsgCategory_t      category,
+                            bit16                 opcode
+                            );
+
+GLOBAL bit32 mpiEchoRsp(
+                        agsaRoot_t          *agRoot,
+                        agsaEchoRsp_t       *pIomb
+                        );
+
+GLOBAL bit32 mpiGetNVMDataRsp(
+  agsaRoot_t          *agRoot,
+  agsaGetNVMDataRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiHWevent(
+  agsaRoot_t        *agRoot,
+  agsaHWEvent_SPC_OUB_t  *pIomb
+  );
+
+GLOBAL bit32 mpiPhyStartEvent(
+  agsaRoot_t        *agRoot,
+  agsaHWEvent_Phy_OUB_t  *pIomb
+  );
+
+GLOBAL bit32 mpiPhyStopEvent(
+  agsaRoot_t        *agRoot,
+  agsaHWEvent_Phy_OUB_t  *pIomb
+  );
+
+GLOBAL bit32 mpiSMPCompletion(
+  agsaRoot_t             *agRoot,
+  agsaSMPCompletionRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiGetDevInfoRspSpc(
+  agsaRoot_t          *agRoot,
+  agsaGetDevInfoRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiGetPhyProfileRsp(
+  agsaRoot_t             *agRoot,
+  agsaGetPhyProfileRspV_t *pIomb
+  );
+
+GLOBAL bit32 mpiSetPhyProfileRsp(
+  agsaRoot_t             *agRoot,
+  agsaSetPhyProfileRspV_t *pIomb
+  );
+
+GLOBAL bit32 mpiGetDevInfoRsp(
+  agsaRoot_t          *agRoot,
+  agsaGetDevInfoRspV_t *pIomb
+  );
+
+GLOBAL bit32 mpiGetDevHandleRsp(
+  agsaRoot_t            *agRoot,
+  agsaGetDevHandleRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiPhyCntrlRsp(
+  agsaRoot_t             *agRoot,
+  agsaLocalPhyCntrlRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiDeviceRegRsp(
+  agsaRoot_t                  *agRoot,
+  agsaDeviceRegistrationRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiDeregDevHandleRsp(
+  agsaRoot_t              *agRoot,
+  agsaDeregDevHandleRsp_t *pIomb
+  );
+
+GLOBAL FORCEINLINE bit32 mpiSSPCompletion(
+  agsaRoot_t        *agRoot,
+  bit32             *pIomb
+  );
+
+GLOBAL FORCEINLINE bit32 mpiSATACompletion(
+  agsaRoot_t        *agRoot,
+  bit32             *pIomb
+  );
+
+GLOBAL bit32 mpiSSPEvent(
+  agsaRoot_t        *agRoot,
+  agsaSSPEventRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSATAEvent(
+  agsaRoot_t         *agRoot,
+  agsaSATAEventRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiFwFlashUpdateRsp(
+  agsaRoot_t             *agRoot,
+  agsaFwFlashUpdateRsp_t *payload
+  );
+
+
+GLOBAL bit32 mpiFwExtFlashUpdateRsp(
+  agsaRoot_t             *agRoot,
+  agsaFwFlashOpExtRsp_t *payload
+  );
+
+#ifdef SPC_ENABLE_PROFILE
+GLOBAL bit32 mpiFwProfileRsp(
+  agsaRoot_t             *agRoot,
+  agsaFwProfileRsp_t *payload
+  );
+#endif
+GLOBAL bit32 mpiSetNVMDataRsp(
+  agsaRoot_t          *agRoot,
+  agsaSetNVMDataRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSSPAbortRsp(
+  agsaRoot_t         *agRoot,
+  agsaSSPAbortRsp_t  *pIomb
+  );
+
+GLOBAL bit32 mpiSATAAbortRsp(
+  agsaRoot_t         *agRoot,
+  agsaSATAAbortRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiGPIORsp(
+  agsaRoot_t          *agRoot,
+  agsaGPIORsp_t       *pIomb
+  );
+
+GLOBAL bit32 mpiGPIOEventRsp(
+  agsaRoot_t          *agRoot,
+  agsaGPIOEvent_t     *pIomb
+  );
+
+GLOBAL bit32 mpiSASDiagStartEndRsp(
+  agsaRoot_t               *agRoot,
+  agsaSASDiagStartEndRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSASDiagExecuteRsp(
+  agsaRoot_t               *agRoot,
+  agsaSASDiagExecuteRsp_t  *pIomb
+  );
+
+GLOBAL bit32 mpiGeneralEventRsp(
+  agsaRoot_t               *agRoot,
+  agsaGeneralEventRsp_t    *pIomb
+  );
+
+GLOBAL bit32 mpiSSPReqReceivedNotify(
+  agsaRoot_t *agRoot,
+  agsaSSPReqReceivedNotify_t *pMsg1
+  );
+
+GLOBAL bit32 mpiDeviceHandleArrived(
+  agsaRoot_t *agRoot,
+  agsaDeviceHandleArrivedNotify_t *pMsg1
+  );
+
+GLOBAL bit32 mpiGetTimeStampRsp(
+  agsaRoot_t               *agRoot,
+  agsaGetTimeStampRsp_t    *pIomb
+  );
+
+GLOBAL bit32 mpiSASHwEventAckRsp(
+  agsaRoot_t               *agRoot,
+  agsaSASHwEventAckRsp_t   *pIomb
+  );
+
+GLOBAL bit32 mpiSetDevInfoRsp(
+  agsaRoot_t             *agRoot,
+  agsaSetDeviceInfoRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSetDeviceStateRsp(
+  agsaRoot_t              *agRoot,
+  agsaSetDeviceStateRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiGetDeviceStateRsp(
+  agsaRoot_t             *agRoot,
+  agsaGetDeviceStateRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSasReInitializeRsp(
+  agsaRoot_t               *agRoot,
+  agsaSasReInitializeRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSetControllerConfigRsp(
+  agsaRoot_t               *agRoot,
+  agsaSetControllerConfigRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiGetControllerConfigRsp(
+  agsaRoot_t                  *agRoot,
+  agsaGetControllerConfigRsp_t *pIomb
+  );
+
+GLOBAL bit32  mpiKekManagementRsp(
+    agsaRoot_t               *agRoot,
+    agsaKekManagementRsp_t   *pIomb
+  );
+
+GLOBAL bit32  mpiDekManagementRsp(
+    agsaRoot_t               *agRoot,
+    agsaDekManagementRsp_t   *pIomb
+  );
+
+GLOBAL bit32 mpiOperatorManagementRsp(
+  agsaRoot_t               *agRoot,
+  agsaOperatorMangmenRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiBistRsp(
+  agsaRoot_t           *agRoot,
+  agsaEncryptBistRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSetOperatorRsp(
+  agsaRoot_t               *agRoot,
+  agsaSetOperatorRsp_t    *pIomb
+  );
+
+GLOBAL bit32 mpiGetOperatorRsp(
+  agsaRoot_t               *agRoot,
+  agsaGetOperatorRsp_t    *pIomb
+  );
+
+GLOBAL bit32 mpiDifEncOffloadRsp(
+  agsaRoot_t               *agRoot,
+  agsaDifEncOffloadRspV_t  *pIomb
+  );
+
+GLOBAL bit32 mpiGetVHistRsp(
+   agsaRoot_t          *agRoot,
+   agsaGetVHistCapRsp_t *pIomb
+  );
+
+
+/*** SAMPICMD.C ***/
+GLOBAL bit32 mpiBuildCmd(
+  agsaRoot_t        *agRoot,
+  bit32             *payload,
+  mpiMsgCategory_t  category,
+  bit16             opcode,
+  bit16             size,
+  bit32             queueNum
+  );
+
+
+GLOBAL bit32 mpiVHistCapCmd(
+  agsaRoot_t    *agRoot,
+  agsaContext_t *agContext,
+  bit32         queueNum,
+  bit32         Channel,
+  bit32         NumBitLo,
+  bit32         NumBitHi,
+  bit32         PcieAddrLo,
+  bit32         PcieAddrHi,
+  bit32         ByteCount );
+
+GLOBAL bit32 mpiEchoCmd(
+  agsaRoot_t          *agRoot,
+  bit32               queueNum,
+  agsaContext_t       *agContext,
+  void                *echoPayload
+  );
+
+GLOBAL bit32 mpiGetPhyProfileCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32                Operation,
+  bit32                PhyId,
+  void                *agCB
+  );
+
+GLOBAL bit32 mpiSetPhyProfileCmd(
+  agsaRoot_t    *agRoot,
+  agsaContext_t *agContext,
+  bit32         Operation,
+  bit32         PhyId,
+  bit32         length,
+  void *        buffer
+  );
+
+GLOBAL bit32 mpiPhyStartCmd(
+  agsaRoot_t          *agRoot,
+  bit32               tag,
+  bit32               phyId,
+  agsaPhyConfig_t     *agPhyConfig,
+  agsaSASIdentify_t   *agSASIdentify,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiPhyStopCmd(
+  agsaRoot_t          *agRoot,
+  bit32               tag,
+  bit32               phyId,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiSMPCmd(
+  agsaRoot_t             *agRoot,
+  void                   *pIomb,
+  bit16                  opcode,
+  agsaSMPCmd_t           *payload,
+  bit8                   inq,
+  bit8                   outq
+  );
+
+GLOBAL bit32 mpiDeregDevHandleCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  agsaDeviceDesc_t    *pDevice,
+  bit32               deviceId,
+  bit32               portId,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiGetDeviceHandleCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32               portId,
+  bit32               flags,
+  bit32               maxDevs,
+  bit32               queueNum,
+  bit32               skipCount
+  );
+
+GLOBAL bit32 mpiLocalPhyControlCmd(
+  agsaRoot_t          *agRoot,
+  bit32               tag,
+  bit32               phyId,
+  bit32               operation,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiGetDeviceInfoCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32               deviceid,
+  bit32               option,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiDevHandleAcceptCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32               ctag,
+  bit32               deviceId,
+  bit32               action,
+  bit32               flag,
+  bit32               itlnx,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiPortControlRsp(
+  agsaRoot_t           *agRoot,
+  agsaPortControlRsp_t *pIomb
+  );
+
+GLOBAL bit32 mpiSMPAbortRsp(
+  agsaRoot_t         *agRoot,
+  agsaSMPAbortRsp_t  *pIomb
+  );
+
+GLOBAL bit32 siGetRegisterDumpGSM(
+  agsaRoot_t        *agRoot,
+  void              *destinationAddress,
+  bit32             regDumpNum,
+  bit32             regDumpOffset,
+  bit32             len
+  );
+
+GLOBAL bit32 mpiNVMReadRegDumpCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32               queueNum,
+  bit32               cpuId,
+  bit32               cOffset,
+  bit32               addrHi,
+  bit32               addrLo,
+  bit32               len
+  );
+
+GLOBAL bit32 mpiDeviceHandleRemoval(
+  agsaRoot_t                *agRoot,
+  agsaDeviceHandleRemoval_t *pMsg1);
+
+GLOBAL bit32 mpiGetNVMDCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  agsaNVMDData_t      *NVMDInfo,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiSetNVMDCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  agsaNVMDData_t      *NVMDInfo,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiSetDeviceInfoCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32               deviceid,
+  bit32               option,
+  bit32               queueNum,
+  bit32               param,
+  ossaSetDeviceInfoCB_t   agCB
+  );
+
+GLOBAL bit32 mpiSetDeviceStateCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32               deviceId,
+  bit32               nds,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiGetDeviceStateCmd(
+  agsaRoot_t          *agRoot,
+  agsaContext_t       *agContext,
+  bit32               deviceId,
+  bit32               queueNum
+  );
+
+GLOBAL bit32 mpiSasReinitializeCmd(
+  agsaRoot_t        *agRoot,
+  agsaContext_t     *agContext,
+  agsaSASReconfig_t *agSASConfig,
+  bit32             queueNum
+  );
+
+GLOBAL bit32 mpiSGpioRsp(
+  agsaRoot_t       *agRoot,
+  agsaSGpioRsp_t   *pInIomb
+  );
+
+GLOBAL bit32 mpiPCIeDiagExecuteRsp(
+  agsaRoot_t    *agRoot,
+  void          *pInIomb
+  );
+
+GLOBAL bit32 mpiGetDFEDataRsp(
+  agsaRoot_t    *agRoot,
+  void          *pInIomb
+  );
+
+GLOBAL bit32 mpiGetVisDataRsp(
+  agsaRoot_t    *agRoot,
+  void          *pIomb
+  );
+
+GLOBAL bit32 mpiSetControllerConfigCmd(
+  agsaRoot_t        *agRoot,
+  agsaContext_t     *agContext,
+  agsaSetControllerConfigCmd_t *agControllerConfig,
+  bit32             queueNum,
+  bit8              modePageContext
+  );
+
+GLOBAL bit32 mpiGetControllerConfigCmd(
+   agsaRoot_t        *agRoot,
+   agsaContext_t     *agContext,
+   agsaGetControllerConfigCmd_t *agControllerConfig,
+   bit32             queueNum
+   );
+
+GLOBAL bit32 mpiKekManagementCmd(
+   agsaRoot_t        *agRoot,
+   agsaContext_t     *agContext,
+   agsaKekManagementCmd_t *agKekMgmt,
+   bit32             queueNum
+   );
+
+GLOBAL bit32 mpiDekManagementCmd(
+   agsaRoot_t        *agRoot,
+   agsaContext_t     *agContext,
+   agsaDekManagementCmd_t *agDekMgmt,
+   bit32             queueNum
+   );
+
+GLOBAL bit32 mpiOperatorManagementCmd(
+  agsaRoot_t                *agRoot,
+  bit32                     queueNum,
+  agsaContext_t             *agContext,
+  agsaOperatorMangmentCmd_t *operatorcode );
+
+GLOBAL bit32 mpiEncryptBistCmd(
+  agsaRoot_t        *agRoot,
+  bit32              queueNum,
+  agsaContext_t     *agContext,
+  agsaEncryptBist_t *bist );
+
+GLOBAL bit32 mpiSetOperatorCmd(
+  agsaRoot_t                *agRoot,
+  bit32                      queueNum,
+  agsaContext_t             *agContext,
+  agsaSetOperatorCmd_t      *operatorcode
+  );
+
+GLOBAL bit32 mpiGetOperatorCmd(
+  agsaRoot_t                *agRoot,
+  bit32                      queueNum,
+  agsaContext_t             *agContext,
+  agsaGetOperatorCmd_t      *operatorcode
+  );
+
+GLOBAL bit32 mpiDIFEncryptionOffloadCmd(
+   agsaRoot_t                *agRoot,
+   agsaContext_t             *agContext,
+   bit32                     queueNum,
+   bit32                     op,
+   agsaDifEncPayload_t      *agDifEncOffload,
+   ossaDIFEncryptionOffloadStartCB_t agCB
+   );
+
+bit32 siOurMSIXInterrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siDisableMSIXInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siReenableMSIXInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+
+bit32 siOurMSIInterrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siDisableMSIInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siReenableMSIInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+
+
+bit32 siOurLegacyInterrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siDisableLegacyInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siReenableLegacyInterrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+
+bit32 siOurMSIX_V_Interrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+bit32 siOurMSI_V_Interrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+bit32 siOurLegacy_V_Interrupt(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+
+void siDisableMSIX_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siDisableMSI_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siDisableLegacy_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+
+void siReenableMSIX_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siReenableMSI_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+void siReenableLegacy_V_Interrupts(agsaRoot_t *agRoot,bit32 interruptVectorIndex);
+
+
+GLOBAL void siUpdateBarOffsetTable(agsaRoot_t     *agRoot, bit32   Spc_Type);
+
+GLOBAL void siPciCpyMem(agsaRoot_t *agRoot,
+                       bit32 soffset,
+                       const void *dst,
+                       bit32 DWcount,
+                       bit32 busBaseNumber
+                       );
+
+GLOBAL void siHalRegWriteExt(
+                             agsaRoot_t  *agRoot,
+                             bit32       generic,
+                             bit32       regOffset,
+                             bit32       regValue
+                             );
+
+GLOBAL bit32 siHalRegReadExt( agsaRoot_t  *agRoot,
+                             bit32       generic,
+                             bit32       regOffset
+                             );
+
+#ifdef SA_FW_TIMER_READS_STATUS
+bit32 siReadControllerStatus(
+                                  agsaRoot_t      *agRoot,
+                                  bit32           Event,
+                                  void *          pParm
+                                  );
+#endif /* SA_FW_TIMER_READS_STATUS */
+
+
+#if defined(SALLSDK_DEBUG)
+void sidump_hwConfig(agsaHwConfig_t  *hwConfig);
+void sidump_swConfig(agsaSwConfig_t  *swConfig);
+void sidump_Q_config( agsaQueueConfig_t *queueConfig );
+#endif
+GLOBAL bit32 siGetTableOffset(
+              agsaRoot_t *agRoot,
+              bit32  TableOffsetInTable
+              );
+
+GLOBAL bit32 siGetPciBar(
+              agsaRoot_t *agRoot
+              );
+
+GLOBAL bit32 siScratchDump(agsaRoot_t *agRoot);
+
+void si_macro_check(agsaRoot_t *agRoot);
+
+GLOBAL bit32 si_check_V_HDA(agsaRoot_t *agRoot);
+GLOBAL bit32 si_check_V_Ready(agsaRoot_t *agRoot);
+
+GLOBAL void siPCITriger(agsaRoot_t *agRoot);
+
+GLOBAL void siCheckQs(agsaRoot_t *agRoot);
+
+
+GLOBAL bit32 smIsCfg_V_ANY( agsaRoot_t *agRoot);
+GLOBAL bit32 smIS_SPC( agsaRoot_t *agRoot);
+GLOBAL bit32 smIS_HIL( agsaRoot_t *agRoot);
+GLOBAL bit32 smIS_SPC6V( agsaRoot_t *agRoot);
+GLOBAL bit32 smIS_SPC12V( agsaRoot_t *agRoot);
+GLOBAL bit32 smIS_SPCV( agsaRoot_t *agRoot);
+GLOBAL bit32 smIS_ENCRYPT( agsaRoot_t *agRoot);
+GLOBAL bit32 smIS_SPCV_2_IOP( agsaRoot_t *agRoot);
+#endif  /*__SAPROTO_H__ */

sys/dev/pms/RefTisa/sallsdk/spc/sasata.c

@@ -0,0 +1,936 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/*! \file sasata.c
+ *  \brief The file implements the functions to SATA IO
+ *
+ */
+/******************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#ifdef siTraceFileID
+#undef siTraceFileID
+#endif
+#define siTraceFileID 'M'
+#endif
+
+/******************************************************************************/
+/*! \brief Start SATA command
+ *
+ *  Start SATA command
+ *
+ *  \param agRoot handles for this instance of SAS/SATA hardware
+ *  \param queueNum
+ *  \param agIORequest
+ *  \param agDevHandle
+ *  \param agRequestType
+ *  \param agSATAReq
+ *  \param agTag
+ *  \param agCB
+ *
+ *  \return If command is started successfully
+ *          - \e AGSA_RC_SUCCESS command is started successfully
+ *          - \e AGSA_RC_FAILURE command is not started successfully
+ */
+/*******************************************************************************/
+GLOBAL bit32 saSATAStart(
+  agsaRoot_t                  *agRoot,
+  agsaIORequest_t             *agIORequest,
+  bit32                       queueNum,
+  agsaDevHandle_t             *agDevHandle,
+  bit32                       agRequestType,
+  agsaSATAInitiatorRequest_t  *agSATAReq,
+  bit8                        agTag,
+  ossaSATACompletedCB_t       agCB
+  )
+
+{
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  mpiICQueue_t        *circularQ = agNULL;
+  agsaDeviceDesc_t    *pDevice   = agNULL;
+  agsaPort_t          *pPort     = agNULL;
+  agsaIORequestDesc_t *pRequest  = agNULL;
+  void                *pMessage  = agNULL;
+  agsaSgl_t           *pSgl      = agNULL;
+  bit32               *payload   = agNULL;
+  bit32               deviceIndex = 0;
+  bit32               ret = AGSA_RC_SUCCESS, retVal = 0;
+  bit32               AtapDir = 0;
+  bit32               encryptFlags = 0;
+  bit16               size = 0;
+  bit16               opCode = 0;
+  bit8                inq = 0, outq = 0;
+
+  OSSA_INP_ENTER(agRoot);
+  smTraceFuncEnter(hpDBG_VERY_LOUD, "8a");
+
+  SA_DBG3(("saSATAStart: in\n"));
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "(saSATAStart) agRoot is NULL");
+  SA_ASSERT((agNULL != agIORequest), "(saSATAStart) agIORequest is NULL");
+  SA_ASSERT((agNULL != agDevHandle), "(saSATAStart) agDevHandle is NULL");
+  SA_ASSERT((agNULL != agSATAReq), "(saSATAStart) agSATAReq is NULL");
+
+  /* Assign inbound and outbound queue */
+  inq = (bit8)(queueNum & MPI_IB_NUM_MASK);
+  outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT);
+  SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range.");
+
+  /* Find the outgoing port for the device */
+  pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+  SA_ASSERT((agNULL != pDevice), "(saSATAStart) pDevice is NULL");
+
+  pPort = pDevice->pPort;
+  SA_ASSERT((agNULL != pPort), "(saSATAStart) pPort is NULL");
+
+  /* SATA DIF is obsolete */
+  if (agSATAReq->option & AGSA_SATA_ENABLE_DIF)
+  {
+    return AGSA_RC_FAILURE;
+  }
+
+  /* find deviceID for IOMB */
+  deviceIndex = pDevice->DeviceMapIndex;
+
+  /*  Get request from free IORequests */
+  ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+  pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests));
+  if ( agNULL != pRequest )
+  {
+    /* If free IOMB avaliable */
+    /* Remove the request from free list */
+    saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode));
+
+    /* Add the request to the pendingSTARequests list of the device */
+    pRequest->valid = agTRUE;
+    saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+    if ((agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION) ||
+          (agSATAReq->option & AGSA_SATA_ENABLE_DIF))
+    {
+        opCode = OPC_INB_SATA_DIF_ENC_OPSTART;
+        size = IOMB_SIZE128;
+    }
+    else
+    {
+        opCode = OPC_INB_SATA_HOST_OPSTART;
+        if (agRequestType == AGSA_SATA_PROTOCOL_NON_PKT ||
+            agRequestType == AGSA_SATA_PROTOCOL_H2D_PKT ||
+            agRequestType == AGSA_SATA_PROTOCOL_D2H_PKT)
+            size = IOMB_SIZE128;
+        else
+            size = IOMB_SIZE64;
+    }
+    /* If LL IO request entry avaliable */
+    /* set up pRequest */
+    pRequest->pIORequestContext = agIORequest;
+    pRequest->pDevice = pDevice;
+    pRequest->pPort = pPort;
+    pRequest->requestType = agRequestType;
+    pRequest->startTick = saRoot->timeTick;
+    pRequest->completionCB = (ossaSSPCompletedCB_t)agCB;
+    /* Set request to the sdkData of agIORequest */
+    agIORequest->sdkData = pRequest;
+
+    /* save tag and IOrequest pointer to IOMap */
+    saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag;
+    saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest;
+
+#ifdef SA_LL_IBQ_PROTECT
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+    /* get a free inbound queue entry */
+    circularQ = &saRoot->inboundQueue[inq];
+    retVal    = mpiMsgFreeGet(circularQ, size, &pMessage);
+
+    if (AGSA_RC_FAILURE == retVal)
+    {
+#ifdef SA_LL_IBQ_PROTECT
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+      /* if not sending return to free list rare */
+      ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+      pRequest->valid = agFALSE;
+      saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+      SA_DBG3(("saSATAStart, error when get free IOMB\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "8a");
+      ret = AGSA_RC_FAILURE;
+      goto ext;
+    }
+
+    /* return busy if inbound queue is full */
+    if (AGSA_RC_BUSY == retVal)
+    {
+#ifdef SA_LL_IBQ_PROTECT
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+      /* if not sending return to free list rare */
+      ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+      pRequest->valid = agFALSE;
+      saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+      SA_DBG1(("saSATAStart, no more IOMB\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "8a");
+      ret = AGSA_RC_BUSY;
+      goto ext;
+    }
+
+  }
+  else   /* If no LL IO request entry available */
+  {
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    SA_DBG1(("saSATAStart, No request from free list\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "8a");
+    ret = AGSA_RC_BUSY;
+    goto ext;
+  }
+
+  payload = (bit32 *)pMessage;
+  SA_DBG4(("saSATAStart: Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage)));
+
+
+  switch ( agRequestType )
+  {
+  case AGSA_SATA_PROTOCOL_FPDMA_READ:
+  case AGSA_SATA_PROTOCOL_FPDMA_WRITE:
+  case AGSA_SATA_PROTOCOL_FPDMA_READ_M:
+  case AGSA_SATA_PROTOCOL_FPDMA_WRITE_M:
+    pSgl = &(agSATAReq->agSgl);
+    AtapDir = agRequestType & (AGSA_DIR_MASK | AGSA_SATA_ATAP_MASK);
+    if (agRequestType & AGSA_MSG)
+    {
+      /* set M bit */
+      AtapDir |= AGSA_MSG_BIT;
+    }
+    break;
+  case AGSA_SATA_PROTOCOL_DMA_READ:
+  case AGSA_SATA_PROTOCOL_DMA_WRITE:
+  case AGSA_SATA_PROTOCOL_DMA_READ_M:
+  case AGSA_SATA_PROTOCOL_DMA_WRITE_M:
+  case AGSA_SATA_PROTOCOL_PIO_READ_M:
+  case AGSA_SATA_PROTOCOL_PIO_WRITE_M:
+  case AGSA_SATA_PROTOCOL_PIO_READ:
+  case AGSA_SATA_PROTOCOL_PIO_WRITE:
+  case AGSA_SATA_PROTOCOL_H2D_PKT:
+  case AGSA_SATA_PROTOCOL_D2H_PKT:
+    agTag = 0; /* agTag not valid for these requests */
+    pSgl = &(agSATAReq->agSgl);
+    AtapDir = agRequestType & (AGSA_DIR_MASK | AGSA_SATA_ATAP_MASK);
+    if (agRequestType & AGSA_MSG)
+    {
+      /* set M bit */
+      AtapDir |= AGSA_MSG_BIT;
+    }
+    break;
+
+  case AGSA_SATA_PROTOCOL_NON_DATA:
+  case AGSA_SATA_PROTOCOL_NON_DATA_M:
+  case AGSA_SATA_PROTOCOL_NON_PKT:
+    agTag = 0; /* agTag not valid for these requests */
+    AtapDir = agRequestType & (AGSA_DIR_MASK | AGSA_SATA_ATAP_MASK);
+    if (agRequestType & AGSA_MSG)
+    {
+      /* set M bit */
+      AtapDir |= AGSA_MSG_BIT;
+    }
+    break;
+
+  case AGSA_SATA_PROTOCOL_SRST_ASSERT:
+    agTag = 0; /* agTag not valid for these requests */
+    AtapDir = AGSA_SATA_ATAP_SRST_ASSERT;
+    break;
+
+  case AGSA_SATA_PROTOCOL_SRST_DEASSERT:
+    agTag = 0; /* agTag not valid for these requests */
+    AtapDir = AGSA_SATA_ATAP_SRST_DEASSERT;
+    break;
+
+  case AGSA_SATA_PROTOCOL_DEV_RESET:
+  case AGSA_SATA_PROTOCOL_DEV_RESET_M: /* TestBase */
+    agTag = 0; /* agTag not valid for these requests */
+    AtapDir = AGSA_SATA_ATAP_PKT_DEVRESET;
+    if (agRequestType & AGSA_MSG)
+    {
+      /* set M bit */
+      AtapDir |= AGSA_MSG_BIT; /* TestBase */
+    }
+    break;
+
+  default:
+    SA_DBG1(("saSATAStart: (Unknown agRequestType) 0x%X \n",agRequestType));
+    SA_ASSERT((0), "saSATAStart: (Unknown agRequestType)");
+
+    break;
+  }
+
+  if ((AGSA_SATA_PROTOCOL_SRST_ASSERT == agRequestType) ||
+       (AGSA_SATA_PROTOCOL_SRST_DEASSERT == agRequestType) ||
+       (AGSA_SATA_PROTOCOL_DEV_RESET == agRequestType))
+  {
+
+    SA_DBG3(("saSATAStart:AGSA_SATA_PROTOCOL_SRST_DEASSERT AGSA_SATA_PROTOCOL_SRST_ASSERT\n"));
+
+    si_memset((void *)payload, 0, sizeof(agsaSATAStartCmd_t));
+    /* build IOMB DW 1 */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t, tag), pRequest->HTag);
+    /* DWORD 2 */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,deviceId ), deviceIndex);
+    /* DWORD 3 */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,dataLen ), 0 );
+    /* DWORD 4 */
+    OSSA_WRITE_LE_32(agRoot, 
+                    payload, 
+                    OSSA_OFFSET_OF(agsaSATAStartCmd_t,optNCQTagataProt ),
+                    (((agSATAReq->option & SATA_FIS_MASK) << SHIFT24)    |
+                    (agTag << SHIFT16)                                   |
+                    AtapDir));
+
+   si_memcpy((void *)(payload+4), (void *)&agSATAReq->fis.fisRegHostToDev, sizeof(agsaFisRegHostToDevice_t));
+  }
+  else
+  {
+    /* build IOMB DW 1 */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t, tag), pRequest->HTag);
+    /* DWORD 2 */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,deviceId ), deviceIndex);
+    /* DWORD 3 */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,dataLen ),  agSATAReq->dataLength );
+
+     /* Since we are writing the payload in order, check for any special modes now. */
+    if (agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION)
+    {
+        SA_ASSERT((opCode == OPC_INB_SATA_DIF_ENC_OPSTART), "opcode");
+        SA_DBG4(("saSATAStart: 1 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage)));
+        AtapDir |= AGSA_ENCRYPT_BIT;
+    }
+
+    if (agSATAReq->option & AGSA_SATA_ENABLE_DIF)
+    {
+        SA_ASSERT((opCode == OPC_INB_SATA_DIF_ENC_OPSTART), "opcode");
+        AtapDir |= AGSA_DIF_BIT;
+    }
+#ifdef CCBUILD_TEST_EPL
+    if(agSATAReq->encrypt.enableEncryptionPerLA)
+        AtapDir |= (1 << SHIFT4);        // enable EPL
+#endif
+    /* DWORD 4 */
+    OSSA_WRITE_LE_32(agRoot, 
+                    payload, 
+                    OSSA_OFFSET_OF(agsaSATAStartCmd_t,optNCQTagataProt ),
+                  (((agSATAReq->option & SATA_FIS_MASK) << SHIFT24) |
+                    (agTag << SHIFT16)                              |
+                    AtapDir));
+
+    /* DWORD 5 6 7 8 9 */
+    si_memcpy((void *)(payload+4), (void *)&agSATAReq->fis.fisRegHostToDev, sizeof(agsaFisRegHostToDevice_t));
+    /* DWORD 10 reserved */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,reserved1 ),  0 );
+
+    /* DWORD 11 reserved */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,reserved2 ),  0 );
+
+    SA_DBG4(("saSATAStart: 2 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage)));
+  }
+  if (agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION)
+  {
+    /* Write 10 dwords of zeroes as payload, skipping all DIF fields */
+    SA_DBG4(("saSATAStart: 2a Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage)));
+    if (opCode == OPC_INB_SATA_DIF_ENC_OPSTART)
+    {
+      /* DW 11 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_EPL_DESCL ),0 );
+      /* DW 12 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,resSKIPBYTES ),0 );
+       /* DW 13 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_DPL_DESCL_NDPLR ),0 );
+      /* DW 14 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_EDPL_DESCH ),0 );
+      /* DW 15 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,DIF_flags ),0 );
+      /* DW 16 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,udt ),0 );
+      /* DW 17 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,udtReplacementLo ),0 );
+      /* DW 18 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,udtReplacementHi ),0 );
+      /* DW 19 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,DIF_seed ),0 );
+    }
+
+    if (agSATAReq->option & AGSA_SATA_ENABLE_ENCRYPTION)
+    {
+        SA_ASSERT((opCode == OPC_INB_SATA_DIF_ENC_OPSTART), "opcode");
+
+        SA_DBG4(("saSATAStart: 3 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage)));
+        /* Configure DWORD 20 */
+        encryptFlags = 0;
+
+        if (agSATAReq->encrypt.keyTagCheck == agTRUE)
+        {
+          encryptFlags |= AGSA_ENCRYPT_KEY_TAG_BIT;
+        }
+
+        if( agSATAReq->encrypt.cipherMode == agsaEncryptCipherModeXTS )
+        {
+          encryptFlags |= AGSA_ENCRYPT_XTS_Mode << SHIFT4;
+        }
+
+        encryptFlags |= agSATAReq->encrypt.dekInfo.dekTable << SHIFT2;
+
+        encryptFlags |= (agSATAReq->encrypt.dekInfo.dekIndex & 0xFFFFFF) << SHIFT8;
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,encryptFlagsLo ),encryptFlags );
+
+        /* Configure DWORD 21*/
+        /* This information is available in the sectorSizeIndex */
+        encryptFlags = agSATAReq->encrypt.sectorSizeIndex;
+        /*
+         * Set Region0 sectors count
+         */
+        if(agSATAReq->encrypt.enableEncryptionPerLA)
+        {
+            encryptFlags |= (agSATAReq->encrypt.EncryptionPerLRegion0SecCount << SHIFT16);
+        }
+
+        encryptFlags |= (agSATAReq->encrypt.kekIndex) << SHIFT5;
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,encryptFlagsHi ),encryptFlags );
+
+        /* Configure DWORD 22*/
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagLo ),  agSATAReq->encrypt.keyTag_W0 );
+        /* Configure DWORD 23 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagHi ),  agSATAReq->encrypt.keyTag_W1 );
+        /* Configure DWORD 24 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W0 ), agSATAReq->encrypt.tweakVal_W0  );
+        /* Configure DWORD 25 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W1 ), agSATAReq->encrypt.tweakVal_W1  );
+        /* Configure DWORD 26 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W2 ), agSATAReq->encrypt.tweakVal_W2  );
+        /* Configure DWORD 27 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W3 ), agSATAReq->encrypt.tweakVal_W3  );
+    }
+    else
+    {
+      /* Write 8 dwords of zeros as payload, skipping all encryption fields */
+      if (opCode == OPC_INB_SATA_DIF_ENC_OPSTART)
+      {
+        /* Configure DWORD 22*/
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagLo ), 0 );
+        /* Configure DWORD 23 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,keyTagHi ), 0 );
+        /* Configure DWORD 24 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W0 ), 0  );
+        /* Configure DWORD 25 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W1 ), 0  );
+        /* Configure DWORD 26 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W2 ), 0  );
+        /* Configure DWORD 27 */
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,tweakVal_W3 ), 0  );
+      }
+    }
+
+    SA_DBG4(("saSATAStart: 4 Payload offset 0x%X\n", (unsigned int)(payload - (bit32 *)pMessage)));
+
+    /* DWORD 11 13 14*/
+    if(agSATAReq->encrypt.enableEncryptionPerLA)
+    {
+      /* DWORD 11 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_EPL_DESCL),
+                         agSATAReq->encrypt.EncryptionPerLAAddrLo);
+      /* DWORD 13 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_DPL_DESCL_NDPLR), 0);
+      /* DWORD 14 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_EDPL_DESCH),
+                      agSATAReq->encrypt.EncryptionPerLAAddrHi);
+    }
+    else
+    {
+      /* DWORD 11 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_EPL_DESCL),0);
+      /* DW 13 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t, Res_DPL_DESCL_NDPLR), 0);
+      /* DWORD 14 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Res_EDPL_DESCH ),0 );
+    }
+
+    /* Configure DWORD 28 for encryption*/
+    if (pSgl)
+    {
+      /* Configure DWORD 28 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrLow0 ),  pSgl->sgLower );
+      /* Configure DWORD 29 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrHi0 ), pSgl->sgUpper  );
+      /* Configure DWORD 30 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Len0 ),  pSgl->len );
+      /* Configure DWORD 31 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,E0 ), pSgl->extReserved  );
+    }
+    else
+    {
+      /* Configure DWORD 28 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrLow0 ),  0 );
+      /* Configure DWORD 29 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,AddrHi0 ),  0 );
+      /* Configure DWORD 30 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,Len0 ),  0 );
+      /* Configure DWORD 31 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAEncryptStartCmd_t,E0 ),  0 );
+    }
+
+  }
+  else
+  {
+    SA_ASSERT((opCode == OPC_INB_SATA_HOST_OPSTART), "opcode");
+    if (pSgl)
+    {
+      /* Configure DWORD 12 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrLow0 ),  pSgl->sgLower );
+      /* Configure DWORD 13 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrHi0 ), pSgl->sgUpper  );
+      /* Configure DWORD 14 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,Len0 ),  pSgl->len );
+      /* Configure DWORD 15 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,E0 ), pSgl->extReserved  );
+    }
+    else
+    {
+      /* Configure DWORD 12 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrLow0 ),  0 );
+      /* Configure DWORD 13 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,AddrHi0 ),  0 );
+      /* Configure DWORD 14 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,Len0 ),  0 );
+      /* Configure DWORD 15 */
+      OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,E0 ),  0 );
+    }
+    /* support ATAPI packet command */
+    if ((agRequestType == AGSA_SATA_PROTOCOL_NON_PKT ||
+        agRequestType == AGSA_SATA_PROTOCOL_H2D_PKT ||
+        agRequestType == AGSA_SATA_PROTOCOL_D2H_PKT))
+     {
+         /*DWORD 16 - 19 as SCSI CDB for support ATAPI Packet command*/
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB ),
+                        (bit32)(agSATAReq->scsiCDB[0]|(agSATAReq->scsiCDB[1]<<8)|(agSATAReq->scsiCDB[2]<<16)|(agSATAReq->scsiCDB[3]<<24)));
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB )+ 4,
+                        (bit32)(agSATAReq->scsiCDB[4]|(agSATAReq->scsiCDB[5]<<8)|(agSATAReq->scsiCDB[6]<<16)|(agSATAReq->scsiCDB[7]<<24)));
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB )+ 8,
+                        (bit32)(agSATAReq->scsiCDB[8]|(agSATAReq->scsiCDB[9]<<8)|(agSATAReq->scsiCDB[10]<<16)|(agSATAReq->scsiCDB[11]<<24)));
+        OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAStartCmd_t,ATAPICDB )+ 12,
+                        (bit32)(agSATAReq->scsiCDB[12]|(agSATAReq->scsiCDB[13]<<8)|(agSATAReq->scsiCDB[14]<<16)|(agSATAReq->scsiCDB[15]<<24)));
+     }
+  }
+
+  /* send IOMB to SPC */
+  ret = mpiMsgProduce(circularQ,
+                      (void *)pMessage,
+                      MPI_CATEGORY_SAS_SATA,
+                      opCode,
+                      outq,
+                      (bit8)circularQ->priority);
+
+#ifdef SA_LL_IBQ_PROTECT
+  ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+#ifdef SALL_API_TEST
+  if (AGSA_RC_FAILURE != ret)
+  {
+    saRoot->LLCounters.IOCounter.numSataStarted++;
+  }
+#endif
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "8a");
+
+ext:
+  OSSA_INP_LEAVE(agRoot);
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Abort SATA command
+ *
+ *  Abort SATA command
+ *
+ *  \param agRoot      handles for this instance of SAS/SATA hardware
+ *  \param queueNum    inbound/outbound queue number
+ *  \param agIORequest the IO Request descriptor
+ *  \param agIOtoBeAborted
+ *
+ *  \return If command is aborted successfully
+ *          - \e AGSA_RC_SUCCESS command is aborted successfully
+ *          - \e AGSA_RC_FAILURE command is not aborted successfully
+ */
+/*******************************************************************************/
+GLOBAL bit32 saSATAAbort(
+  agsaRoot_t      *agRoot,
+  agsaIORequest_t *agIORequest,
+  bit32           queueNum,
+  agsaDevHandle_t *agDevHandle,
+  bit32           flag,
+  void            *abortParam,
+  ossaGenericAbortCB_t   agCB
+  )
+{
+  bit32 ret = AGSA_RC_SUCCESS, retVal;
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaIORequestDesc_t *pRequest;
+  agsaIORequestDesc_t *pRequestABT = agNULL;
+  agsaDeviceDesc_t    *pDevice = agNULL;
+  agsaDeviceDesc_t    *pDeviceABT = NULL;
+  agsaPort_t          *pPort = agNULL;
+  mpiICQueue_t        *circularQ;
+  void                *pMessage;
+  agsaSATAAbortCmd_t  *payload;
+  agsaIORequest_t     *agIOToBeAborted;
+  bit8                inq, outq;
+  bit32               flag_copy = flag;
+
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"8b");
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  SA_ASSERT((agNULL != agIORequest), "");
+
+  SA_DBG3(("saSATAAbort: Aborting request %p ITtoBeAborted %p\n", agIORequest, abortParam));
+
+  /* Assign inbound and outbound Ring Buffer */
+  inq = (bit8)(queueNum & MPI_IB_NUM_MASK);
+  outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT);
+  SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range.");
+
+  if( ABORT_SINGLE == (flag & ABORT_MASK) )
+  {
+    agIOToBeAborted = (agsaIORequest_t *)abortParam;
+    /* Get LL IORequest entry for saSATAAbort() */
+    pRequest = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData);
+    if (agNULL == pRequest)
+    {
+      /* no pRequest found - can not Abort */
+      SA_DBG1(("saSATAAbort: pRequest AGSA_RC_FAILURE\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "8b");
+      return AGSA_RC_FAILURE;
+    }
+    /* Find the device the request sent to */
+    pDevice = pRequest->pDevice;
+    /* Get LL IORequest entry */
+    pRequestABT = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData);
+    /* Find the device the request sent to */
+    if (agNULL == pRequestABT)
+    {
+      /* no pRequestABT - can not find pDeviceABT */
+      SA_DBG1(("saSATAAbort: pRequestABT AGSA_RC_FAILURE\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "8b");
+      return AGSA_RC_FAILURE;
+    }
+    pDeviceABT = pRequestABT->pDevice;
+
+    if (agNULL == pDeviceABT)
+    {
+      /* no deviceID - can not build IOMB */
+      SA_DBG1(("saSATAAbort: pDeviceABT AGSA_RC_FAILURE\n"));
+
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "8b");
+      return AGSA_RC_FAILURE;
+    }
+
+    if (agNULL != pDevice)
+    {
+      /* Find the port the request was sent to */
+      pPort = pDevice->pPort;
+    }
+
+    /* Get request from free IORequests */
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests));
+  }
+  else
+  {
+    if (ABORT_ALL == (flag & ABORT_MASK))
+    {
+      /* abort all */
+      /* Find the outgoing port for the device */
+      pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+      pPort = pDevice->pPort;
+      ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests));
+    }
+    else
+    {
+      /* only support 00 and 01 for flag */
+      SA_DBG1(("saSATAAbort: flag AGSA_RC_FAILURE\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "8b");
+      return AGSA_RC_FAILURE;
+    }
+  }
+
+  /* If no LL IO request entry avalable */
+  if ( agNULL == pRequest )
+  {
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    SA_DBG1(("saSATAAbort, No request from free list\n" ));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "8b");
+    return AGSA_RC_BUSY;
+  }
+
+  /* If free IOMB avaliable */
+  /* Remove the request from free list */
+  saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode));
+
+  SA_ASSERT((!pRequest->valid), "The pRequest is in use");
+  /* Add the request to the pendingIORequests list of the device */
+  pRequest->valid = agTRUE;
+  saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+  /* set up pRequest */
+
+  ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+  pRequest->pIORequestContext = agIORequest;
+  pRequest->requestType = AGSA_SATA_REQTYPE;
+  pRequest->pDevice = pDevice;
+  pRequest->pPort = pPort;
+  pRequest->completionCB = (void*)agCB;
+/* pRequest->abortCompletionCB = agCB; */
+  pRequest->startTick = saRoot->timeTick;
+
+  /* Set request to the sdkData of agIORequest */
+  agIORequest->sdkData = pRequest;
+
+  /* save tag and IOrequest pointer to IOMap */
+  saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag;
+  saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest;
+
+#ifdef SA_LL_IBQ_PROTECT
+  ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+  /* If LL IO request entry avaliable */
+  /* Get a free inbound queue entry */
+  circularQ = &saRoot->inboundQueue[inq];
+  retVal    = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage);
+
+  /* if message size is too large return failure */
+  if (AGSA_RC_FAILURE == retVal)
+  {
+#ifdef SA_LL_IBQ_PROTECT
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+    pRequest->valid = agFALSE;
+    saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+    SA_DBG1(("saSATAAbort, error when get free IOMB\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "8b");
+    return AGSA_RC_FAILURE;
+  }
+
+  /* return busy if inbound queue is full */
+  if (AGSA_RC_BUSY == retVal)
+  {
+#ifdef SA_LL_IBQ_PROTECT
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+    pRequest->valid = agFALSE;
+    saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+    SA_DBG1(("saSATASAbort, no more IOMB\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "8b");
+    return AGSA_RC_BUSY;
+  }
+
+
+  /* setup payload */
+  payload = (agsaSATAAbortCmd_t*)pMessage;
+  OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, tag), pRequest->HTag);
+
+  if( ABORT_SINGLE == (flag & ABORT_MASK) )
+  {
+    /* If no device  */
+    if ( agNULL == pDeviceABT )
+    {
+      #ifdef SA_LL_IBQ_PROTECT
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+      #endif /* SA_LL_IBQ_PROTECT */
+
+      ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+      pRequest->valid = agFALSE;
+      saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+      SA_DBG1(("saSATAAbort,no device\n" ));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "8b");
+      return AGSA_RC_FAILURE;
+    }
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, deviceId), pDeviceABT->DeviceMapIndex);
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, HTagAbort), pRequestABT->HTag);
+  }
+  else
+  {
+    /* abort all */
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, deviceId), pDevice->DeviceMapIndex);
+    OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, HTagAbort), 0);
+  }
+
+  if(flag & ABORT_TSDK_QUARANTINE)
+  {
+    if(smIS_SPCV(agRoot))
+    {
+      flag_copy &= ABORT_SCOPE;
+      flag_copy |= ABORT_QUARANTINE_SPCV;
+    }
+  }
+  OSSA_WRITE_LE_32(agRoot, payload, OSSA_OFFSET_OF(agsaSATAAbortCmd_t, abortAll), flag_copy);
+
+
+
+  SA_DBG1(("saSATAAbort, HTag 0x%x HTagABT 0x%x deviceId 0x%x\n", payload->tag, payload->HTagAbort, payload->deviceId));
+
+  /* post the IOMB to SPC */
+  ret = mpiMsgProduce(circularQ, (void *)pMessage, MPI_CATEGORY_SAS_SATA, OPC_INB_SATA_ABORT, outq, (bit8)circularQ->priority);
+
+#ifdef SA_LL_IBQ_PROTECT
+  ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+#ifdef SALL_API_TEST
+  if (AGSA_RC_FAILURE != ret)
+  {
+    saRoot->LLCounters.IOCounter.numSataAborted++;
+  }
+#endif
+
+  siCountActiveIORequestsOnDevice( agRoot,   payload->deviceId );
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "8b");
+
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Routine to handle for received SATA with data payload event
+ *
+ *  The handle for received SATA with data payload event
+ *
+ *  \param agRoot       handles for this instance of SAS/SATA hardware
+ *  \param pRequest     the IO request descriptor
+ *  \param agFirstDword pointer to the first Dword
+ *  \param pResp        pointer to the rest of SATA response
+ *  \param lengthResp   total length of SATA Response frame
+ *
+ *  \return -void-
+ */
+/*******************************************************************************/
+GLOBAL void siEventSATAResponseWtDataRcvd(
+  agsaRoot_t              *agRoot,
+  agsaIORequestDesc_t     *pRequest,
+  bit32                   *agFirstDword,
+  bit32                   *pResp,
+  bit32                   lengthResp
+  )
+{
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaDeviceDesc_t    *pDevice;
+#if defined(SALLSDK_DEBUG)
+  agsaFrameHandle_t   frameHandle;
+  /* get frame handle */
+  frameHandle = (agsaFrameHandle_t)(pResp);
+#endif  /* SALLSDK_DEBUG */
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"8c");
+
+  /* If the request is still valid */
+  if ( agTRUE == pRequest->valid )
+  {
+    /* get device */
+    pDevice = pRequest->pDevice;
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+    /* Delete the request from the pendingIORequests */
+    saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+    (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot,
+                                                       pRequest->pIORequestContext,
+                                                       OSSA_IO_SUCCESS,
+                                                       agFirstDword,
+                                                       lengthResp,
+                                                       (void *)pResp);
+
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    pRequest->valid = agFALSE;
+    /* return the request to free pool */
+    saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+  }
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "8c");
+
+  return;
+}
+
+/******************************************************************************/
+/*! \brief copy a SATA signature to another
+ *
+ *  copy a SATA signature to another
+ *
+ *  \param pDstSignature pointer to the destination signature
+ *  \param pSrcSignature pointer to the source signature
+ *
+ *  \return If they match
+ *          - \e agTRUE match
+ *          - \e agFALSE  doesn't match
+ */
+/*******************************************************************************/
+GLOBAL void siSATASignatureCpy(
+  bit8  *pDstSignature,
+  bit8  *pSrcSignature
+  )
+{
+  bit32   i;
+
+  for ( i = 0; i < 5; i ++ )
+  {
+    pDstSignature[i] = pSrcSignature[i];
+  }
+
+  return;
+}
+
+
+

sys/dev/pms/RefTisa/sallsdk/spc/sasmp.c

@@ -0,0 +1,727 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/*! \file sasmp.c
+ *  \brief The file implements the functions for SMP request/response
+ *
+ */
+/*******************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#ifdef siTraceFileID
+#undef siTraceFileID
+#endif
+#define siTraceFileID 'N'
+#endif
+
+/******************************************************************************/
+/*! \brief Start SMP request
+ *
+ *  Start SMP request
+ *
+ *  \param agRoot handles for this instance of SAS/SATA hardware
+ *  \param queueNum
+ *  \param agIORequest
+ *  \param agDevHandle
+ *  \param agRequestType
+ *  \param agRequestBody
+ *  \param agCB
+ * Spc - support    direct mode direct response
+ * SpcV - support   direct mode direct response
+ * SpcV - support indirect mode  direct response
+ * SpcV - support indirect mode indirect response
+ *
+ *  \return If request is started successfully
+ *          - \e AGSA_RC_SUCCESS request is started successfully
+ *          - \e AGSA_RC_BUSY No resource available, try again later
+ */
+/*******************************************************************************/
+GLOBAL bit32 saSMPStart(
+  agsaRoot_t            *agRoot,
+  agsaIORequest_t       *agIORequest,
+  bit32                 queueNum,
+  agsaDevHandle_t       *agDevHandle,
+  bit32                 agRequestType,
+  agsaSASRequestBody_t  *agRequestBody,
+  ossaSMPCompletedCB_t  agCB
+  )
+{
+  bit32                     ret = AGSA_RC_SUCCESS, retVal;
+  agsaLLRoot_t              *saRoot = agNULL;
+  mpiICQueue_t              *circularQ;
+  agsaDeviceDesc_t          *pDevice;
+  agsaPort_t                *pPort;
+  agsaIORequestDesc_t       *pRequest;
+  void                      *pMessage;
+  bit8                      i, inq, outq;
+  bit8                      using_reserved = agFALSE;
+  bit8                      *payload_ptr;
+  agsaSMPFrame_t            *pSMPFrame;
+
+  SA_DBG4(("saSMPStart: start\n"));
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD, "9a");
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  SA_ASSERT((agNULL != agIORequest), "");
+  SA_ASSERT((agNULL != agDevHandle), "");
+  SA_ASSERT((agNULL != agRequestBody), "");
+
+  /* sanity check */
+  saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  SA_ASSERT((agNULL != saRoot), "");
+
+  if(saRoot == agNULL)
+  {
+    SA_DBG1(("saSMPStart : saRoot is NULL!!\n"));
+    return AGSA_RC_FAILURE;
+  }
+  
+  /* Assign inbound and outbound queue number */
+  inq = (bit8)(queueNum & MPI_IB_NUM_MASK);
+  outq = (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT);
+  SA_ASSERT((AGSA_MAX_INBOUND_Q > inq), "The IBQ Number is out of range.");
+
+  /* Find the outgoing port for the device */
+  if (agNULL == agDevHandle->sdkData)
+  {
+    /* Device has been removed */
+    SA_DBG1(("saSMPStart, Device has been removed. agDevHandle=%p\n", agDevHandle));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "9a");
+    return AGSA_RC_FAILURE;
+  }
+
+  pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+
+  pPort = pDevice->pPort;
+
+  /* Get request from free IO Requests */
+  ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+  pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests)); /**/
+
+  /* If no LL IO request entry available */
+  if ( agNULL == pRequest )
+  {
+
+    pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests));
+
+    if(agNULL != pRequest)
+    {
+      using_reserved = agTRUE;
+      SA_DBG1(("saSMPStart, using saRoot->freeReservedRequests\n"));
+    }
+    else
+    {
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      SA_DBG1(("saSMPStart, No request from free list Not using saRoot->freeReservedRequests\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "9a");
+      return AGSA_RC_BUSY;
+    }
+  }
+
+  /* If free IOMB avaliable */
+  /* Remove the request from free list */
+  if( using_reserved )
+  {
+    saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
+  }
+  else
+  {
+    saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode));
+  }
+
+  /* Add the request to the pendingSMPRequests list of the device */
+  saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+  SA_ASSERT((!pRequest->valid), "The pRequest is in use");
+  pRequest->valid             = agTRUE;
+  ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+  /* set up pRequest */
+  pRequest->pIORequestContext = agIORequest;
+  pRequest->pDevice           = pDevice;
+  pRequest->pPort             = pPort;
+  pRequest->requestType       = agRequestType;
+  pRequest->startTick         = saRoot->timeTick;
+  pRequest->completionCB      = (ossaSSPCompletedCB_t)agCB;
+
+  /* Set request to the sdkData of agIORequest */
+  agIORequest->sdkData        = pRequest;
+
+  /* save tag to IOMap */
+  saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag;
+  saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest;
+
+#ifdef SA_LL_IBQ_PROTECT
+  ossaSingleThreadedEnter(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+  /* If LL IO request entry avaliable */
+  /* Get a free inbound queue entry */
+  circularQ = &saRoot->inboundQueue[inq];
+  retVal    = mpiMsgFreeGet(circularQ, IOMB_SIZE64, &pMessage);
+
+  if (AGSA_RC_FAILURE == retVal)
+  {
+#ifdef SA_LL_IBQ_PROTECT
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+    /* if not sending return to free list rare */
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+    pRequest->valid = agFALSE;
+    saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+    SA_DBG1(("saSMPStart, error when get free IOMB\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "9a");
+    return AGSA_RC_FAILURE;
+  }
+
+  /* return busy if inbound queue is full */
+  if (AGSA_RC_BUSY == retVal)
+  {
+#ifdef SA_LL_IBQ_PROTECT
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+    /* if not sending return to free list rare */
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+    pRequest->valid = agFALSE;
+    saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+
+    SA_DBG1(("saSMPStart, no more IOMB\n"));
+    smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "9a");
+    return AGSA_RC_BUSY;
+  }
+
+  /* Setup SMP Frame */
+  pSMPFrame = (agsaSMPFrame_t *) &(agRequestBody->smpFrame);
+
+  SA_DBG2(("saSMPStart:DeviceMapIndex 0x%x portId 0x%x portId 0x%x\n",pDevice->DeviceMapIndex,pPort->portId,pPort->portId));
+
+#if defined(SALLSDK_DEBUG)
+
+  SA_DBG2(("saSMPStart: outFrameBuf  %p\n",pSMPFrame->outFrameBuf));
+
+  if(pSMPFrame->outFrameBuf )
+  {
+    SA_DBG2(("saSMPStart: outFrameBuf 0  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+0) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 1  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+1) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 2  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+2) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 3  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+3) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 4  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+4) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 5  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+5) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 6  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+6) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 7  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+7) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 8  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+8) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 9  0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+9) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 11 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+10) ));
+    SA_DBG2(("saSMPStart: outFrameBuf 11 0x%08X\n",*((bit32*)pSMPFrame->outFrameBuf+11) ));
+  }
+  SA_DBG2(("saSMPStart: outFrameAddrUpper32 0x%08X\n",pSMPFrame->outFrameAddrUpper32));
+  SA_DBG2(("saSMPStart: outFrameAddrLower32 0x%08X\n",pSMPFrame->outFrameAddrLower32));
+  SA_DBG2(("saSMPStart: outFrameLen         0x%08X\n",pSMPFrame->outFrameLen));
+  SA_DBG2(("saSMPStart: inFrameAddrUpper32  0x%08X\n",pSMPFrame->inFrameAddrUpper32));
+  SA_DBG2(("saSMPStart: inFrameAddrLower32  0x%08X\n",pSMPFrame->inFrameAddrLower32));
+  SA_DBG2(("saSMPStart: inFrameLen          0x%08X\n",pSMPFrame->inFrameLen));
+  SA_DBG2(("saSMPStart: expectedRespLen     0x%08X\n",pSMPFrame->expectedRespLen));
+  SA_DBG2(("saSMPStart: flag                0x%08X\n",pSMPFrame->flag));
+#endif /* SALLSDK_DEBUG */
+
+  if(smIS_SPC(agRoot))
+  // if(1)
+  {
+    agsaSMPCmd_t payload;
+    switch ( agRequestType )
+    {
+      case AGSA_SMP_INIT_REQ:
+      {
+        bit32 IR_IP_OV_res_phyId_DPdLen_res = 0;
+        /* Prepare the payload of IOMB */
+        si_memset(&payload, 0, sizeof(agsaSMPCmd_t));
+        OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, tag), pRequest->HTag);
+        OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, deviceId), pDevice->DeviceMapIndex);
+
+        /* check SMP Response Frame with IR mode */
+        /* check if the SMP Response is indirect mode */
+        if (0 == pSMPFrame->inFrameLen)
+        {
+          /* PHY override not support */
+          /* Direct Response mode */
+          pRequest->IRmode = DIRECT_MODE;
+        }
+        else
+        {
+          /* Indirect Response mode */
+          pRequest->IRmode = INDIRECT_MODE;
+          IR_IP_OV_res_phyId_DPdLen_res = 1;
+          /* check SMP direct payload mode len */
+          if (pSMPFrame->outFrameLen > 32)
+          {
+#ifdef SA_LL_IBQ_PROTECT
+            ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+            /* if not sending return to free list rare */
+            ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+            saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+            pRequest->valid = agFALSE;
+            saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+            ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+            /* can not handle SMP frame length > 32 bytes it if IP=0 and IR=1 */
+            SA_DBG1(("saSMPStart, outFrameLen > 32 bytes error.\n"));
+            smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "9a");
+            return AGSA_RC_FAILURE;
+          }
+        }
+
+        /* check Direct mode or Indirect mode for IP mode */
+        if ( (pSMPFrame->outFrameBuf &&
+              (pSMPFrame->outFrameLen <= AGSA_MAX_SMPPAYLOAD_VIA_SFO)) ||
+             ((pSMPFrame->outFrameBuf == agNULL) &&
+              (pSMPFrame->outFrameLen == 0) )
+           )
+        {
+          SA_DBG4(("saSMPStart: DIRECT Request SMP\n"));
+
+          IR_IP_OV_res_phyId_DPdLen_res = (DIRECT_MODE << 1) | IR_IP_OV_res_phyId_DPdLen_res;
+
+          /* Direct payload length */
+          IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16);
+
+          /* copy payload - upto 48 bytes */
+          si_memcpy(&(payload.SMPCmd[0]),pSMPFrame->outFrameBuf,pSMPFrame->outFrameLen);
+          for ( i = 0; i < pSMPFrame->outFrameLen / sizeof(bit32)+1; i ++ )
+          {
+            SA_DBG4(("saSMPStart: payload.SMPCmd[%d] %x\n", i, payload.SMPCmd[i]));
+          }
+        }
+        else
+        {
+          SA_DBG4(("saSMPStart: INDIRECT Request SMP\n"));
+          /* use physical address */
+          IR_IP_OV_res_phyId_DPdLen_res = (INDIRECT_MODE << 1) | IR_IP_OV_res_phyId_DPdLen_res;
+
+          /* Direct payload length = 0 */
+          IR_IP_OV_res_phyId_DPdLen_res = IR_IP_OV_res_phyId_DPdLen_res & 0xff00ffff;
+
+          /* payload */
+          OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[4]), (pSMPFrame->outFrameAddrLower32));
+          OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[5]), (pSMPFrame->outFrameAddrUpper32));
+          OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[6]), (pSMPFrame->outFrameLen));
+        }
+        /* Write IR_IP_OV_res_phyId_DPdLen_res field in the payload*/
+        OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res);
+
+        /* check IR bit */
+        if (IR_IP_OV_res_phyId_DPdLen_res & INDIRECT_MODE)
+        {
+          /* setup indirect response frame address */
+          OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[8]), (pSMPFrame->inFrameAddrLower32));
+          OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[9]), (pSMPFrame->inFrameAddrUpper32));
+          OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPCmd_t, SMPCmd[10]), (pSMPFrame->inFrameLen));
+        }
+
+        /* Build IOMB command and send it to SPC */
+        payload_ptr = (bit8 *)&payload;
+        ret = mpiSMPCmd(agRoot, pMessage, OPC_INB_SMP_REQUEST, (agsaSMPCmd_t *)payload_ptr, inq, outq);
+
+  #ifdef SA_LL_IBQ_PROTECT
+        ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+  #endif /* SA_LL_IBQ_PROTECT */
+
+        break;
+      }
+      default:
+      {
+        SA_DBG1(("saSMPStart: SPC unknown agRequestType  %x\n",agRequestType));
+        break;
+      }
+    }
+
+#ifdef SALL_API_TEST
+  if (ret == AGSA_RC_SUCCESS)
+    saRoot->LLCounters.IOCounter.numSMPStarted++;
+#endif
+  }
+  else /* IOMB is different for SPCV SMP */
+  {
+   agsaSMPCmd_V_t vpayload;
+
+    switch ( agRequestType )
+    {
+      case AGSA_SMP_INIT_REQ:
+      {
+        bit32 IR_IP_OV_res_phyId_DPdLen_res = 0;
+        /* Prepare the payload of IOMB */
+        si_memset(&vpayload, 0, sizeof(agsaSMPCmd_V_t));
+        OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, tag), pRequest->HTag);
+        OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, deviceId), pDevice->DeviceMapIndex);
+
+        /* Request header must be valid regardless of IP bit */
+        OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMPHDR ), *((bit32*)pSMPFrame->outFrameBuf+0) );
+
+        /* check SMP Response Frame with IR mode */
+        /* check if the SMP Response is indirect mode */
+        // smpFrameFlagDirectResponse smpFrameFlagDirectPayload
+        if ( 0 == pSMPFrame->flag && pSMPFrame->outFrameBuf )
+        {
+          /* PHY override not support */
+          /* Direct Response mode */
+          pRequest->IRmode = DIRECT_MODE;
+          SA_DBG2(("saSMPStart:V DIRECT Request SMP\n"));
+
+          IR_IP_OV_res_phyId_DPdLen_res = (DIRECT_MODE << 1) | IR_IP_OV_res_phyId_DPdLen_res;
+
+          /* Direct payload length */
+          IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16);
+          /* Write IR_IP_OV_res_phyId_DPdLen_res field in the payload*/
+          /* fatal error if missing */
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res);
+          /* fatal error if missing */
+
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP3_0 ), *((bit32*)pSMPFrame->outFrameBuf+1) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP7_4 ), *((bit32*)pSMPFrame->outFrameBuf+2) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP11_8), *((bit32*)pSMPFrame->outFrameBuf+3) );
+
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ),     *((bit32*)pSMPFrame->outFrameBuf+4) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ),  *((bit32*)pSMPFrame->outFrameBuf+5) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ),*((bit32*)pSMPFrame->outFrameBuf+6) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,R_or_SMPRF27_24),        *((bit32*)pSMPFrame->outFrameBuf+7) );
+
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRAL_or_SMPRF31_28 ),   *((bit32*)pSMPFrame->outFrameBuf+8) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRAH_or_SMPRF35_32 ),   *((bit32*)pSMPFrame->outFrameBuf+9) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,ISRL_or_SMPRF39_36 ),    *((bit32*)pSMPFrame->outFrameBuf+10) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,R_or_SMPRF43_40 ),       *((bit32*)pSMPFrame->outFrameBuf+11) );
+
+        }
+        else if (smpFrameFlagIndirectResponse & pSMPFrame->flag && smpFrameFlagIndirectPayload & pSMPFrame->flag) /* */
+        {
+          /* IR IP */
+          SA_DBG2(("saSMPStart:V smpFrameFlagIndirectResponse smpFrameFlagIndirectPayload SMP\n"));
+
+          pRequest->IRmode = INDIRECT_MODE;
+          IR_IP_OV_res_phyId_DPdLen_res = 3;
+
+          /* Indirect payload mode */
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ), pSMPFrame->outFrameAddrLower32);
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ), pSMPFrame->outFrameAddrUpper32);
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ), pSMPFrame->outFrameLen);
+          /* Indirect Response mode */
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAL_or_SMPRF31_28 ), (pSMPFrame->inFrameAddrLower32));
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAH_or_SMPRF35_32 ), (pSMPFrame->inFrameAddrUpper32));
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRL_or_SMPRF39_36 ), (pSMPFrame->inFrameLen));
+        }
+        else if (smpFrameFlagIndirectPayload & pSMPFrame->flag ) /* */
+        {
+          /* IP */
+          SA_DBG2(("saSMPStart:V  smpFrameFlagIndirectPayload SMP\n"));
+          pRequest->IRmode = DIRECT_MODE;
+          IR_IP_OV_res_phyId_DPdLen_res = 2;
+
+          /* Indirect payload mode */
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ), pSMPFrame->outFrameAddrLower32);
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ), pSMPFrame->outFrameAddrUpper32);
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ), pSMPFrame->outFrameLen);
+        }
+        else if (smpFrameFlagIndirectResponse & pSMPFrame->flag ) /* */
+        {
+          /* check IR bit */
+          /* Indirect Response mode */
+          pRequest->IRmode = INDIRECT_MODE;
+          SA_DBG2(("saSMPStart:V smpFrameFlagIndirectResponse SMP\n"));
+          /* use physical address */
+          IR_IP_OV_res_phyId_DPdLen_res = 1;
+          /* Direct payload length */
+          IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16);
+
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP3_0 ), *((bit32*)pSMPFrame->outFrameBuf+1) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP7_4 ), *((bit32*)pSMPFrame->outFrameBuf+2) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,SMP11_8), *((bit32*)pSMPFrame->outFrameBuf+3) );
+
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirL_SMPRF15_12 ),     *((bit32*)pSMPFrame->outFrameBuf+4) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirH_or_SMPRF19_16 ),  *((bit32*)pSMPFrame->outFrameBuf+5) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,IndirLen_or_SMPRF23_20 ),*((bit32*)pSMPFrame->outFrameBuf+6) );
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t,R_or_SMPRF27_24),        *((bit32*)pSMPFrame->outFrameBuf+7) );
+
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAL_or_SMPRF31_28 ), (pSMPFrame->inFrameAddrLower32));
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRAH_or_SMPRF35_32 ), (pSMPFrame->inFrameAddrUpper32));
+          OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, ISRL_or_SMPRF39_36 ), (pSMPFrame->inFrameLen));
+        }
+        IR_IP_OV_res_phyId_DPdLen_res |= (pSMPFrame->flag & 3);
+        /* fatal error if missing */
+        OSSA_WRITE_LE_32(agRoot, &vpayload, OSSA_OFFSET_OF(agsaSMPCmd_V_t, IR_IP_OV_res_phyId_DPdLen_res), IR_IP_OV_res_phyId_DPdLen_res);
+        /* fatal error if missing */
+      }
+      /* Build IOMB command and send it to SPCv */
+      payload_ptr = (bit8 *)&vpayload;
+      ret = mpiSMPCmd(agRoot, pMessage, OPC_INB_SMP_REQUEST, (agsaSMPCmd_t *)payload_ptr, inq, outq);
+
+#ifdef SA_LL_IBQ_PROTECT
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_IBQ0_LOCK + inq);
+#endif /* SA_LL_IBQ_PROTECT */
+
+      break;
+      default:
+      {
+        SA_DBG1(("saSMPStart: SPCv unknown agRequestType  %x\n",agRequestType));
+        break;
+      }
+    }
+  }
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "9a");
+
+  /* return */
+  return ret;
+}
+
+/******************************************************************************/
+/*! \brief Abort SMP request
+ *
+ *  Abort SMP request
+ *
+ *  \param agRoot handles for this instance of SAS/SATA hardware
+ *  \param queueNum
+ *  \param agIORequest
+ *
+ *  \return If request is aborted successfully
+ *          - \e AGSA_RC_SUCCESS request is aborted successfully
+ *          - \e AGSA_RC_FAILURE request is not aborted successfully
+ */
+/*******************************************************************************/
+GLOBAL bit32 saSMPAbort(
+  agsaRoot_t           *agRoot,
+  agsaIORequest_t      *agIORequest,
+  bit32                 queueNum,
+  agsaDevHandle_t      *agDevHandle,
+  bit32                 flag,
+  void                 *abortParam,
+  ossaGenericAbortCB_t  agCB
+  )
+{
+  bit32 ret = AGSA_RC_SUCCESS;
+  agsaLLRoot_t        *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaIORequestDesc_t *pRequest;
+  agsaIORequestDesc_t *pRequestABT = NULL;
+  agsaIORequest_t     *agIOToBeAborted;
+  agsaDeviceDesc_t    *pDevice;
+  agsaSMPAbortCmd_t   payload;
+  bit32               using_reserved = agFALSE;
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"9b");
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  SA_ASSERT((agNULL != agIORequest), "");
+  SA_ASSERT((agNULL != agDevHandle), "");
+
+  SA_DBG3(("saSMPAbort: Aborting request %p\n", agIORequest));
+
+  if( ABORT_SINGLE == (flag & ABORT_MASK) )
+  {
+    agIOToBeAborted = (agsaIORequest_t *)abortParam;
+    /* Get LL IORequest entry for saSMPAbort() */
+    pRequestABT = (agsaIORequestDesc_t *) (agIOToBeAborted->sdkData);
+    if (agNULL == pRequestABT)
+    {
+      /* The IO to Be Abort is no longer exist - can not Abort */
+      SA_DBG1(("saSMPAbort: pRequestABT AGSA_RC_FAILURE\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "9b");
+      return AGSA_RC_FAILURE;
+    }
+
+    /* Find the device the request Abort to */
+    pDevice = pRequestABT->pDevice;
+
+    if (agNULL == pDevice)
+    {
+      /* no deviceID - can not build IOMB */
+      SA_DBG1(("saSMPAbort: pDevice AGSA_RC_FAILURE\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "9b");
+      return AGSA_RC_FAILURE;
+    }
+  }
+  else
+  {
+    if (ABORT_ALL == (flag & ABORT_MASK))
+    {
+      /* abort All with Device or Port */
+      /* Find the outgoing port for the device */
+      pDevice = (agsaDeviceDesc_t *) (agDevHandle->sdkData);
+      if (agNULL == pDevice)
+      {
+        /* no deviceID - can not build IOMB */
+        SA_DBG1(("saSMPAbort:ABORT_ALL pDevice AGSA_RC_FAILURE\n"));
+        smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "9b");
+        return AGSA_RC_FAILURE;
+      }
+    }
+    else
+    {
+      /* only support 00 and 01 for flag */
+      SA_DBG1(("saSMPAbort:flag  AGSA_RC_FAILURE\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "9b");
+      return AGSA_RC_FAILURE;
+    }
+  }
+
+  /* Get LL IORequest entry */
+  ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+  pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests));
+
+  /* If no LL IO request entry available */
+  if ( agNULL == pRequest )
+  {
+    pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeReservedRequests)); /**/
+    /* If no LL Control request entry available */
+    if(agNULL != pRequest)
+    {
+      using_reserved = agTRUE;
+      SA_DBG1(("saSMPAbort, using saRoot->freeReservedRequests\n"));
+    }
+    else
+    {
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      SA_DBG1(("saSMPAbort, No request from free list Not using saRoot->freeReservedRequests\n"));
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "9b");
+      return AGSA_RC_BUSY;
+    }
+  }
+
+  /* If free IOMB avaliable */
+  /* Remove the request from free list */
+  if( using_reserved )
+  {
+    saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
+  }
+  else
+  {
+    saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode));
+  }
+
+  /* Add the request to the pendingSMPRequests list of the device */
+  saLlistIOAdd(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+  SA_ASSERT((!pRequest->valid), "The pRequest is in use");
+  pRequest->valid             = agTRUE;
+  ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+  /* set up pRequest */
+  pRequest->pIORequestContext = agIORequest;
+  pRequest->requestType       = AGSA_SMP_REQTYPE;
+  pRequest->completionCB = (void*)agCB;
+  pRequest->pDevice           = pDevice;
+  pRequest->startTick         = saRoot->timeTick;
+
+  /* Set request to the sdkData of agIORequest */
+  agIORequest->sdkData        = pRequest;
+
+  /* save tag to IOMap */
+  saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag;
+  saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest;
+
+  /* setup payload */
+  OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, tag), pRequest->HTag);
+
+  if( ABORT_SINGLE == (flag & ABORT_MASK) )
+  {
+    if (agNULL == pRequestABT)
+    {
+      /* remove the request from IOMap */
+      saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF;
+      saRoot->IOMap[pRequest->HTag].IORequest = agNULL;
+      saRoot->IOMap[pRequest->HTag].agContext = agNULL;
+      /* Delete the request from the pendingSMPRequests */
+      ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+      /* return the request to free pool */
+      if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT)
+      {
+        SA_DBG1(("saSMPAbort: saving pRequest (%p) for later use\n", pRequest));
+        saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
+      }
+      else
+      {
+        /* return the request to free pool */
+        saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+      }
+      ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+      SA_DBG1(("saSMPAbort, agNULL == pRequestABT\n"));
+      /* The IO to Be Abort is no longer exist - can not Abort */
+      smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "9b");
+      return AGSA_RC_FAILURE;
+    }
+    OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, HTagAbort), pRequestABT->HTag);
+  }
+  else
+  {
+    /* abort all */
+    OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, HTagAbort), 0);
+  }
+  OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, deviceId), pDevice->DeviceMapIndex);
+  OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaSMPAbortCmd_t, Scp), flag);
+
+  SA_DBG1(("saSMPAbort, HTag 0x%x HTagABT 0x%x deviceId 0x%x\n", payload.tag, payload.HTagAbort, payload.deviceId));
+
+  /* build IOMB command and send to SPC */
+  ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_SMP_ABORT, IOMB_SIZE64, queueNum);
+  if (AGSA_RC_SUCCESS != ret)
+  {
+    /* remove the request from IOMap */
+    saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF;
+    saRoot->IOMap[pRequest->HTag].IORequest = agNULL;
+    saRoot->IOMap[pRequest->HTag].agContext = agNULL;
+    /* Delete the request from the pendingSMPRequests */
+    ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode));
+    /* return the request to free pool */
+    if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT)
+    {
+      SA_DBG1(("saSMPAbort: saving pRequest (%p) for later use\n", pRequest));
+      saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
+    }
+    else
+    {
+      /* return the request to free pool */
+      saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
+    }
+    ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK);
+    SA_DBG1(("saSMPAbort, sending IOMB failed\n" ));
+  }
+#ifdef SALL_API_TEST
+  else
+  {
+    saRoot->LLCounters.IOCounter.numSMPAborted++;
+  }
+#endif
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "9b");
+
+  return ret;
+}
+
+
+

sys/dev/pms/RefTisa/sallsdk/spc/satimer.c

@@ -0,0 +1,410 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/*! \file satimer.c
+ *  \brief The file implements the timerTick function
+ *
+ */
+/******************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+#ifdef SA_FW_TEST_BUNCH_STARTS
+void mpiMsgProduceBunch(  agsaLLRoot_t  *saRoot);
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#ifdef siTraceFileID
+#undef siTraceFileID
+#endif
+#define siTraceFileID 'P'
+#endif
+
+/******************************************************************************/
+/*! \brief TimerTick
+ *
+ *  TimerTick
+ *
+ *  \param agRoot handles for this instance of SAS/SATA hardware
+ *
+ *  \return -void-
+ */
+/*******************************************************************************/
+GLOBAL void saTimerTick(
+  agsaRoot_t  *agRoot
+  )
+{
+  agsaLLRoot_t    *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaTimerDesc_t *pTimer;
+  bit32           Event;
+  void *          pParm;
+
+  if(agNULL ==  saRoot)
+  {
+    SA_DBG1(("saTimerTick:agNULL ==  saRoot \n"));
+    return;
+  }
+
+  /* (1) Acquire timer list lock */
+  ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK);
+
+  /* (2) Find the timers are timeout */
+  pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers));
+  while ( agNULL != pTimer )
+  {
+    /* (2.1) Find the first timer is timeout */
+    if ( pTimer->timeoutTick == saRoot->timeTick )
+    {
+      /* (2.1.1) remove the timer from valid timer list */
+      saLlistRemove(&(saRoot->validTimers), &(pTimer->linkNode));
+      /* (2.1.2) Invalid timer */
+      pTimer->valid = agFALSE;
+      /* (2.1.3) Get timer event and param */
+      Event = pTimer->Event;
+      pParm = pTimer->pParm;
+      /* (2.1.4) Release timer list lock */
+      ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK);
+
+      /* (2.1.5) Timer Callback */
+      pTimer->pfnTimeout(agRoot, Event, pParm);
+
+      /* (2.1.6) Acquire timer list lock again */
+      ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK);
+      /* (2.1.7) return the timer to free timer list */
+      saLlistAdd(&(saRoot->freeTimers), &(pTimer->linkNode));
+    }
+    /* (2.2) the first timer is not timeout */
+    else
+    {
+      break;
+    }
+    pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers));
+  }
+
+  /* (3) increment timeTick */
+  saRoot->timeTick ++;
+
+  if( saRoot->ResetFailed )
+  {
+    SA_DBG1(("saTimerTick: siChipResetV saRoot->ResetFailed\n"));
+  }
+
+#ifdef SA_FW_TEST_BUNCH_STARTS
+  if (saRoot->BunchStarts_Enable &&
+      saRoot->BunchStarts_Pending)
+  {
+      SA_DBG3(("saTimerTick: mpiMsgProduceBunch\n"));
+      mpiMsgProduceBunch(  saRoot);
+  }
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+
+
+#ifdef SA_FW_TEST_INTERRUPT_REASSERT
+
+  if(1)
+  {
+    mpiOCQueue_t         *circularQ;
+    int i;
+    SA_DBG4(("saTimerTick:SA_FW_TEST_INTERRUPT_REASSERT\n"));
+    for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ )
+    {
+      circularQ = &saRoot->outboundQueue[i];
+      OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0);
+      if(circularQ->producerIdx != circularQ->consumerIdx)
+      {
+        if( saRoot->OldCi[i] == circularQ->consumerIdx && saRoot->OldPi[i] >= circularQ->producerIdx)
+        {
+          agsaEchoCmd_t       payload;
+          payload.tag = 0xF0;
+          payload.payload[0]= 0x0;
+          if( ++saRoot->OldFlag[i] > 1 )
+          {
+            saRoot->CheckAll++;
+          }
+          SA_DBG1(("saTimerTick:Q %d (%d) PI 0x%03x CI 0x%03x (%d) CheckAll %d %d\n",i,
+            saRoot->OldFlag[i],
+            circularQ->producerIdx,
+            circularQ->consumerIdx,
+            (circularQ->producerIdx > circularQ->consumerIdx ? (circularQ->producerIdx - circularQ->consumerIdx) :   (circularQ->numElements -  circularQ->consumerIdx ) + circularQ->producerIdx),
+            saRoot->CheckAll,
+            saRoot->sysIntsActive ));
+
+          if(smIS64bInt(agRoot))
+          {
+            SA_DBG1(("saTimerTick:CheckAll %d ODR 0x%08X%08X ODMR 0x%08X%08X our Int %x\n",
+              saRoot->CheckAll,
+              ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Set_RegisterU),
+              ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Set_Register),
+              ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Mask_Set_RegisterU),
+              ossaHwRegReadExt(agRoot, 0, V_Outbound_Doorbell_Mask_Set_Register),
+              saRoot->OurInterrupt(agRoot,i)
+              ));
+          }
+          else
+          {
+            SA_DBG1(("saTimerTick:CheckAll %d ODR 0x%08X ODMR 0x%08X our Int %x\n",
+              saRoot->CheckAll,
+              siHalRegReadExt(agRoot, GEN_MSGU_ODR,  V_Outbound_Doorbell_Set_Register),
+              siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register),
+              saRoot->OurInterrupt(agRoot,i)
+              ));
+          }
+
+
+          if( saRoot->CheckAll > 1)
+          {
+            saEchoCommand(agRoot,agNULL, ((i << 16) & 0xFFFF0000 ), (void *)&payload);
+          }
+
+        }
+        else
+        {
+          saRoot->OldFlag[i] = 0;
+        }
+
+        saRoot->OldPi[i] = circularQ->producerIdx;
+        saRoot->OldCi[i] = circularQ->consumerIdx;
+
+      }
+    }
+  }
+#endif /* SA_FW_TEST_INTERRUPT_REASSERT */
+
+  /* (4) Release timer list lock */
+  ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK);
+#ifdef SA_FW_TEST_INTERRUPT_REASSERT
+  if(saRoot->CheckAll )
+  {
+    int a;
+    for(a=0; a < 32; a++ )
+    {
+      if (saRoot->interruptVecIndexBitMap[a] & (1 << a))
+      {
+        SA_DBG1(("saTimerTick DI %d\n",a));
+        saSystemInterruptsEnable  ( agRoot, a );
+
+      }
+    }
+  }
+#endif /* SA_FW_TEST_INTERRUPT_REASSERT */
+}
+
+/******************************************************************************/
+/*! \brief add a timer
+ *
+ *  add a timer
+ *
+ *  \param agRoot       handles for this instance of SAS/SATA hardware
+ *  \param pTimer       the pointer to the timer being added
+ *  \param timeout      the timeout ticks from now
+ *  \param pfnTimeout   callback function when time is out
+ *  \param Event        the Event code passed to callback function
+ *  \param pParm        the pointer to parameter passed to callback function
+ *
+ *  \return If the timer is added successfully
+ *          - \e AGSA_RC_SUCCESS timer is added successfully
+ *          - \e AGSA_RC_FAILURE cannot add new timer, run out of resource
+ */
+/*******************************************************************************/
+GLOBAL agsaTimerDesc_t *siTimerAdd(
+  agsaRoot_t      *agRoot,
+  bit32           timeout,
+  agsaCallback_t  pfnTimeout,
+  bit32           Event,
+  void *          pParm
+  )
+{
+  agsaLLRoot_t    *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaTimerDesc_t *pTimer;
+  agsaTimerDesc_t *pValidTimer;
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD, "Ta");
+  /* (1) Acquire timer list lock */
+  ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK);
+
+  /* (2) Get a free timer */
+  pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->freeTimers));
+
+  /* (3) If the timer is availble  */
+  if ( agNULL != pTimer )
+  {
+    saLlistRemove(&(saRoot->freeTimers), &(pTimer->linkNode));
+
+    /* (3.1) Setup timer */
+    saLlinkInitialize(&(pTimer->linkNode));
+    /*--------------------------------------**
+    ** the timeout shall greater than 0 **
+    **--------------------------------------*/
+    if ( 0 == timeout )
+    {
+      timeout = timeout + 1;
+    }
+    pTimer->valid = agTRUE;
+    pTimer->timeoutTick = saRoot->timeTick + timeout;
+    pTimer->pfnTimeout = pfnTimeout;
+    pTimer->Event = Event;
+    pTimer->pParm = pParm;
+
+    /* (3.2) Add timer the timer to valid timer list */
+    pValidTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers));
+    /* (3.3) for each timer in the valid timer list */
+    while ( agNULL != pValidTimer )
+    {
+      /* (3.3.1) If the timeoutTick is not wrapped around */
+      if ( pTimer->timeoutTick > saRoot->timeTick )
+      {
+        /* (3.3.1.1) If validTimer wrapped around */
+        if ( pValidTimer->timeoutTick < saRoot->timeTick )
+        {
+          saLlistInsert(&(saRoot->validTimers), &(pValidTimer->linkNode), &(pTimer->linkNode));
+          break;
+        }
+        /* (3.3.1.2) If validTimer is not wrapped around */
+        else
+        {
+          if ( pValidTimer->timeoutTick > pTimer->timeoutTick )
+          {
+            saLlistInsert(&(saRoot->validTimers), &(pValidTimer->linkNode), &(pTimer->linkNode));
+            break;
+          }
+        }
+      }
+      /* (3.3.2) If the timeoutTick is wrapped around */
+      else
+      {
+        /* (3.3.2.1) If validTimer is wrapped around */
+        if ( pValidTimer->timeoutTick < saRoot->timeTick )
+        {
+          if ( pValidTimer->timeoutTick > pTimer->timeoutTick )
+          {
+            saLlistInsert(&(saRoot->validTimers), &(pValidTimer->linkNode), &(pTimer->linkNode));
+            break;
+          }
+        }
+      }
+      /* (3.3.3) Continue to the next valid timer */
+      pValidTimer = (agsaTimerDesc_t *) saLlistGetNext(&(saRoot->validTimers), &(pValidTimer->linkNode));
+    }
+
+    /* (3.4) No timers in the validtimer list is greater than this timer */
+    if ( agNULL == pValidTimer )
+    {
+      saLlistAdd(&(saRoot->validTimers), &(pTimer->linkNode));
+    }
+  }
+
+  /* (4) Release timer list lock */
+  ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK);
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Ta");
+
+  return pTimer;
+}
+
+/******************************************************************************/
+/*! \brief remove a valid timer
+ *
+ *  remove a timer
+ *
+ *  \param agRoot       handles for this instance of SAS/SATA hardware
+ *  \param pTimer       the timer to be removed
+ *
+ *  \return -void-
+ */
+/*******************************************************************************/
+GLOBAL void siTimerRemove(
+  agsaRoot_t      *agRoot,
+  agsaTimerDesc_t *pTimer
+  )
+{
+  agsaLLRoot_t    *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+
+  /* (1) Acquire timer list lock */
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"Tb");
+  ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK);
+
+  /* (2) If the timer is still valid */
+  if ( agTRUE == pTimer->valid )
+  {
+    /* (2.1) remove from the valid timer list */
+    saLlistRemove(&(saRoot->validTimers), &(pTimer->linkNode));
+    /* (2.2) Invalid the timer */
+    pTimer->valid = agFALSE;
+    /* (2.3) return the timer to the free timer list */
+    saLlistAdd(&(saRoot->freeTimers), &(pTimer->linkNode));
+  }
+  /* (3) Release timer list lock */
+  ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK);
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Tb");
+
+  return;
+}
+
+/******************************************************************************/
+/*! \brief remove all valid timer
+ *
+ *  remove all timer
+ *
+ *  \param agRoot       handles for this instance of SAS/SATA hardware
+ *
+ *  \return -void-
+ */
+/*******************************************************************************/
+GLOBAL void siTimerRemoveAll(
+  agsaRoot_t      *agRoot
+  )
+{
+  agsaLLRoot_t    *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  agsaTimerDesc_t *pTimer;
+
+  smTraceFuncEnter(hpDBG_VERY_LOUD,"Tc");
+
+  /* (1) Acquire timer list lock */
+  ossaSingleThreadedEnter(agRoot, LL_TIMER_LOCK);
+
+  /* (2) Get a valid timer */
+  pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers));
+
+  /* (3) If the timer is valid  */
+  while ( agNULL != pTimer )
+  {
+    /* (3.1) remove from the valid timer list */
+    saLlistRemove(&(saRoot->validTimers), &(pTimer->linkNode));
+
+    /* (3.2) Invalid timer */
+    pTimer->valid = agFALSE;
+
+    /* (3.3) return the timer to the free timer list */
+    saLlistAdd(&(saRoot->freeTimers), &(pTimer->linkNode));
+
+    /* (3.4) get next valid timer */
+    pTimer = (agsaTimerDesc_t *) saLlistGetHead(&(saRoot->validTimers));
+  }
+
+  /* (4) Release timer list lock */
+  ossaSingleThreadedLeave(agRoot, LL_TIMER_LOCK);
+
+  smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "Tc");
+
+  return;
+}

sys/dev/pms/RefTisa/sallsdk/spc/satypes.h

@@ -0,0 +1,369 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file satypes.h
+ *  \brief The file defines the internal data structure types used by LL layer
+ *
+ */
+/*******************************************************************************/
+
+#ifndef  __SATYPES_H__
+
+#define __SATYPES_H__
+
+/** \brief the callback function of an timer
+ *
+ * the definition of the timer callback function
+ */
+typedef bit32 (* agsaCallback_t) (agsaRoot_t *agRoot,
+                                  bit32      Event,
+                                  void       *Parm);
+
+/** \brief the data structure of a timer
+ *
+ * use to describe timer
+ *
+ */
+typedef struct agsaTimerDesc_s
+{
+  SALINK          linkNode; /**< the link node data structure of the timer */
+  bit32           valid;  /**< the valid bit of the timer descriptor */
+  bit32           timeoutTick; /**< the timeout tick of the timer */
+  agsaCallback_t  pfnTimeout; /**< the callback function fo the timer */
+  bit32           Event; /**< the event paramter of the timer callback function */
+  void *          pParm; /**< the point to the paramter passed to callback function */
+} agsaTimerDesc_t;
+
+/** \brief the port
+ *
+ * describe port data structure
+ *
+ */
+typedef struct agsaPort_s
+{
+  SALINK              linkNode;     /**< the link node data structure of the port */
+  agsaPortContext_t   portContext; /**< the port context of the port */
+  SALINK_LIST         listSASATADevices; /**< SAS/SATA devices list of the port */
+  bit32               phyMap[AGSA_MAX_VALID_PHYS]; /**< Boolean arrar: the Phys included in the port. */
+  bit32               status;  /**< port state */
+  bit32               tobedeleted;  /**< mark for deletetion after callback  */
+  bit32               portId; /** Port Id from SPC */
+  bit8                portIdx; /**< the Index of the port */
+  bit8                reserved[3];
+} agsaPort_t;
+
+/** \brief the phy
+ *
+ * phy data structure
+ *
+ */
+typedef struct agsaPhy_s
+{
+  agsaPort_t          *pPort; /**< pointer to the port includes the phy */
+  agsaSASIdentify_t   sasIdentify; /**< the SAS identify of the phy */
+  agsaContext_t       *agContext; /**< agContext for the Phy */
+  bit32               status; /**< the status of the phy */
+  bit8                phyId; /**< the Id of the phy */
+  bit8                linkstatus; /**< the link status of the phy */
+  bit8                reserved[2];
+#if defined(SALLSDK_DEBUG)
+  bit8                remoteSignature[8]; /* the remote signature of the phy is the phy is in native SATA mode */
+#endif
+} agsaPhy_t;
+
+/** \brief the LL defined SAS/SATA device information
+ *
+ * LL defined SAS/SATA device information
+ *
+ */
+typedef union agsaSASSATADevInfo_s
+{
+  agsaSASDeviceInfo_t   sasDeviceInfo;  /**< SAS device information of the device */
+  agsaSATADeviceInfo_t  sataDeviceInfo; /**< SATA device information of the device */
+} agsaSASSATADevInfo_t;
+
+/** \brief the LL defined device descriptor
+ *
+ * LL defined device descriptor
+ *
+ */
+typedef struct agsaDeviceDesc_s
+{
+  SALINK                linkNode; /**< the link node data structure of the device */
+  agsaDevHandle_t       initiatorDevHandle; /**< the device handle of an initiator device */
+  agsaDevHandle_t       targetDevHandle; /**< the device handle of a target device */
+  SALINK_LIST           pendingIORequests; /**< the pending IO requests, for SSP or SATA */
+  agsaPort_t            *pPort; /**< the port discovered the device */
+  bit8                  deviceType; /**< the device type */
+  bit8                  reserved[3];
+  bit32                 option;
+  bit32                 param;
+  agsaSASSATADevInfo_t  devInfo; /**< SAS/SATA device information */
+  bit32                 DeviceMapIndex;  /**< device index for device handle */
+} agsaDeviceDesc_t;
+
+/** \brief the LL defined IO request descriptor
+ *
+ * LL defined IO Request descriptor
+ *
+ */
+typedef struct agsaIORequestDesc_s
+{
+  SALINK            linkNode;          /**< the link node data structure of the IO request */
+  agsaIORequest_t   *pIORequestContext;/**< the IO request context */
+  agsaDeviceDesc_t  *pDevice;          /**< the pointer to the device, to which the request is sent */
+  agsaPort_t        *pPort;            /**< the pointer to the port - using by HW_EVENT_ACK with PHY_DOWN event */
+  ossaSSPCompletedCB_t completionCB;   /**< completion callback to be called */
+  bit32             requestType;       /**< the request type */
+  bit16             HwAckType;         /**< Track HW_acks */
+  bit16             SOP;               /**< SetPhyProfile page not returned in reply */
+  bit32             startTick;         /**< start time for this IO */
+  bit32             HTag;              /**< the host tag to index into the IORequest array */
+  bit8              valid;             /**< boolean flag: the request is valid */
+  bit8              IRmode;            /**< indirect smp response mode */
+  bit8              modePageContext;   /**< request is for security mode change */
+  bit8              DeviceInfoCmdOption;/**<  */
+#ifdef FAST_IO_TEST
+  SALINK            fastLink; /* Fast I/O's chain */
+#endif
+} agsaIORequestDesc_t;
+
+/** \brief the LL defined SMP Response Frame header and payload
+ *
+ * LL defined SMP Response Frame header and payload
+ *
+ */
+typedef struct agsaSMPRspFrame_s
+{
+  agsaSMPFrameHeader_t smpHeader;
+  bit8                 smpPayload[1020];
+} agsaSMPRspFrame_t;
+
+/** \brief the agsaIOMap_t
+ *
+ * data storage for IO Request Mapping
+ *
+ */
+typedef struct agsaIOMap_s
+{
+  bit32 Tag;
+  agsaIORequestDesc_t *IORequest;
+  agsaContext_t *agContext;
+} agsaIOMap_t;
+
+/** \brief the agsaPortMap_t
+ *
+ * data storage for Port Context Mapping
+ *
+ */
+typedef struct agsaPortMap_s
+{
+  bit32 PortID;
+  bit32 PortStatus;
+  void  *PortContext;
+} agsaPortMap_t;
+
+/** \brief the agsaDeviceMap_t
+ *
+ * data storage for Device Handle Mapping
+ *
+ */
+typedef struct agsaDeviceMap_s
+{
+  bit32 DeviceIdFromFW;
+  void  *DeviceHandle;
+} agsaDeviceMap_t;
+
+#ifdef FAST_IO_TEST
+/* interleaved Fast IO's are not allowed */
+#define LL_FAST_IO_SIZE  1
+#endif
+
+/** \brief the LLRoot
+ *
+ * root data structure
+ *
+ */
+typedef struct agsaLLRoot_s
+{
+  agsaMem_t       deviceLinkMem; /**< Device Link System Memory */
+  SALINK_LIST     freeDevicesList; /**< List of free IO device handles */
+
+  agsaMem_t       IORequestMem; /**< IO Request Link System Memory */
+  SALINK_LIST     freeIORequests; /**< List of free IORequests */
+  SALINK_LIST     freeReservedRequests; /**< List of reserved IORequests not for normal IO! */
+
+  agsaMem_t       timerLinkMem; /**< Timer Link System Memory */
+  SALINK_LIST     freeTimers; /**< List of free timers */
+  SALINK_LIST     validTimers; /**< List of valid timers */
+
+  agsaPhy_t       phys[AGSA_MAX_VALID_PHYS]; /**< Phys */
+
+  agsaPort_t      ports[AGSA_MAX_VALID_PORTS]; /**< Ports */
+  SALINK_LIST     freePorts; /**< List of free ports */
+  SALINK_LIST     validPorts; /**< List of valid ports */
+
+  bit8            phyCount; /**< number of phys */
+  bit8            portCount; /**< number of ports */
+  bit8            sysIntsActive; /**< whether interrupt is enabled */
+  bit8            reserved; /**< reserved */
+
+  bit32           usecsPerTick; /**< timer tick unit */
+  bit32           minStallusecs; /**< shorest available stall */
+  bit32           timeTick; /**< the current timer tick */
+  bit32           ResetStartTick; /* Reset StartTick */
+  bit32           chipStatus; /**< chip status */
+
+  bit32           interruptVecIndexBitMap[MAX_NUM_VECTOR]; /**< Interrupt Vector Index BitMap */
+  bit32           interruptVecIndexBitMap1[MAX_NUM_VECTOR]; /**< Interrupt Vector Index BitMap1 */
+
+  agsaBarOffset_t SpcBarOffset[60];
+  bit32           ChipId; /* Subversion PCI ID */
+
+  agsaPortMap_t   PortMap[AGSA_MAX_VALID_PORTS]; /**< Port Mapping for PortContext */
+  agsaDeviceMap_t DeviceMap[MAX_IO_DEVICE_ENTRIES]; /**< Device Map for Device Handle */
+  agsaIOMap_t     IOMap[MAX_ACTIVE_IO_REQUESTS]; /**< IO MAP for IO Request */
+  agsaDevHandle_t *DeviceHandle[MAX_IO_DEVICE_ENTRIES]; /**< used for get device handles */
+  agsaDevHandle_t *pDeviceHandle; /**< used for get device handles */
+
+  agsaMemoryRequirement_t memoryAllocated; /**< SAS LL memory Allocation */
+  agsaHwConfig_t          hwConfig; /**< copy of hwConfig */
+  agsaSwConfig_t          swConfig; /**< copy of swConfig */
+  agsaQueueConfig_t       QueueConfig; /* copy of MPI IBQ/OBQ configuration */
+
+  mpiConfig_t     mpiConfig; /**< MPI Configuration */
+  mpiMemReq_t     mpiMemoryAllocated; /**< MPI memory */
+  mpiICQueue_t    inboundQueue[AGSA_MAX_INBOUND_Q];   /**< Outbound queue descriptor array */
+  mpiOCQueue_t    outboundQueue[AGSA_MAX_OUTBOUND_Q]; /**< Outbound queue descriptor array */
+  mpiHostLLConfigDescriptor_t    mainConfigTable; /**< LL main Configuration Table */
+
+  ossaDeviceRegistrationCB_t     DeviceRegistrationCB; /**< Device Registration CB */
+  ossaDeregisterDeviceHandleCB_t DeviceDeregistrationCB;/**< Device DeRegistration CB */
+
+  bit32           numInterruptVectors; /**< Number of Interrupt Vectors configured from OS */
+  bit32           Use64bit;            /**< Only write upper bits if needed */
+
+  EnadDisabHandler_t DisableInterrupts;              /*Interrupt type dependant function pointer to disable interrupts */
+  EnadDisabHandler_t ReEnableInterrupts;             /*Interrupt type dependant reenable  */
+  InterruptOurs_t OurInterrupt;                      /*Interrupt type dependant check for our interrupt */
+
+#ifdef SA_FW_TEST_BUNCH_STARTS
+  /**
+   * Following variables are needed to handle Bunch Starts (bulk update of PI)
+   * - saRoot (agsaLLRoot_t): Global Flags, apply to all queues
+   *   1. BunchStarts_Enable 
+   *   2. BunchStarts_Threshold
+   *   3. BunchStarts_Pending
+   *   4. BunchStarts_TimeoutTicks
+   *
+   * - Circular Q (mpiICQueue_s): Queue specific flags
+   *   1. BunchStarts_QPending
+   *   2. BunchStarts_QPendingTick
+   */
+  bit32           BunchStarts_Enable;       // enables/disables whole feature
+  bit32           BunchStarts_Threshold;    // global min number of IOs to bunch per queue.
+  bit32           BunchStarts_Pending;      // global counter collects all Q->BunchStarts_QPending
+  bit32           BunchStarts_TimeoutTicks; // global time out value beyond which bunched IOs will be started even below BunchStarts_Threshold.
+#endif /* SA_FW_TEST_BUNCH_STARTS */
+
+#ifdef SA_FW_TIMER_READS_STATUS
+  spc_GSTableDescriptor_t  mpiGSTable;
+  bit32    MsguTcnt_last;             /**< DW3 - MSGU Tick count */
+  bit32    IopTcnt_last;              /**< DW4 - IOP Tick count */
+  bit32    Iop1Tcnt_last;              /**< DW4 - IOP Tick count */
+
+#endif /* SA_FW_TIMER_READS_STATUS */
+
+  agsaControllerInfo_t ControllerInfo;
+  agsaIOErrorEventStats_t   IoErrorCount;
+  agsaIOErrorEventStats_t   IoEventCount;
+
+  bit32           ResetFailed;
+  //bit32           FatalDone;
+  bit32           ForensicLastOffset;
+  //bit32           FatalAccumLen;
+  //bit32           NonFatalForensicLastOffset;
+  //bit32           FatalCurrentLength;
+  bit32           FatalForensicStep;
+  bit32           FatalForensicShiftOffset;
+  bit32           FatalBarLoc;
+
+#ifdef HIALEAH_ENCRYPTION
+  agsaEncryptGeneralPage_t EncGenPage;
+#endif /* HIALEAH_ENCRYPTION */
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+  bit8  traceBuffLookup[16];
+
+  bit32           TraceDestination;
+  bit32           TraceMask;
+
+  bit32           TraceBufferLength;
+  bit32           CurrentTraceIndexWrapCount;
+  bit32           CurrentTraceIndex;
+  bit32           traceLineFeedCnt;
+  bit8            *TraceBuffer;
+  bit32           TraceBlockReInit;
+
+#endif /*SA_ENABLE_TRACE_FUNCTIONS*/
+
+  bit32           registerDump0[REGISTER_DUMP_BUFF_SIZE/4];  /**< register dump buffer 0 */
+  bit32           registerDump1[REGISTER_DUMP_BUFF_SIZE/4];  /**< register dump buffer 1 */
+
+  bit32           autoDeregDeviceflag[AGSA_MAX_VALID_PORTS];
+
+#ifdef SA_FW_TEST_INTERRUPT_REASSERT
+  bit32           CheckAll;
+  bit32           OldPi[64];
+  bit32           OldCi[64];
+  bit32           OldFlag[64];
+#endif /* SA_FW_TEST_INTERRUPT_REASSERT */
+
+
+#ifdef SALL_API_TEST
+  agsaLLCountInfo_t LLCounters;
+#endif
+#ifdef FAST_IO_TEST
+  void            *freeFastReq[LL_FAST_IO_SIZE]; /* saFastRequest_t* */
+  int             freeFastIdx;
+#endif
+} agsaLLRoot_t;
+
+#ifdef FAST_IO_TEST
+/*
+  one struct per all prepared Fast IO's;
+  freed after all IO's are posted to FW and interrupt is triggered;
+  maintained for error rollback or cancel functionality
+*/
+typedef struct saFastRequest_s
+{
+  bit32       beforePI[AGSA_MAX_INBOUND_Q];
+  bit32       inqList[AGSA_MAX_INBOUND_Q];
+  bit32       inqMax;
+  SALINK_LIST requests; /* List of all Fast IORequests */
+  void        *agRoot;  /* agsaRoot_t * */
+  bit8        valid;    /* to avoid usage when the struct is freed */
+} saFastRequest_t;
+#endif
+
+#endif  /*__SATYPES_H__ */

sys/dev/pms/RefTisa/sallsdk/spc/sautil.c

@@ -0,0 +1,834 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/*! \file sautil.c
+ *  \brief The file contains general helper routines.
+ *
+ *
+ */
+/******************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h>
+#ifdef SA_TESTBASE_EXTRA
+#include <string.h>
+#endif /*  SA_TESTBASE_EXTRA */
+
+
+#ifdef SA_ENABLE_TRACE_FUNCTIONS
+#ifdef siTraceFileID
+#undef siTraceFileID
+#endif
+#define siTraceFileID 'S'
+#endif
+
+/******************************************************************************/
+/*! \brief Check for Hex digit
+ *
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+int siIsHexDigit(char a)
+{
+  return (  (((a) >= 'a') && ((a) <= 'z')) ||
+            (((a) >= 'A') && ((a) <= 'Z')) ||
+            (((a) >= '0') && ((a) <= '9')) ||
+            ( (a) == '*'));
+}
+
+/******************************************************************************/
+/*! \brief memcopy
+ *
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+FORCEINLINE
+void*
+si_memcpy(void *dst,  void *src, bit32 count)
+{
+/*
+  bit32 x;
+  unsigned char *dst1 = (unsigned char *)dst;
+  unsigned char *src1 = (unsigned char *)src;
+
+  for (x=0; x < count; x++)
+    dst1[x] = src1[x];
+
+  return dst;
+*/
+ return memcpy(dst, src, count);
+}
+
+
+/******************************************************************************/
+/*! \brief memset
+ *
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+FORCEINLINE
+void*
+si_memset(void *s, int c, bit32 n)
+{
+/*
+  bit32   i;
+  char *dst = (char *)s;
+  for (i=0; i < n; i++)
+  {
+    dst[i] = (char) c;
+  }
+  return (void *)(&dst[i-n]);
+*/
+  return memset(s, c, n);
+}
+
+
+/******************************************************************************/
+/*! \brief siDumpActiveIORequests
+ *
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+GLOBAL void
+siDumpActiveIORequests(
+  agsaRoot_t              *agRoot,
+  bit32                   count)
+{
+  bit32                 j, num_found = 0;
+  agsaIORequestDesc_t   *pRequestDesc = agNULL;
+  agsaLLRoot_t          *saRoot = agNULL;
+  bit32 i;
+  mpiOCQueue_t          *circularQ;
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  SA_ASSERT((agNULL != saRoot), "");
+
+
+  saCountActiveIORequests(agRoot);
+  // return;
+
+
+  if(smIS_SPCV(agRoot))
+  {
+    bit32 sp1;
+    sp1= ossaHwRegRead(agRoot,V_Scratchpad_1_Register );
+
+    if(SCRATCH_PAD1_V_ERROR_STATE(sp1))
+    {
+      SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD1_V_ERROR_STAT 0x%x\n",sp1 ));
+    }
+    SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_0_Register)));
+    SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_1_Register)));
+    SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_2_Register)));
+    SA_DBG1(("siDumpActiveIORequests: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_3_Register)));
+  }
+
+  for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ )
+  {
+    circularQ = &saRoot->outboundQueue[i];
+    OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0);
+    if(circularQ->producerIdx != circularQ->consumerIdx)
+    {
+      SA_DBG1(("siDumpActiveIORequests:OBQ%d PI 0x%03x CI 0x%03x\n", i,circularQ->producerIdx, circularQ->consumerIdx  ));
+    }
+  }
+
+  pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0);
+  SA_DBG1(("siDumpActiveIORequests: Current Time: %d ticks (usecpertick=%d)\n",
+    saRoot->timeTick, saRoot->usecsPerTick));
+
+  for ( j = 0; j < count; j ++ )
+  {
+    pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j);
+
+    if (pRequestDesc->valid == agTRUE)
+    {
+      num_found++;
+      SA_DBG1(("siDumpActiveIORequests: IO #%4d: %p Tag=%03X  Type=%08X Device 0x%X Pending for %d seconds\n",
+        j,
+        pRequestDesc->pIORequestContext,
+        pRequestDesc->HTag,
+        pRequestDesc->requestType,
+        pRequestDesc->pDevice ? pRequestDesc->pDevice->DeviceMapIndex : 0,
+        ((saRoot->timeTick - pRequestDesc->startTick)*saRoot->usecsPerTick)/1000000 ));
+
+    }
+  }
+  if(count)
+  {
+    SA_DBG1(("siDumpActiveIORequests: %d found active\n",num_found));
+  }
+
+}
+
+/******************************************************************************/
+/*! \brief saCountActiveIORequests
+ *
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+GLOBAL void
+siClearActiveIORequests(
+  agsaRoot_t              *agRoot)
+{
+  bit32                 j;
+  bit32                 num_found = 0;
+  agsaIORequestDesc_t   *pRequestDesc = agNULL;
+  agsaLLRoot_t          *saRoot = agNULL;
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  SA_ASSERT((agNULL != saRoot), "");
+
+  if(saRoot)
+  {
+    pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0);
+
+    for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ )
+    {
+      pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j);
+
+      if (pRequestDesc->valid == agTRUE)
+      {
+        num_found++;
+        pRequestDesc->valid =  agFALSE;
+      }
+    }
+    if(num_found)
+    {
+      SA_DBG1(("siClearActiveIORequests %d found active\n",num_found));
+    }
+  }
+  else
+  {
+     SA_DBG1(("siClearActiveIORequests saroot NULL\n"));
+  }
+
+}
+
+/******************************************************************************/
+/*! \brief siCountActiveIORequestsOnDevice
+ *   count all active IO's
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+GLOBAL void
+siClearActiveIORequestsOnDevice(
+  agsaRoot_t *agRoot,
+  bit32      device )
+{
+  bit32                 j, num_found = 0;
+  agsaIORequestDesc_t   *pRequestDesc = agNULL;
+  agsaLLRoot_t          *saRoot = agNULL;
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  SA_ASSERT((agNULL != saRoot), "");
+
+  pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0);
+
+  for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ )
+  {
+    pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j);
+
+    if (pRequestDesc->valid == agTRUE)
+    {
+      if (pRequestDesc->pDevice)
+      {
+        if (pRequestDesc->pDevice->DeviceMapIndex == device)
+        {
+          num_found++;
+          pRequestDesc->valid = agFALSE;
+        }
+      }
+    }
+  }
+  if(num_found)
+  {
+    SA_DBG1(("siClearActiveIORequestsOnDevice 0x%x %d cleared\n",device,num_found));
+  }
+
+}
+
+
+
+/******************************************************************************/
+/*! \brief siCountActiveIORequestsOnDevice
+ *   count all active IO's
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+GLOBAL void
+siCountActiveIORequestsOnDevice(
+  agsaRoot_t *agRoot,
+  bit32      device )
+{
+  bit32                 j, num_found = 0;
+  agsaIORequestDesc_t   *pRequestDesc = agNULL;
+  agsaLLRoot_t          *saRoot = agNULL;
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  SA_ASSERT((agNULL != saRoot), "");
+
+  pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0);
+
+  for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ )
+  {
+    pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j);
+
+    if (pRequestDesc->valid == agTRUE)
+    {
+      if (pRequestDesc->pDevice)
+      {
+        if (pRequestDesc->pDevice->DeviceMapIndex == device)
+        {
+          num_found++;
+          if(saRoot->ResetStartTick > pRequestDesc->startTick)
+          {
+            SA_DBG2(("siCountActiveIORequestsOnDevice: saRoot->ResetStartTick %d pRequestDesc->startTick %d\n",
+                    saRoot->ResetStartTick, pRequestDesc->startTick));
+          }
+        }
+      }
+    }
+  }
+  if(num_found)
+  {
+    SA_DBG1(("siCountActiveIORequestsOnDevice 0x%x %d found active\n",device,num_found));
+  }
+
+}
+
+
+
+/******************************************************************************/
+/*! \brief saCountActiveIORequests
+ *   count all active IO's
+ *
+ *  \param char value
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+GLOBAL void
+saCountActiveIORequests(
+  agsaRoot_t              *agRoot)
+{
+  bit32                 j, num_found = 0;
+  agsaIORequestDesc_t   *pRequestDesc = agNULL;
+  agsaLLRoot_t          *saRoot = agNULL;
+
+  /* sanity check */
+  SA_ASSERT((agNULL != agRoot), "");
+  if( agRoot == agNULL)
+  {
+    return;
+  }
+  saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
+  if( saRoot == agNULL)
+  {
+    return;
+  }
+  pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), 0);
+
+  for ( j = 0; j < saRoot->swConfig.maxActiveIOs; j++ )
+  {
+    pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), j);
+
+    if (pRequestDesc->valid == agTRUE)
+    {
+      num_found++;
+      if(saRoot->ResetStartTick > pRequestDesc->startTick)
+      {
+        SA_DBG2(("saCountActiveIORequests: saRoot->ResetStartTick %d pRequestDesc->startTick %d\n",
+                saRoot->ResetStartTick, pRequestDesc->startTick));
+      }
+    }
+  }
+  if(num_found)
+  {
+    SA_DBG1(("saCountActiveIORequests %d found active\n",num_found));
+  }
+
+}
+
+
+GLOBAL bit32 smIsCfg_V_ANY( agsaRoot_t *agRoot)
+{
+
+  if(smIsCfg_V8008(agRoot) == 1) return 1;
+  if(smIsCfg_V8009(agRoot) == 1) return 1;
+  if(smIsCfg_V8018(agRoot) == 1) return 1;
+  if(smIsCfg_V8019(agRoot) == 1) return 1;
+  if(smIsCfg_V8088(agRoot) == 1) return 1;
+  if(smIsCfg_V8089(agRoot) == 1) return 1;
+  if(smIsCfg_V8070(agRoot) == 1) return 1;
+  if(smIsCfg_V8071(agRoot) == 1) return 1;
+  if(smIsCfg_V8072(agRoot) == 1) return 1;
+  if(smIsCfg_V8073(agRoot) == 1) return 1;
+  if(smIS_SPCV8074(agRoot) == 1) return 1;
+  if(smIS_SPCV8075(agRoot) == 1) return 1;
+  if(smIS_SPCV8076(agRoot) == 1) return 1;
+  if(smIS_SPCV8077(agRoot) == 1) return 1;
+  if(smIsCfg_V8025(agRoot) == 1) return 1;
+  if(smIsCfg_V9015(agRoot) == 1) return 1;
+  if(smIsCfg_V9060(agRoot) == 1) return 1;
+  if(smIsCfg_V8006(agRoot) == 1) return 1;
+
+  return 0;
+}
+
+GLOBAL bit32 smIS_SPC( agsaRoot_t *agRoot) 
+{
+  if(smIS_spc8001(agRoot)    == 1) return 1;
+  if(smIS_spc8081(agRoot)    == 1) return 1;
+  if(smIS_SFC_AS_SPC(agRoot) == 1) return 1;
+  return 0;
+}
+
+
+GLOBAL bit32 smIS_HIL( agsaRoot_t *agRoot) /* or delray */ 
+{
+  if(smIS_spc8081(agRoot)  == 1) return 1;
+  if(smIS_ADAP8088(agRoot) == 1) return 1;
+  if(smIS_ADAP8089(agRoot) == 1) return 1;
+  if(smIS_SPCV8074(agRoot) == 1) return 1;
+  if(smIS_SPCV8075(agRoot) == 1) return 1;
+  if(smIS_SPCV8076(agRoot) == 1) return 1;
+  if(smIS_SPCV8077(agRoot) == 1) return 1;
+  return 0;
+
+}
+
+GLOBAL bit32 smIS_SPC6V( agsaRoot_t *agRoot)
+{
+  if(smIS_SPCV8008(agRoot) == 1) return 1;
+  if(smIS_SPCV8009(agRoot) == 1) return 1;
+  if(smIS_SPCV8018(agRoot) == 1) return 1;
+  if(smIS_SPCV8019(agRoot) == 1) return 1;
+  if(smIS_ADAP8088(agRoot) == 1) return 1;
+  if(smIS_ADAP8089(agRoot) == 1) return 1;
+  return 0;
+}
+
+GLOBAL bit32 smIS_SPC12V( agsaRoot_t *agRoot) 
+{
+  if(smIS_SPCV8070(agRoot) == 1) return 1;
+  if(smIS_SPCV8071(agRoot) == 1) return 1;
+  if(smIS_SPCV8072(agRoot) == 1) return 1;
+  if(smIS_SPCV8073(agRoot) == 1) return 1;
+  if(smIS_SPCV8074(agRoot) == 1) return 1;
+  if(smIS_SPCV8075(agRoot) == 1) return 1;
+  if(smIS_SPCV8076(agRoot) == 1) return 1;
+  if(smIS_SPCV8077(agRoot) == 1) return 1;
+  if(smIS_SPCV9015(agRoot) == 1) return 1;
+  if(smIS_SPCV9060(agRoot) == 1) return 1;
+  if(smIS_SPCV8006(agRoot) == 1) return 1;
+  return 0;
+}
+
+GLOBAL bit32 smIS_SPCV_2_IOP( agsaRoot_t *agRoot)
+{
+  if(smIS_SPCV8009(agRoot) == 1) return 1;
+  if(smIS_SPCV8018(agRoot) == 1) return 1;
+  if(smIS_SPCV8019(agRoot) == 1) return 1;
+  if(smIS_SPCV8071(agRoot) == 1) return 1;
+  if(smIS_SPCV8072(agRoot) == 1) return 1;
+  if(smIS_SPCV8073(agRoot) == 1) return 1;
+  if(smIS_SPCV8076(agRoot) == 1) return 1;
+  if(smIS_SPCV8077(agRoot) == 1) return 1;
+  if(smIS_ADAP8088(agRoot) == 1) return 1;
+  if(smIS_ADAP8089(agRoot) == 1) return 1;
+  if(smIS_SPCV8006(agRoot) == 1) return 1;
+  return 0;
+}
+
+GLOBAL bit32 smIS_SPCV( agsaRoot_t *agRoot)
+{
+  if(smIS_SPC6V(agRoot)    == 1) return 1;
+  if(smIS_SPC12V(agRoot)   == 1) return 1;
+  if(smIS_SFC_AS_V(agRoot) == 1 ) return 1;
+  return 0;
+}
+
+GLOBAL bit32 smIS_ENCRYPT( agsaRoot_t *agRoot)
+{
+  if(smIS_SPCV8009(agRoot) == 1) return 1;
+  if(smIS_ADAP8088(agRoot) == 1) return 1;
+  if(smIS_SPCV8019(agRoot) == 1) return 1;
+  if(smIS_SPCV8071(agRoot) == 1) return 1;
+  if(smIS_SPCV8073(agRoot) == 1) return 1;
+  if(smIS_SPCV8077(agRoot) == 1) return 1;
+  if(smIS_SPCV9015(agRoot) == 1) return 1;
+  if(smIS_SPCV9060(agRoot) == 1) return 1;
+  return 0;
+}
+
+
+
+#if defined(SALLSDK_DEBUG)
+
+/******************************************************************************/
+/*! \brief Routine print buffer
+ *
+ *
+ *  \param debugLevel     verbosity level
+ *  \param header         header to print
+ *  \param buffer         buffer to print
+ *  \param  length        length of buffer in bytes
+ *
+ *  \return -void-
+ *
+ */
+/*******************************************************************************/
+GLOBAL void siPrintBuffer(
+  bit32                 debugLevel,
+  siPrintType           type,
+  char                  *header,
+  void                  *a,
+  bit32                 length
+  )
+{
+  bit32 x, rem;
+  bit8 *buffer = (bit8 *)a;
+  bit32 *lPtr;
+  bit8 temp[16];
+
+  ossaLogDebugString(gLLDebugLevel, debugLevel, ("%s\n", header));
+
+  if (type == SA_8)
+  {
+    for (x=0; x < length/16; x++)
+    {
+      ossaLogDebugString(gLLDebugLevel, debugLevel,
+        ("%02x %02x %02x %02x %02x %02x %02x %02x - %02x %02x %02x %02x %02x %02x %02x %02x  == "
+         "%c%c%c%c%c%c%c%c - %c%c%c%c%c%c%c%c\n",
+        *(buffer),
+        *(buffer+1),
+        *(buffer+2),
+        *(buffer+3),
+        *(buffer+4),
+        *(buffer+5),
+        *(buffer+6),
+        *(buffer+7),
+        *(buffer+8),
+        *(buffer+9),
+        *(buffer+10),
+        *(buffer+11),
+        *(buffer+12),
+        *(buffer+13),
+        *(buffer+14),
+        *(buffer+15),
+        siIsHexDigit(*(buffer)) ? *(buffer) : ' ',
+        siIsHexDigit(*(buffer+1)) ? *(buffer+1) : ' ',
+        siIsHexDigit(*(buffer+2)) ? *(buffer+2) : ' ',
+        siIsHexDigit(*(buffer+3)) ? *(buffer+3) : ' ',
+        siIsHexDigit(*(buffer+4)) ? *(buffer+4) : ' ',
+        siIsHexDigit(*(buffer+5)) ? *(buffer+5) : ' ',
+        siIsHexDigit(*(buffer+6)) ? *(buffer+6) : ' ',
+        siIsHexDigit(*(buffer+7)) ? *(buffer+7) : ' ',
+        siIsHexDigit(*(buffer+8)) ? *(buffer+8) : ' ',
+        siIsHexDigit(*(buffer+9)) ? *(buffer+9) : ' ',
+        siIsHexDigit(*(buffer+10)) ? *(buffer+10) : ' ',
+        siIsHexDigit(*(buffer+11)) ? *(buffer+11) : ' ',
+        siIsHexDigit(*(buffer+12)) ? *(buffer+12) : ' ',
+        siIsHexDigit(*(buffer+13)) ? *(buffer+13) : ' ',
+        siIsHexDigit(*(buffer+14)) ? *(buffer+14) : ' ',
+        siIsHexDigit(*(buffer+15)) ? *(buffer+15) : ' ')
+        );
+
+      buffer += 16;
+    }
+
+    rem = length%16;
+    if (rem)
+    {
+      for (x = 0; x < 16; x++)
+      {
+        temp[x] = ' ';
+      }
+
+      for (x = 0; x < rem; x++)
+      {
+        temp[x] = *(buffer+x);
+      }
+
+      buffer = temp;
+
+      ossaLogDebugString(gLLDebugLevel, debugLevel,
+        ("%02x %02x %02x %02x %02x %02x %02x %02x - %02x %02x %02x %02x %02x %02x %02x %02x  == "
+         "%c%c%c%c%c%c%c%c - %c%c%c%c%c%c%c%c\n",
+        *(buffer),
+        *(buffer+1),
+        *(buffer+2),
+        *(buffer+3),
+        *(buffer+4),
+        *(buffer+5),
+        *(buffer+6),
+        *(buffer+7),
+        *(buffer+8),
+        *(buffer+9),
+        *(buffer+10),
+        *(buffer+11),
+        *(buffer+12),
+        *(buffer+13),
+        *(buffer+14),
+        *(buffer+15),
+        siIsHexDigit(*(buffer)) ? *(buffer) : ' ',
+        siIsHexDigit(*(buffer+1)) ? *(buffer+1) : ' ',
+        siIsHexDigit(*(buffer+2)) ? *(buffer+2) : ' ',
+        siIsHexDigit(*(buffer+3)) ? *(buffer+3) : ' ',
+        siIsHexDigit(*(buffer+4)) ? *(buffer+4) : ' ',
+        siIsHexDigit(*(buffer+5)) ? *(buffer+5) : ' ',
+        siIsHexDigit(*(buffer+6)) ? *(buffer+6) : ' ',
+        siIsHexDigit(*(buffer+7)) ? *(buffer+7) : ' ',
+        siIsHexDigit(*(buffer+8)) ? *(buffer+8) : ' ',
+        siIsHexDigit(*(buffer+9)) ? *(buffer+9) : ' ',
+        siIsHexDigit(*(buffer+10)) ? *(buffer+10) : ' ',
+        siIsHexDigit(*(buffer+11)) ? *(buffer+11) : ' ',
+        siIsHexDigit(*(buffer+12)) ? *(buffer+12) : ' ',
+        siIsHexDigit(*(buffer+13)) ? *(buffer+13) : ' ',
+        siIsHexDigit(*(buffer+14)) ? *(buffer+14) : ' ',
+        siIsHexDigit(*(buffer+15)) ? *(buffer+15) : ' ')
+        );
+    }
+  }
+  else
+  {
+    bit32 *ltemp = (bit32 *)temp;
+    lPtr = (bit32 *) a;
+
+    for (x=0; x < length/4; x++)
+    {
+      ossaLogDebugString(gLLDebugLevel, debugLevel,
+        ("%08x %08x %08x %08x\n",
+        *(lPtr),
+        *(lPtr+1),
+        *(lPtr+2),
+        *(lPtr+3))
+        );
+
+      lPtr += 4;
+    }
+
+    rem = length%4;
+    if (rem)
+    {
+      for (x = 0; x < 4; x++)
+      {
+        ltemp[x] = 0;
+      }
+
+      for (x = 0; x < rem; x++)
+      {
+        ltemp[x] = lPtr[x];
+      }
+
+      lPtr = ltemp;
+
+      ossaLogDebugString(gLLDebugLevel, debugLevel,
+        ("%08x %08x %08x %08x\n",
+        *(lPtr),
+        *(lPtr+1),
+        *(lPtr+2),
+        *(lPtr+3))
+        );
+    }
+  }
+
+}
+
+
+
+void sidump_hwConfig(agsaHwConfig_t  *hwConfig)
+{
+  SA_DBG2(("sidump_hwConfig:hwConfig->hwInterruptCoalescingTimer                             0x%x\n",hwConfig->hwInterruptCoalescingTimer                            ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->hwInterruptCoalescingControl                           0x%x\n",hwConfig->hwInterruptCoalescingControl                          ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->intReassertionOption                                   0x%x\n",hwConfig->intReassertionOption                                  ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister0  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister0 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister1  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister1 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister2  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister2 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister3  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister3 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister4  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister4 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister5  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister5 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister6  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister6 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister7  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister7 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister8  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister8 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister9  0x%x\n",hwConfig->phyAnalogConfig.phyAnalogSetupRegisters->spaRegister9 ));
+  SA_DBG2(("sidump_hwConfig:hwConfig->hwOption                                               0x%x\n",hwConfig->hwOption                                              ));
+}
+
+void sidump_swConfig(agsaSwConfig_t  *swConfig)
+{
+  SA_DBG2(("sidump_swConfig:swConfig->maxActiveIOs               0x%x\n",swConfig->maxActiveIOs              ));
+  SA_DBG2(("sidump_swConfig:swConfig->numDevHandles              0x%x\n",swConfig->numDevHandles             ));
+  SA_DBG2(("sidump_swConfig:swConfig->smpReqTimeout              0x%x\n",swConfig->smpReqTimeout             ));
+  SA_DBG2(("sidump_swConfig:swConfig->numberOfEventRegClients    0x%x\n",swConfig->numberOfEventRegClients   ));
+  SA_DBG2(("sidump_swConfig:swConfig->sizefEventLog1             0x%x\n",swConfig->sizefEventLog1            ));
+  SA_DBG2(("sidump_swConfig:swConfig->sizefEventLog2             0x%x\n",swConfig->sizefEventLog2            ));
+  SA_DBG2(("sidump_swConfig:swConfig->eventLog1Option            0x%x\n",swConfig->eventLog1Option           ));
+  SA_DBG2(("sidump_swConfig:swConfig->eventLog2Option            0x%x\n",swConfig->eventLog2Option           ));
+  SA_DBG2(("sidump_swConfig:swConfig->fatalErrorInterruptEnable  0x%x\n",swConfig->fatalErrorInterruptEnable ));
+  SA_DBG2(("sidump_swConfig:swConfig->fatalErrorInterruptVector  0x%x\n",swConfig->fatalErrorInterruptVector ));
+  SA_DBG2(("sidump_swConfig:swConfig->max_MSI_InterruptVectors   0x%x\n",swConfig->max_MSI_InterruptVectors  ));
+  SA_DBG2(("sidump_swConfig:swConfig->max_MSIX_InterruptVectors  0x%x\n",swConfig->max_MSIX_InterruptVectors ));
+  SA_DBG2(("sidump_swConfig:swConfig->legacyInt_X                0x%x\n",swConfig->legacyInt_X               ));
+  SA_DBG2(("sidump_swConfig:swConfig->hostDirectAccessSupport    0x%x\n",swConfig->hostDirectAccessSupport   ));
+  SA_DBG2(("sidump_swConfig:swConfig->hostDirectAccessMode       0x%x\n",swConfig->hostDirectAccessMode      ));
+  SA_DBG2(("sidump_swConfig:swConfig->param1                     0x%x\n",swConfig->param1                    ));
+  SA_DBG2(("sidump_swConfig:swConfig->param2                     0x%x\n",swConfig->param2                    ));
+  SA_DBG2(("sidump_swConfig:swConfig->param3                     %p\n",swConfig->param3                    ));
+  SA_DBG2(("sidump_swConfig:swConfig->param4                     %p\n",swConfig->param4                    ));
+
+}
+
+
+void sidump_Q_config( agsaQueueConfig_t         *queueConfig )
+{
+  bit32 x;
+
+  SA_DBG2(("sidump_Q_config: queueConfig->generalEventQueue                0x%x\n", queueConfig->generalEventQueue                ));
+  SA_DBG2(("sidump_Q_config: queueConfig->numInboundQueues                 0x%x\n", queueConfig->numInboundQueues                 ));
+  SA_DBG2(("sidump_Q_config: queueConfig->numOutboundQueues                0x%x\n", queueConfig->numOutboundQueues                ));
+  SA_DBG2(("sidump_Q_config: queueConfig->iqHighPriorityProcessingDepth    0x%x\n", queueConfig->iqHighPriorityProcessingDepth    ));
+  SA_DBG2(("sidump_Q_config: queueConfig->iqNormalPriorityProcessingDepth  0x%x\n", queueConfig->iqNormalPriorityProcessingDepth  ));
+  SA_DBG2(("sidump_Q_config: queueConfig->queueOption                      0x%x\n", queueConfig->queueOption                      ));
+  SA_DBG2(("sidump_Q_config: queueConfig->tgtDeviceRemovedEventQueue       0x%x\n", queueConfig->tgtDeviceRemovedEventQueue       ));
+
+  for(x=0;x < queueConfig->numInboundQueues;x++)
+  {
+    SA_DBG2(("sidump_Q_config: queueConfig->inboundQueues[%d].elementCount  0x%x\n",x,queueConfig->inboundQueues[x].elementCount  ));
+    SA_DBG2(("sidump_Q_config: queueConfig->inboundQueues[%d].elementSize   0x%x\n",x,queueConfig->inboundQueues[x].elementSize   ));
+  }
+
+  for(x=0;x < queueConfig->numOutboundQueues;x++)
+  {
+
+    SA_DBG2(("sidump_Q_config: queueConfig->outboundQueues[%d].elementCount 0x%x\n",x,queueConfig->outboundQueues[x].elementCount ));
+    SA_DBG2(("sidump_Q_config: queueConfig->outboundQueues[%d].elementSize  0x%x\n",x,queueConfig->outboundQueues[x].elementSize  ));
+  }
+
+}
+#endif
+
+#ifdef SALL_API_TEST
+/******************************************************************************/
+/*! \brief Get Performance IO counters
+ *
+ *  Start/Abort SAS/SATA discovery
+ *
+ *  \param agRoot         Handles for this instance of SAS/SATA hardware
+ *  \param counters       bit map of the counters
+ *  \param LLCountInfo    pointer to the LLCounters
+ *
+ *  \return
+ *          - \e AGSA_RC_SUCCESS
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saGetLLCounters(
+                      agsaRoot_t          *agRoot,
+                      bit32               counters,
+                      agsaLLCountInfo_t   *LLCountInfo
+                      )
+{
+  agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+  bit32 i;
+
+  for (i = 0; i < LL_COUNTERS; i++)
+  {
+    if (counters & (1 << i))
+      LLCountInfo->arrayIOCounter[i] = saRoot->LLCounters.arrayIOCounter[i];
+  }
+
+  return AGSA_RC_SUCCESS;
+}
+
+/******************************************************************************/
+/*! \brief Function for target to remove stale initiator device handle
+ *
+ *  function is called to ask the LL layer to remove all LL layer and SPC firmware
+ *  internal resources associated with a device handle
+ *
+ *  \param agRoot       Handles for this instance of SAS/SATA hardware
+ *  \param counters     Bit map of the IO counters
+ *
+ *  \return
+ *          - \e AGSA_RC_SUCCESS
+ *
+ */
+/*******************************************************************************/
+GLOBAL bit32 saResetLLCounters(
+                      agsaRoot_t *agRoot,
+                      bit32      counters
+                      )
+{
+  agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
+  bit32 i;
+
+  for (i = 0; i < LL_COUNTERS; i++)
+  {
+    if (counters & (1 << i))
+      saRoot->LLCounters.arrayIOCounter[i] = 0;
+  }
+
+  return AGSA_RC_SUCCESS;
+}
+#endif
+

sys/dev/pms/RefTisa/sallsdk/spc/spcdefs.h

@@ -0,0 +1,553 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/*! \file spcdefs.h
+ *  \brief The file defines the MPI Application Programming Interface (API)
+ *
+ * The file defines the MPI Application Programming Interfacde (API)
+ *
+ */
+/*******************************************************************************/
+#ifndef __SPCDEFS_H__
+#define __SPCDEFS_H__
+
+/*******************************************************************************/
+/*******************************************************************************/
+/* CONSTANTS                                                                    */
+/*******************************************************************************/
+/*******************************************************************************/
+/*******************************************************************************/
+/* MSGU CONFIGURATION TABLE                                                    */
+/*******************************************************************************/
+#define SPC_MSGU_CFG_TABLE_UPDATE               0x001   /* Inbound doorbell bit0 */
+#define SPC_MSGU_CFG_TABLE_RESET                0x002   /* Inbound doorbell bit1 */
+#define SPC_MSGU_CFG_TABLE_FREEZE               0x004   /* Inbound doorbell bit2 */
+#define SPC_MSGU_CFG_TABLE_UNFREEZE             0x008   /* Inbound doorbell bit4 */
+#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x080   /* Inbound doorbell bit7 SPCV */
+#define SPCV_MSGU_HALT_CPUS                     0x100   /* Inbound doorbell bit8 SPCV */
+
+/***** Notes *****/
+/* The firmware side is using Little Endian (MIPs). */
+/* So anything sending or receiving from FW must be in Little Endian */
+/*******************************************************************************/
+/** \struct mpiMsgHeader_s
+ *  \brief MPI message header
+ *
+ * The mpiMsgHeader_s defines the fields in the header of every message
+ */
+/*******************************************************************************/
+/* This structire defines the fields in the header of every message */
+
+
+struct mpiMsgHeader_s
+{
+  bit32 Header;             /* Bits [11:0]  - Message operation code */
+                            /* Bits [15:12] - Message Category */
+                            /* Bits [21:16] - Outboundqueue ID for the operation completion message */
+                            /* Bits [23:22] - Reserved */
+                            /* Bits [28:24] - Buffer Count, indicates how many buffer are allocated for the massage */
+                            /* Bits [30:29] - Reserved */
+                            /* Bits [31]    - Message Valid bit */
+};
+
+typedef struct mpiMsgHeader_s  mpiMsgHeader_t;
+
+#define V_BIT          0x1
+
+#define V_MASK         0x1
+#define BC_MASK        0x1F
+#define OBID_MASK      0x3F
+#define CAT_MASK       0x0F
+#define OPCODE_MASK    0xFFF
+#define HEADER_V_MASK  0x80000000
+#define HEADER_BC_MASK 0x1f000000
+
+#ifndef SPC_CONFIG
+/*******************************************************************************/
+/** \struct spc_ConfigMainDescriptor_s
+ *  \brief This structure is used to configure main part of Configuration Table
+ *
+ * This structure specifies all required attributes to configuration table
+ */
+/*******************************************************************************/
+/* new MPI configuration main table */
+struct  spc_configMainDescriptor_s
+{
+  bit8  Signature[4];                      /**< DW0 signature - Indicate coherent table */
+  bit32 InterfaceRev;                      /**< DW1 Revsion of Interface */
+  bit32 FWRevision;                        /**< DW2 Revsion of FW */
+  bit32 MaxOutstandingIO;                  /**< DW3 Max outstanding IO */
+  bit32 MDevMaxSGL;                        /**< DW4 Maximum SGL elements  & Max Devices */
+        /* bit0-15  Maximum SGL */
+        /* bit16-31 Maximum Devices */
+  bit32 ContrlCapFlag;                     /**< DW5 Controller Capability */
+        /* bit0-7   Max number of inbound queue */
+        /* bit8-15  Max number of outbound queue */
+        /* bit16    high priority of inbound queue is supported */
+        /* bit17    reserved */
+        /* bit18    interrupt coalescing is supported, SPCV-reserved */
+        /* bit19-24 Maximum number of valid phys */
+        /* bit25-31 SAS Revision SPecification */
+  bit32 GSTOffset;                         /**< DW6 General Status Table */
+  bit32 inboundQueueOffset;                /**< DW7 inbound configuration table offset */
+        /* bit23-0  inbound queue table offset */
+        /* bit31-24 entry size, new in SPCV */
+  bit32 outboundQueueOffset;               /**< DW8 outbound configuration table offset */
+        /* bit23-0  outbound queue table offset */
+        /* bit31-24 entry size, new in SPCV */
+  bit32 iQNPPD_HPPD_GEvent;                /**< DW9 inbound Queue Process depth and General Event */
+        /* bit0-7   inbound normal priority process depth */
+        /* bit8-15  inbound high priority process depth */
+        /* bit16-23 OQ number to receive GENERAL_EVENT Notification */
+        /* bit24-31 OQ number to receive DEVICE_HANDLE_REMOVAL Notification */
+  bit32 outboundHWEventPID0_3;             /**< DWA outbound HW event for PortId 0 to 3, SPCV-reserved */
+        /* bit0-7   outbound queue number of SAS_HW event for PhyId 0 */
+        /* bit8-15  outbound queue number of SAS_HW event for PhyId 1 */
+        /* bit16-23 outbound queue number of SAS_HW event for PhyId 2 */
+        /* bit24-31 outbound queue number of SAS_HW event for PhyId 3 */
+  bit32 outboundHWEventPID4_7;             /**< DWB outbound HW event for PortId 4 to 7, SPCV-reserved */
+        /* bit0-7   outbound queue number of SAS_HW event for PhyId 4 */
+        /* bit8-15  outbound queue number of SAS_HW event for PhyId 5 */
+        /* bit16-23 outbound queue number of SAS_HW event for PhyId 6 */
+        /* bit24-31 outbound queue number of SAS_HW event for PhyId 7 */
+  bit32 outboundNCQEventPID0_3;            /**< DWC outbound NCQ event for PortId 0 to 3, SPCV-reserved */
+        /* bit0-7   outbound queue number of SATA_NCQ event for PhyId 0 */
+        /* bit8-15  outbound queue number of SATA_NCQ event for PhyId 1 */
+        /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 2 */
+        /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */
+  bit32 outboundNCQEventPID4_7;            /**< DWD outbound NCQ event for PortId 4 to 7, SPCV-reserved*/
+        /* bit0-7   outbound queue number of SATA_NCQ event for PhyId 4 */
+        /* bit8-15  outbound queue number of SATA_NCQ event for PhyId 5 */
+        /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 6 */
+        /* bit24-31 outbound queue number of SATA_NCQ event for PhyId 7 */
+  bit32 outboundTargetITNexusEventPID0_3;  /**< DWE outbound target ITNexus Event for PortId 0 to 3, SPCV-reserved */
+        /* bit0-7   outbound queue number of ITNexus event for PhyId 0 */
+        /* bit8-15  outbound queue number of ITNexus event for PhyId 1 */
+        /* bit16-23 outbound queue number of ITNexus event for PhyId 2 */
+        /* bit24-31 outbound queue number of ITNexus event for PhyId 3 */
+  bit32 outboundTargetITNexusEventPID4_7;  /**< DWF outbound target ITNexus Event for PortId 4 to 7, SPCV-reserved */
+        /* bit0-7   outbound queue number of ITNexus event for PhyId 4 */
+        /* bit8-15  outbound queue number of ITNexus event for PhyId 5 */
+        /* bit16-23 outbound queue number of ITNexus event for PhyId 6 */
+        /* bit24-31 outbound queue number of ITNexus event for PhyId 7 */
+  bit32 outboundTargetSSPEventPID0_3;      /**< DW10 outbound target SSP event for PordId 0 to 3, SPCV-reserved */
+        /* bit0-7   outbound queue number of SSP event for PhyId 0 */
+        /* bit8-15  outbound queue number of SSP event for PhyId 1 */
+        /* bit16-23 outbound queue number of SSP event for PhyId 2 */
+        /* bit24-31 outbound queue number of SSP event for PhyId 3 */
+  bit32 outboundTargetSSPEventPID4_7;      /**< DW11 outbound target SSP event for PordId 4 to 7, SPCV-reserved */
+        /* bit0-7   outbound queue number of SSP event for PhyId 4 */
+        /* bit8-15  outbound queue number of SSP event for PhyId 5 */
+        /* bit16-23 outbound queue number of SSP event for PhyId 6 */
+        /* bit24-31 outbound queue number of SSP event for PhyId 7 */
+  bit32 ioAbortDelay;                      /**< DW12 IO Abort Delay (bit15:0) MPI_TABLE_CHANGE*/
+  bit32 custset;                           /**< DW13 custset */
+  bit32 upperEventLogAddress;              /**< DW14 Upper physical MSGU Event log address */
+  bit32 lowerEventLogAddress;              /**< DW15 Lower physical MSGU Event log address */
+  bit32 eventLogSize;                      /**< DW16 Size of MSGU Event log, 0 means log disable */
+  bit32 eventLogOption;                    /**< DW17 Option of MSGU Event log */
+        /* bit3-0 log severity, 0x0 Disable Logging */
+        /*                      0x1 Critical Error */
+        /*                      0x2 Minor Error    */
+        /*                      0x3 Warning        */
+        /*                      0x4 Information    */
+        /*                      0x5 Debugging      */
+        /*                      0x6 - 0xF Reserved */
+  bit32 upperIOPeventLogAddress;           /**< DW18 Upper physical IOP Event log address */
+  bit32 lowerIOPeventLogAddress;           /**< DW19 Lower physical IOP Event log address */
+  bit32 IOPeventLogSize;                   /**< DW1A Size of IOP Event log, 0 means log disable */
+  bit32 IOPeventLogOption;                 /**< DW1B Option of IOP Event log */
+        /* bit3-0 log severity, 0x0 Critical Error */
+        /*                      0x1 Minor Error    */
+        /*                      0x2 Warning        */
+        /*                      0x3 Information    */
+        /*                      0x4 Unknown        */
+        /*                      0x5 - 0xF Reserved */
+  bit32 FatalErrorInterrupt;               /**< DW1C Fatal Error Interrupt enable and vector */
+        /* bit0     Fatal Error Interrupt Enable   */
+        /* bit1     PI/CI 64bit address            */
+        /* bit2     SGPIO IOMB support */
+        /* bit6-2   Reserved                       */
+        /* bit7     OQ NP/HPriority Path enable    */
+        /* bit15-8  Fatal Error Interrupt Vector   */
+        /* bit16    Enable IQ/OQ 64                */
+        /* bit17    Interrupt Reassertion Enable   */
+        /* bit18    Interrupt Reassertion Delay in ms          */
+        /* bit31-19 Interrupt Reassertion delay, 0-default 1ms */
+  bit32 FatalErrorDumpOffset0;             /**< DW1D FERDOMS-GU Fatal Error Register Dump Offset for MSGU */
+  bit32 FatalErrorDumpLength0;             /**< DW1E FERDLMS-GU Fatal Error Register Dump Length for MSGU */
+  bit32 FatalErrorDumpOffset1;             /**< DW1F FERDO-SSTRUCPCS Fatal Error Register Dump Offset for IOP */
+  bit32 FatalErrorDumpLength1;             /**< DW20 FERDLSTRUCTTPCS  Fatal Error Register Dump Length for IOP */
+  bit32 HDAModeFlags;                      /**< DW21 HDA Mode Flags, SPCV-reserved */
+  bit32 analogSetupTblOffset;              /**< DW22 SPASTO Phy Calibration Table offset */
+        /* bit23-0  phy calib table offset */
+        /* bit31-24 entry size */
+  bit32 InterruptVecTblOffset;             /**< DW23 Interrupt Vector Table MPI_TABLE_CHANG */
+        /* bit23-0  interrupt vector table offset */
+        /* bit31-24 entry size */
+  bit32 phyAttributeTblOffset;             /**< DW24 SAS Phy Attribute Table Offset MPI_TABLE_CHANG*/
+        /* bit23-0  phy attribute table offset */
+        /* bit31-24 entry size */
+  bit32 portRecoveryResetTimer;            /* Offset 0x25 [31:16] Port recovery timer default that is 0
+                                              used for all SAS ports. Granularity of this timer is 100ms. The host can
+                                              change the individual port recovery timer by using the PORT_CONTROL
+                                              [15:0] Port reset timer default that is used 3 (i.e 300ms) for all
+                                              SAS ports. Granularity of this timer is 100ms. Host can change the
+                                              individual port recovery timer by using PORT_CONTROL Command */
+  bit32 interruptReassertionDelay;         /* Offset 0x26 [23:0] Remind host of outbound completion 0 disabled 100usec per increment */
+
+  bit32     ilaRevision;                   /* Offset 0x27 */
+};
+
+/* main configuration offset - byte offset */
+#define MAIN_SIGNATURE_OFFSET          0x00    /* DWORD 0x00 (R) */
+#define MAIN_INTERFACE_REVISION        0x04    /* DWORD 0x01 (R) */
+#define MAIN_FW_REVISION               0x08    /* DWORD 0x02 (R) */
+#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C    /* DWORD 0x03 (R) */
+#define MAIN_MAX_SGL_OFFSET            0x10    /* DWORD 0x04 (R) */
+#define MAIN_CNTRL_CAP_OFFSET          0x14    /* DWORD 0x05 (R) */
+#define MAIN_GST_OFFSET                0x18    /* DWORD 0x06 (R) */
+#define MAIN_IBQ_OFFSET                0x1C    /* DWORD 0x07 (R) */
+#define MAIN_OBQ_OFFSET                0x20    /* DWORD 0x08 (R) */
+#define MAIN_IQNPPD_HPPD_OFFSET        0x24    /* DWORD 0x09 (W) */
+#define MAIN_OB_HW_EVENT_PID03_OFFSET  0x28    /* DWORD 0x0A (W) */ /* reserved for SPCV */
+#define MAIN_OB_HW_EVENT_PID47_OFFSET  0x2C    /* DWORD 0x0B (W) */ /* reserved for SPCV */
+#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30    /* DWORD 0x0C (W) */ /* reserved for SPCV */
+#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34    /* DWORD 0x0D (W) */ /* reserved for SPCV */
+#define MAIN_TITNX_EVENT_PID03_OFFSET  0x38    /* DWORD 0x0E (W) */ /* reserved for SPCV */
+#define MAIN_TITNX_EVENT_PID47_OFFSET  0x3C    /* DWORD 0x0F (W) */ /* reserved for SPCV */
+#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40    /* DWORD 0x10 (W) */ /* reserved for SPCV */
+#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44    /* DWORD 0x11 (W) */ /* reserved for SPCV */
+#define MAIN_IO_ABORT_DELAY            0x48    /* DWORD 0x12 (W) */ /* reserved for SPCV */
+#define MAIN_CUSTOMER_SETTING          0x4C    /* DWORD 0x13 (W) */ /* reserved for SPCV */
+#define MAIN_EVENT_LOG_ADDR_HI         0x50    /* DWORD 0x14 (W) */
+#define MAIN_EVENT_LOG_ADDR_LO         0x54    /* DWORD 0x15 (W) */
+#define MAIN_EVENT_LOG_BUFF_SIZE       0x58    /* DWORD 0x16 (W) */
+#define MAIN_EVENT_LOG_OPTION          0x5C    /* DWORD 0x17 (W) */
+#define MAIN_IOP_EVENT_LOG_ADDR_HI     0x60    /* DWORD 0x18 (W) */
+#define MAIN_IOP_EVENT_LOG_ADDR_LO     0x64    /* DWORD 0x19 (W) */
+#define MAIN_IOP_EVENT_LOG_BUFF_SIZE   0x68    /* DWORD 0x1A (W) */
+#define MAIN_IOP_EVENT_LOG_OPTION      0x6C    /* DWORD 0x1B (W) */
+#define MAIN_FATAL_ERROR_INTERRUPT     0x70    /* DWORD 0x1C (W) */
+#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74    /* DWORD 0x1D (R) */
+#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78    /* DWORD 0x1E (R) */
+#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C    /* DWORD 0x1F (R) */
+#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80    /* DWORD 0x20 (R) */
+#define MAIN_HDA_FLAGS_OFFSET          0x84    /* DWORD 0x21 (R) */ /* reserved for SPCV */
+#define MAIN_ANALOG_SETUP_OFFSET       0x88    /* DWORD 0x22 (R) */
+#define MAIN_INT_VEC_TABLE_OFFSET      0x8C    /* DWORD 0x23 (W) */ /*  for SPCV */
+#define MAIN_PHY_ATTRIBUTE_OFFSET      0x90    /* DWORD 0x24 (W) */ /*  for SPCV */
+#define MAIN_PRECTD_PRESETD            0x94    /* DWORD 0x25 (W) */ /*  for SPCV */
+#define MAIN_IRAD_RESERVED             0x98    /* DWORD 0x26 (W) */ /*  for SPCV */
+#define MAIN_MOQFOT_MOQFOES            0x9C    /* DWORD 0x27 (W) */ /*  for SPCV */
+#define MAIN_MERRDCTO_MERRDCES         0xA0    /* DWORD 0x28 (W) */ /*  for SPCV */
+#define MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN  0xA4 /* DWORD 0x29 (W) */ /*  for SPCV */
+#define MAIN_INACTIVE_ILA_REVSION      0xA8    /* DWORD 0x2A (W) */ /*  for SPCV V 3.02 */
+#define MAIN_SEEPROM_REVSION           0xAC    /* DWORD 0x2B (W) */ /*  for SPCV V 3.02 */
+#define MAIN_UNKNOWN1                  0xB0    /* DWORD 0x2C (W) */ /*  for SPCV V 3.03 */
+#define MAIN_UNKNOWN2                  0xB4    /* DWORD 0x2D (W) */ /*  for SPCV V 3.03 */
+#define MAIN_UNKNOWN3                  0xB8    /* DWORD 0x2E (W) */ /*  for SPCV V 3.03 */
+#define MAIN_XCBI_REF_TAG_PAT          0xBC    /* DWORD 0x2F (W) */ /*  for SPCV V 3.03 */
+#define MAIN_AWT_MIDRANGE              0xC0    /* DWORD 0x30 (W) */ /*  for SPCV V 3.03 */
+
+
+typedef struct spc_configMainDescriptor_s spc_configMainDescriptor_t;
+#define SPC_CONFIG
+#endif
+
+/* bit to disable end to end crc checking ins SPCv */
+#define MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x00010000
+
+/* bit mask for field Controller Capability in main part */
+#define MAIN_MAX_IB_MASK               0x000000ff  /* bit7-0 */
+#define MAIN_MAX_OB_MASK               0x0000ff00  /* bit15-8 */
+#define MAIN_PHY_COUNT_MASK            0x01f80000  /* bit24-19 */
+#define MAIN_QSUPPORT_BITS             0x0007ffff
+#define MAIN_SAS_SUPPORT_BITS          0xfe000000
+
+/* bit mask for field max sgl in main part */
+#define MAIN_MAX_SGL_BITS              0xFFFF
+#define MAIN_MAX_DEV_BITS              0xFFFF0000
+
+/* bit mask for HDA flags field */
+#define MAIN_HDA_FLAG_BITS             0x000000FF
+
+#define FATAL_ERROR_INT_BITS           0xFF
+#define INT_REASRT_ENABLE              0x00020000
+#define INT_REASRT_MS_ENABLE           0x00040000
+#define INT_REASRT_DELAY_BITS          0xFFF80000
+
+#define MAX_VALID_PHYS                 8
+#define IB_QUEUE_CFGSIZE               64
+#define OB_QUEUE_CFGSIZE               64
+
+/* inbound queue configuration offset - byte offset */
+#define IB_PROPERITY_OFFSET            0x00
+#define IB_BASE_ADDR_HI_OFFSET         0x04
+#define IB_BASE_ADDR_LO_OFFSET         0x08
+#define IB_CI_BASE_ADDR_HI_OFFSET      0x0C
+#define IB_CI_BASE_ADDR_LO_OFFSET      0x10
+#define IB_PIPCI_BAR                   0x14
+#define IB_PIPCI_BAR_OFFSET            0x18
+#define IB_RESERVED_OFFSET             0x1C
+
+/* outbound queue configuration offset - byte offset */
+#define OB_PROPERITY_OFFSET            0x00
+#define OB_BASE_ADDR_HI_OFFSET         0x04
+#define OB_BASE_ADDR_LO_OFFSET         0x08
+#define OB_PI_BASE_ADDR_HI_OFFSET      0x0C
+#define OB_PI_BASE_ADDR_LO_OFFSET      0x10
+#define OB_CIPCI_BAR                   0x14
+#define OB_CIPCI_BAR_OFFSET            0x18
+#define OB_INTERRUPT_COALES_OFFSET     0x1C
+#define OB_DYNAMIC_COALES_OFFSET       0x20
+
+#define OB_PROPERTY_INT_ENABLE         0x40000000
+
+/* General Status Table offset - byte offset */
+#define GST_GSTLEN_MPIS_OFFSET         0x00
+#define GST_IQ_FREEZE_STATE0_OFFSET    0x04
+#define GST_IQ_FREEZE_STATE1_OFFSET    0x08
+#define GST_MSGUTCNT_OFFSET            0x0C
+#define GST_IOPTCNT_OFFSET             0x10
+#define GST_IOP1TCNT_OFFSET            0x14
+#define GST_PHYSTATE_OFFSET            0x18  /* SPCV reserved */
+#define GST_PHYSTATE0_OFFSET           0x18  /* SPCV reserved */
+#define GST_PHYSTATE1_OFFSET           0x1C  /* SPCV reserved */
+#define GST_PHYSTATE2_OFFSET           0x20  /* SPCV reserved */
+#define GST_PHYSTATE3_OFFSET           0x24  /* SPCV reserved */
+#define GST_PHYSTATE4_OFFSET           0x28  /* SPCV reserved */
+#define GST_PHYSTATE5_OFFSET           0x2C  /* SPCV reserved */
+#define GST_PHYSTATE6_OFFSET           0x30  /* SPCV reserved */
+#define GST_PHYSTATE7_OFFSET           0x34  /* SPCV reserved */
+#define GST_GPIO_PINS_OFFSET           0x38
+#define GST_RERRINFO_OFFSET            0x44
+
+/* General Status Table - MPI state */
+#define GST_MPI_STATE_UNINIT           0x00
+#define GST_MPI_STATE_INIT             0x01
+#define GST_MPI_STATE_TERMINATION      0x02
+#define GST_MPI_STATE_ERROR            0x03
+#define GST_MPI_STATE_MASK             0x07
+
+#define GST_INF_STATE_BITS             0xfffe0007
+
+
+/* MPI fatal and non fatal offset mask */
+#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
+#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)    /*  for SPCV */
+
+/* MPI fatal and non fatal Error dump capture table offset - byte offset */
+#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET            0x00     /* HNFBUFL */
+#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET            0x04     /* HNFBUFH */
+#define MPI_FATAL_EDUMP_TABLE_LENGTH               0x08     /* HNFBLEN */
+#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE            0x0C     /* FDDHSHK */
+#define MPI_FATAL_EDUMP_TABLE_STATUS               0x10     /* FDDTSTAT */
+#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN            0x14     /* ACCDDLEN */
+/*  */
+#define MPI_FATAL_EDUMP_HANDSHAKE_RDY              0x1
+#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY             0x0
+/*  */
+#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD                 0x0
+#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED           0x1
+#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
+#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE      0x3
+
+#define IOCTL_ERROR_NO_FATAL_ERROR           0x77
+
+/*******************************************************************************/
+/** \struct spc_GSTableDescriptor_s
+ *  \brief This structure is used for SPC MPI General Status Table
+ *
+ * This structure specifies all required attributes to Gereral Status Table
+ */
+/*******************************************************************************/
+struct spc_GSTableDescriptor_s
+{
+  bit32    GSTLenMPIS;           /**< DW0 - GST Length, MPI State */
+                                  /**< bit02-00 MPI state */
+                                  /**< 000 - not initialized, 001 - initialized,
+                                       010 - Configuration termination in progress */
+                                  /**< bit3 - IQ Frozen */
+                                  /**< bit15-04 GST Length */
+                                  /**< bit31-16 MPI-S Initialize Error */
+  bit32    IQFreezeState0;       /**< DW1 - Inbound Queue Freeze State0 */
+  bit32    IQFreezeState1;       /**< DW2 - Inbound Qeue Freeze State1 */
+  bit32    MsguTcnt;             /**< DW3 - MSGU Tick count */
+  bit32    IopTcnt;              /**< DW4 - IOP Tick count */
+  bit32    Iop1Tcnt;             /**< DW5 - IOP1 Tick count */
+  bit32    PhyState[MAX_VALID_PHYS];  /* SPCV = reserved */
+                                 /**< DW6 to DW 0D - Phy Link state 0 to 7, Phy Start State 0 to 7 */
+                                  /**< bit00 Phy Start state n, 0 not started, 1 started */
+                                  /**< bit01 Phy Link state n, 0 link down, 1 link up */
+                                  /**< bit31-2 Reserved */
+  bit32    GPIOpins;             /**< DWE - GPIO pins */
+  bit32    reserved1;            /**< DWF - reserved */
+  bit32    reserved2;            /**< DW10 - reserved */
+  bit32    recoverErrInfo[8];    /**< DW11 to DW18 - Recoverable Error Information */
+};
+
+typedef struct spc_GSTableDescriptor_s spc_GSTableDescriptor_t;
+
+/*******************************************************************************/
+/** \struct spc_SPASTable_s
+ *  \brief SAS Phy Analog Setup Table
+ *
+ * The spc_SPASTable_s structure is used to set Phy Calibration
+ * attributes
+ */
+/*******************************************************************************/
+struct spc_SPASTable_s
+{
+  bit32   spaReg0;            /* transmitter per port configuration 1 SAS_SATA G1 */
+  bit32   spaReg1;            /* transmitter per port configuration 2 SAS_SATA G1*/
+  bit32   spaReg2;            /* transmitter per port configuration 3 SAS_SATA G1*/
+  bit32   spaReg3;            /* transmitter configuration 1 */
+  bit32   spaReg4;            /* reveiver per port configuration 1 SAS_SATA G1G2 */
+  bit32   spaReg5;            /* reveiver per port configuration 2 SAS_SATA G3 */
+  bit32   spaReg6;            /* reveiver per configuration 1 */
+  bit32   spaReg7;            /* reveiver per configuration 2 */
+  bit32   reserved[2];        /* reserved */
+};
+
+typedef struct spc_SPASTable_s spc_SPASTable_t;
+
+/*******************************************************************************/
+/** \struct spc_inboundQueueDescriptor_s
+ *  \brief This structure is used to configure inbound queues
+ *
+ * This structure specifies all required attributes to configure inbound queues
+ */
+/*******************************************************************************/
+struct spc_inboundQueueDescriptor_s
+{
+  bit32    elementPriSizeCount;  /**< Priority, Size, Count in the queue */
+                                  /**< bit00-15 Count */
+                                  /**< When set to 0, this queue is disabled */
+                                  /**< bit16-29 Size */
+                                  /**< bit30-31 Priority 00:Normal, 01:High Priority */
+  bit32    upperBaseAddress;     /**< Upper address bits for the queue message buffer pool */
+  bit32    lowerBaseAddress;     /**< Lower address bits for the queue message buffer pool */
+  bit32    ciUpperBaseAddress;   /**< Upper physical address for inbound queue CI */
+  bit32    ciLowerBaseAddress;   /**< Lower physical address for inbound queue CI */
+  bit32    PIPCIBar;             /**< PCI BAR for PI Offset */
+  bit32    PIOffset;             /**< Offset address for inbound queue PI */
+  bit32    reserved;             /**< reserved */
+};
+
+typedef struct spc_inboundQueueDescriptor_s spc_inboundQueueDescriptor_t;
+
+/*******************************************************************************/
+/** \struct spc_outboundQueueDescriptor_s
+ *  \brief This structure is used to configure outbound queues
+ *
+ * This structure specifies all required attributes to configure outbound queues
+ */
+/*******************************************************************************/
+struct spc_outboundQueueDescriptor_s
+{
+  bit32    elementSizeCount;      /**< Size & Count of each element (slot) in the queue) */
+                                   /**< bit00-15 Count */
+                                   /**< When set to 0, this queue is disabled */
+                                   /**< bit16-29 Size */
+                                   /**< bit30    Interrupt enable/disable */
+                                   /**< bit31    reserved */
+  bit32    upperBaseAddress;      /**< Upper address bits for the queue message buffer pool */
+  bit32    lowerBaseAddress;      /**< Lower address bits for the queue message buffer pool */
+  bit32    piUpperBaseAddress;    /**< PI Upper Base Address for outbound queue */
+  bit32    piLowerBaseAddress;    /**< PI Lower Base Address for outbound queue */
+  bit32    CIPCIBar;              /**< PCI BAR for CI Offset */
+  bit32    CIOffset;              /**< Offset address for outbound queue CI */
+  bit32    interruptVecCntDelay;  /**< Delay in microseconds before the interrupt is asserted */
+                                   /**< if the interrupt threshold has not been reached */
+                                   /**< Number of interrupt events before the interrupt is asserted */
+                                   /**< If set to 0, interrupts for this queue are disable */
+                                   /**< Interrupt vector number for this queue */
+                                   /**< Note that the interrupt type can be MSI or MSI-X */
+                                   /**< depending on the system configuration */
+                                   /**< bit00-15 Delay */
+                                   /**< bit16-23 Count */
+                                   /**< bit24-31 Vector */
+  bit32    DInterruptTOPCIOffset; /**< Dynamic Interrupt Coalescing Timeout PCI Bar Offset */
+};
+
+typedef struct spc_outboundQueueDescriptor_s spc_outboundQueueDescriptor_t;
+
+typedef struct InterruptVT_s
+{
+  bit32 iccict;        /**< DW0 - Interrupt Colescing Control and Timer */
+  bit32 iraeirad;      /**< DW1 - Interrupt Reassertion Enable/Delay */
+} InterruptVT_t;
+
+typedef struct mpiInterruptVT_s
+{
+  InterruptVT_t IntVecTble[MAX_NUM_VECTOR << 1];
+} mpiInterruptVT_t;
+
+#define INT_VT_Coal_CNT_TO 0
+#define INT_VT_Coal_ReAssert_Enab 4
+
+typedef struct phyAttrb_s
+{
+  bit32    phyState;
+  bit32    phyEventOQ;
+} phyAttrb_t;
+
+typedef struct sasPhyAttribute_s
+{
+  phyAttrb_t phyAttribute[MAX_VALID_PHYS];
+}sasPhyAttribute_t;
+
+
+#define PHY_STATE    0
+#define PHY_EVENT_OQ 4
+
+/*******************************************************************************/
+/** \struct spcMSGUConfig_s
+ *  \brief This structure is used to configure controller's message unit
+ *
+ */
+/*******************************************************************************/
+typedef struct fwMSGUConfig_s
+{
+  spc_configMainDescriptor_t      mainConfiguration;                /**< main part of Configuration Table */
+  spc_GSTableDescriptor_t         GeneralStatusTable;               /**< MPI general status table */
+  spc_inboundQueueDescriptor_t    inboundQueue[IB_QUEUE_CFGSIZE];   /**< Inbound queue configuration array */
+  spc_outboundQueueDescriptor_t   outboundQueue[OB_QUEUE_CFGSIZE];  /**< Outbound queue configuration array */
+  agsaPhyAnalogSetupTable_t       phyAnalogConfig;
+  mpiInterruptVT_t                interruptVTable;
+  sasPhyAttribute_t               phyAttributeTable;
+}fwMSGUConfig_t;
+
+
+typedef void (*EnadDisabHandler_t)(
+                            agsaRoot_t  *agRoot,
+                            bit32       interruptVectorIndex
+                              );
+
+typedef bit32 (*InterruptOurs_t)(
+                            agsaRoot_t  *agRoot,
+                            bit32       interruptVectorIndex
+                              );
+#endif /* __SPC_DEFS__ */

sys/dev/pms/RefTisa/sat/api/sm.h

@@ -0,0 +1,292 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+**    
+*   sm.h 
+*
+*   Abstract:   This module defines the contants, enum and #define definition used
+*               by SAT Moduled (SM).
+*     
+********************************************************************************/
+
+#ifndef SM_H
+#define SM_H
+
+/*************************************************
+ *   constants for type field in smMem_t
+ *************************************************/
+#define SM_CACHED_MEM                             0x00     /**< CACHED memory type */
+#define SM_DMA_MEM                                0x01     /**< DMA memory type */
+#define SM_CACHED_DMA_MEM                         0x02     /**< CACHED DMA memory type */
+
+/*************************************************
+ *   constants for API return values
+ *************************************************/
+typedef enum
+{
+  SM_RC_SUCCESS,
+  SM_RC_FAILURE,
+  SM_RC_BUSY,
+  SM_RC_NODEVICE,
+  SM_RC_VERSION_INCOMPATIBLE,
+  SM_RC_VERSION_UNTESTED,
+  SM_RC_RSV1,
+  SM_RC_RSV2,
+  SM_RC_RSV3,
+  SM_RC_RSV4,
+  SM_RC_DEVICE_BUSY, /* must be the same as tiDeviceBusy */
+  
+} smStatus_t;
+
+typedef enum
+{
+  smIOSuccess,
+  smIOOverRun,
+  smIOUnderRun,
+  smIOFailed,
+  smIODifError,
+  smIOEncryptError,
+  smIORetry,           /* open retry timeout */
+  smIOSTPResourceBusy, /* stp resource busy */
+} smIOStatus_t;
+
+typedef enum
+{
+  smDetailBusy,
+  smDetailNotValid,
+  smDetailNoLogin,
+  smDetailAbortLogin,
+  smDetailAbortReset,
+  smDetailAborted,
+  smDetailDifMismatch,
+  smDetailDifAppTagMismatch,
+  smDetailDifRefTagMismatch,
+  smDetailDifCrcMismatch,
+  smDetailDekKeyCacheMiss,
+  smDetailCipherModeInvalid,
+  smDetailDekIVMismatch,
+  smDetailDekRamInterfaceError,
+  smDetailDekIndexOutofBounds,
+  smDetailOtherError
+} smIOStatusDetail_t;
+
+/*
+ * Data direction for I/O request
+ */
+typedef enum
+{
+  smDirectionIn   = 0x0000,
+  smDirectionOut  = 0x0001
+}smDataDirection_t;
+
+/*
+ * Event types for tdsmEventCB()
+ * do not change: Needs to be in sync with TISA API
+ */
+typedef enum
+{
+  smIntrEventTypeCnxError,
+  smIntrEventTypeDiscovery,
+  smIntrEventTypeTransportRecovery,
+  smIntrEventTypeTaskManagement,
+  smIntrEventTypeDeviceChange,
+  smIntrEventTypeLogin,
+  smIntrEventTypeLocalAbort  
+} smIntrEventType_t;
+
+typedef enum
+{
+  smTMOK,
+  smTMFailed
+} smTMEventStatus_t;
+
+/*
+ * Flags in smSuperScsiInitiatorRequest_t
+ */
+#define SM_SCSI_INITIATOR_DIF         0x00000001
+#define SM_SCSI_INITIATOR_ENCRYPT     0x00000002
+
+/*
+ * Flags in smSuperScsiInitiatorRequest_t
+ */
+#define SM_SCSI_TARGET_DIF         0x00000001
+#define SM_SCSI_TARGET_MIRROR      0x00000002
+#define SM_SCSI_TARGET_ENCRYPT     0x00000004
+
+typedef struct {
+                void		*tdData;
+                void		*smData;
+} smContext_t;
+
+
+typedef    smContext_t    smDeviceHandle_t;
+
+typedef    smContext_t    smIORequest_t;
+
+typedef    smContext_t    smRoot_t;
+
+typedef struct 
+{
+	bit8  lun[8];               /* logical unit number  */
+} smLUN_t;
+
+typedef struct{
+		smLUN_t         lun;
+		bit32           expDataLength;
+		bit32           taskAttribute;
+		bit32           crn;
+		bit8            cdb[16];
+} smIniScsiCmnd_t;
+
+
+
+typedef struct{
+               void 	*virtPtr;
+               void 	*osHandle;
+               bit32 	physAddrUpper;
+               bit32 	physAddrLower;
+               bit32 	totalLength;
+               bit32 	numElements;
+               bit32 	singleElementLength;
+               bit32 	alignment;
+               bit32 	type;
+               bit32 	reserved;
+} smMem_t;
+
+#define SM_NUM_MEM_CHUNKS 8
+
+typedef struct{
+               bit32            count;
+               smMem_t          smMemory[SM_NUM_MEM_CHUNKS];
+} smMemoryRequirement_t;
+
+typedef struct{
+	       bit32 	lower;
+	       bit32 	upper;
+	       bit32 	len;
+	       bit32 	type;
+} smSgl_t;
+
+/*
+ * DIF operation
+ */
+#define DIF_INSERT                     0
+#define DIF_VERIFY_FORWARD             1
+#define DIF_VERIFY_DELETE              2
+#define DIF_VERIFY_REPLACE             3
+#define DIF_VERIFY_UDT_REPLACE_CRC     5
+#define DIF_REPLACE_UDT_REPLACE_CRC    7
+
+#define DIF_UDT_SIZE              6
+
+typedef struct smDif
+{
+  agBOOLEAN   enableDIFPerLA;
+  bit32       flag;
+  bit16       initialIOSeed;
+  bit16       reserved;
+  bit32       DIFPerLAAddrLo;
+  bit32       DIFPerLAAddrHi;
+  bit16       DIFPerLARegion0SecCount;
+  bit16       DIFPerLANumOfRegions;
+  bit8        udtArray[DIF_UDT_SIZE];
+  bit8        udrtArray[DIF_UDT_SIZE];  
+} smDif_t;
+
+typedef struct smEncryptDek {
+    bit32          dekTable;
+    bit32          dekIndex;
+} smEncryptDek_t;
+
+typedef struct smEncrypt {
+  smEncryptDek_t     dekInfo;	
+  bit32          kekIndex;
+  agBOOLEAN      keyTagCheck;
+  agBOOLEAN  	   enableEncryptionPerLA;    
+  bit32          sectorSizeIndex;
+  bit32          encryptMode;
+  bit32          keyTag_W0;
+  bit32          keyTag_W1;
+  bit32          tweakVal_W0;
+  bit32          tweakVal_W1;
+  bit32          tweakVal_W2;
+  bit32          tweakVal_W3;
+  bit32          EncryptionPerLAAddrLo;
+  bit32          EncryptionPerLAAddrHi;
+  bit16          EncryptionPerLRegion0SecCount;
+  bit16          reserved;
+} smEncrypt_t;
+
+typedef struct smScsiInitiatorRequest {
+	      void                     *sglVirtualAddr;
+	      smIniScsiCmnd_t          scsiCmnd;
+	      smSgl_t                  smSgl1;
+	      smDataDirection_t        dataDirection;
+} smScsiInitiatorRequest_t;
+
+typedef struct smSuperScsiInitiatorRequest
+{
+  void                *sglVirtualAddr;
+  smIniScsiCmnd_t     scsiCmnd;     
+  smSgl_t             smSgl1;
+  smDataDirection_t   dataDirection;
+  bit32               flags; /* 
+                               bit 0-1: reserved
+                               bit 2: enable encryption
+                               bit 3: enable dif
+                               bit 4-7: reserved
+                               bit 8-23: DIF SKIP Bytes
+                               bit 24-31: Reserved
+                             */
+  smDif_t             Dif;
+  smEncrypt_t         Encrypt;
+} smSuperScsiInitiatorRequest_t;
+
+typedef struct{
+	       void     *senseData;
+	       bit8 	senseLen;
+} smSenseData_t;
+
+typedef struct{
+               bit32			maxActiveIOs;
+               bit32			numDevHandles;
+#ifdef SM_DEBUG
+               bit32			SMDebugLevel;
+#endif
+} smSwConfig_t;
+
+
+#define smBOOLEAN  bit32
+
+
+
+
+
+
+
+
+
+
+#endif  /* SM_H */
+

sys/dev/pms/RefTisa/sat/api/smapi.h

@@ -0,0 +1,122 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+*   smapi.h 
+*
+*   Abstract:   This module contains function prototype of the SAT
+*               Module (SM) API for initiator.
+*******************************************************************************/
+
+#ifndef SMAPI_H
+#define SMAPI_H
+
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+
+osGLOBAL bit32
+smRegisterDevice(
+                 smRoot_t                       *smRoot,
+                 agsaDevHandle_t                *agDevHandle,
+                 smDeviceHandle_t               *smDeviceHandle,
+                 agsaDevHandle_t                *agExpDevHandle,
+                 bit32                          phyID,
+                 bit32                          DeviceType
+                );
+
+osGLOBAL bit32
+smDeregisterDevice(
+                   smRoot_t                     *smRoot,
+                   agsaDevHandle_t              *agDevHandle,
+                   smDeviceHandle_t             *smDeviceHandle
+                  );
+		  
+osGLOBAL void
+smGetRequirements(
+                  smRoot_t                      *smRoot,
+                  smSwConfig_t                  *swConfig,
+                  smMemoryRequirement_t         *memoryRequirement,
+                  bit32                         *usecsPerTick,
+                  bit32                         *maxNumLocks
+                 );
+
+osGLOBAL bit32
+smIDStart(
+          smRoot_t                     *smRoot,
+          smIORequest_t                *smIORequest,
+          smDeviceHandle_t             *smDeviceHandle
+         );
+
+osGLOBAL bit32
+smInitialize(
+             smRoot_t                           *smRoot,
+             agsaRoot_t                         *agRoot,
+             smMemoryRequirement_t              *memoryAllocated,
+             smSwConfig_t                       *swConfig,
+             bit32                              usecsPerTick 
+            );
+
+osGLOBAL bit32
+smIOAbort(
+           smRoot_t                     *smRoot,
+           smIORequest_t                *tasktag
+         );
+
+osGLOBAL bit32
+smIOAbortAll(
+             smRoot_t                     *smRoot,
+             smDeviceHandle_t             *smDeviceHandle
+            );
+
+osGLOBAL FORCEINLINE bit32
+smIOStart(
+          smRoot_t                      *smRoot,
+          smIORequest_t                 *smIORequest,
+          smDeviceHandle_t              *smDeviceHandle,
+          smScsiInitiatorRequest_t      *smSCSIRequest,
+          bit32                         interruptContext
+         );
+
+osGLOBAL bit32
+smSuperIOStart(
+               smRoot_t                         *smRoot,
+               smIORequest_t                    *smIORequest,
+               smDeviceHandle_t                 *smDeviceHandle,
+               smSuperScsiInitiatorRequest_t    *smSCSIRequest,
+               bit32                            AddrHi,
+               bit32                            AddrLo,	       
+               bit32                            interruptContext
+              );
+	 
+osGLOBAL bit32
+smTaskManagement(
+                 smRoot_t                       *smRoot,
+                 smDeviceHandle_t               *smDeviceHandle,
+                 bit32                          task,
+                 smLUN_t                        *lun,
+                 smIORequest_t                  *taskTag,
+                 smIORequest_t                  *currentTaskTag
+                );
+
+#endif  /* SMAPI_H */
+

sys/dev/pms/RefTisa/sat/api/tdsmapi.h

@@ -0,0 +1,211 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+*   tmsmapi.h 
+*
+*   Abstract:   This module contains function prototype of the SAT
+*               Module (SM) API callback for initiator.
+*******************************************************************************/
+
+#ifndef TDSMAPI_H
+#define TDSMAPI_H
+
+osGLOBAL void	
+tdsmIDCompletedCB(
+                  smRoot_t   *smRoot,
+                  smIORequest_t   *smIORequest,
+                  smDeviceHandle_t   *smDeviceHandle,
+                  bit32    status,
+                  void    *IDdata
+                 );
+
+osGLOBAL FORCEINLINE void 
+tdsmIOCompletedCB(
+                  smRoot_t   *smRoot,
+                  smIORequest_t   *smIORequest,
+                  bit32    status,
+                  bit32    statusDetail,
+                  smSenseData_t   *senseData,
+                  bit32    interruptContext
+                  );
+osGLOBAL void 
+tdsmEventCB(
+                smRoot_t          *smRoot,
+                smDeviceHandle_t  *smDeviceHandle,
+                smIntrEventType_t  eventType,
+                bit32              eventStatus,
+                void              *parm
+                );
+
+osGLOBAL FORCEINLINE void 
+tdsmSingleThreadedEnter(
+                        smRoot_t   *smRoot,
+                        bit32       syncLockId
+                       );
+
+osGLOBAL FORCEINLINE void 
+tdsmSingleThreadedLeave(
+                        smRoot_t   *smRoot,
+                        bit32       syncLockId
+                        );
+
+osGLOBAL FORCEINLINE bit8 
+tdsmBitScanForward(
+                  smRoot_t   *smRoot,
+                  bit32      *Index,
+                  bit32       Mask
+                  );
+
+#ifdef LINUX_VERSION_CODE
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmInterlockedIncrement(
+                   smRoot_t        *smRoot,
+                   sbit32 volatile *Addend
+                   );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmInterlockedDecrement(
+                   smRoot_t         *smRoot,
+                   sbit32 volatile  *Addend
+                   );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmAtomicBitClear(
+               smRoot_t         *smRoot,
+               sbit32 volatile  *Destination,
+               sbit32            Value
+               );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmAtomicBitSet(
+               smRoot_t         *smRoot,
+               sbit32 volatile  *Destination,
+               sbit32            Value
+               );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmAtomicExchange(
+               smRoot_t        *smRoot,
+               sbit32 volatile *Target,
+               sbit32           Value
+               );
+#else
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmInterlockedIncrement(
+                   smRoot_t        *smRoot,
+                   sbit32 volatile *Addend
+                   );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmInterlockedDecrement(
+                   smRoot_t        *smRoot,
+                   sbit32 volatile *Addend
+                   );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmInterlockedAnd(
+               smRoot_t         *smRoot,
+               sbit32 volatile  *Destination,
+               sbit32            Value
+               );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmInterlockedOr(
+               smRoot_t         *smRoot,
+               sbit32 volatile  *Destination,
+               sbit32            Value
+               );
+
+osGLOBAL FORCEINLINE sbit32 
+tdsmInterlockedExchange(
+               smRoot_t        *smRoot,
+               sbit32 volatile *Target,
+               sbit32           Value
+               );
+
+#endif /*LINUX_VERSION_CODE*/
+
+osGLOBAL bit32 
+tdsmAllocMemory(
+                smRoot_t    *smRoot,
+                void        **osMemHandle,
+                void        ** virtPtr, 
+                bit32       * physAddrUpper,
+                bit32       * physAddrLower,
+                bit32       alignment,
+                bit32       allocLength,
+                smBOOLEAN   isCacheable
+               );
+
+osGLOBAL bit32 
+tdsmFreeMemory(
+               smRoot_t    *smRoot,
+               void        *osDMAHandle,
+               bit32        allocLength
+              );
+
+osGLOBAL FORCEINLINE bit32
+tdsmRotateQnumber(smRoot_t        *smRoot,
+                         smDeviceHandle_t *smDeviceHandle
+                         );
+
+osGLOBAL bit32
+tdsmSetDeviceQueueDepth(smRoot_t      *smRoot,
+                                 smIORequest_t *smIORequest,
+                                 bit32          QueueDepth
+                                 );
+
+
+#ifndef tdsmLogDebugString 
+GLOBAL void tdsmLogDebugString(
+                         smRoot_t     *smRoot,
+                         bit32        level,
+                         char         *string,
+                         void         *ptr1,
+                         void         *ptr2,
+                         bit32        value1,
+                         bit32        value2
+                         );
+#endif
+
+  
+
+osGLOBAL bit32 tdsmGetTransportParam(
+                        smRoot_t    *smRoot,
+                        char        *key,
+                        char        *subkey1,
+                        char        *subkey2,
+                        char        *subkey3,
+                        char        *subkey4,
+                        char        *subkey5,
+                        char        *valueName,
+                        char        *buffer,
+                        bit32       bufferLen,
+                        bit32       *lenReceived
+                        );
+
+#endif  /* TDSMAPI_H */
+

sys/dev/pms/RefTisa/sat/src/smdefs.h

@@ -0,0 +1,851 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+#ifndef __SMDEFS_H__
+#define __SMDEFS_H__
+
+#include <dev/pms/RefTisa/tisa/sassata/common/ossa.h>
+
+/* the index for memory requirement, must be continious */
+#define SM_ROOT_MEM_INDEX                          0                       /**< the index of dm root memory */
+#define SM_DEVICE_MEM_INDEX                        1                       /**< the index of Device descriptors memory */
+#define SM_IO_MEM_INDEX                            2                       /**< the index of IO command descriptors memory */
+
+
+#define SM_MAX_DEV                              256
+#define SM_MAX_IO                               1024
+
+#define SM_USECS_PER_TICK                       1000000                   /**< defines the heart beat of the LL layer 10ms */
+
+enum sm_locks_e
+{
+  SM_TIMER_LOCK = 0,
+  SM_DEVICE_LOCK,
+  SM_INTERNAL_IO_LOCK,
+  SM_EXTERNAL_IO_LOCK,
+  SM_NCQ_TAG_LOCK,
+  SM_TBD_LOCK,
+  SM_MAX_LOCKS
+};
+
+/* ATA device type */
+#define SATA_ATA_DEVICE                           0x01                       /**< ATA ATA device type */
+#define SATA_ATAPI_DEVICE                         0x02                       /**< ATA ATAPI device type */
+#define SATA_PM_DEVICE                            0x03                       /**< ATA PM device type */
+#define SATA_SEMB_DEVICE                          0x04                       /**< ATA SEMB device type */
+#define SATA_SEMB_WO_SEP_DEVICE                   0x05                       /**< ATA SEMB without SEP device type */
+#define UNKNOWN_DEVICE                            0xFF
+
+/*
+ *  FIS type 
+ */
+#define PIO_SETUP_DEV_TO_HOST_FIS   0x5F
+#define REG_DEV_TO_HOST_FIS         0x34 
+#define SET_DEV_BITS_FIS            0xA1
+
+/* 
+ * ATA Command code 
+ */
+#define SAT_READ_FPDMA_QUEUED                 0x60
+#define SAT_READ_DMA_EXT                      0x25
+#define SAT_READ_DMA                          0xC8
+#define SAT_WRITE_FPDMA_QUEUED                0x61
+#define SAT_WRITE_DMA_EXT                     0x35
+#define SAT_WRITE_DMA_FUA_EXT                 0x3D
+#define SAT_WRITE_DMA                         0xCA
+#define SAT_CHECK_POWER_MODE                  0xE5
+#define SAT_READ_LOG_EXT                      0x2F
+#define SAT_READ_VERIFY_SECTORS               0x40
+#define SAT_READ_VERIFY_SECTORS_EXT           0x42
+#define SAT_SMART                             0xB0
+#define SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE   0xD4
+#define SAT_SMART_RETURN_STATUS               0xDA
+#define SAT_SMART_READ_LOG                    0xD5
+#define SAT_SMART_ENABLE_OPERATIONS           0xD8
+#define SAT_SMART_DISABLE_OPERATIONS          0xD9
+#define SAT_FLUSH_CACHE                       0xE7
+#define SAT_FLUSH_CACHE_EXT                   0xEA
+#define SAT_STANDBY                           0xE2
+#define SAT_MEDIA_EJECT                       0xED
+#define SAT_WRITE_SECTORS                     0x30
+#define SAT_WRITE_SECTORS_EXT                 0x34
+#define SAT_READ_SECTORS                      0x20
+#define SAT_READ_SECTORS_EXT                  0x24
+#define SAT_GET_MEDIA_STATUS                  0xDA
+#define SAT_SET_FEATURES                      0xEF
+#define SAT_IDENTIFY_DEVICE                   0xEC
+#define SAT_READ_BUFFER                       0xE4
+#define SAT_WRITE_BUFFER                      0xE8
+
+/* 
+ * ATAPI Command code 
+*/
+#define SAT_IDENTIFY_PACKET_DEVICE            0xA1
+#define SAT_PACKET                            0xA0
+#define SAT_DEVICE_RESET                      0x08
+#define SAT_EXECUTE_DEVICE_DIAGNOSTIC         0x90
+
+
+/* 
+ * ATA Status Register Mask 
+ */
+#define ERR_ATA_STATUS_MASK                   0x01    /* Error/check bit  */
+#define DRQ_ATA_STATUS_MASK                   0x08    /* Data Request bit */
+#define DF_ATA_STATUS_MASK                    0x20    /* Device Fault bit */
+#define DRDY_ATA_STATUS_MASK                  0x40    /* Device Ready bit */
+#define BSY_ATA_STATUS_MASK                   0x80    /* Busy bit         */
+
+/* 
+ * ATA Error Register Mask 
+ */
+#define NM_ATA_ERROR_MASK                     0x02    /* No media present bit         */
+#define ABRT_ATA_ERROR_MASK                   0x04    /* Command aborted bit          */
+#define MCR_ATA_ERROR_MASK                    0x08    /* Media change request bit     */
+#define IDNF_ATA_ERROR_MASK                   0x10    /* Address not found bit        */
+#define MC_ATA_ERROR_MASK                     0x20    /* Media has changed bit        */
+#define UNC_ATA_ERROR_MASK                    0x40    /* Uncorrectable data error bit */
+#define ICRC_ATA_ERROR_MASK                   0x80    /* Interface CRC error bit      */
+
+
+
+
+/*
+ *  transfer length and LBA limit 2^28 See identify device data word 61:60
+ *  ATA spec p125
+ *  7 zeros
+ */
+#define SAT_TR_LBA_LIMIT                      0x10000000
+
+/*
+ *  transfer length and LBA limit 2^48 See identify device data word 61:60
+ *  ATA spec p125
+ *  12 zeros
+ */
+#define SAT_EXT_TR_LBA_LIMIT                  0x1000000000000
+
+
+/*
+ * ATA command type. This is for setting LBA, Sector Count
+ */
+#define SAT_NON_EXT_TYPE                      0
+#define SAT_EXT_TYPE                          1
+#define SAT_FP_TYPE                           2
+
+
+/*
+ * Report LUNs response data.
+ */
+typedef struct smScsiReportLun_s
+{
+  bit8              len[4];
+  bit32             reserved;
+  tiLUN_t           lunList[1];
+} smScsiReportLun_t;
+
+/* Inquiry vendor string */
+#define AG_SAT_VENDOR_ID_STRING               "ATA     "
+
+/*
+ * Simple form of SATA Identify Device Data, similar definition is defined by
+ * LL Layer as agsaSATAIdentifyData_t.
+ */
+typedef struct satSimpleSATAIdentifyData_s
+{
+  bit16   word[256];
+} satSimpleSATAIdentifyData_t;
+
+
+/*
+ * READ LOG EXT page 10h
+ */
+typedef struct satReadLogExtPage10h_s
+{
+  bit8   byte[512];
+} satReadLogExtPage10h_t;
+
+/*
+ * READ LOG EXT Extended Self-test log
+ * ATA Table27 p196
+ */
+typedef struct satReadLogExtSelfTest_s
+{
+  bit8   byte[512];
+} satReadLogExtSelfTest_t;
+
+/*
+ * SMART READ LOG Self-test log 
+ * ATA Table60 p296
+ */
+typedef struct satSmartReadLogSelfTest_s
+{
+  bit8   byte[512];
+} satSmartReadLogSelfTest_t;
+
+
+/* 
+ * Flag definition for satIntFlag field in smSatInternalIo_t.
+ */
+
+/* Original NCQ I/O already completed, so at the completion of READ LOG EXT
+ *  page 10h, ignore the TAG tranaltion to get the failed I/O
+ */
+#define AG_SAT_INT_IO_FLAG_ORG_IO_COMPLETED   0x00000001
+
+#define INQUIRY_SUPPORTED_VPD_PAGE                          0x00
+#define INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE                 0x80
+#define INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE              0x83
+#define INQUIRY_ATA_INFORMATION_VPD_PAGE                    0x89
+#define INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE       0xB1
+
+#define MODESENSE_CONTROL_PAGE                            0x0A
+#define MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE          0x01
+#define MODESENSE_CACHING                                 0x08
+#define MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE      0x1C
+#define MODESENSE_RETURN_ALL_PAGES                        0x3F
+#define MODESENSE_VENDOR_SPECIFIC_PAGE                    0x00
+
+#define MODESELECT_CONTROL_PAGE                           0x0A
+#define MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE         0x01
+#define MODESELECT_CACHING                                0x08
+#define MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE     0x1C
+#define MODESELECT_RETURN_ALL_PAGES                       0x3F
+#define MODESELECT_VENDOR_SPECIFIC_PAGE                   0x00
+
+#define LOGSENSE_SUPPORTED_LOG_PAGES                      0x00
+#define LOGSENSE_SELFTEST_RESULTS_PAGE                    0x10
+#define LOGSENSE_INFORMATION_EXCEPTIONS_PAGE              0x2F
+
+
+/*
+ *  Bit mask definition
+ */
+#define SCSI_EVPD_MASK               0x01
+#define SCSI_IMMED_MASK              0x01
+#define SCSI_NACA_MASK               0x04
+#define SCSI_LINK_MASK               0x01
+#define SCSI_PF_MASK                 0x10
+#define SCSI_DEVOFFL_MASK            0x02
+#define SCSI_UNITOFFL_MASK           0x01
+#define SCSI_START_MASK              0x01
+#define SCSI_LOEJ_MASK               0x02
+#define SCSI_NM_MASK                 0x02
+#define SCSI_FLUSH_CACHE_IMMED_MASK              0x02
+#define SCSI_FUA_NV_MASK                         0x02
+#define SCSI_VERIFY_BYTCHK_MASK                  0x02
+#define SCSI_FORMAT_UNIT_IMMED_MASK              0x02
+#define SCSI_FORMAT_UNIT_FOV_MASK                0x80
+#define SCSI_FORMAT_UNIT_DCRT_MASK               0x20
+#define SCSI_FORMAT_UNIT_IP_MASK                 0x08
+#define SCSI_WRITE_SAME_LBDATA_MASK              0x02
+#define SCSI_WRITE_SAME_PBDATA_MASK              0x04
+#define SCSI_SYNC_CACHE_IMMED_MASK               0x02
+#define SCSI_WRITE_N_VERIFY_BYTCHK_MASK          0x02
+#define SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK       0x04
+#define SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK 0x07
+#define SCSI_FORMAT_UNIT_FMTDATA_MASK            0x10
+#define SCSI_FORMAT_UNIT_DCRT_MASK               0x20
+#define SCSI_FORMAT_UNIT_CMPLIST_MASK            0x08
+#define SCSI_FORMAT_UNIT_LONGLIST_MASK           0x20
+#define SCSI_READ10_FUA_MASK                     0x08
+#define SCSI_READ12_FUA_MASK                     0x08
+#define SCSI_READ16_FUA_MASK                     0x08
+#define SCSI_WRITE10_FUA_MASK                    0x08
+#define SCSI_WRITE12_FUA_MASK                    0x08
+#define SCSI_WRITE16_FUA_MASK                    0x08
+#define SCSI_READ_CAPACITY10_PMI_MASK            0x01
+#define SCSI_READ_CAPACITY16_PMI_MASK            0x01
+#define SCSI_MODE_SENSE6_PC_MASK                 0xC0
+#define SCSI_MODE_SENSE6_PAGE_CODE_MASK          0x3F
+#define SCSI_MODE_SENSE10_PC_MASK                0xC0
+#define SCSI_MODE_SENSE10_LLBAA_MASK             0x10
+#define SCSI_MODE_SENSE10_PAGE_CODE_MASK         0x3F
+#define SCSI_SEND_DIAGNOSTIC_TEST_CODE_MASK      0xE0
+#define SCSI_LOG_SENSE_PAGE_CODE_MASK            0x3F
+#define SCSI_MODE_SELECT6_PF_MASK                0x10
+#define SCSI_MODE_SELECT6_AWRE_MASK              0x80
+#define SCSI_MODE_SELECT6_RC_MASK                0x10
+#define SCSI_MODE_SELECT6_EER_MASK               0x08
+#define SCSI_MODE_SELECT6_PER_MASK               0x04
+#define SCSI_MODE_SELECT6_DTE_MASK               0x02
+#define SCSI_MODE_SELECT6_DCR_MASK               0x01
+#define SCSI_MODE_SELECT6_WCE_MASK               0x04
+#define SCSI_MODE_SELECT6_DRA_MASK               0x20
+#define SCSI_MODE_SELECT6_PERF_MASK              0x80
+#define SCSI_MODE_SELECT6_TEST_MASK              0x04
+#define SCSI_MODE_SELECT6_DEXCPT_MASK            0x08
+#define SCSI_MODE_SELECT10_PF_MASK               0x10
+#define SCSI_MODE_SELECT10_LONGLBA_MASK          0x01
+#define SCSI_MODE_SELECT10_AWRE_MASK             0x80
+#define SCSI_MODE_SELECT10_RC_MASK               0x10
+#define SCSI_MODE_SELECT10_EER_MASK              0x08
+#define SCSI_MODE_SELECT10_PER_MASK              0x04
+#define SCSI_MODE_SELECT10_DTE_MASK              0x02
+#define SCSI_MODE_SELECT10_DCR_MASK              0x01
+#define SCSI_MODE_SELECT10_WCE_MASK              0x04
+#define SCSI_MODE_SELECT10_DRA_MASK              0x20
+#define SCSI_MODE_SELECT10_PERF_MASK             0x80
+#define SCSI_MODE_SELECT10_TEST_MASK             0x04
+#define SCSI_MODE_SELECT10_DEXCPT_MASK           0x08
+#define SCSI_WRITE_N_VERIFY10_FUA_MASK           0x08
+#define SCSI_REQUEST_SENSE_DESC_MASK             0x01
+#define SCSI_READ_BUFFER_MODE_MASK               0x1F
+
+#define ATA_REMOVABLE_MEDIA_DEVICE_MASK          0x80
+#define SCSI_REASSIGN_BLOCKS_LONGLIST_MASK       0x01
+#define SCSI_REASSIGN_BLOCKS_LONGLBA_MASK        0x02
+
+
+#define SENSE_DATA_LENGTH                        0x12 /* 18 */    
+#define SELFTEST_RESULTS_LOG_PAGE_LENGTH         404
+#define INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH   11
+#define ZERO_MEDIA_SERIAL_NUMBER_LENGTH          8                  
+
+#define LOG_SENSE_0 0
+#define LOG_SENSE_1 1
+#define LOG_SENSE_2 2
+
+#define READ_BUFFER_DATA_MODE                    0x02
+#define READ_BUFFER_DESCRIPTOR_MODE              0x03
+#define READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN     0x04
+
+#define WRITE_BUFFER_DATA_MODE                   0x02
+#define WRITE_BUFFER_DL_MICROCODE_SAVE_MODE      0x05
+
+/* bit mask */
+#define BIT0_MASK                                0x01
+#define BIT1_MASK                                0x02
+#define BIT2_MASK                                0x04
+#define BIT3_MASK                                0x08
+#define BIT4_MASK                                0x10
+#define BIT5_MASK                                0x20
+#define BIT6_MASK                                0x40
+#define BIT7_MASK                                0x80
+
+#define MODE_SENSE6_RETURN_ALL_PAGES_LEN         68
+#define MODE_SENSE6_CONTROL_PAGE_LEN             24
+#define MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24
+#define MODE_SENSE6_CACHING_LEN                  32
+#define MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24
+
+
+#define MODE_SENSE10_RETURN_ALL_PAGES_LEN         68 + 4
+#define MODE_SENSE10_CONTROL_PAGE_LEN             24 + 4
+#define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 + 4
+#define MODE_SENSE10_CACHING_LEN                  32 + 4
+#define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 + 4
+
+#define MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN         68 + 4 + 8
+#define MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN             24 + 4 + 8
+#define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN 24 + 4 + 8
+#define MODE_SENSE10_CACHING_LLBAA_LEN                  32 + 4 + 8
+#define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8
+
+/*****************************************************************************
+** SCSI SENSE KEY VALUES
+*****************************************************************************/
+
+#define SCSI_SNSKEY_NO_SENSE           0x00
+#define SCSI_SNSKEY_RECOVERED_ERROR    0x01
+#define SCSI_SNSKEY_NOT_READY          0x02
+#define SCSI_SNSKEY_MEDIUM_ERROR       0x03
+#define SCSI_SNSKEY_HARDWARE_ERROR     0x04
+#define SCSI_SNSKEY_ILLEGAL_REQUEST    0x05
+#define SCSI_SNSKEY_UNIT_ATTENTION     0x06
+#define SCSI_SNSKEY_DATA_PROTECT       0x07
+#define SCSI_SNSKEY_ABORTED_COMMAND    0x0B
+#define SCSI_SNSKEY_MISCOMPARE         0x0E
+
+/*****************************************************************************
+** SCSI Additional Sense Codes and Qualifiers combo two-bytes
+*****************************************************************************/
+
+#define SCSI_SNSCODE_NO_ADDITIONAL_INFO                         0x0000
+#define SCSI_SNSCODE_LUN_CRC_ERROR_DETECTED                     0x0803
+#define SCSI_SNSCODE_INVALID_COMMAND                            0x2000
+#define SCSI_SNSCODE_LOGICAL_BLOCK_OUT                          0x2100
+#define SCSI_SNSCODE_INVALID_FIELD_IN_CDB                       0x2400
+#define SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED                      0x2500
+#define SCSI_SNSCODE_POWERON_RESET                              0x2900
+#define SCSI_SNSCODE_EVERLAPPED_CMDS                            0x4e00
+#define SCSI_SNSCODE_INTERNAL_TARGET_FAILURE                    0x4400
+#define SCSI_SNSCODE_MEDIUM_NOT_PRESENT                         0x3a00
+#define SCSI_SNSCODE_UNRECOVERED_READ_ERROR                     0x1100
+#define SCSI_SNSCODE_RECORD_NOT_FOUND                           0x1401
+#define SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE                  0x2800
+#define SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST            0x5a01
+#define SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR                 0x4703
+#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS  0x0404
+#define SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE                 0x5d10
+#define SCSI_SNSCODE_LOW_POWER_CONDITION_ON                     0x5e00
+#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INIT_REQUIRED       0x0402
+#define SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST               0x2600
+#define SCSI_SNSCODE_ATA_DEVICE_FAILED_SET_FEATURES             0x4471
+#define SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED             0x670B
+#define SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST              0x3E03
+#define SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR                     0x2C00
+#define SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE         0x2100
+#define SCSI_SNSCODE_LOGICAL_UNIT_FAILURE                       0x3E01
+#define SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED                 0x5300
+#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED 0x0402
+#define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE          0x0400
+#define SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION           0x0500
+#define SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN         0x4000
+#define SCSI_SNSCODE_COMMANDS_CLEARED_BY_ANOTHER_INITIATOR      0x2F00
+#define SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED       0x0C02
+#define SCSI_SNSCODE_ATA_PASS_THROUGH_INFORMATION_AVAILABLE     0x001D
+
+/*****************************************************************************
+** SCSI Additional Sense Codes and Qualifiers saparate bytes
+*****************************************************************************/
+
+#define SCSI_ASC_NOTREADY_INIT_CMD_REQ    0x04
+#define SCSI_ASCQ_NOTREADY_INIT_CMD_REQ   0x02
+
+
+/*****************************************************************************
+** Inquiry command fields and response sizes
+*****************************************************************************/
+#define SCSIOP_INQUIRY_CMDDT        0x02
+#define SCSIOP_INQUIRY_EVPD         0x01
+#define STANDARD_INQUIRY_SIZE       36
+#define SATA_PAGE83_INQUIRY_WWN_SIZE       16      /* SAT, revision8, Table81, p78, 12 + 4 */
+#define SATA_PAGE83_INQUIRY_NO_WWN_SIZE    76      /* SAT, revision8, Table81, p78, 72 + 4 */
+#define SATA_PAGE89_INQUIRY_SIZE    572     /* SAT, revision8, Table87, p84 */
+#define SATA_PAGE0_INQUIRY_SIZE     9       /* SPC-4, 7.6.9   Table331, p345 */
+#define SATA_PAGE80_INQUIRY_SIZE    24     /* SAT, revision8, Table79, p77 */
+#define SATA_PAGEB1_INQUIRY_SIZE    64     /* SBC-3, revision31, Table193, p273 */
+
+/*****************************************************************************
+** SCSI Operation Codes (first byte in CDB)
+*****************************************************************************/
+
+
+#define SCSIOPC_TEST_UNIT_READY     0x00
+#define SCSIOPC_INQUIRY             0x12
+#define SCSIOPC_MODE_SENSE_6        0x1A
+#define SCSIOPC_MODE_SENSE_10       0x5A
+#define SCSIOPC_MODE_SELECT_6       0x15
+#define SCSIOPC_START_STOP_UNIT     0x1B
+#define SCSIOPC_READ_CAPACITY_10    0x25
+#define SCSIOPC_READ_CAPACITY_16    0x9E
+#define SCSIOPC_READ_6              0x08
+#define SCSIOPC_READ_10             0x28
+#define SCSIOPC_READ_12             0xA8
+#define SCSIOPC_READ_16             0x88
+#define SCSIOPC_WRITE_6             0x0A 
+#define SCSIOPC_WRITE_10            0x2A
+#define SCSIOPC_WRITE_12            0xAA
+#define SCSIOPC_WRITE_16            0x8A
+#define SCSIOPC_WRITE_VERIFY        0x2E
+#define SCSIOPC_VERIFY_10           0x2F
+#define SCSIOPC_VERIFY_12           0xAF
+#define SCSIOPC_VERIFY_16           0x8F
+#define SCSIOPC_REQUEST_SENSE       0x03
+#define SCSIOPC_REPORT_LUN          0xA0
+#define SCSIOPC_FORMAT_UNIT         0x04
+#define SCSIOPC_SEND_DIAGNOSTIC     0x1D
+#define SCSIOPC_WRITE_SAME_10       0x41
+#define SCSIOPC_WRITE_SAME_16       0x93
+#define SCSIOPC_READ_BUFFER         0x3C
+#define SCSIOPC_WRITE_BUFFER        0x3B
+
+#define SCSIOPC_LOG_SENSE           0x4D
+#define SCSIOPC_LOG_SELECT          0x4C
+#define SCSIOPC_MODE_SELECT_6       0x15
+#define SCSIOPC_MODE_SELECT_10      0x55
+#define SCSIOPC_SYNCHRONIZE_CACHE_10 0x35
+#define SCSIOPC_SYNCHRONIZE_CACHE_16 0x91
+#define SCSIOPC_WRITE_AND_VERIFY_10 0x2E
+#define SCSIOPC_WRITE_AND_VERIFY_12 0xAE
+#define SCSIOPC_WRITE_AND_VERIFY_16 0x8E
+#define SCSIOPC_READ_MEDIA_SERIAL_NUMBER 0xAB
+#define SCSIOPC_REASSIGN_BLOCKS     0x07
+
+#define SCSIOPC_GET_CONFIG          0x46
+#define SCSIOPC_GET_EVENT_STATUS_NOTIFICATION        0x4a
+#define SCSIOPC_REPORT_KEY          0xA4
+#define SCSIOPC_SEND_KEY            0xA3
+#define SCSIOPC_READ_DVD_STRUCTURE  0xAD
+#define SCSIOPC_TOC                 0x43
+#define SCSIOPC_PREVENT_ALLOW_MEDIUM_REMOVAL         0x1E
+#define SCSIOPC_READ_VERIFY         0x42
+#define SCSIOPC_ATA_PASS_THROUGH12	0xA1
+#define SCSIOPC_ATA_PASS_THROUGH16	0x85
+
+
+/*! \def MIN(a,b)
+* \brief MIN macro
+*
+* use to find MIN of two values
+*/
+#ifndef MIN
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#endif
+
+/*! \def MAX(a,b)
+* \brief MAX macro
+*
+* use to find MAX of two values
+*/
+#ifndef MAX
+#define MAX(a,b) ((a) < (b) ? (b) : (a))
+#endif
+
+/* for debugging print */
+#if defined(SM_DEBUG)
+  
+/*
+* for debugging purposes.  
+*/
+extern bit32 gSMDebugLevel;
+
+#define SM_DBG0(format) tdsmLogDebugString(gSMDebugLevel, 0, format)
+#define SM_DBG1(format) tdsmLogDebugString(gSMDebugLevel, 1, format)
+#define SM_DBG2(format) tdsmLogDebugString(gSMDebugLevel, 2, format)
+#define SM_DBG3(format) tdsmLogDebugString(gSMDebugLevel, 3, format)
+#define SM_DBG4(format) tdsmLogDebugString(gSMDebugLevel, 4, format)
+#define SM_DBG5(format) tdsmLogDebugString(gSMDebugLevel, 5, format)
+#define SM_DBG6(format) tdsmLogDebugString(gSMDebugLevel, 6, format)
+
+#else
+
+#define SM_DBG0(format)
+#define SM_DBG1(format)
+#define SM_DBG2(format)
+#define SM_DBG3(format)
+#define SM_DBG4(format)
+#define SM_DBG5(format)
+#define SM_DBG6(format)
+
+#endif /* SM_DEBUG */
+
+//#define SM_ASSERT OS_ASSERT
+//#define tdsmLogDebugString TIDEBUG_MSG
+
+/*
+ * SAT specific structure per SATA drive 
+ */
+#define SAT_NONNCQ_MAX  1
+#define SAT_NCQ_MAX     32
+#define SAT_MAX_INT_IO  16
+#define SAT_APAPI_CMDQ_MAX 2
+
+/* Device state */
+#define SAT_DEV_STATE_NORMAL                  0  /* Normal */
+#define SAT_DEV_STATE_IN_RECOVERY             1  /* SAT in recovery mode */
+#define SAT_DEV_STATE_FORMAT_IN_PROGRESS      2  /* Format unit in progress */
+#define SAT_DEV_STATE_SMART_THRESHOLD         3  /* SMART Threshold Exceeded Condition*/
+#define SAT_DEV_STATE_LOW_POWER               4  /* Low Power State*/
+
+#ifndef agNULL
+#define agNULL     ((void *)0)
+#endif
+
+#define SM_SET_ESGL_EXTEND(val) \
+ ((val) = (val) | 0x80000000)
+
+#define SM_CLEAR_ESGL_EXTEND(val) \
+ ((val) = (val) & 0x7FFFFFFF)
+
+#ifndef OPEN_RETRY_RETRIES
+#define OPEN_RETRY_RETRIES	10
+#endif
+
+/*********************************************************************
+* CPU buffer access macro                                            *
+*                                                                    *
+*/
+
+#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD)              \
+        (bitptr)&(((STRUCT_TYPE *)0)->FEILD)
+        
+
+#if defined(SA_CPU_LITTLE_ENDIAN)
+
+#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16)     \
+        (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
+
+#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32)     \
+        (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
+
+#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET)       \
+        (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
+    
+#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET)       \
+        (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
+
+#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16)     \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))))   = (bit8)((((bit16)VALUE16)>>8)&0xFF);  \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
+     
+#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32)     \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))))   = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF);  \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
+
+#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET)       \
+        (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))));   \
+        (*(bit8 *)(((bit8 *)ADDR16)))   = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
+
+#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET)       \
+        (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))));   \
+        (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
+        (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
+        (*(bit8 *)(((bit8 *)ADDR32)))   = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
+
+#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN)                        \
+        si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
+
+
+#elif defined(SA_CPU_BIG_ENDIAN)
+
+#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16)     \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF);   \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))))   = (bit8)(((bit16)VALUE16)&0xFF);
+
+#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32)     \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF);  \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF);  \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF);   \
+        (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))))   = (bit8)(((bit32)VALUE32)&0xFF);
+
+#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET)       \
+        (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))));   \
+        (*(bit8 *)(((bit8 *)ADDR16)))   = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
+
+#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET)       \
+        (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET))));   \
+        (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
+        (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
+        (*((bit8 *)(((bit8 *)ADDR32))))   = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
+
+#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16)         \
+        (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
+
+#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32)         \
+        (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
+
+#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET)           \
+        (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
+
+#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET)           \
+        (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
+
+#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN)    \
+        si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
+
+#else
+
+#error (Host CPU endianess undefined!!)
+
+#endif
+
+
+#if defined(SA_CPU_LITTLE_ENDIAN)
+
+#ifndef LEBIT16_TO_BIT16
+#define LEBIT16_TO_BIT16(_x)   (_x)
+#endif
+
+#ifndef BIT16_TO_LEBIT16
+#define BIT16_TO_LEBIT16(_x)   (_x)
+#endif
+
+#ifndef BIT16_TO_BEBIT16
+#define BIT16_TO_BEBIT16(_x)   AGSA_FLIP_2_BYTES(_x)
+#endif
+
+#ifndef BEBIT16_TO_BIT16
+#define BEBIT16_TO_BIT16(_x)   AGSA_FLIP_2_BYTES(_x)
+#endif
+
+#ifndef LEBIT32_TO_BIT32
+#define LEBIT32_TO_BIT32(_x)   (_x)
+#endif
+
+#ifndef BIT32_TO_LEBIT32
+#define BIT32_TO_LEBIT32(_x)   (_x)
+#endif
+
+
+#ifndef BEBIT32_TO_BIT32
+#define BEBIT32_TO_BIT32(_x)   AGSA_FLIP_4_BYTES(_x)
+#endif
+
+#ifndef BIT32_TO_BEBIT32
+#define BIT32_TO_BEBIT32(_x)   AGSA_FLIP_4_BYTES(_x)
+#endif
+
+#elif defined(SA_CPU_BIG_ENDIAN)
+
+#ifndef LEBIT16_TO_BIT16
+#define LEBIT16_TO_BIT16(_x)   AGSA_FLIP_2_BYTES(_x)
+#endif
+
+#ifndef BIT16_TO_LEBIT16
+#define BIT16_TO_LEBIT16(_x)   AGSA_FLIP_2_BYTES(_x)
+#endif
+
+#ifndef BIT16_TO_BEBIT16
+#define BIT16_TO_BEBIT16(_x)   (_x)
+#endif
+
+#ifndef BEBIT16_TO_BIT16
+#define BEBIT16_TO_BIT16(_x)   (_x)
+#endif
+
+#ifndef LEBIT32_TO_BIT32
+#define LEBIT32_TO_BIT32(_x)   AGSA_FLIP_4_BYTES(_x)
+#endif
+
+#ifndef BIT32_TO_LEBIT32
+#define BIT32_TO_LEBIT32(_x)   AGSA_FLIP_4_BYTES(_x)
+#endif
+
+#ifndef BEBIT32_TO_BIT32
+#define BEBIT32_TO_BIT32(_x)   (_x)
+#endif
+
+#ifndef BIT32_TO_BEBIT32
+#define BIT32_TO_BEBIT32(_x)   (_x)
+#endif
+
+#else  
+
+#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN
+
+#endif 
+
+
+/* 
+ * Task Management task used in tiINITaskManagement()
+ *
+ * 1 SM_ABORT TASK - aborts the task identified by the Referenced  Task Tag field.
+ * 2 SM_ABORT TASK SET - aborts all Tasks issued by this initiator on the Logical Unit 
+ * 3 SM_CLEAR ACA - clears the Auto Contingent Allegiance condition.
+ * 4 SM_CLEAR TASK SET - Aborts all Tasks (from all initiators) for the Logical Unit.
+ * 5 SM_LOGICAL UNIT RESET 
+ * 6 SM_TARGET WARM RESET  - iSCSI only
+ * 7 SM_TARGET_COLD_RESET  - iSCSI only
+ * 8 SM_TASK_REASSIGN      - iSCSI only
+ * 9 SM_QUERY_TASK         - SAS only
+ */
+
+#define SM_ABORT_TASK          1
+#define SM_ABORT_TASK_SET      2
+#define SM_CLEAR_ACA           3
+#define SM_CLEAR_TASK_SET      4
+#define SM_LOGICAL_UNIT_RESET  5
+#define SM_TARGET_WARM_RESET   6    /* iSCSI only */
+#define SM_TARGET_COLD_RESET   7    /* iSCSI only */
+#define SM_TASK_REASSIGN       8    /* iSCSI only */
+#define SM_QUERY_TASK          9    /* SAS only   */
+
+/* SMP PHY CONTROL OPERATION */
+#define SMP_PHY_CONTROL_NOP                        0x00
+#define SMP_PHY_CONTROL_LINK_RESET                 0x01
+#define SMP_PHY_CONTROL_HARD_RESET                 0x02
+#define SMP_PHY_CONTROL_DISABLE                    0x03
+#define SMP_PHY_CONTROL_CLEAR_ERROR_LOG            0x05
+#define SMP_PHY_CONTROL_CLEAR_AFFILIATION          0x06
+#define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL        0x07
+
+/****************************************************************
+ *            Phy Control request
+ ****************************************************************/
+typedef struct smpReqPhyControl_s
+{
+  bit8   reserved1[4];
+  bit8   reserved2;
+  bit8   phyIdentifier;
+  bit8   phyOperation;
+  bit8   updatePartialPathwayTOValue;
+    /* b7-1 : reserved */
+    /* b0   : update partial pathway timeout value */
+  bit8   reserved3[20];
+  bit8   programmedMinPhysicalLinkRate;
+    /* b7-4 : programmed Minimum Physical Link Rate*/
+    /* b3-0 : reserved */
+  bit8   programmedMaxPhysicalLinkRate;
+    /* b7-4 : programmed Maximum Physical Link Rate*/
+    /* b3-0 : reserved */
+  bit8   reserved4[2];
+  bit8   partialPathwayTOValue;
+    /* b7-4 : reserved */
+    /* b3-0 : partial Pathway TO Value */
+  bit8   reserved5[3];
+} smpReqPhyControl_t;
+
+
+typedef struct smSMPFrameHeader_s
+{
+    bit8   smpFrameType;      /* The first byte of SMP frame represents the SMP FRAME TYPE */ 
+    bit8   smpFunction;       /* The second byte of the SMP frame represents the SMP FUNCTION */
+    bit8   smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */
+    bit8   smpReserved;       /* reserved */
+} smSMPFrameHeader_t;
+
+/* SMP direct payload size limit: IOMB direct payload size = 48 */
+#define SMP_DIRECT_PAYLOAD_LIMIT 44
+
+#define SMP_REQUEST        0x40
+#define SMP_RESPONSE       0x41
+
+#define SMP_PHY_CONTROL                            0x91
+
+/* SMP function results */
+#define SMP_FUNCTION_ACCEPTED                      0x00
+
+/* bit8 array[4] -> bit32 */
+#define SM_GET_SAS_ADDRESSLO(sasAddressLo)                  \
+    DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo)
+
+#define SM_GET_SAS_ADDRESSHI(sasAddressHi)                  \
+    DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi)
+
+/* SATA sector size 512 bytes = 0x200 bytes */
+#define SATA_SECTOR_SIZE                          0x200
+/* TL limit in sector */
+/* for SAT_READ/WRITE_DMA and SAT_READ/WRITE_SECTORS ATA command */
+#define NON_BIT48_ADDRESS_TL_LIMIT                0x100
+/* for SAT_READ/WRITE_DMA_EXT and SAT_READ/WRITE_SECTORS_EXT and  SAT_READ/WRITE_FPDMA_QUEUEDATA command */
+#define BIT48_ADDRESS_TL_LIMIT                    0xFFFF
+
+#define VEN_DEV_SPC                               0x800111f8
+#define VEN_DEV_SPCv                              0x800811f8
+#define VEN_DEV_SPCve                             0x800911f8
+#define VEN_DEV_SPCvplus                          0x801811f8
+#define VEN_DEV_SPCveplus                         0x801911f8
+
+#define SMIsSPC(agr) (VEN_DEV_SPC  == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPC */
+#define SMIsSPCv(agr)  (VEN_DEV_SPCv == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv */
+#define SMIsSPCve(agr) (VEN_DEV_SPCve  == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve */
+#define SMIsSPCvplus(agr)  (VEN_DEV_SPCvplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv+ */
+#define SMIsSPCveplus(agr)  (VEN_DEV_SPCveplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve+ */
+
+#define DEFAULT_KEY_BUFFER_SIZE     64
+
+
+#endif /* __SMDEFS_H__ */
+

sys/dev/pms/RefTisa/sat/src/sminit.c

@@ -0,0 +1,503 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+
+#include <dev/pms/RefTisa/sat/src/smdefs.h>
+#include <dev/pms/RefTisa/sat/src/smproto.h>
+#include <dev/pms/RefTisa/sat/src/smtypes.h>
+
+#ifdef SM_DEBUG
+bit32 gSMDebugLevel = 1;
+#endif
+smRoot_t *gsmRoot = agNULL;
+
+/* start smapi defined APIS */
+osGLOBAL void
+smGetRequirements(
+                  smRoot_t 	  		*smRoot,
+                  smSwConfig_t			*swConfig,
+                  smMemoryRequirement_t		*memoryRequirement,
+                  bit32                         *usecsPerTick,
+                  bit32				*maxNumLocks
+                 )
+{
+  bit32               memoryReqCount = 0;
+  bit32               i; 
+  bit32               max_dev = SM_MAX_DEV; 
+  char                *buffer;
+  bit32               buffLen;
+  bit32               lenRecv = 0;
+  static char         tmpBuffer[DEFAULT_KEY_BUFFER_SIZE];
+  char                *pLastUsedChar = agNULL;
+  char                globalStr[]     = "Global";
+  char                iniParmsStr[]   = "InitiatorParms";
+  SM_DBG2(("smGetRequirements: start\n"));  
+  
+  /* sanity check */
+  SM_ASSERT((agNULL != swConfig), "");
+  SM_ASSERT((agNULL != memoryRequirement), "");
+  SM_ASSERT((agNULL != usecsPerTick), "");
+  SM_ASSERT((agNULL != maxNumLocks), ""); 
+  
+  /* memory requirement for smRoot, CACHE memory */
+  memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].singleElementLength = sizeof(smIntRoot_t);
+  memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].numElements = 1;
+  memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].totalLength = 
+      (memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].singleElementLength) * (memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].numElements);
+  memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].alignment = 4;
+  memoryRequirement->smMemory[SM_ROOT_MEM_INDEX].type = SM_CACHED_MEM;
+  memoryReqCount++;
+  
+  /* reading the configurable parameter of MaxTargets */
+  buffer = tmpBuffer;
+  buffLen = sizeof(tmpBuffer);
+  sm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  if ((tdsmGetTransportParam(
+                             smRoot, 
+                             globalStr,
+                             iniParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "MaxTargets",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == SM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      max_dev = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      max_dev = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+  }
+  SM_DBG3(("smGetRequirements: max_expander %d\n", max_dev));
+  /* memory requirement for Device Links, CACHE memory */
+  memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].singleElementLength = sizeof(smDeviceData_t);
+  memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].numElements = max_dev; 
+  memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].totalLength = 
+      (memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].singleElementLength) * (memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].numElements);
+  memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].alignment = 4;
+  memoryRequirement->smMemory[SM_DEVICE_MEM_INDEX].type = SM_CACHED_MEM;
+  memoryReqCount++;
+  
+  /* memory requirement for IO inks, CACHE memory */
+  memoryRequirement->smMemory[SM_IO_MEM_INDEX].singleElementLength = sizeof(smIORequestBody_t);
+  memoryRequirement->smMemory[SM_IO_MEM_INDEX].numElements = SM_MAX_IO; 
+  memoryRequirement->smMemory[SM_IO_MEM_INDEX].totalLength = 
+      (memoryRequirement->smMemory[SM_IO_MEM_INDEX].singleElementLength) * (memoryRequirement->smMemory[SM_IO_MEM_INDEX].numElements);
+  memoryRequirement->smMemory[SM_IO_MEM_INDEX].alignment = 4;
+  memoryRequirement->smMemory[SM_IO_MEM_INDEX].type = SM_CACHED_MEM;
+  memoryReqCount++;
+  
+  /* for debugging */
+  for (i=0;i< memoryReqCount;i++)
+  {
+    SM_DBG3(("smGetRequirements: index %d numElements %d totalLength %d singleElementLength %d alignment %d\n", i
+    , memoryRequirement->smMemory[i].numElements, memoryRequirement->smMemory[i].totalLength, 
+    memoryRequirement->smMemory[i].singleElementLength,memoryRequirement->smMemory[i].alignment ));
+  }
+  /* set up memory requirement count */
+  memoryRequirement->count = memoryReqCount;
+  
+  /* requirement for locks */
+  *maxNumLocks = SM_MAX_LOCKS;   
+
+  /* setup the time tick */  
+  *usecsPerTick = SM_USECS_PER_TICK;
+
+  /* set up the number of active IOs */
+  swConfig->maxActiveIOs = SM_MAX_IO;
+  
+  /* set up the number of device handles */
+  swConfig->numDevHandles = SM_MAX_DEV;
+  
+  
+  return;
+}		
+
+osGLOBAL bit32
+smInitialize(
+             smRoot_t				*smRoot,
+             agsaRoot_t                         *agRoot,
+             smMemoryRequirement_t		*memoryAllocated,
+             smSwConfig_t			*swConfig,
+             bit32				usecsPerTick 
+            )
+{
+  smIntRoot_t               *smIntRoot;
+  smDeviceData_t            *smDevice;  
+  smIORequestBody_t         *smIORequest; 
+  smIntContext_t            *smAllShared;
+  bit32                     i;
+  bit32                     max_dev = SM_MAX_DEV; 
+  char                      *buffer;
+  bit32                     buffLen;
+  bit32                     lenRecv = 0;
+  static char               tmpBuffer[DEFAULT_KEY_BUFFER_SIZE];
+  char                      *pLastUsedChar = agNULL;
+  char                      globalStr[]     = "Global";
+  char                      iniParmsStr[]   = "InitiatorParms";
+  
+  SM_DBG2(("smInitialize: start\n"));  
+  
+  /* sanity check */  
+  SM_ASSERT((agNULL != smRoot), "");
+  SM_ASSERT((agNULL != agRoot), "");
+  SM_ASSERT((agNULL != memoryAllocated), "");
+  SM_ASSERT((agNULL != swConfig), "");
+  SM_ASSERT((SM_ROOT_MEM_INDEX < memoryAllocated->count), "");
+  SM_ASSERT((SM_DEVICE_MEM_INDEX < memoryAllocated->count), "");
+  SM_ASSERT((SM_IO_MEM_INDEX < memoryAllocated->count), "");
+  
+  /* Check the memory allocated */
+  for ( i = 0; i < memoryAllocated->count; i ++ )
+  {
+    /* If memory allocatation failed  */
+    if (memoryAllocated->smMemory[i].singleElementLength &&
+        memoryAllocated->smMemory[i].numElements)
+    {
+      if ( (0 != memoryAllocated->smMemory[i].numElements)
+          && (0 == memoryAllocated->smMemory[i].totalLength) )
+      {
+        /* return failure */
+        SM_DBG1(("smInitialize: Memory[%d]  singleElementLength = 0x%x  numElements = 0x%x NOT allocated!!!\n",
+          i,
+          memoryAllocated->smMemory[i].singleElementLength,
+          memoryAllocated->smMemory[i].numElements));
+        return SM_RC_FAILURE;
+      }
+    }
+  }
+  
+  /* for debugging */
+  for ( i = 0; i < memoryAllocated->count; i ++ )
+  {
+    SM_DBG3(("smInitialize: index %d virtPtr %p osHandle%p\n",i, memoryAllocated->smMemory[i].virtPtr, memoryAllocated->smMemory[i].osHandle)); 
+    SM_DBG3(("smInitialize: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d numElements %d\n", i, 
+    memoryAllocated->smMemory[i].physAddrUpper, 
+    memoryAllocated->smMemory[i].physAddrLower, 
+    memoryAllocated->smMemory[i].totalLength, 
+    memoryAllocated->smMemory[i].numElements));
+    SM_DBG3(("smInitialize: index %d singleElementLength 0x%x alignment 0x%x type %d reserved %d\n", i, 
+    memoryAllocated->smMemory[i].singleElementLength, 
+    memoryAllocated->smMemory[i].alignment, 
+    memoryAllocated->smMemory[i].type, 
+    memoryAllocated->smMemory[i].reserved));
+  }  
+  
+  /* SM's internal root */
+  smIntRoot  = (smIntRoot_t *) (memoryAllocated->smMemory[SM_ROOT_MEM_INDEX].virtPtr);
+  smRoot->smData = (void *) smIntRoot;
+  
+  smAllShared = (smIntContext_t *)&(smIntRoot->smAllShared);
+  /**<  Initialize the TDM data part of the interrupt context */
+  smAllShared->smRootOsData.smRoot     = smRoot;
+  smAllShared->smRootOsData.smAllShared   = (void *) smAllShared;
+  gsmRoot = smRoot; 
+  smAllShared->FCA = agTRUE;
+  
+  /* Devices */
+  smDevice = (smDeviceData_t *) (memoryAllocated->smMemory[SM_DEVICE_MEM_INDEX].virtPtr);
+  smAllShared->DeviceMem = (smDeviceData_t *)smDevice;
+  
+  /* IOs */
+  smIORequest = (smIORequestBody_t *) (memoryAllocated->smMemory[SM_IO_MEM_INDEX].virtPtr);
+  smAllShared->IOMem = (smIORequestBody_t *)smIORequest;
+  
+  smAllShared->agRoot = agRoot;
+  
+  smAllShared->usecsPerTick = usecsPerTick;	   
+  
+  /**< initializes timers */
+  smInitTimers(smRoot);
+  
+  /**< initializes devices */
+  buffer = tmpBuffer;
+  buffLen = sizeof(tmpBuffer);
+  sm_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+  if ((tdsmGetTransportParam(
+                             smRoot, 
+                             globalStr,
+                             iniParmsStr,
+                             agNULL,
+                             agNULL,
+                             agNULL, 
+                             agNULL, 
+                             "MaxTargets",
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == SM_RC_SUCCESS) && (lenRecv != 0))
+  {
+    if (osti_strncmp(buffer, "0x", 2) == 0)
+    { 
+      max_dev = osti_strtoul (buffer, &pLastUsedChar, 0);
+    }
+    else
+    {
+      max_dev = osti_strtoul (buffer, &pLastUsedChar, 10);
+    }
+   SM_DBG1(("smInitialize: MaxTargets %d\n", max_dev));
+ }  
+
+  smDeviceDataInit(smRoot, max_dev);
+  
+  /**< initializes IOs */
+  smIOInit(smRoot);
+
+#ifdef SM_DEBUG
+  gSMDebugLevel = swConfig->SMDebugLevel;
+#endif    
+  
+  return SM_RC_SUCCESS;
+}		
+
+osGLOBAL void
+smInitTimers(
+             smRoot_t *smRoot 
+            )
+{
+  smIntRoot_t               *smIntRoot    = (smIntRoot_t *)smRoot->smData;
+  smIntContext_t            *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared;
+  
+  SM_DBG2(("smInitTimers: start\n"));  
+  
+  /* initialize the timerlist */
+  SMLIST_INIT_HDR(&(smAllShared->timerlist));
+
+  return;
+}
+
+osGLOBAL void
+smDeviceDataReInit(
+                   smRoot_t		  *smRoot,
+                   smDeviceData_t         *oneDeviceData		     
+                  )
+{
+  int               j=0;
+  smSatInternalIo_t   *satIntIO;
+  
+  SM_DBG2(("smDeviceDataReInit: start \n"));
+  
+  if (oneDeviceData->satPendingIO != 0)
+  {
+    SM_DBG1(("smDeviceDataReInit: did %d\n", oneDeviceData->id));
+    SM_DBG1(("smDeviceDataReInit: satPendingIO %d satNCQMaxIO %d!!!\n", oneDeviceData->satPendingIO, oneDeviceData->satNCQMaxIO ));
+    SM_DBG1(("smDeviceDataReInit: satPendingNCQIO %d satPendingNONNCQIO %d!!!\n", oneDeviceData->satPendingNCQIO, oneDeviceData->satPendingNONNCQIO));
+  }
+
+//  oneDeviceData->smRoot = agNULL;
+  oneDeviceData->agDevHandle = agNULL;
+  oneDeviceData->valid = agFALSE;
+  oneDeviceData->SMAbortAll = agFALSE;
+  oneDeviceData->smDevHandle = agNULL;
+  oneDeviceData->directlyAttached = agFALSE;
+  oneDeviceData->agExpDevHandle = agNULL;
+  oneDeviceData->phyID = 0xFF;
+  oneDeviceData->SMNumOfFCA = 0;
+  
+  /* default */
+  oneDeviceData->satDriveState = SAT_DEV_STATE_NORMAL;
+  oneDeviceData->satNCQMaxIO =SAT_NCQ_MAX;
+  oneDeviceData->satPendingIO = 0;
+  oneDeviceData->satPendingNCQIO = 0;
+  oneDeviceData->satPendingNONNCQIO = 0;
+  oneDeviceData->IDDeviceValid = agFALSE;
+  oneDeviceData->freeSATAFDMATagBitmap = 0;
+  oneDeviceData->NumOfFCA = 0;
+  oneDeviceData->NumOfIDRetries = 0;
+  oneDeviceData->ID_Retries = 0;
+  oneDeviceData->OSAbortAll = agFALSE;
+    
+  sm_memset(oneDeviceData->satMaxLBA, 0, sizeof(oneDeviceData->satMaxLBA));
+  sm_memset(&(oneDeviceData->satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t));
+
+  oneDeviceData->satSaDeviceData = oneDeviceData;
+    
+  satIntIO = (smSatInternalIo_t *)&(oneDeviceData->satIntIo[0]);
+  for (j = 0; j < SAT_MAX_INT_IO; j++)
+  {
+    SM_DBG2(("tdsaDeviceDataReInit: in loop of internal io free, id %d\n", satIntIO->id));
+    smsatFreeIntIoResource(smRoot, oneDeviceData, satIntIO);    
+    satIntIO = satIntIO + 1;    
+  }
+  
+  return;
+}	    
+osGLOBAL void
+smDeviceDataInit(
+                 smRoot_t *smRoot,
+                 bit32    max_dev		  
+                )
+{
+  smIntRoot_t               *smIntRoot    = (smIntRoot_t *)smRoot->smData;
+  smIntContext_t            *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared;  
+  smDeviceData_t            *smDeviceData = (smDeviceData_t *)smAllShared->DeviceMem;
+  int                       i,j;
+  smSatInternalIo_t           *satIntIO;
+  
+  SM_DBG2(("smDeviceDataInit: start \n"));
+  
+  SMLIST_INIT_HDR(&(smAllShared->MainDeviceList));
+  SMLIST_INIT_HDR(&(smAllShared->FreeDeviceList));
+  
+  for(i=0;i<(int)max_dev;i++)
+  {
+    SMLIST_INIT_ELEMENT(&(smDeviceData[i].FreeLink));
+    SMLIST_INIT_ELEMENT(&(smDeviceData[i].MainLink));
+    smDeviceData[i].id = i;
+    smDeviceData[i].smRoot = agNULL;
+    smDeviceData[i].agDevHandle = agNULL;
+    smDeviceData[i].valid = agFALSE;
+    smDeviceData[i].SMAbortAll = agFALSE;
+    smDeviceData[i].smDevHandle = agNULL;
+    smDeviceData[i].directlyAttached = agFALSE;
+    smDeviceData[i].agExpDevHandle = agNULL;
+    smDeviceData[i].phyID = 0xFF;
+    smDeviceData[i].SMNumOfFCA = 0;
+ 
+    
+    SMLIST_INIT_HDR(&(smDeviceData[i].satIoLinkList));
+    SMLIST_INIT_HDR(&(smDeviceData[i].satFreeIntIoLinkList));
+    SMLIST_INIT_HDR(&(smDeviceData[i].satActiveIntIoLinkList));
+    
+    /* default */
+    smDeviceData[i].satDriveState = SAT_DEV_STATE_NORMAL;
+    smDeviceData[i].satNCQMaxIO =SAT_NCQ_MAX;
+    smDeviceData[i].satPendingIO = 0;
+    smDeviceData[i].satPendingNCQIO = 0;
+    smDeviceData[i].satPendingNONNCQIO = 0;
+    smDeviceData[i].IDDeviceValid = agFALSE;
+    smDeviceData[i].freeSATAFDMATagBitmap = 0;
+    smDeviceData[i].NumOfFCA = 0;
+    smDeviceData[i].NumOfIDRetries = 0;
+    smDeviceData[i].ID_Retries = 0;
+    smDeviceData[i].OSAbortAll = agFALSE;
+    smInitTimerRequest(smRoot, &(smDeviceData[i].SATAIDDeviceTimer));
+   
+    sm_memset(&(smDeviceData[i].satIdentifyData), 0xFF, sizeof(agsaSATAIdentifyData_t));
+    sm_memset(smDeviceData[i].satMaxLBA, 0, sizeof(smDeviceData[i].satMaxLBA));
+
+    smDeviceData[i].satSaDeviceData = &smDeviceData[i];
+    
+#if 1    
+    satIntIO = &smDeviceData[i].satIntIo[0];
+    for (j = 0; j < SAT_MAX_INT_IO; j++)
+    {
+      SMLIST_INIT_ELEMENT (&satIntIO->satIntIoLink);
+      SMLIST_ENQUEUE_AT_TAIL (&satIntIO->satIntIoLink, 
+                              &smDeviceData[i].satFreeIntIoLinkList);
+      satIntIO->satOrgSmIORequest = agNULL;
+      satIntIO->id = j;
+      satIntIO = satIntIO + 1;
+    }
+#endif
+    
+    /* some other variables */
+    SMLIST_ENQUEUE_AT_TAIL(&(smDeviceData[i].FreeLink), &(smAllShared->FreeDeviceList)); 
+  }  
+  
+  return;
+}
+
+osGLOBAL void
+smIOInit(
+         smRoot_t *smRoot 
+        )
+{
+  smIntRoot_t               *smIntRoot    = (smIntRoot_t *)smRoot->smData;
+  smIntContext_t            *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared;  
+  smIORequestBody_t         *smIOCommand = (smIORequestBody_t *)smAllShared->IOMem;
+  int                       i = 0;
+  
+  SM_DBG3(("smIOInit: start\n"));  
+  
+  SMLIST_INIT_HDR(&(smAllShared->freeIOList));
+  SMLIST_INIT_HDR(&(smAllShared->mainIOList));
+  
+  for(i=0;i<SM_MAX_IO;i++)
+  {
+    SMLIST_INIT_ELEMENT(&(smIOCommand[i].satIoBodyLink));
+    smIOCommand[i].id = i;
+    smIOCommand[i].InUse = agFALSE;
+    smIOCommand[i].ioStarted = agFALSE;
+    smIOCommand[i].ioCompleted = agFALSE;
+    smIOCommand[i].reTries = 0;
+
+    smIOCommand[i].smDevHandle = agNULL;
+    smIOCommand[i].smIORequest = agNULL;
+    smIOCommand[i].smIOToBeAbortedRequest = agNULL;
+    smIOCommand[i].transport.SATA.satIOContext.satOrgIOContext = agNULL;
+        
+    sm_memset(&(smIOCommand[i].transport.SATA.agSATARequestBody), 0, sizeof(agsaSATAInitiatorRequest_t));   
+    
+    
+    SMLIST_ENQUEUE_AT_TAIL(&(smIOCommand[i].satIoBodyLink), &(smAllShared->freeIOList)); 
+  }
+  
+  return;
+}
+	    	    
+FORCEINLINE void
+smIOReInit(
+          smRoot_t          *smRoot,
+          smIORequestBody_t *smIORequestBody
+          )
+{
+  SM_DBG3(("smIOReInit: start\n"));  
+  smIORequestBody->InUse = agTRUE;
+  smIORequestBody->ioStarted = agFALSE;
+  smIORequestBody->ioCompleted = agFALSE;
+  smIORequestBody->reTries = 0;
+  smIORequestBody->smDevHandle = agNULL;
+  smIORequestBody->smIORequest = agNULL;
+  smIORequestBody->smIOToBeAbortedRequest = agNULL;
+  smIORequestBody->transport.SATA.satIOContext.satOrgIOContext = agNULL;
+  /*sm_memset(&(smIORequestBody->transport.SATA.agSATARequestBody), 0, sizeof(agsaSATAInitiatorRequest_t));*/
+  return;
+}
+
+/* end smapi defined APIS */
+

sys/dev/pms/RefTisa/sat/src/smlist.h

@@ -0,0 +1,161 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+
+#ifndef __SMLIST_H__
+#define __SMLIST_H__
+
+typedef struct smList_s smList_t;
+
+struct smList_s {
+  smList_t  *flink;
+  smList_t  *blink;
+};
+
+#define SMLIST_INIT_HDR(hdr)                        \
+  do {                                              \
+    ((smList_t *)(hdr))->flink = (smList_t *)(hdr); \
+    ((smList_t *)(hdr))->blink = (smList_t *)(hdr); \
+  } while (0)
+
+#define SMLIST_INIT_ELEMENT(hdr)                     \
+  do {                                               \
+    ((smList_t *)(hdr))->flink = (smList_t *)agNULL; \
+    ((smList_t *)(hdr))->blink = (smList_t *)agNULL; \
+  } while (0)
+
+#define SMLIST_ENQUEUE_AT_HEAD(toAddHdr,listHdr)                                \
+  do {                                                                          \
+    ((smList_t *)(toAddHdr))->flink           = ((smList_t *)(listHdr))->flink; \
+    ((smList_t *)(toAddHdr))->blink           = (smList_t *)(listHdr) ;         \
+    ((smList_t *)(listHdr))->flink->blink     = (smList_t *)(toAddHdr);         \
+    ((smList_t *)(listHdr))->flink            = (smList_t *)(toAddHdr);         \
+  } while (0)
+
+#define SMLIST_ENQUEUE_AT_TAIL(toAddHdr,listHdr)                                \
+  do {                                                                          \
+    ((smList_t *)(toAddHdr))->flink           = (smList_t *)(listHdr);          \
+    ((smList_t *)(toAddHdr))->blink           = ((smList_t *)(listHdr))->blink; \
+    ((smList_t *)(listHdr))->blink->flink     = (smList_t *)(toAddHdr);         \
+    ((smList_t *)(listHdr))->blink            = (smList_t *)(toAddHdr);         \
+  } while (0)
+
+#define SMLIST_EMPTY(listHdr) \
+  (((smList_t *)(listHdr))->flink == ((smList_t *)(listHdr)))
+
+#define SMLIST_NOT_EMPTY(listHdr) \
+  (!SMLIST_EMPTY(listHdr))
+
+#define SMLIST_DEQUEUE_THIS(hdr)                                      \
+  do {                                                                \
+    ((smList_t *)(hdr))->blink->flink = ((smList_t *)(hdr))->flink;   \
+    ((smList_t *)(hdr))->flink->blink = ((smList_t *)(hdr))->blink;   \
+    ((smList_t *)(hdr))->flink = ((smList_t *)(hdr))->blink = agNULL; \
+  } while (0)
+
+#define SMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr)                              \
+  do {                                                                                \
+    *((smList_t **)(atHeadHdr))                 = ((smList_t *)(listHdr))->flink;     \
+    (*((smList_t **)(atHeadHdr)))->flink->blink = (smList_t *)(listHdr);              \
+    ((smList_t *)(listHdr))->flink              = (*(smList_t **)(atHeadHdr))->flink; \
+  } while (0)
+
+#define SMLIST_DEQUEUE_FROM_HEAD(atHeadHdr,listHdr)             \
+do {                                                            \
+  if (SMLIST_NOT_EMPTY((listHdr)))                              \
+  {                                                             \
+    SMLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr);           \
+  }                                                             \
+  else                                                          \
+  {                                                             \
+    (*((smList_t **)(atHeadHdr))) = (smList_t *)agNULL;         \
+  }                                                             \
+} while (0)
+  
+#define SMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr)                                \
+  do {                                                                                  \
+    (*((smList_t **)(atTailHdr)))               = ((smList_t *)(listHdr))->blink;       \
+    (*((smList_t **)(atTailHdr)))->blink->flink = (smList_t *)(listHdr);                \
+    ((smList_t *)(listHdr))->blink              = (*((smList_t **)(atTailHdr)))->blink; \
+  } while (0)
+
+#define SMLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr)               \
+  do {                                                            \
+    if (SMLIST_NOT_EMPTY((listHdr)))                              \
+    {                                                             \
+      SMLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr);           \
+    }                                                             \
+    else                                                          \
+    {                                                             \
+      (*((smList_t **)(atTailHdr))) = (smList_t *)agNULL;         \
+    }                                                             \
+  } while (0)
+
+#define SMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr)               \
+  do {                                                                        \
+    ((smList_t *)toAddListHdr)->blink->flink = ((smList_t *)listHdr);         \
+    ((smList_t *)toAddListHdr)->flink->blink = ((smList_t *)listHdr)->blink;  \
+    ((smList_t *)listHdr)->blink->flink = ((smList_t *)toAddListHdr)->flink;  \
+    ((smList_t *)listHdr)->blink = ((smList_t *)toAddListHdr)->blink;         \
+    SMLIST_INIT_HDR(toAddListHdr);                                            \
+  } while (0)
+
+#define SMLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr)                    \
+  do {                                                                        \
+    if (SMLIST_NOT_EMPTY(toAddListHdr))                                       \
+    {                                                                         \
+      SMLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr);                \
+    }                                                                         \
+  } while (0)
+
+#define SMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr)               \
+  do {                                                                        \
+    ((smList_t *)toAddListHdr)->blink->flink = ((smList_t *)listHdr)->flink;  \
+    ((smList_t *)toAddListHdr)->flink->blink = ((smList_t *)listHdr);         \
+    ((smList_t *)listHdr)->flink->blink = ((smList_t *)toAddListHdr)->blink;  \
+    ((smList_t *)listHdr)->flink = ((smList_t *)toAddListHdr)->flink;         \
+    SMLIST_INIT_HDR(toAddListHdr);                                            \
+  } while (0)
+
+#define SMLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr)                    \
+  do {                                                                        \
+    if (SMLIST_NOT_EMPTY(toAddListHdr))                                       \
+    {                                                                         \
+      SMLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr);                \
+    }                                                                         \
+  } while (0)
+
+#define TD_FIELD_OFFSET(baseType,fieldName) \
+                    ((bit32)((bitptr)(&(((baseType *)0)->fieldName))))
+
+#define SMLIST_OBJECT_BASE(baseType,fieldName,fieldPtr)         \
+                    (void *)fieldPtr == (void *)0 ? (baseType *)0 :             \
+                    ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName)))))
+
+
+
+
+#endif /* __SMLIST_H__ */
+
+
+

sys/dev/pms/RefTisa/sat/src/smmisc.c

@@ -0,0 +1,116 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+
+#include <dev/pms/RefTisa/sat/src/smdefs.h>
+#include <dev/pms/RefTisa/sat/src/smproto.h>
+#include <dev/pms/RefTisa/sat/src/smtypes.h>
+
+FORCEINLINE void*
+sm_memset(void *s, int c, bit32 n)
+{
+/*  bit32   i;
+
+  char *dst = (char *)s;
+  for (i=0; i < n; i++)
+  {
+    dst[i] = (char) c;
+  }
+  return (void *)(&dst[i-n]);
+*/
+  return memset(s, c, n);
+}
+
+FORCEINLINE void*
+sm_memcpy(void *dst, const void *src, bit32 count)
+{
+/*
+  bit32 x;
+  unsigned char *dst1 = (unsigned char *)dst;
+  unsigned char *src1 = (unsigned char *)src;
+
+  for (x=0; x < count; x++)
+    dst1[x] = src1[x];
+
+  return dst;
+*/  
+  return memcpy(dst, src, count);
+}
+
+osGLOBAL char 
+*sm_strncpy(char *dst, const char *src, bit32 len)
+{
+/*  char *ret = dst;
+    do {
+        if (!len--)
+            return ret;
+    } while ((*dst++ = *src++));
+    while (len--)
+        *dst++ = 0;
+    return ret;  
+*/ return strncpy(dst, src, len);
+}
+
+/** hexidecimal dump */
+osGLOBAL void 
+smhexdump(const char *ptitle, bit8 *pbuf, size_t len)
+{
+  size_t i;
+  SM_DBG1(("%s - smhexdump(len=%d):\n", ptitle, (int)len));
+  if (!pbuf)
+  {
+    SM_DBG1(("pbuf is NULL\n"));
+    return;
+  }
+  for (i = 0; i < len; )
+  {
+    if (len - i > 4)
+    {
+      SM_DBG1((" 0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", pbuf[i], pbuf[i+1], pbuf[i+2], pbuf[i+3]));
+      i += 4;
+    }
+    else
+    {
+      SM_DBG1((" 0x%02x,", pbuf[i]));
+      i++;
+    }
+  }
+  SM_DBG1(("\n"));
+}
+
+

sys/dev/pms/RefTisa/sat/src/smsathw.c

@@ -0,0 +1,530 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+
+#include <dev/pms/RefTisa/sat/src/smdefs.h>
+#include <dev/pms/RefTisa/sat/src/smproto.h>
+#include <dev/pms/RefTisa/sat/src/smtypes.h>
+
+/*
+ * This table is used to map LL Layer saSATAStart() status to TISA status.
+ */
+
+
+FORCEINLINE bit32  
+smsataLLIOStart(
+                smRoot_t                  *smRoot, 
+                smIORequest_t             *smIORequest,
+                smDeviceHandle_t          *smDeviceHandle,
+                smScsiInitiatorRequest_t  *smScsiRequest,
+                smSatIOContext_t          *satIOContext
+               )
+{
+  smDeviceData_t              *oneDeviceData  = (smDeviceData_t *)smDeviceHandle->smData;
+  smIntRoot_t                 *smIntRoot      = (smIntRoot_t *) smRoot->smData;
+  smIntContext_t              *smAllShared    = (smIntContext_t *)&(smIntRoot->smAllShared);
+  smIORequestBody_t           *smIORequestBody = (smIORequestBody_t *)satIOContext->smRequestBody;
+  smDeviceData_t              *pSatDevData   = satIOContext->pSatDevData;
+  smSatInternalIo_t           *satIntIo      = satIOContext->satIntIoContext;
+  agsaRoot_t                  *agRoot        = smAllShared->agRoot;
+  agsaIORequest_t             *agIORequest   = &(smIORequestBody->agIORequest);
+  agsaDevHandle_t             *agDevHandle   = oneDeviceData->agDevHandle;
+  agsaSATAInitiatorRequest_t  *agSATAReq     = &(smIORequestBody->transport.SATA.agSATARequestBody);
+  bit32                       RLERecovery    = agFALSE;
+  bit32                       status         = SM_RC_FAILURE;
+  bit32                       nQNumber       = 0;
+  /* 
+   * If this is a super I/O request, check for optional settings.
+   * Be careful. Use the superRequest pointer for all references 
+   * in this block of code.
+   */
+  agSATAReq->option = 0;
+  if (satIOContext->superIOFlag)
+  {
+    smSuperScsiInitiatorRequest_t *superRequest = (smSuperScsiInitiatorRequest_t *) smScsiRequest;
+
+    if (superRequest->flags & SM_SCSI_INITIATOR_ENCRYPT)
+    {
+      /* Copy all of the relevant encrypt information  */
+      agSATAReq->option |= AGSA_SATA_ENABLE_ENCRYPTION;
+      sm_memcpy(&agSATAReq->encrypt, &superRequest->Encrypt, sizeof(agsaEncrypt_t));
+    }
+    {
+      /* initialize expDataLength */
+      if (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_DATA ||  
+          satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_ASSERT ||
+          satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_DEASSERT )
+      { 
+        smIORequestBody->IOType.InitiatorRegIO.expDataLength = 0;
+      }
+      else
+      {
+        smIORequestBody->IOType.InitiatorRegIO.expDataLength = smScsiRequest->scsiCmnd.expDataLength;
+      }
+          
+      agSATAReq->dataLength = smIORequestBody->IOType.InitiatorRegIO.expDataLength;
+    }
+  } 
+  else
+  {
+    /* initialize expDataLength */
+    if (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_DATA ||  
+        satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_ASSERT ||
+        satIOContext->reqType == AGSA_SATA_PROTOCOL_SRST_DEASSERT )
+    { 
+      smIORequestBody->IOType.InitiatorRegIO.expDataLength = 0;
+    }
+    else
+    {
+      smIORequestBody->IOType.InitiatorRegIO.expDataLength = smScsiRequest->scsiCmnd.expDataLength;
+    }
+
+    agSATAReq->dataLength = smIORequestBody->IOType.InitiatorRegIO.expDataLength;
+  }
+
+  if ( (pSatDevData->satDriveState == SAT_DEV_STATE_IN_RECOVERY) && 
+       (satIOContext->pFis->h.command == SAT_READ_LOG_EXT) )
+  {
+     RLERecovery = agTRUE;
+  }
+
+  /* check max io, be sure to free */
+  if ( (pSatDevData->satDriveState != SAT_DEV_STATE_IN_RECOVERY) ||
+       (RLERecovery == agTRUE) )  
+  {
+    if (RLERecovery == agFALSE) /* RLE is not checked against pending IO's */
+    {
+#ifdef CCFLAG_OPTIMIZE_SAT_LOCK
+      bit32 volatile satPendingNCQIO = 0;
+      bit32 volatile satPendingNONNCQIO = 0;
+      bit32 volatile satPendingIO = 0;
+
+      tdsmInterlockedExchange(smRoot, &satPendingNCQIO, pSatDevData->satPendingNCQIO);
+      tdsmInterlockedExchange(smRoot, &satPendingNONNCQIO, pSatDevData->satPendingNONNCQIO);
+      tdsmInterlockedExchange(smRoot, &satPendingIO, pSatDevData->satPendingIO);
+#endif
+    
+      if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) ||
+           (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) )
+      {
+      #ifdef CCFLAG_OPTIMIZE_SAT_LOCK
+        if ( satPendingNCQIO >= pSatDevData->satNCQMaxIO ||
+             satPendingNONNCQIO != 0)
+        {
+          SM_DBG1(("smsataLLIOStart: 1st busy did %d!!!\n", pSatDevData->id));
+          SM_DBG1(("smsataLLIOStart: 1st busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", satPendingNCQIO, 
+                    satPendingNONNCQIO, satPendingIO));
+          /* free resource */
+          smsatFreeIntIoResource( smRoot,
+                                  pSatDevData,
+                                  satIntIo); 
+          return SM_RC_DEVICE_BUSY;
+        }
+      #else
+        tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK);
+        if (pSatDevData->satPendingNCQIO >= pSatDevData->satNCQMaxIO ||
+            pSatDevData->satPendingNONNCQIO != 0)
+        {
+          SM_DBG1(("smsataLLIOStart: 1st busy did %d!!!\n", pSatDevData->id));
+          SM_DBG1(("smsataLLIOStart: 1st busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", pSatDevData->satPendingNCQIO, 
+                    pSatDevData->satPendingNONNCQIO, pSatDevData->satPendingIO));
+          tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+          /* free resource */
+          smsatFreeIntIoResource( smRoot,
+                                  pSatDevData,
+                                  satIntIo); 
+          return SM_RC_DEVICE_BUSY;
+        }
+        tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+      #endif
+      
+      }
+      else if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_D2H_PKT) ||
+                (satIOContext->reqType == AGSA_SATA_PROTOCOL_H2D_PKT) ||
+                (satIOContext->reqType == AGSA_SATA_PROTOCOL_NON_PKT) )
+      {
+        sm_memcpy(agSATAReq->scsiCDB, smScsiRequest->scsiCmnd.cdb, 16);    
+      #ifdef CCFLAG_OPTIMIZE_SAT_LOCK
+        if ( satPendingNONNCQIO >= SAT_APAPI_CMDQ_MAX ||
+             satPendingNCQIO != 0)
+        {
+          SM_DBG1(("smsataLLIOStart: ATAPI busy did %d!!!\n", pSatDevData->id));
+          SM_DBG1(("smsataLLIOStart: ATAPI busy NON-NCQ. NCQ Pending 0x%x NON-NCQ Pending 0x%x All Pending 0x%x!!!\n", satPendingNCQIO, 
+                    satPendingNONNCQIO, satPendingIO));
+          /* free resource */
+          smsatFreeIntIoResource( smRoot,
+                                  pSatDevData,
+                                  satIntIo); 
+          return SM_RC_DEVICE_BUSY;
+        }
+      #else
+        tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK);
+        if ( pSatDevData->satPendingNONNCQIO >= SAT_APAPI_CMDQ_MAX ||
+             pSatDevData->satPendingNCQIO != 0)
+        {
+          SM_DBG1(("smsataLLIOStart: ATAPI busy did %d!!!\n", pSatDevData->id));
+          SM_DBG1(("smsataLLIOStart: ATAPI busy NON-NCQ. NCQ Pending 0x%x NON-NCQ Pending 0x%x All Pending 0x%x!!!\n", pSatDevData->satPendingNCQIO, 
+                    pSatDevData->satPendingNONNCQIO, pSatDevData->satPendingIO));
+          tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+          /* free resource */
+          smsatFreeIntIoResource( smRoot,
+                                  pSatDevData,
+                                  satIntIo); 
+          return SM_RC_DEVICE_BUSY;
+        }
+        tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+      #endif
+      
+      }
+      else
+      {
+#ifdef CCFLAG_OPTIMIZE_SAT_LOCK
+        if ( satPendingNONNCQIO >= SAT_NONNCQ_MAX ||
+             satPendingNCQIO != 0)
+        {
+          SM_DBG1(("smsataLLIOStart: 2nd busy did %d!!!\n", pSatDevData->id));
+          SM_DBG1(("smsataLLIOStart: 2nd busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", satPendingNCQIO, 
+                    satPendingNONNCQIO, satPendingIO));
+          /* free resource */
+          smsatFreeIntIoResource( smRoot,
+                                  pSatDevData,
+                                  satIntIo); 
+          return SM_RC_DEVICE_BUSY;
+        }
+#else
+        tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK);
+        if (pSatDevData->satPendingNONNCQIO >= SAT_NONNCQ_MAX ||
+            pSatDevData->satPendingNCQIO != 0)
+        {
+          SM_DBG1(("smsataLLIOStart: 2nd busy did %d!!!\n", pSatDevData->id));
+          SM_DBG1(("smsataLLIOStart: 2nd busy NCQ. NCQ Pending 0x%x NONNCQ Pending 0x%x All Pending 0x%x!!!\n", pSatDevData->satPendingNCQIO, 
+                    pSatDevData->satPendingNONNCQIO, pSatDevData->satPendingIO));
+          tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+          /* free resource */
+          smsatFreeIntIoResource( smRoot,
+                                  pSatDevData,
+                                  satIntIo); 
+          return SM_RC_DEVICE_BUSY;
+        }
+        tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+#endif
+      }
+    } /* RLE */
+    /* for internal SATA command only */
+    if (satIOContext->satOrgIOContext != agNULL)
+    {  
+      /* Initialize tiIORequest */
+      smIORequestBody->smIORequest = smIORequest;
+      if (smIORequest == agNULL)
+      {
+        SM_DBG1(("smsataLLIOStart: 1 check!!!\n"));
+      }
+    }
+    /* Initialize tiDevhandle */
+    smIORequestBody->smDevHandle = smDeviceHandle;
+       
+    /* Initializes Scatter Gather and ESGL */
+    status = smsatIOPrepareSGL( smRoot, 
+                                smIORequestBody, 
+                                &smScsiRequest->smSgl1, 
+                                smScsiRequest->sglVirtualAddr );
+      
+    if (status != SM_RC_SUCCESS)
+    {
+      SM_DBG1(("smsataLLIOStart: can't get SGL!!!\n"));
+      /* free resource */
+      smsatFreeIntIoResource( smRoot,
+                              pSatDevData,
+                              satIntIo);
+      return status;
+    }
+
+    /* Initialize LL Layer agIORequest */    
+    agIORequest->osData = (void *) smIORequestBody;
+    agIORequest->sdkData = agNULL; /* SA takes care of this */
+
+    smIORequestBody->ioStarted = agTRUE;
+    smIORequestBody->ioCompleted = agFALSE;
+
+    /* assign tag value for SATA */
+    if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) ||
+         (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) )
+    {
+      if (agFALSE == smsatTagAlloc(smRoot, pSatDevData, &satIOContext->sataTag))
+      {
+        SM_DBG1(("smsataLLIOStart: No more NCQ tag!!!\n"));
+        smIORequestBody->ioStarted = agFALSE;
+        smIORequestBody->ioCompleted = agTRUE;
+        return SM_RC_DEVICE_BUSY;
+      }
+      SM_DBG3(("smsataLLIOStart: ncq tag 0x%x\n",satIOContext->sataTag));
+    }
+    else
+    {
+      satIOContext->sataTag = 0xFF;
+    }
+  }
+  else /* AGSA_SATA_PROTOCOL_SRST_ASSERT or AGSA_SATA_PROTOCOL_SRST_DEASSERT 
+          or SAT_CHECK_POWER_MODE as ABORT */
+  {
+    agsaSgl_t          *agSgl;
+  
+    /* for internal SATA command only */
+    if (satIOContext->satOrgIOContext != agNULL)
+    {  
+      /* Initialize tiIORequest */
+      smIORequestBody->smIORequest = smIORequest;
+      if (smIORequest == agNULL)
+      {
+        SM_DBG1(("smsataLLIOStart: 2 check!!!\n"));
+      }
+    }
+    /* Initialize tiDevhandle */
+    smIORequestBody->smDevHandle = smDeviceHandle;
+    
+    
+    smIORequestBody->IOType.InitiatorRegIO.expDataLength = 0;
+    /* SGL for SATA request */
+    agSgl = &(smIORequestBody->transport.SATA.agSATARequestBody.agSgl);
+    agSgl->len = 0;
+
+    agSgl->sgUpper = 0;
+    agSgl->sgLower = 0;
+    agSgl->len = 0;
+    SM_CLEAR_ESGL_EXTEND(agSgl->extReserved);
+  
+    /* Initialize LL Layer agIORequest */
+    agIORequest = &(smIORequestBody->agIORequest);
+    agIORequest->osData = (void *) smIORequestBody;
+    agIORequest->sdkData = agNULL; /* SA takes care of this */
+
+    smIORequestBody->ioStarted = agTRUE;
+    smIORequestBody->ioCompleted = agFALSE;
+  
+    /* setting the data length */
+    agSATAReq->dataLength = 0;
+  
+  }
+
+
+  smIORequestBody->reTries = 0;
+  
+#ifdef TD_INTERNAL_DEBUG
+  smhexdump("smsataLLIOStart", (bit8 *)satIOContext->pFis, sizeof(agsaFisRegHostToDevice_t)); 
+  smhexdump("smsataLLIOStart LL", (bit8 *)&agSATAReq->fis.fisRegHostToDev,
+            sizeof(agsaFisRegHostToDevice_t));
+#endif  
+
+  SM_DBG6(("smsataLLIOStart: agDevHandle %p\n", agDevHandle));
+
+  /* to get better IO performance, rotate the OBQ number on main IO path */
+  if (smScsiRequest == agNULL)
+  {
+    nQNumber = 0;
+  }
+  else
+  {
+    switch (smScsiRequest->scsiCmnd.cdb[0])
+    {
+      case SCSIOPC_READ_10:
+      case SCSIOPC_WRITE_10:
+      case SCSIOPC_READ_6:
+      case SCSIOPC_WRITE_6:
+      case SCSIOPC_READ_12:
+      case SCSIOPC_WRITE_12:
+      case SCSIOPC_READ_16:
+      case SCSIOPC_WRITE_16:
+         nQNumber = tdsmRotateQnumber(smRoot, smDeviceHandle);
+         break;
+
+      default:
+         nQNumber = 0;
+         break;
+    }
+  }
+
+  SM_DBG3(("sataLLIOStart: Lock in\n"));
+  
+#ifdef CCFLAG_OPTIMIZE_SAT_LOCK
+  if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) ||
+       (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) )
+  {
+     tdsmInterlockedIncrement(smRoot,&pSatDevData->satPendingNCQIO); 
+  }
+  else
+  {
+     tdsmInterlockedIncrement(smRoot,&pSatDevData->satPendingNONNCQIO);
+  }
+  tdsmInterlockedIncrement(smRoot,&pSatDevData->satPendingIO);
+#else
+  tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK);
+  if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) ||
+       (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) )
+  {
+     pSatDevData->satPendingNCQIO++;
+  }
+  else
+  {
+     pSatDevData->satPendingNONNCQIO++;
+  }    
+  pSatDevData->satPendingIO++;
+
+  SMLIST_INIT_ELEMENT (&satIOContext->satIoContextLink);
+  SMLIST_ENQUEUE_AT_TAIL (&satIOContext->satIoContextLink, &pSatDevData->satIoLinkList);
+  tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+#endif
+  /* post SATA command to low level MPI */
+  status = saSATAStart( agRoot,
+                        agIORequest,
+                        nQNumber,                        
+                        agDevHandle,
+                        satIOContext->reqType,
+                        agSATAReq,
+                        satIOContext->sataTag,
+                        smllSATACompleted
+                        );
+    
+  if (status != AGSA_RC_SUCCESS)
+  {
+    if (status == AGSA_RC_BUSY)
+    {
+      SM_DBG1(("smsataLLIOStart: saSATAStart busy!!!\n")); 
+      status = SM_RC_BUSY;
+    }
+    else
+    {
+      SM_DBG1(("smsataLLIOStart: saSATAStart failed!!!\n"));
+      status = SM_RC_FAILURE;
+    }
+
+    if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) ||
+         (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) )
+    {
+      smsatTagRelease(smRoot, pSatDevData, satIOContext->sataTag);
+    }
+
+#ifdef CCFLAG_OPTIMIZE_SAT_LOCK
+    if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) ||
+         (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) )
+    {
+      tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingNCQIO);
+    }
+    else
+    {
+      tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingNONNCQIO);
+    }
+    tdsmInterlockedDecrement(smRoot,&oneDeviceData->satPendingIO);      
+#else
+    if ( (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_WRITE) ||
+         (satIOContext->reqType == AGSA_SATA_PROTOCOL_FPDMA_READ) )
+    {
+      tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK);
+      oneDeviceData->satPendingNCQIO--;
+      oneDeviceData->satPendingIO--;
+      SMLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink);
+      tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);
+    }
+    else
+    {
+      tdsmSingleThreadedEnter(smRoot, SM_EXTERNAL_IO_LOCK);
+      oneDeviceData->satPendingNONNCQIO--;
+      oneDeviceData->satPendingIO--;
+      SMLIST_DEQUEUE_THIS (&satIOContext->satIoContextLink);
+      tdsmSingleThreadedLeave(smRoot, SM_EXTERNAL_IO_LOCK);     
+    }    
+#endif /* CCFLAG_OPTIMIZE_SAT_LOCK */
+    
+    /* Free the ESGL pages associated with this I/O */
+    smIORequestBody->ioStarted = agFALSE;
+    smIORequestBody->ioCompleted = agTRUE;
+    return (status);
+  }
+  
+  return SM_RC_SUCCESS;
+}	       
+
+
+osGLOBAL FORCEINLINE bit32 
+smsatIOPrepareSGL(
+                  smRoot_t                 *smRoot,
+                  smIORequestBody_t        *smIORequestBody,
+                  smSgl_t                  *smSgl1,
+                  void                     *sglVirtualAddr
+                  )
+{
+  agsaSgl_t          *agSgl;
+  
+  /* Uppper should be zero-out */
+  SM_DBG5(("smsatIOPrepareSGL: start\n"));
+  
+  SM_DBG5(("smsatIOPrepareSGL: smSgl1->upper %d smSgl1->lower %d smSgl1->len %d\n", 
+    smSgl1->upper, smSgl1->lower, smSgl1->len));
+  SM_DBG5(("smsatIOPrepareSGL: smSgl1->type %d\n", smSgl1->type)); 
+
+  /* SGL for SATA request */
+  agSgl = &(smIORequestBody->transport.SATA.agSATARequestBody.agSgl);
+  agSgl->len = 0;
+
+  if (smSgl1 == agNULL)
+  {
+    SM_DBG1(("smsatIOPrepareSGL: Error smSgl1 is NULL!!!\n"));
+    return tiError;
+  }
+
+  if (smIORequestBody->IOType.InitiatorRegIO.expDataLength == 0)
+  {
+    SM_DBG3(("smsatIOPrepareSGL: expDataLength is 0\n"));
+    agSgl->sgUpper = 0;
+    agSgl->sgLower = 0;
+    agSgl->len = 0;
+    SM_CLEAR_ESGL_EXTEND(agSgl->extReserved);
+    return SM_RC_SUCCESS;
+  }
+
+  agSgl->sgUpper = smSgl1->upper;
+  agSgl->sgLower = smSgl1->lower;
+  agSgl->len = smSgl1->len;
+  agSgl->extReserved = smSgl1->type;
+
+  return SM_RC_SUCCESS;
+
+}		  
+
+
+
+

sys/dev/pms/RefTisa/sat/src/smtimer.c

@@ -0,0 +1,161 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+
+#include <dev/pms/RefTisa/sat/src/smdefs.h>
+#include <dev/pms/RefTisa/sat/src/smproto.h>
+#include <dev/pms/RefTisa/sat/src/smtypes.h>
+
+osGLOBAL void   
+smTimerTick(smRoot_t 		*smRoot )
+{
+  SM_DBG6(("smTimerTick: start\n"));
+  
+  smProcessTimers(smRoot);
+
+  return;
+}	  																
+				
+osGLOBAL void
+smInitTimerRequest(
+                     smRoot_t                *smRoot, 
+                     smTimerRequest_t        *timerRequest
+                     )
+{
+  timerRequest->timeout       = 0;
+  timerRequest->timerCBFunc   = agNULL;
+  timerRequest->timerData1     = agNULL;
+  timerRequest->timerData2     = agNULL;
+  timerRequest->timerData3     = agNULL;
+  SMLIST_INIT_ELEMENT((&timerRequest->timerLink));
+}
+
+osGLOBAL void
+smSetTimerRequest(
+                  smRoot_t            *smRoot,
+                  smTimerRequest_t    *timerRequest,
+                  bit32               timeout,
+                  smTimerCBFunc_t     CBFunc,
+                  void                *timerData1,
+                  void                *timerData2,
+                  void                *timerData3
+                  )
+{
+  timerRequest->timeout     = timeout;
+  timerRequest->timerCBFunc = CBFunc;
+  timerRequest->timerData1   = timerData1;
+  timerRequest->timerData2   = timerData2;
+  timerRequest->timerData3   = timerData3;
+}
+
+osGLOBAL void
+smAddTimer(
+           smRoot_t            *smRoot,
+           smList_t            *timerListHdr, 
+           smTimerRequest_t    *timerRequest
+          )
+{
+  tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK);
+  SMLIST_ENQUEUE_AT_TAIL(&(timerRequest->timerLink), timerListHdr);
+  timerRequest->timerRunning = agTRUE;
+  tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK);
+}
+
+osGLOBAL void
+smKillTimer(
+            smRoot_t            *smRoot,
+            smTimerRequest_t    *timerRequest
+           )
+{
+  tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK);
+  timerRequest->timerRunning = agFALSE;
+  SMLIST_DEQUEUE_THIS(&(timerRequest->timerLink));
+  tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK);
+}
+
+osGLOBAL void 
+smProcessTimers(
+                smRoot_t *smRoot
+                )
+{
+  smIntRoot_t               *smIntRoot    = (smIntRoot_t *)smRoot->smData;
+  smIntContext_t            *smAllShared = (smIntContext_t *)&smIntRoot->smAllShared;
+  smTimerRequest_t          *timerRequest_to_process = agNULL;
+  smList_t                  *timerlist_to_process, *nexttimerlist = agNULL;
+
+  
+  timerlist_to_process = &smAllShared->timerlist;
+  
+  timerlist_to_process = timerlist_to_process->flink;
+
+  while ((timerlist_to_process != agNULL) && (timerlist_to_process != &smAllShared->timerlist))
+  {
+    nexttimerlist = timerlist_to_process->flink;
+    
+    tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK);
+    timerRequest_to_process = SMLIST_OBJECT_BASE(smTimerRequest_t, timerLink, timerlist_to_process);
+    tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK);
+
+    if (timerRequest_to_process == agNULL)
+    {
+      SM_DBG1(("smProcessTimers: timerRequest_to_process is NULL! Error!!!\n"));
+      return;      
+    }
+    
+    timerRequest_to_process->timeout--;
+    
+    if (timerRequest_to_process->timeout == 0)
+    {
+      timerRequest_to_process->timerRunning = agFALSE;
+      
+      tdsmSingleThreadedEnter(smRoot, SM_TIMER_LOCK);
+      SMLIST_DEQUEUE_THIS(timerlist_to_process);
+      tdsmSingleThreadedLeave(smRoot, SM_TIMER_LOCK);
+      /* calling call back function */
+      (timerRequest_to_process->timerCBFunc)(smRoot, 
+                                             timerRequest_to_process->timerData1, 
+                                             timerRequest_to_process->timerData2, 
+                                             timerRequest_to_process->timerData3 
+                                             );
+    }
+    timerlist_to_process = nexttimerlist;
+  }
+
+ return;
+}
+

sys/dev/pms/RefTisa/sat/src/smtypes.h

@@ -0,0 +1,359 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+#ifndef __SMTYPES_H__
+#define __SMTYPES_H__
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+
+#include <dev/pms/RefTisa/sat/src/smlist.h>
+
+/*
+ * SAT specific structure per SATA drive 
+ */
+#define SAT_NONNCQ_MAX  1
+#define SAT_NCQ_MAX     32
+#define SAT_MAX_INT_IO  16
+#define SAT_APAPI_CMDQ_MAX 2
+
+/* SMP direct payload size limit: IOMB direct payload size = 48 */
+#define SMP_DIRECT_PAYLOAD_LIMIT 44
+
+/* timer functions ; both I and T */
+typedef void (*smTimerCBFunc_t)(smRoot_t *smRoot, void *timerData1, void *timerData2, void *timerData3);
+
+
+/** \brief data structure for timer request
+ *  Timer requests are enqueued and dequeued using smList_t
+ *  and have a callback function
+ */
+typedef struct smTimerRequest_s {
+  /* the number of ticks */
+  bit32             timeout;
+  void              *timerData1;
+  void              *timerData2;
+  void              *timerData3;
+  smTimerCBFunc_t   timerCBFunc;
+  smList_t          timerLink;
+  bit32             timerRunning;
+}  smTimerRequest_t;
+
+
+
+typedef struct smSatInternalIo_s
+{
+  smList_t                    satIntIoLink;
+  smIORequest_t               satIntSmIORequest; /* old satIntTiIORequest */
+  void                        *satIntRequestBody; /* maps to smIOrequestBody */
+  smScsiInitiatorRequest_t    satIntSmScsiXchg; /* old satIntTiScsiXchg*/
+  smMem_t                     satIntDmaMem;
+  smMem_t                     satIntReqBodyMem;
+  bit32                       satIntFlag;
+  smIORequest_t               *satOrgSmIORequest; /* old satOrgTiIORequest */
+  bit32                       id;
+} smSatInternalIo_t;
+
+
+
+typedef struct smDeviceData_s  {
+  smList_t                FreeLink; /* free dev list */
+  smList_t                MainLink; /* main(in use) dev list */
+  bit32                   id; /* for debugging only */
+  smRoot_t                *smRoot;
+  agsaDevHandle_t         *agDevHandle;
+  bit32                   valid; /* valid or registered */
+  smTimerRequest_t        SATAIDDeviceTimer; /* ID Device Data timer for SATA device */
+  bit32                   SMAbortAll; /* flag for abortall case */ 
+  smDeviceHandle_t        *smDevHandle;
+  bit32                   directlyAttached;
+  agsaDevHandle_t         *agExpDevHandle; /* expander a device is attached to if expander attached */
+  bit32                   phyID;
+  agsaContext_t           agDeviceResetContext; /* used in saLocalPhyControl() */
+  bit32                   SMNumOfFCA;
+    
+  /* from satDeviceData_t */
+  smList_t                satIoLinkList;            /* Normal I/O from TISA         */
+  smList_t                satFreeIntIoLinkList;     /* SAT internal I/O free list   */
+  smList_t                satActiveIntIoLinkList;   /* SAT internal I/O active list */
+  smSatInternalIo_t       satIntIo[SAT_MAX_INT_IO]; /* Internal I/O resource        */
+  agsaSATAIdentifyData_t  satIdentifyData;          /* Copy of SATA Id Dev data     */
+  bit32                   satNCQ;                   /* Flag for NCQ support         */ 
+  bit32                   sat48BitSupport;          /* Flag for 48-bit addressing   */
+  bit32                   satSMARTSelfTest;         /* Flag for SMART self test     */
+  bit32                   satSMARTFeatureSet;       /* Flag for SMART feature set   */
+  bit32                   satSMARTEnabled;          /* Flag for SMART enabled       */
+  bit32                   satRemovableMedia;        /* Flag for Removable Media     */
+  bit32                   satRemovableMediaEnabled; /* Flag for Removable Media Enabled */
+  bit32                   satDMASupport;            /* Flag for DMA Support         */
+  bit32                   satDMAEnabled;            /* Flag for DMA Enabled         */
+  bit32                   satUltraDMAMode;          /* Ultra DMA mode value        */
+  bit32                   satDMADIRSupport;         /* Flag for DMA direction       */
+  bit32                   satReadLookAheadSupport;  /* Flag for Read Look Ahead */
+  bit32                   satVolatileWriteCacheSupport; /* Flag for Volatile Write Cache support*/
+  bit32                   satWWNSupport;            /* Flag for DMA Enabled         */
+  bit32                   satDMASetupAA;            /* Flag for DMA Setup Auto-Activate */
+  bit32                   satNCQQMgntCmd;           /* Flag for NCQ Queue Management Command */
+  bit32 volatile          satPendingIO;             /* Number of pending I/O        */
+  bit32 volatile          satPendingNCQIO;          /* Number of pending NCQ I/O    */
+  bit32 volatile          satPendingNONNCQIO;       /* Number of pending NON NCW I/O*/
+  bit32                   satNCQMaxIO;              /* Max NCQ I/O in SAT or drive  */
+  bit32                   satDriveState;            /* State of SAT/drive           */
+  bit32                   satAbortAfterReset;       /* Flag: abort after SATA reset */
+  bit32                   satAbortCalled;           /* Flag: abort called indication*/
+  bit32                   satVerifyState;           /* Flag: Read Vrf state for diag*/
+  bit32                   satMaxUserAddrSectors;    /* max user addressable setctors*/
+  bit32                   satWriteCacheEnabled;     /* Flag for write cache enabled */
+  bit32                   satLookAheadEnabled;      /* Flag for look ahead enabled  */
+  bit32                   satDeviceFaultState;      /* State of DF                  */
+  bit32                   satStopState;             /* State of Start and Stop      */
+  bit32                   satFormatState;           /* State of format              */
+  bit32                   satPMField;               /* PM field, first 4 bits       */
+  bit8                    satSignature[8];          /* Signature                    */
+  bit32                   satDeviceType;            /* ATA device type              */
+  bit32                   satSectorDone;            /* Number of Sector done by Cmnd*/
+  bit32                   freeSATAFDMATagBitmap;    /* SATA NCQ tag bit map         */
+  bit32                   IDDeviceValid;            /* ID DeviceData valid bit      */
+  bit8                    satMaxLBA[8];             /* MAXLBA is from read capacity */
+  bit32                   satBGPendingDiag;         /* Pending Diagnostic in backgound */
+  bit32                   NumOfFCA;                 /* number of SMP HARD RESET on this device */   
+  bit32                   NumOfIDRetries;           /* number of SMP HARD RESET after ID retries */   
+  smIORequest_t           *satTmTaskTag;            /* TM Task Tag                  */
+  void                    *satSaDeviceData;         /* Pointer back to sa dev data  */
+  bit32                   ID_Retries;               /* identify device data retries */
+  bit32                   OSAbortAll;               /* OS calls abort all           */
+  bit32                   ReadCapacity;             /* Read Capacity Type; 10, 16   */
+  bit32                   sasAddressLo;             /**< HOST SAS address lower part */
+  bit32                   sasAddressHi;             /**< HOST SAS address higher part */
+
+}  smDeviceData_t;
+
+typedef struct smAtaPassThroughHdr_s
+{
+  bit8 opc;
+  bit8 mulCount : 3;
+  bit8 proto : 4;
+  bit8 extend : 1;
+  bit8 offline : 2;
+  bit8 ckCond : 1;
+  bit8 tType : 1;
+  bit8 tDir : 1;
+  bit8 byteBlock : 1;
+  bit8 tlength : 2;
+  
+}smAtaPassThroughHdr_t;
+
+/*
+ * SCSI Sense Data
+ */
+typedef struct 
+{
+  bit8       snsRespCode;
+  bit8       snsSegment;
+  bit8       senseKey;          /* sense key                                */
+  bit8       info[4];
+  bit8       addSenseLen;       /* 11 always                                */
+  bit8       cmdSpecific[4];
+  bit8       addSenseCode;      /* additional sense code                    */
+  bit8       senseQual;         /* additional sense code qualifier          */
+  bit8       fru;
+  bit8       skeySpecific[3];
+} smScsiRspSense_t;
+
+
+/* 
+ * SATA SAT specific function pointer for SATA completion for SAT commands.
+ */
+typedef void (*smSatCompleteCbPtr_t  )(
+                          agsaRoot_t        *agRoot,
+                          agsaIORequest_t   *agIORequest,
+                          bit32             agIOStatus,
+                          agsaFisHeader_t   *agFirstDword,
+                          bit32             agIOInfoLen,
+                          agsaFrameHandle_t agFrameHandle,
+                          void              *satIOContext
+                       );
+
+/* for SMP only */
+typedef void (*smSMPCompleted_t)(
+                                  agsaRoot_t            *,
+                                  agsaIORequest_t       *,
+                                  bit32                 ,
+                                  bit32                 ,
+                                  agsaFrameHandle_t     
+                                );
+
+
+/* 
+ * SATA SAT specific function for I/O context
+ */
+typedef struct smSatIOContext_s 
+{
+  smList_t                    satIoContextLink;
+  smDeviceData_t              *pSatDevData;
+  agsaFisRegHostToDevice_t    *pFis;
+  smIniScsiCmnd_t             *pScsiCmnd;
+  smScsiRspSense_t            *pSense;
+  smSenseData_t               *pSmSenseData; /* old pTiSenseData */
+  void                        *smRequestBody;  /* smIORequestBody_t; old tiRequestBody*/
+  void                        *smScsiXchg; /* for writesame10(); old tiScsiXchg */
+  bit32                       reqType;
+  bit32                       interruptContext;
+  smSatCompleteCbPtr_t        satCompleteCB;
+  smSatInternalIo_t           *satIntIoContext; /* SATM generated IOs */
+  smDeviceHandle_t            *psmDeviceHandle; /* old ptiDeviceHandle */
+  bit8                        sataTag;
+  bit8                        superIOFlag;/* Flag indicating type for smScsiXchg */
+  bit8                        reserved1;  /* Padding for allignment */
+  bit8                        reserved2;  /* Padding for allignment */
+  bit32                       currentLBA; /* current LBA for read and write */
+  bit32                       ATACmd;     /* ATA command */
+  bit32                       OrgTL;      /* original tranfer length(tl) */
+  bit32                       LoopNum;    /* denominator tl */
+  bit32                       LoopNum2;    /* denominator tl */
+  bit8                        LBA[8];     /* for reassign blocks; current LBA */
+  bit32                       ParmIndex;  /* for reassign blocks;current idx in defective LBA LIST */
+  bit32                       ParmLen;    /* for reassign blocks; defective LBA list length */
+  bit32                       NotifyOS;   /* only for task management */
+  bit32                       TMF;        /* task management function */
+  struct smSatIOContext_s     *satToBeAbortedIOContext; 
+  struct smSatIOContext_s     *satOrgIOContext;
+  bit32                       UpperAddr;
+  bit32                       LowerAddr;
+  bit32                       SplitIdx;
+  bit32                       AdjustBytes;
+  bit32                       EsglLen;
+  /* For the SAT Passthrough */
+  bit8                        ck_cond;  
+  bit8                        extend;
+  bit8                        sectorCnt07;
+  bit8                        LBAHigh07;
+  bit8                        LBAMid07;
+  bit8                        LBALow07;
+  bit8                        Sector_Cnt_Upper_Nonzero;
+  bit8                        LBA_Upper_Nonzero;  
+  bit32                       pid;        /* port id; used to protect double completion */
+  bit32                       id;         /* for debugging */
+} smSatIOContext_t;
+
+typedef struct smIORequestBody_s {
+  smList_t                    satIoBodyLink;
+  smDeviceHandle_t            *smDevHandle;
+  smIORequest_t               *smIORequest;
+  agsaIORequest_t             agIORequest;
+  smIORequest_t               *smIOToBeAbortedRequest; /* IO to be aborted; old tiIOToBeAbortedRequest */
+  bit32                       id;
+  bit32                       InUse;  
+  union {
+    struct {
+      agsaSATAInitiatorRequest_t    agSATARequestBody;
+      smScsiRspSense_t              sensePayload;
+      smSenseData_t                 smSenseData; /* old tiSenseData */
+      smSatIOContext_t              satIOContext;
+    } SATA;
+  } transport;  
+  bit32                          ioStarted;
+  bit32                          ioCompleted;
+  bit32                          reTries;
+  union {
+    struct {
+      bit32                     expDataLength;
+      smSgl_t                   smSgl1; /* old tiSgl1 */
+      smSgl_t                   smSgl2; /* old tiSgl2 */
+      void                      *sglVirtualAddr;
+    } InitiatorRegIO;  /* regular IO */
+    struct {
+      void                      *osMemHandle;
+      smIORequest_t             *CurrentTaskTag;
+      smIORequest_t             *TaskTag;
+    } InitiatorTMIO;  /* task management */
+  } IOType;
+  
+} smIORequestBody_t;
+
+typedef struct smSMPRequestBody_s {
+  smSMPCompleted_t               SMPCompletionFunc;/* must be the second */
+  
+  smDeviceHandle_t               *smDevHandle;    /* not used for SM generated SMP */
+  agsaIORequest_t                agIORequest;
+  agsaSASRequestBody_t           agSASRequestBody;
+  void                           *osMemHandle;
+  smDeviceData_t                 *smDeviceData;
+  smIORequest_t                  *CurrentTaskTag; /* SMP is used for simulate target reset */
+//  tdsaPortContext_t              *tdPortContext; /* portcontext where SMP is sent from */
+  bit8                           smpPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /* for smp retries; 
+                                                                          only for direct SMP */
+  bit32                          retries; /* number of retries */
+ 
+}  smSMPRequestBody_t;
+
+
+typedef struct smRootOsData_s {
+  smRoot_t  *smRoot;            /**< Pointer back to smRoot                 */
+  void      *smAllShared;       /**< Pointer to smIntContext_t               */
+  void      *smIni;             /**< Pointer to SAS/SATA initiator               */
+}  smRootOsData_t;
+
+typedef struct smIntContext_s {
+  /**< agsaRoot_t->osData points to this */
+  struct smRootOsData_s      smRootOsData;
+  
+  bit32               usecsPerTick;
+  agsaRoot_t          *agRoot;
+  
+  /**< software-related initialization params used in saInitialize() */
+  smSwConfig_t        SwConfig;  
+  
+  /**< timers used commonly in SAS/SATA */
+  smList_t                      timerlist;
+  
+  /**< pointer to Device memory */
+  smDeviceData_t             *DeviceMem;  
+  smList_t                   FreeDeviceList;
+  smList_t                   MainDeviceList;
+
+  /**< pointer to IO memory */
+  smIORequestBody_t         *IOMem; 
+  smList_t                   freeIOList;
+  smList_t                   mainIOList;  
+  bit32                      FCA;
+}  smIntContext_t;
+
+typedef struct smIntRoot_s
+{
+  /**<< common data structure for SAS/SATA */
+  smIntContext_t          smAllShared;
+} smIntRoot_t;
+
+
+#endif                          /* __SMTYPES_H__ */
+

sys/dev/pms/RefTisa/tisa/api/ostiapi.h

@@ -0,0 +1,487 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+**
+** Version Control Information:
+**
+**
+*******************************************************************************/
+/********************************************************************************
+**
+**   ostiapi.h
+**
+**   Abstract:   This module contains function prototype of the Transport
+**               Independent (TIAPI) OS Callback interface.
+**
+********************************************************************************/
+
+#ifndef OSTIAPI_H
+
+#define OSTIAPI_H
+
+/*
+ * Definition for return status is defined in tiStatus_t in TIDEFS.H
+ */
+
+/*****************************************************************************
+ *  Initiator/Target Shared Callbacks
+ *****************************************************************************/
+
+osGLOBAL bit32 ostiGetTransportParam(
+                        tiRoot_t    *tiRoot,
+                        char        *key,
+                        char        *subkey1,
+                        char        *subkey2,
+                        char        *subkey3,
+                        char        *subkey4,
+                        char        *subkey5,
+                        char        *valueName,
+                        char        *buffer,
+                        bit32       bufferLen,
+                        bit32       *lenReceived
+                        );
+
+osGLOBAL void  ostiPortEvent(
+                        tiRoot_t      *tiRoot,
+                        tiPortEvent_t eventType,
+                        bit32         status,
+                        void          *pParm
+                        );
+
+osGLOBAL bit32  ostiTimeStamp( tiRoot_t  *tiRoot);
+osGLOBAL bit64  ostiTimeStamp64( tiRoot_t  *tiRoot);
+
+osGLOBAL FORCEINLINE bit32 ostiChipConfigReadBit32(
+                        tiRoot_t      *tiRoot,
+                        bit32         chipConfigOffset
+                        );
+
+osGLOBAL FORCEINLINE void ostiChipConfigWriteBit32(
+                        tiRoot_t      *tiRoot,
+                        bit32         chipConfigOffset,
+                        bit32         chipConfigValue
+                        );
+
+osGLOBAL FORCEINLINE bit32 ostiChipReadBit32(
+                        tiRoot_t      *tiRoot,
+                        bit32         chipOffset
+                        );
+
+osGLOBAL FORCEINLINE void ostiChipWriteBit32(
+                        tiRoot_t      *tiRoot,
+                        bit32         chipOffset,
+                        bit32         chipValue
+                        );
+
+osGLOBAL FORCEINLINE bit8 ostiChipReadBit8(
+                        tiRoot_t      *tiRoot,
+                        bit32         chipOffset
+                        );
+
+osGLOBAL FORCEINLINE void ostiChipWriteBit8(
+                        tiRoot_t      *tiRoot,
+                        bit32         chipOffset,
+                        bit8          chipValue
+                        );
+
+osGLOBAL void ostiFlashReadBlock(
+                        tiRoot_t      *tiRoot,
+                        bit32         flashOffset,
+                        void          *buffer,
+                        bit32         bufferLen
+                        );
+
+osGLOBAL FORCEINLINE
+tiDeviceHandle_t*
+ostiGetDevHandleFromSasAddr(
+  tiRoot_t    *root,
+  unsigned char *sas_addr
+);
+
+osGLOBAL FORCEINLINE void ostidisableEncryption(tiRoot_t *root);
+
+osGLOBAL FORCEINLINE void ostiSingleThreadedEnter(
+                        tiRoot_t      *tiRoot,
+                        bit32         queueId
+                        );
+
+osGLOBAL FORCEINLINE void ostiSingleThreadedLeave(
+                        tiRoot_t      *tiRoot,
+                        bit32         queueId
+                        );
+
+
+osGLOBAL bit32 ostiNumOfLUNIOCTLreq(tiRoot_t           *root,
+									void               *param1,
+                                    void               *param2,
+                                    void                           **tiRequestBody,
+                                    tiIORequest_t          **tiIORequest
+                                    );
+
+#ifdef PERF_COUNT
+osGLOBAL void ostiEnter(tiRoot_t *ptiRoot, bit32 layer, int io);
+osGLOBAL void ostiLeave(tiRoot_t *ptiRoot, bit32 layer, int io);
+#define OSTI_INP_ENTER(root) ostiEnter(root, 2, 0)
+#define OSTI_INP_LEAVE(root) ostiLeave(root, 2, 0)
+#define OSTI_OUT_ENTER(root) ostiEnter(root, 2, 1)
+#define OSTI_OUT_LEAVE(root) ostiLeave(root, 2, 1)
+#else
+#define OSTI_INP_ENTER(root)
+#define OSTI_INP_LEAVE(root)
+#define OSTI_OUT_ENTER(root)
+#define OSTI_OUT_LEAVE(root)
+#endif
+
+osGLOBAL void  ostiStallThread(
+                        tiRoot_t      *tiRoot,
+                        bit32         microseconds
+                        );
+
+osGLOBAL FORCEINLINE bit8
+ostiBitScanForward(
+                  tiRoot_t   *root,
+                  bit32      *Index,
+                  bit32       Mask
+                  );
+
+#ifdef LINUX_VERSION_CODE
+
+osGLOBAL sbit32
+ostiAtomicIncrement(
+                   tiRoot_t        *root,
+                   sbit32 volatile *Addend
+                   );
+
+osGLOBAL sbit32
+ostiAtomicDecrement(
+                   tiRoot_t        *root,
+                   sbit32 volatile *Addend
+                   );
+
+
+osGLOBAL sbit32
+ostiAtomicBitClear(
+                   tiRoot_t          *root,
+                   sbit32 volatile   *Destination,
+                   sbit32             Value
+                   );
+
+osGLOBAL sbit32
+ostiAtomicBitSet(
+                   tiRoot_t          *root,
+                   sbit32 volatile   *Destination,
+                   sbit32             Value
+                   );
+
+osGLOBAL sbit32
+ostiAtomicExchange(
+                   tiRoot_t         *root,
+                   sbit32 volatile  *Target,
+                   sbit32            Value
+                   );
+
+#else
+
+osGLOBAL FORCEINLINE sbit32
+ostiInterlockedIncrement(
+                   tiRoot_t        *root,
+                   sbit32 volatile *Addend
+                   );
+
+osGLOBAL FORCEINLINE sbit32
+ostiInterlockedDecrement(
+                   tiRoot_t         *root,
+                   sbit32 volatile  *Addend
+                   );
+
+
+osGLOBAL FORCEINLINE sbit32
+ostiInterlockedAnd(
+                   tiRoot_t         *root,
+                   sbit32 volatile  *Destination,
+                   sbit32            Value
+                   );
+
+osGLOBAL FORCEINLINE sbit32
+ostiInterlockedOr(
+                   tiRoot_t         *root,
+                   sbit32 volatile  *Destination,
+                   sbit32            Value
+                   );
+
+osGLOBAL FORCEINLINE sbit32
+ostiInterlockedExchange(
+                   tiRoot_t        *root,
+                   sbit32 volatile *Target,
+                   sbit32           Value
+                   );
+#endif /*LINUX_VERSION_CODE*/
+
+osGLOBAL bit32 ostiAllocMemory(
+                        tiRoot_t    *tiRoot,
+                        void        **osMemHandle,
+                        void        ** virtPtr,
+                        bit32       * physAddrUpper,
+                        bit32       * physAddrLower,
+                        bit32       alignment,
+                        bit32       allocLength,
+                        agBOOLEAN   isCacheable
+                        );
+
+osGLOBAL bit32 ostiFreeMemory(
+                        tiRoot_t    *tiRoot,
+                        void        *osDMAHandle,
+                        bit32       allocLength
+                        );
+
+osGLOBAL FORCEINLINE void ostiCacheFlush(
+                        tiRoot_t    *tiRoot,
+                        void        *osMemHandle,
+                        void        *virtPtr,
+                        bit32       length
+                        );
+
+osGLOBAL FORCEINLINE void ostiCacheInvalidate(
+                        tiRoot_t    *tiRoot,
+                        void        *osMemHandle,
+                        void        *virtPtr,
+                        bit32       length
+                        );
+
+osGLOBAL FORCEINLINE void ostiCachePreFlush(
+                        tiRoot_t    *tiRoot,
+                        void        *osMemHandle,
+                        void        *virtPtr,
+                        bit32       length
+                        );
+
+/*
+ *  The following two functions are for SAS/SATA
+ */
+osGLOBAL void
+ostiInterruptEnable(
+                        tiRoot_t  *ptiRoot,
+                        bit32     channelNum
+                        );
+
+osGLOBAL void
+ostiInterruptDisable(
+                       tiRoot_t  *ptiRoot,
+                       bit32     channelNum
+                       );
+
+osGLOBAL FORCEINLINE bit32
+ostiChipReadBit32Ext(
+                        tiRoot_t  *tiRoot,
+                        bit32     busBaseNumber,
+                        bit32     chipOffset
+                        );
+
+osGLOBAL FORCEINLINE void
+ostiChipWriteBit32Ext(
+                        tiRoot_t  *tiRoot,
+                        bit32     busBaseNumber,
+                        bit32     chipOffset,
+                        bit32     chipValue
+                        );
+
+
+/*****************************************************************************
+ *  Initiator specific Callbacks
+ *****************************************************************************/
+
+/*
+ * Initiator specific IO Completion
+ */
+osGLOBAL void ostiInitiatorIOCompleted(
+                        tiRoot_t            *tiRoot,
+                        tiIORequest_t       *tiIORequest,
+                        tiIOStatus_t        status,
+                        bit32               statusDetail,
+                        tiSenseData_t       *senseData,
+                        bit32               context
+                        );
+
+osGLOBAL tiDeviceHandle_t*
+ostiMapToDevHandle(tiRoot_t  *root,
+                          bit8      pathId,
+                          bit8      targetId,
+                          bit8      LUN
+                          );
+osGLOBAL bit32 ostiSendResetDeviceIoctl(tiRoot_t *root,
+			  void *pccb,
+			  bit8 pathId,
+  			  bit8 targetId,
+			  bit8 lun,
+			  unsigned long resetType
+			);
+
+osGLOBAL void
+ostiGetSenseKeyCount(tiRoot_t  *root,
+                            bit32      fIsClear,
+                            void      *SenseKeyCount,
+                            bit32      length
+                            );
+
+osGLOBAL void
+ostiGetSCSIStatusCount(tiRoot_t  *root,
+                            bit32      fIsClear,
+                            void      *ScsiStatusCount,
+                            bit32      length
+                            );
+
+osGLOBAL bit32
+ostiSetDeviceQueueDepth(tiRoot_t       *tiRoot,
+                                tiIORequest_t  *tiIORequest,
+                                bit32           QueueDepth
+                                );
+
+
+#ifdef FAST_IO_TEST
+typedef void (*ostiFastSSPCb_t)(tiRoot_t     *ptiRoot,
+                                 void         *arg,
+                                 tiIOStatus_t IOStatus,
+                                 bit32         statusDetail);
+
+void osti_FastIOCb(tiRoot_t     *ptiRoot,
+                   void         *arg,
+                   tiIOStatus_t IOStatus,
+                   bit32        statusDetail);
+#endif
+
+osGLOBAL void
+ostiInitiatorSMPCompleted(tiRoot_t    *tiRoot,
+               tiIORequest_t  *tiSMPRequest,
+               tiSMPStatus_t  smpStatus,
+               bit32          tiSMPInfoLen,
+               void           *tiFrameHandle,
+               bit32          context);
+/*
+ * Initiator specific event
+ */
+osGLOBAL void ostiInitiatorEvent (
+                        tiRoot_t            *tiRoot,
+                        tiPortalContext_t   *portalContext,
+                        tiDeviceHandle_t    *tiDeviceHandle,
+                        tiIntrEventType_t   eventType,
+                        bit32               eventStatus,
+                        void                *parm
+                        );
+
+
+/*
+ * PMC-Sierra IOCTL semaphoring
+ */
+osGLOBAL void ostiIOCTLClearSignal (
+                        tiRoot_t    *tiRoot,
+                        void        **agParam1,
+                        void        **agParam2,
+                        void        **agParam3
+                        );
+
+osGLOBAL void ostiIOCTLWaitForSignal (
+                        tiRoot_t    *tigRoot,
+                        void        *agParam1,
+                        void        *agParam2,
+                        void        *agParam3
+                        );
+
+osGLOBAL void ostiIOCTLSetSignal (
+                        tiRoot_t    *tiRoot,
+                        void        *agParam1,
+                        void        *agParam2,
+                        void        *agParam3
+                        );
+
+osGLOBAL void ostiIOCTLWaitForComplete (
+                        tiRoot_t    *tigRoot,
+                        void        *agParam1,
+                        void        *agParam2,
+                        void        *agParam3
+                        );
+
+osGLOBAL void ostiIOCTLComplete (
+                        tiRoot_t    *tiRoot,
+                        void        *agParam1,
+                        void        *agParam2,
+                        void        *agParam3
+                        );
+
+/*****************************************************************************
+ *  Target specific Callbacks
+ *****************************************************************************/
+
+osGLOBAL void ostiProcessScsiReq(
+                        tiRoot_t            *tiRoot,
+                        tiTargetScsiCmnd_t  *tiTgtScsiCmnd,
+                        void                *agFrameHandle,
+                        bit32               immDataLength,
+                        tiIORequest_t       *tiIORequest,
+                        tiDeviceHandle_t    *tiDeviceHandle);
+
+osGLOBAL void ostiNextDataPhase(
+                        tiRoot_t          *tiRoot,
+                        tiIORequest_t     *tiIORequest);
+
+osGLOBAL void ostiTaskManagement (
+                        tiRoot_t          *tiRoot,
+                        bit32             task,
+                        bit8              *scsiLun,
+                        tiIORequest_t     *refTiIORequest,
+                        tiIORequest_t     *tiTMRequest,
+                        tiDeviceHandle_t  *tiDeviceHandle);
+
+osGLOBAL void ostiTargetIOCompleted(
+                        tiRoot_t          *tiRoot,
+                        tiIORequest_t     *tiIORequest,
+                        tiIOStatus_t      status
+                        );
+
+osGLOBAL bit32 ostiTargetEvent (
+                        tiRoot_t          *tiRoot,
+                        tiPortalContext_t *portalContext,
+                        tiDeviceHandle_t  *tiDeviceHandle,
+                        tiTgtEventType_t  eventType,
+                        bit32             eventStatus,
+                        void              *parm
+                        );
+
+osGLOBAL void ostiTargetIOError(
+                        tiRoot_t          *tiRoot,
+                        tiIORequest_t     *tiIORequest,
+                        tiIOStatus_t      status,
+                        bit32             statusDetail
+                        );
+
+osGLOBAL void ostiTargetTmCompleted(
+                        tiRoot_t          *tiRoot,
+                        tiIORequest_t     *tiTmRequest,
+                        tiIOStatus_t      status,
+                        bit32             statusDetail
+                        );
+
+osGLOBAL void ostiPCI_TRIGGER( tiRoot_t *tiRoot );
+
+
+#endif  /* OSTIAPI_H */

sys/dev/pms/RefTisa/tisa/api/tiapi.h

@@ -0,0 +1,586 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+*   tiapi.h
+*
+*   Abstract:   This module contains function prototype of the Transport
+*               Independent API (TIAPI) Layer for both initiator and target.
+** Version Control Information:
+**
+**
+*******************************************************************************/
+
+
+#ifndef TIAPI_H
+#define TIAPI_H
+
+#include <dev/pms/RefTisa/tisa/api/tiglobal.h>
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+
+/*****************************************************************************
+ *  INITIATOR/TARGET SHARED APIs
+ *****************************************************************************/
+
+osGLOBAL void tiCOMGetResource (
+                        tiRoot_t                *tiRoot,
+                        tiLoLevelResource_t     *loResource,
+                        tiInitiatorResource_t   *initiatorResource,
+                        tiTargetResource_t      *targetResource,
+                        tiTdSharedMem_t         *tdSharedMem
+                        );
+
+osGLOBAL bit32 tiCOMInit(
+                        tiRoot_t                *tiRoot,
+                        tiLoLevelResource_t     *loResource,
+                        tiInitiatorResource_t   *initiatorResource,
+                        tiTargetResource_t      *targetResource,
+                        tiTdSharedMem_t         *tdSharedMem
+                        );
+
+osGLOBAL bit32 tiCOMPortInit(
+                        tiRoot_t   *tiRoot,
+                        bit32       sysIntsActive
+                        );
+
+osGLOBAL bit32 tiCOMPortStart(
+                        tiRoot_t          *tiRoot,
+                        bit32             portID,
+                        tiPortalContext_t *portalContext,
+                        bit32             option
+                        );
+
+osGLOBAL void tiCOMShutDown( tiRoot_t    *tiRoot);
+
+osGLOBAL bit32 tiCOMPortStop(
+                        tiRoot_t          *tiRoot,
+                        tiPortalContext_t *portalContext
+                        );
+
+osGLOBAL void tiCOMReset (
+                        tiRoot_t    *tiRoot,
+                        bit32       option
+                        );
+
+osGLOBAL bit32 
+tdsaGetNumOfLUNIOCTL(
+               tiRoot_t            *tiRoot,
+               tiIOCTLPayload_t    *agIOCTLPayload,
+               void                *agParam1,
+               void                *agParam2,
+               void                *agParam3
+               );
+
+osGLOBAL void ostiNumOfLUNIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+osGLOBAL bit32
+tiNumOfLunIOCTLreq(
+             tiRoot_t                       *tiRoot, 
+             tiIORequest_t                  *tiIORequest,
+             tiDeviceHandle_t               *tiDeviceHandle,
+             void                           *tiRequestBody,
+             tiIOCTLPayload_t               *agIOCTLPayload,
+             void                           *agParam1,
+             void                           *agParam2
+             );
+
+
+osGLOBAL FORCEINLINE bit32 tiCOMInterruptHandler(
+                        tiRoot_t    *tiRoot,
+                        bit32       channelNum
+                        );
+
+osGLOBAL FORCEINLINE bit32 tiCOMDelayedInterruptHandler (
+                        tiRoot_t    *tiRoot,
+                        bit32       channelNum,
+                        bit32       count,
+                        bit32       context
+                        );
+
+osGLOBAL bit32  tiCOMLegacyInterruptHandler(
+                        tiRoot_t    *tiRoot,
+                        bit32       channelNum
+                        );
+
+
+osGLOBAL void tiCOMLegacyDelayedInterruptHandler(
+                        tiRoot_t    *tiRoot,
+                        bit32       channelNum,
+                        bit32       count,
+                        bit32       context
+                        );
+osGLOBAL void tiCOMTimerTick( tiRoot_t  *tiRoot );
+
+osGLOBAL void tiCOMSystemInterruptsActive (
+                        tiRoot_t    *tiRoot ,
+                        bit32       sysIntsActive
+                        );
+
+
+osGLOBAL FORCEINLINE void
+tiCOMInterruptEnable(
+                      tiRoot_t * tiRoot,
+                      bit32      channelNum);
+
+osGLOBAL void tiCOMFrameReadBlock(
+                        tiRoot_t          *tiRoot,
+                        void              *agFrame,
+                        bit32             FrameOffset,
+                        void              *FrameBuffer,
+                        bit32             FrameBufLen );
+osGLOBAL bit32 tiCOMEncryptGetInfo(
+                        tiRoot_t            *tiRoot);
+
+osGLOBAL bit32 tiCOMEncryptSetMode(
+                        tiRoot_t            *tiRoot,
+                        bit32               securityCipherMode
+                        );
+
+osGLOBAL bit32  tiCOMSetControllerConfig (
+                    tiRoot_t   *tiRoot,
+                    bit32       modePage,
+                    bit32       length,
+                    void        *buffer,
+                    void        *context
+                    );
+
+osGLOBAL bit32 tiCOMGetControllerConfig(
+                    tiRoot_t    *tiRoot,
+                    bit32       modePage,
+                    bit32       flag,
+                    void        *context
+                    );
+
+
+osGLOBAL bit32 tiCOMEncryptDekAdd(
+                        tiRoot_t            *tiRoot,
+                        bit32               kekIndex,
+                        bit32               dekTableSelect,
+                        bit32               dekAddrHi,
+                        bit32               dekAddrLo,
+                        bit32               dekIndex,
+                        bit32               dekNumberOfEntries,
+                        bit32               dekBlobFormat,
+                        bit32               dekTableKeyEntrySize
+                        );
+
+osGLOBAL bit32 tiCOMEncryptDekInvalidate(
+                        tiRoot_t            *tiRoot,
+                        bit32               dekTable,
+                        bit32               dekIndex
+                        );
+
+
+osGLOBAL bit32 tiCOMEncryptKekAdd(
+                        tiRoot_t            *tiRoot,
+                        bit32               kekIndex,
+                        bit32               wrapperKekIndex,
+                        bit32               blobFormat,
+                        tiEncryptKekBlob_t  *encryptKekBlob
+                        );
+
+osGLOBAL tiDeviceHandle_t *
+tiINIGetExpDeviceHandleBySasAddress(
+                      tiRoot_t          * tiRoot,
+                      tiPortalContext_t * tiPortalContext,
+					  bit32 sas_addr_hi,
+					  bit32 sas_addr_lo,
+					  bit32               maxDevs
+                      );
+
+
+#ifdef HIALEAH_ENCRYPTION 
+osGLOBAL bit32 tiCOMEncryptHilSet(tiRoot_t  *tiRoot );
+#endif /* HIALEAH_ENCRYPTION */
+
+osGLOBAL bit32 tiCOMEncryptKekStore(
+                        tiRoot_t            *tiRoot,
+                        bit32               kekIndex
+                        );
+
+osGLOBAL bit32 tiCOMEncryptKekLoad(
+                        tiRoot_t            *tiRoot,
+                        bit32               kekIndex
+                        );
+
+osGLOBAL bit32 tiCOMEncryptSelfTest(
+                        tiRoot_t  *tiRoot,
+                        bit32     type,
+                        bit32     length,
+                        void      *TestDescriptor
+                        );
+
+osGLOBAL bit32 tiCOMSetOperator(
+                        tiRoot_t      *tiRoot,
+                        bit32          flag,
+                        void           *cert
+                        );
+
+osGLOBAL bit32 tiCOMGetOperator(
+                           tiRoot_t   *tiRoot,
+                           bit32       option,
+                           bit32       AddrHi,
+                           bit32       AddrLo
+                           );
+
+osGLOBAL bit32 tiCOMOperatorManagement(
+                        tiRoot_t            *tiRoot,
+                        bit32                flag,
+                        bit8                 role,
+                        tiID_t              *idString,
+                        tiEncryptKekBlob_t  *kekBlob
+                        );
+
+/*
+ * PMC-Sierra Management IOCTL module
+ */
+osGLOBAL bit32 tiCOMMgntIOCTL(
+                        tiRoot_t            *tiRoot,
+                        tiIOCTLPayload_t    *agIOCTLPayload,
+                        void                *agParam1,
+                        void                *agParam2,
+                        void                *agParam3
+                        );
+
+osGLOBAL void ostiCOMMgntIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+
+osGLOBAL void ostiRegDumpIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+
+osGLOBAL void ostiSetNVMDIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+
+osGLOBAL void ostiGetPhyProfileIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+
+osGLOBAL void ostiGetNVMDIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+osGLOBAL bit32 tiCOMGetPortInfo(
+                        tiRoot_t            *tiRoot,
+                        tiPortalContext_t   *portalContext,
+                        tiPortInfo_t        *tiPortInfo
+                        );
+
+osGLOBAL void ostiSendSMPIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+
+osGLOBAL void ostiGenEventIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status
+                        );
+
+osGLOBAL void
+ostiGetDeviceInfoIOCTLRsp(
+                        tiRoot_t    *tiRoot,
+                        bit32        status,
+                        void        *param
+                        );
+
+osGLOBAL void
+ostiGetIoErrorStatsIOCTLRsp(
+                        tiRoot_t    *tiRoot,
+                        bit32        status,
+                        void        *param
+                        );
+
+osGLOBAL void
+ostiGetIoEventStatsIOCTLRsp(
+                        tiRoot_t    *tiRoot,
+                        bit32        status,
+                        void        *param
+                        );
+
+osGLOBAL void
+ostiGetForensicDataIOCTLRsp(
+                        tiRoot_t    *tiRoot,
+                        bit32        status,
+                        void        *param
+                        );
+
+
+#ifdef SPC_ENABLE_PROFILE
+osGLOBAL void ostiFWProfileIOCTLRsp(
+                        tiRoot_t            *tiRoot,
+                        bit32               status,
+    bit32               len
+                        );
+#endif
+
+/*****************************************************************************
+ *  INITIATOR SPECIFIC APIs
+ *****************************************************************************/
+
+/*
+ * Session management module.
+ */
+osGLOBAL bit32 tiINIGetExpander(
+                  tiRoot_t          * tiRoot,
+                  tiPortalContext_t * tiPortalContext,
+                  tiDeviceHandle_t  * tiDev,
+                  tiDeviceHandle_t  ** tiExp
+                 );
+osGLOBAL bit32 tiINIGetDeviceHandles(
+                        tiRoot_t            *tiRoot,
+                        tiPortalContext_t   *portalContext,
+                        tiDeviceHandle_t    *agDev[],
+                        bit32               maxDevs
+                        );
+
+osGLOBAL bit32 tiINIGetDeviceHandlesForWinIOCTL(
+                        tiRoot_t            *tiRoot,
+                        tiPortalContext_t   *portalContext,
+                        tiDeviceHandle_t    *agDev[],
+                        bit32               maxDevs
+                        );
+
+osGLOBAL void tiIniGetDirectSataSasAddr(tiRoot_t * tiRoot, bit32 phyId, bit8 **sasAddressHi, bit8 **sasAddressLo);
+osGLOBAL bit32 tiINIDiscoverTargets(
+                        tiRoot_t            *tiRoot,
+                        tiPortalContext_t   *portalContext,
+                        bit32               option
+                        );
+
+osGLOBAL bit32 tiINILogin(
+                        tiRoot_t            *tiRoot,
+                        tiDeviceHandle_t    *tiDeviceHandle
+                        );
+
+osGLOBAL bit32 tiINILogout(
+                        tiRoot_t            *tiRoot,
+                        tiDeviceHandle_t    *tiDeviceHandle
+                        );
+
+osGLOBAL bit32 tiINIGetDeviceInfo(
+                        tiRoot_t            *tiRoot,
+                        tiDeviceHandle_t    *tiDeviceHandle,
+                        tiDeviceInfo_t      *tiDeviceInfo);
+
+/*
+ * Transport recovery module.
+ */
+osGLOBAL void tiINITransportRecovery(
+                        tiRoot_t            *tiRoot,
+                        tiDeviceHandle_t    *tiDeviceHandle
+                        );
+
+osGLOBAL bit32 tiINITaskManagement (
+                        tiRoot_t          *tiRoot,
+                        tiDeviceHandle_t  *tiDeviceHandle,
+                        bit32             task,
+                        tiLUN_t           *lun,
+                        tiIORequest_t     *taskTag,
+                        tiIORequest_t     *currentTaskTag
+                        );
+osGLOBAL bit32 tiINISMPStart(
+            tiRoot_t                  *tiRoot,
+            tiIORequest_t             *tiIORequest,
+            tiDeviceHandle_t          *tiDeviceHandle,
+            tiSMPFrame_t              *tiScsiRequest,
+            void                      *tiSMPBody,
+            bit32                     interruptContext
+            );
+/*
+ * I/O module.
+ */
+osGLOBAL bit32 tiINIIOStart(
+                        tiRoot_t                    *tiRoot,
+                        tiIORequest_t               *tiIORequest,
+                        tiDeviceHandle_t            *tiDeviceHandle,
+                        tiScsiInitiatorRequest_t   *tiScsiRequest,
+                        void                        *tiRequestBody,
+                        bit32                       interruptContext
+                        );
+
+osGLOBAL void tiINIDebugDumpIO(
+                        tiRoot_t                  *tiRoot,
+                        tiIORequest_t             *tiIORequest
+                        );
+
+osGLOBAL bit32 tiINIIOStartDif(
+                        tiRoot_t                    *tiRoot,
+                        tiIORequest_t               *tiIORequest,
+                        tiDeviceHandle_t            *tiDeviceHandle,
+                        tiScsiInitiatorRequest_t   *tiScsiRequest,
+                        void                        *tiRequestBody,
+                        bit32                       interruptContext,
+                        tiDif_t                     *difOption
+                        );
+osGLOBAL bit32 tiINISuperIOStart (
+        tiRoot_t                      *tiRoot,
+        tiIORequest_t                 *tiIORequest,
+        tiDeviceHandle_t              *tiDeviceHandle,
+        tiSuperScsiInitiatorRequest_t *tiScsiRequest,
+        void                          *tiRequestBody,
+        bit32                         interruptContext
+        );
+
+#ifdef FAST_IO_TEST
+osGLOBAL void *tiINIFastIOPrepare(
+             tiRoot_t                 *tiRoot,
+             void                     *ioHandle,
+             agsaFastCommand_t        *fc);
+
+osGLOBAL void*
+tiINIFastIOPrepare2(
+            tiRoot_t          *tiRoot,
+            void              *ioHandle,
+            agsaFastCommand_t *fc,
+            void                 *pMessage,
+            void  *pRequest);
+
+osGLOBAL bit32 tiINIFastIOSend(void *ioHandle);
+osGLOBAL bit32 tiINIFastIOCancel(void *ioHandle);
+#endif
+
+osGLOBAL bit32 tiCOMEncryptGetMode(tiRoot_t            *tiRoot);
+osGLOBAL bit32 tiCOMEncryptSetOn_Off(tiRoot_t          *tiRoot, bit32 On);
+
+osGLOBAL bit32 tiInitDevEncrypt(
+        tiRoot_t                      *tiRoot,
+        void                          *tideviceptr );
+
+osGLOBAL bit32 tiTGTSuperIOStart (
+                              tiRoot_t         *tiRoot,
+                              tiIORequest_t    *tiIORequest,
+                              tiSuperScsiTargetRequest_t *tiScsiRequest
+                              );
+
+osGLOBAL void tiINITimerTick(
+                        tiRoot_t            *tiRoot
+                        );
+
+
+osGLOBAL bit32 tiINIIOAbort(
+                        tiRoot_t            *tiRoot,
+                        tiIORequest_t       *taskTag
+                        );
+
+osGLOBAL bit32 tiINIIOAbortAll(
+                        tiRoot_t            *tiRoot,
+                        tiDeviceHandle_t    *tiDeviceHandle
+                        );
+/*
+ * Event Logging module
+ */
+osGLOBAL bit32 tiINIReportErrorToEventLog(
+                        tiRoot_t            *tiRoot,
+                        tiEVTData_t         *agEventData
+                        );
+
+
+/*****************************************************************************
+ *  TARGET SPECIFIC APIs
+ *****************************************************************************/
+
+osGLOBAL void tiTGTTimerTick(
+                        tiRoot_t  *tiRoot
+                        );
+
+osGLOBAL void *tiTGTSenseBufferGet(
+                        tiRoot_t        *tiRoot,
+                        tiIORequest_t   *tiIORequest,
+                        bit32           length
+                        );
+
+osGLOBAL void tiTGTSetResp(
+                        tiRoot_t        *tiRoot,
+                        tiIORequest_t   *tiIORequest,
+                        bit32           dataSentLength,
+                        bit8            ScsiStatus,
+                        bit32           senseLength
+                        );
+
+osGLOBAL bit32 tiTGTIOStart (
+                        tiRoot_t        *tiRoot,
+                        tiIORequest_t   *tiIORequest,
+                        bit32           dataOffset,
+                        bit32           dataLength,
+                        tiSgl_t         *dataSGL,
+                        void            *sglVirtualAddr
+                        );
+
+osGLOBAL bit32 tiTGTIOStartMirror (
+                        tiRoot_t        *tiRoot,
+                        tiIORequest_t   *tiIORequest,
+                        bit32           dataOffset,
+                        bit32           dataLength,
+                        tiSgl_t         *dataSGL,
+                        void            *sglVirtualAddr,
+                        tiSgl_t         *dataSGLMirror,
+                        void            *sglVirtualAddrMirror
+                        );
+
+osGLOBAL bit32 tiTGTIOStartDif (
+                        tiRoot_t        *tiRoot,
+                        tiIORequest_t   *tiIORequest,
+                        bit32           dataOffset,
+                        bit32           dataLength,
+                        tiSgl_t         *dataSGL,
+                        void            *sglVirtualAddr,
+                        tiDif_t         *difOption
+                        );
+
+
+osGLOBAL bit32 tiTGTGetDeviceHandles(
+                        tiRoot_t          *tiRoot,
+                        tiPortalContext_t *portalContext,
+                        tiDeviceHandle_t  *agDev[],
+                        bit32             maxDevs
+                        );
+
+osGLOBAL bit32 tiTGTGetDeviceInfo(
+                        tiRoot_t            *tiRoot,
+                        tiDeviceHandle_t    *tiDeviceHandle,
+                        tiDeviceInfo_t      *tiDeviceInfo);
+
+osGLOBAL bit32 tiTGTIOAbort(
+                        tiRoot_t            *tiRoot,
+                        tiIORequest_t       *taskTag
+                        );
+
+osGLOBAL bit32 tiTGTSendTmResp (
+                        tiRoot_t          *tiRoot,
+                        tiIORequest_t     *tiTMRequest,
+                        bit32             status
+                        );
+
+void tiPCI_TRIGGER( tiRoot_t        *tiRoot);
+
+void tiComCountActiveIORequests( tiRoot_t        *tiRoot);
+
+#endif  /* TIAPI_H */

sys/dev/pms/RefTisa/tisa/api/tidefs.h

@@ -0,0 +1,610 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+**
+** Version Control Information:
+**
+**
+*******************************************************************************/
+/********************************************************************************
+**    
+*   tidefs.h 
+*
+*   Abstract:   This module contains enum and #define definition used
+*               by Transport Independent API (TIAPI) Layer.
+*     
+********************************************************************************/
+
+#ifndef TIDEFS_H
+
+#define TIDEFS_H
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+/*****************************************************************************
+ *  INITIATOR/TARGET SHARED DEFINES AND ENUMS
+ *****************************************************************************/
+
+/*
+ *  Option mask parameter for tiCOMPortStart() 
+ */
+#define PORTAL_ADD_MASK   0x00000001
+
+/* 
+ * Maximum memory descriptor for Low-Level layer.
+ */
+#define MAX_LL_LAYER_MEM_DESCRIPTORS  64
+
+
+/* 
+ * TI API function return types 
+ */
+typedef enum
+{
+  tiSuccess,
+  tiError,
+  tiBusy,
+  tiIONoDevice,
+  tiMemoryTooLarge,
+  tiMemoryNotAvail,
+  tiInvalidHandle,
+  tiNotSupported,
+  tiReject,
+  tiIncorrectLun,
+  tiDeviceBusy,
+} tiStatus_t;
+
+/*
+ * Type of memory, OR-ed the bit fields.
+ */
+
+/* Bit 0-1, cached or dma-uncached dma-cached */
+
+#define TI_DMA_MEM        0x00000000      /* uncached DMA capable memory   */
+#define TI_CACHED_MEM     0x00000001      /* cached non-DMA capable memory */
+#define TI_CACHED_DMA_MEM 0x00000002      /* cached DMA capable memory */
+#define TI_DMA_MEM_CHIP   0x00000003      /* Internal HW/chip memory  */
+
+/* Bit2-3: location of memory */
+#define TI_LOC_HOST     0x00000000      /* default, allocated from host */
+#define TI_LOC_ON_CHIP  0x00000004      /* memory is from on-chip RAM   */
+#define TI_LOC_ON_CARD  0x00000008      /* memory is from on-card RAM   */
+
+/* Type of SGL list
+ *
+ */
+typedef enum
+{
+  tiSgl=0,
+  tiSglList=0x80000000,
+  tiExtHdr
+}tiSglType_t;
+
+/* 
+ * Type of mutex semaphoring/synchronization
+ */
+typedef enum
+{
+  tiSingleMutexLockPerPort,
+  tiOneMutexLockPerQueue
+}tiMutexType_t;
+
+/* 
+ * Context (interrupt or non-interrupt)
+ */
+typedef enum
+{
+  tiInterruptContext,
+  tiNonInterruptContext
+}tiIntContextType_t;
+
+/*
+ * Port Event type.
+ */
+typedef enum
+{
+  tiPortPanic,
+  tiPortResetComplete,
+  tiPortNameServerDown,
+  tiPortLinkDown,
+  tiPortLinkUp,
+  tiPortStarted,
+  tiPortStopped,
+  tiPortShutdown,
+  tiPortDiscoveryReady,
+  tiPortResetNeeded,
+  tiEncryptOperation,
+  tiModePageOperation
+} tiPortEvent_t;
+
+/*
+ * tiEncryptOperation Event types
+ */
+typedef enum
+{
+  tiEncryptGetInfo,
+  tiEncryptSetMode,
+  tiEncryptKekAdd,
+  tiEncryptDekInvalidate,
+  tiEncryptKekStore,
+  tiEncryptKekLoad,
+  tiEncryptAttribRegUpdate,
+  tiEncryptDekAdd,
+  /* new */
+  tiEncryptOperatorManagement,
+  tiEncryptSelfTest,
+  tiEncryptSetOperator,
+  tiEncryptGetOperator
+} tiEncryptOp_t;
+
+/* 
+ * ostiPortEvent() status values for tiCOMOperatorManagement()
+ */
+typedef enum
+{
+  tiOMNotSupported,
+  tiOMIllegalParam,
+  tiOMKENUnwrapFail,
+  tiOMNvramOpFailure,
+} tiOperatorManagementStatus_t;
+
+/* 
+ * ostiInitiatorIOCompleted() and ostiTargetIOError() status values 
+ */
+typedef enum
+{
+  tiIOSuccess,
+  tiIOOverRun,
+  tiIOUnderRun,
+  tiIOFailed,
+  tiIODifError,
+  tiIOEncryptError,
+} tiIOStatus_t;
+
+/* 
+ * ostiInitiatorIOCompleted() and ostiTargetIOError() statusDetail values 
+ */
+typedef enum
+{
+  tiSMPSuccess,
+  tiSMPAborted,
+  tiSMPFailed,
+} tiSMPStatus_t;
+
+typedef enum
+{
+  tiDetailBusy,
+  tiDetailNotValid,
+  tiDetailNoLogin,
+  tiDetailAbortLogin,
+  tiDetailAbortReset,
+  tiDetailAborted,
+  tiDetailDifMismatch,
+  tiDetailDifAppTagMismatch,
+  tiDetailDifRefTagMismatch,
+  tiDetailDifCrcMismatch,
+  tiDetailDekKeyCacheMiss,
+  tiDetailCipherModeInvalid,
+  tiDetailDekIVMismatch,
+  tiDetailDekRamInterfaceError,
+  tiDetailDekIndexOutofBounds,
+  tiDetailOtherError,
+  tiDetailOtherErrorNoRetry,
+} tiIOStatusDetail_t;
+
+/* 
+ * IOCTL Status Codes
+ */
+#define IOCTL_ERR_STATUS_OK                  0x00
+#define IOCTL_ERR_STATUS_MORE_DATA           0x01
+#define IOCTL_ERR_STATUS_NO_MORE_DATA        0x02
+#define IOCTL_ERR_STATUS_INVALID_CODE        0x03
+#define IOCTL_ERR_STATUS_INVALID_DEVICE      0x04
+#define IOCTL_ERR_STATUS_NOT_RESPONDING      0x05
+#define IOCTL_ERR_STATUS_INTERNAL_ERROR      0x06
+#define IOCTL_ERR_STATUS_NOT_SUPPORTED       0x07
+#define IOCTL_ERR_FW_EVENTLOG_DISABLED       0x08
+#define IOCTL_MJ_FATAL_ERROR_SOFT_RESET_TRIG 0x72
+#define IOCTL_MJ_FATAL_ERR_CHK_SEND_TRUE     0x77
+#define IOCTL_MJ_FATAL_ERR_CHK_SEND_FALSE    0x76
+#define IOCTL_ERROR_NO_FATAL_ERROR           0x77
+
+#define ADAPTER_WWN_START_OFFSET	     0x804
+#define ADAPTER_WWN_END_OFFSET		     0x80b
+#define ADAPTER_WWN_SPC_START_OFFSET	     0x704
+#define ADAPTER_WWN_SPC_END_OFFSET	     0x70b
+
+/*
+ * IOCTL Return Codes 
+ */
+#define IOCTL_CALL_SUCCESS                  0x00
+#define IOCTL_CALL_FAIL                     0x01
+#define IOCTL_CALL_PENDING                  0x02
+#define IOCTL_CALL_INVALID_CODE             0x03
+#define IOCTL_CALL_INVALID_DEVICE           0x04
+#define IOCTL_CALL_TIMEOUT                  0x08
+
+/*
+ * DIF operation
+ */
+#define DIF_INSERT                0
+#define DIF_VERIFY_FORWARD        1
+#define DIF_VERIFY_DELETE         2
+#define DIF_VERIFY_REPLACE        3
+
+#define DIF_UDT_SIZE              6
+
+/*
+ * Login state in tiDeviceInfo_t
+ */
+#define INI_LGN_STATE_FREE            0x00000000
+#define INI_LGN_STATE_LOGIN           0x00000001
+#define INI_LGN_STATE_FAIL            0x00000002
+#define INI_LGN_STATE_OTHERS          0x0000000F
+
+/*
+ * SecurityCipherMode in tiEncryptInfo_t and tiCOMEncryptSetMode()
+ */
+#define TI_ENCRYPT_SEC_MODE_FACT_INIT 0x00000000
+#define TI_ENCRYPT_SEC_MODE_A         0x40000000
+#define TI_ENCRYPT_SEC_MODE_B         0x80000000
+#define TI_ENCRYPT_ATTRIB_ALLOW_SMF   0x00000200
+#define TI_ENCRYPT_ATTRIB_AUTH_REQ    0x00000100
+#define TI_ENCRYPT_ATTRIB_CIPHER_XTS  0x00000002
+#define TI_ENCRYPT_ATTRIB_CIPHER_ECB  0x00000001
+
+/*
+ * Status in tiEncryptInfo_t 
+ */
+#define TI_ENCRYPT_STATUS_NO_NVRAM        0x00000001
+#define TI_ENCRYPT_STATUS_NVRAM_ERROR     0x00000002
+#define TI_ENCRYPT_STATUS_ENGINE_ERROR    0x00000004
+
+/*
+ * EncryptMode in tiEncrypt_t
+ */
+#define TI_ENCRYPT_MODE_XTS_AES       0x00400000
+#define TI_ENCRYPT_MODE_ECB_AES       0x00000000
+
+/*
+ * Encrypt blob types
+ */
+#define TI_PLAINTEXT          0
+#define TI_ENCRYPTED_KEK_PMCA 1
+#define TI_ENCRYPTED_KEK_PMCB 2
+
+/*
+ * Encrypt DEK table key entry sizes
+ */
+#define TI_DEK_TABLE_KEY_SIZE16 0
+#define TI_DEK_TABLE_KEY_SIZE24 1
+#define TI_DEK_TABLE_KEY_SIZE32 2
+#define TI_DEK_TABLE_KEY_SIZE40 3
+#define TI_DEK_TABLE_KEY_SIZE48 4
+#define TI_DEK_TABLE_KEY_SIZE56 5
+#define TI_DEK_TABLE_KEY_SIZE64 6
+#define TI_DEK_TABLE_KEY_SIZE72 7
+#define TI_DEK_TABLE_KEY_SIZE80 8
+
+/* KEK blob size and DEK blob size and host DEK table entry number */
+#define TI_KEK_BLOB_SIZE           48
+#define TI_KEK_MAX_TABLE_ENTRIES   8
+
+#define TI_DEK_MAX_TABLES          2
+#define TI_DEK_MAX_TABLE_ENTRIES   (1024*4)
+
+#define TI_DEK_BLOB_SIZE           80
+
+
+/************************************************************
+*  tiHWEventMode_t page operation definitions
+************************************************************/
+#define tiModePageGet                                    1
+#define tiModePageSet                                    2
+
+/* controller configuration page code */
+#define TI_SAS_PROTOCOL_TIMER_CONFIG_PAGE     0x04
+#define TI_INTERRUPT_CONFIGURATION_PAGE       0x05
+#define TI_ENCRYPTION_GENERAL_CONFIG_PAGE     0x20
+#define TI_ENCRYPTION_DEK_CONFIG_PAGE         0x21
+#define TI_ENCRYPTION_CONTROL_PARM_PAGE       0x22
+#define TI_ENCRYPTION_HMAC_CONFIG_PAGE        0x23
+
+
+/* encryption self test type */
+#define TI_ENCRYPTION_TEST_TYPE_BIST          0x01
+#define TI_ENCRYPTION_TEST_TYPE_HMAC          0x02
+
+/* SHA algorithm type */
+#define TI_SHA_ALG_1                          0x04
+#define TI_SHA_ALG_256                        0x08
+#define TI_SHA_ALG_224                        0x10
+#define TI_SHA_ALG_512                        0x20
+#define TI_SHA_ALG_384                        0x40
+
+#define TI_SHA_1_DIGEST_SIZE                    20
+#define TI_SHA_256_DIGEST_SIZE                  32
+#define TI_SHA_224_DIGEST_SIZE                  28
+#define TI_SHA_512_DIGEST_SIZE                  64
+#define TI_SHA_384_DIGEST_SIZE                  48
+
+
+/*****************************************************************************
+ *  INITIATOR SPECIFIC DEFINES AND ENUMS
+ *****************************************************************************/
+
+/* 
+ * ostiInitiatorIOCompleted() statusDetail contains SCSI status,
+ * when status passed in ostiInitiatorIOCompleted() is tiIOSuccess.
+ */
+#define SCSI_STAT_GOOD              0x00
+#define SCSI_STAT_CHECK_CONDITION   0x02
+#define SCSI_STAT_CONDITION_MET     0x04
+#define SCSI_STAT_BUSY              0x08
+#define SCSI_STAT_INTERMEDIATE      0x10
+#define SCSI_STAT_INTER_CONDIT_MET  0x14
+#define SCSI_STAT_RESV_CONFLICT     0x18
+#define SCSI_STAT_COMMANDTERMINATED 0x22
+#define SCSI_STAT_TASK_SET_FULL     0x28
+#define SCSI_STAT_ACA_ACTIVE        0x30
+#define SCSI_STAT_TASK_ABORTED      0x40
+
+/*
+01: soft error 
+02: not ready 
+03: medium error 
+04: hardware error 
+05: illegal request 
+06: unit attention 
+0b: abort command 
+*/ 
+#define SCSI_SENSE_KEY_NO_SENSE         0x00
+#define SCSI_SENSE_KEY_RECOVERED_ERROR  0x01
+#define SCSI_SENSE_KEY_NOT_READY        0x02
+#define SCSI_SENSE_KEY_MEDIUM_ERROR     0x03
+#define SCSI_SENSE_KEY_HARDWARE_ERROR   0x04
+#define SCSI_SENSE_KEY_ILLEGAL_REQUEST  0x05
+#define SCSI_SENSE_KEY_UNIT_ATTENTION   0x06
+#define SCSI_SENSE_KEY_DATA_PROTECT     0x07
+#define SCSI_SENSE_KEY_BLANK_CHECK      0x08
+#define SCSI_SENSE_KEY_UNIQUE           0x09
+#define SCSI_SENSE_KEY_COPY_ABORTED     0x0A
+#define SCSI_SENSE_KEY_ABORTED_COMMAND  0x0B
+#define SCSI_SENSE_KEY_EQUAL            0x0C
+#define SCSI_SENSE_KEY_VOL_OVERFLOW     0x0D
+#define SCSI_SENSE_KEY_MISCOMPARE       0x0E
+#define SCSI_SENSE_KEY_RESERVED         0x0F
+
+
+
+
+/* 
+ * Reset option in tiCOMReset() 
+ */
+typedef enum
+{
+  tiSoftReset,
+  tiHardReset,
+  tiAutoReset
+} tiReset_t;
+
+/* 
+ * Bit 0 Mask for the persistent option in tiINIDiscoverTargets() 
+ */
+#define NORMAL_ASSIGN_MASK            0x00000000
+#define FORCE_PERSISTENT_ASSIGN_MASK  0x00000001
+
+/* 
+ * Bit 1 Mask for the auto login option in tiINIDiscoverTargets() 
+ */
+#define AUTO_LOGIN_MASK               0x00000000
+#define NO_AUTO_LOGIN_MASK            0x00000002
+
+
+/* 
+ * Task Management task used in tiINITaskManagement()
+ *
+ * 1 AG_ABORT TASK - aborts the task identified by the Referenced  Task Tag field.
+ * 2 AG_ABORT TASK SET - aborts all Tasks issued by this initiator on the Logical Unit 
+ * 3 AG_CLEAR ACA - clears the Auto Contingent Allegiance condition.
+ * 4 AG_CLEAR TASK SET - Aborts all Tasks (from all initiators) for the Logical Unit.
+ * 5 AG_LOGICAL UNIT RESET 
+ * 6 AG_TARGET WARM RESET  - iSCSI only
+ * 7 AG_TARGET_COLD_RESET  - iSCSI only
+ * 8 AG_TASK_REASSIGN      - iSCSI only
+ * 9 AG_QUERY_TASK         - SAS only
+ */
+
+#define AG_ABORT_TASK          1
+#define AG_ABORT_TASK_SET      2
+#define AG_CLEAR_ACA           3
+#define AG_CLEAR_TASK_SET      4
+#define AG_LOGICAL_UNIT_RESET  5
+#define AG_TARGET_WARM_RESET   6    /* iSCSI only */
+#define AG_TARGET_COLD_RESET   7    /* iSCSI only */
+#define AG_TASK_REASSIGN       8    /* iSCSI only */
+#define AG_QUERY_TASK          9    /* SAS only   */
+
+
+/*
+ * Event types for ostiInitiatorEvent()
+ */
+typedef enum
+{
+  tiIntrEventTypeCnxError,
+  tiIntrEventTypeDiscovery,
+  tiIntrEventTypeTransportRecovery,
+  tiIntrEventTypeTaskManagement,
+  tiIntrEventTypeDeviceChange,
+  tiIntrEventTypeLogin,
+  tiIntrEventTypeLocalAbort  
+} tiIntrEventType_t;
+
+/*
+ * Event status for ostiInitiatorEvent()
+ */
+typedef enum
+{
+  tiCnxUp,
+  tiCnxDown
+} tiCnxEventStatus_t;
+
+typedef enum
+{
+  tiDiscOK,
+  tiDiscFailed
+} tiDiscEventStatus_t;
+
+typedef enum
+{
+  tiLoginOK,
+  tiLoginFailed,
+  tiLogoutOK,
+  tiLogoutFailed
+} tiLoginEventStatus_t;
+
+typedef enum
+{
+  tiRecOK,
+  tiRecFailed,
+  tiRecStarted
+} tiRecEventStatus_t;
+
+typedef enum
+{
+  tiTMOK,
+  tiTMFailed
+} tiTMEventStatus_t;
+
+typedef enum
+{
+  tiDeviceRemoval,
+  tiDeviceArrival,
+  tiDeviceLoginReceived
+} tiDevEventStatus_t;
+
+typedef enum
+{
+  tiAbortOK,
+  tiAbortFailed,
+  tiAbortDelayed,  
+  tiAbortInProgress
+} tiAbortEventStatus_t;
+
+/* 
+ * SCSI SAM-2 Task Attribute
+ */
+#define TASK_UNTAGGED       0       /* Untagged      */
+#define TASK_SIMPLE         1       /* Simple        */
+#define TASK_ORDERED        2       /* Ordered       */
+#define TASK_HEAD_OF_QUEUE  3       /* Head of Queue */
+#define TASK_ACA            4       /* ACA           */
+
+/*
+ * Data direction for I/O request
+ */
+typedef enum
+{
+  tiDirectionIn   = 0x0000,
+  tiDirectionOut  = 0x0001
+}tiDataDirection_t;
+
+/*
+ * NVRAM error subEvents for encryption 
+ */
+typedef enum
+{
+    tiNVRAMSuccess       = 0x0000,
+    tiNVRAMWriteFail     = 0x0001,
+    tiNVRAMReadFail      = 0x0002,
+    tiNVRAMNotFound      = 0x0003,
+    tiNVRAMAccessTimeout = 0x0004
+}tiEncryptSubEvent_t;
+
+/* Event Logging */
+
+/* Event Severity Codes */
+#define IOCTL_EVT_SEV_OFF            0x00
+#define IOCTL_EVT_SEV_ALWAYS_ON      0x01
+#define IOCTL_EVT_SEV_ERROR          0x02
+#define IOCTL_EVT_SEV_WARNING        0x03
+#define IOCTL_EVT_SEV_INFORMATIONAL  0x04
+#define IOCTL_EVT_SEV_DEBUG_L1       0x05
+#define IOCTL_EVT_SEV_DEBUG_L2       0x06
+#define IOCTL_EVT_SEV_DEBUG_L3       0x07
+
+/* Event Source */
+#define IOCTL_EVT_SRC_HW            0xF0000000
+#define IOCTL_EVT_SRC_ITSDK         0x0F000000
+#define IOCTL_EVT_SRC_FW            0x00F00000
+#define IOCTL_EVT_SRC_TD_LAYER      0x000F0000
+#define IOCTL_EVT_SRC_TARGET        0x0000F000
+#define IOCTL_EVT_SRC_OSLAYER       0x00000F00
+#define IOCTL_EVT_SRC_RESERVED      0x000000F0
+#define IOCTL_EVT_SRC_RESERVED1     0x0000000F
+/* Event Shifter */
+#define IOCTL_EVT_SRC_HW_SHIFTER            28
+#define IOCTL_EVT_SRC_ITSDK_SHIFTER         24
+#define IOCTL_EVT_SRC_FW_SHIFTER            20
+#define IOCTL_EVT_SRC_COMMON_LAYER_SHIFTER  16
+#define IOCTL_EVT_SRC_TARGET_SHIFTER        12
+#define IOCTL_EVT_SRC_OSLAYER_SHIFTER       8
+#define IOCTL_EVT_SRC_RESERVED_SHIFTER      4
+#define IOCTL_EVT_SRC_RESERVED1_SHIFTER     0
+
+#define EVENTLOG_MAX_MSG_LEN          110
+
+#define EVENT_ID_MAX        0xffffffff
+
+#define DISCOVERY_IN_PROGRESS 0xFFFFFFFF
+
+#define TI_SSP_INDIRECT_CDB_SIZE         64
+/*
+ * Flags in tiSuperScsiInitiatorRequest_t
+ */
+#define TI_SCSI_INITIATOR_DIF             0x00000001
+#define TI_SCSI_INITIATOR_ENCRYPT         0x00000002
+#define TI_SCSI_INITIATOR_INDIRECT_CDB    0x00000004
+/*****************************************************************************
+ *  TARGET SPECIFIC DEFINES AND ENUMS
+ *****************************************************************************/
+
+/*
+ * Event types for ostiTargetEvent()
+ */
+typedef enum
+{
+  tiTgtEventTypeCnxError,
+  tiTgtEventTypeDeviceChange
+} tiTgtEventType_t;
+
+/*
+ * Flags in tiSuperScsiTargetRequest_t
+ */
+#define TI_SCSI_TARGET_DIF         0x00000001
+#define TI_SCSI_TARGET_MIRROR      0x00000002
+#define TI_SCSI_TARGET_ENCRYPT     0x00000004
+#endif  /* TIDEFS_H */

sys/dev/pms/RefTisa/tisa/api/tiglobal.h

@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+ ********************************************************************************/
+/********************************************************************************
+ **
+ **   tiglobal.h
+ **
+ **   Abstract:
+ **
+ ********************************************************************************/
+
+
+#ifndef TIGLOBAL_H
+#define TIGLOBAL_H
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#ifndef TIDEBUG_MSG
+#define TIDEBUG_MSG(mask, val, format)
+#endif
+
+extern bit32 gTiDebugLevel;
+
+#define TI_DBG0(a)    TIDEBUG_MSG0(a) /* always print */
+
+#define TI_DBG1(a)    TIDEBUG_MSG(gTiDebugLevel,1, a )
+#define TI_DBG2(a)    TIDEBUG_MSG(gTiDebugLevel,2, a )
+#define TI_DBG3(a)    TIDEBUG_MSG(gTiDebugLevel,3, a )
+#define TI_DBG4(a)    TIDEBUG_MSG(gTiDebugLevel,4, a )
+#define TI_DBG5(a)    TIDEBUG_MSG(gTiDebugLevel,5, a ) /* OsDebugLevel 4 */
+#define TI_DBG6(a)    TIDEBUG_MSG(gTiDebugLevel,6, a ) 
+#define TI_DBG7(a)    
+
+extern bit32 gTiDebugMask;
+#define TI_BIT1(a)    TIDEBUG_MSG(gTiDebugMask,0x00000001, a )
+#define TI_BIT2(a)    TIDEBUG_MSG(gTiDebugMask,0x00000002, a )
+#define TI_BIT3(a)    TIDEBUG_MSG(gTiDebugMask,0x00000004, a )
+#define TI_BIT4(a)    TIDEBUG_MSG(gTiDebugMask,0x00000008, a )
+#define TI_BIT5(a)    TIDEBUG_MSG(gTiDebugMask,0x00000010, a )
+#define TI_BIT6(a)    TIDEBUG_MSG(gTiDebugMask,0x00000020, a )
+
+
+
+#endif  /* TIGLOBAL_H */

sys/dev/pms/RefTisa/tisa/api/tiscsi.h

@@ -0,0 +1,61 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+**
+** Version Control Information:
+**
+**
+*******************************************************************************/
+/********************************************************************************
+**    
+**   tiscsi.h
+**
+**   Abstract:   This module contains SCSI related data structure definition.
+**     
+********************************************************************************/
+
+#ifndef TISCSI_H
+#define TISCSI_H
+
+
+/*
+ * SCSI Sense Data
+ */
+typedef struct 
+{
+  bit8       snsRespCode;
+  bit8       snsSegment;
+  bit8       senseKey;          /* sense key                                */
+  bit8       info[4];
+  bit8       addSenseLen;       /* 11 always                                */
+  bit8       cmdSpecific[4];
+  bit8       addSenseCode;      /* additional sense code                    */
+  bit8       senseQual;         /* additional sense code qualifier          */
+  bit8       fru;
+  bit8       skeySpecific[3];
+} scsiRspSense_t;
+
+
+
+#endif  /* TISCSI_H */

sys/dev/pms/RefTisa/tisa/api/titypes.h

@@ -0,0 +1,636 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/********************************************************************************
+**
+** Version Control Information:
+**
+**
+*******************************************************************************/
+/********************************************************************************
+**
+**   titypes.h
+**
+**   Abstract:   This module contains data structure definition used
+**               by the Transport Independent API (TIAPI) Layer.
+**
+********************************************************************************/
+
+#include <dev/pms/RefTisa/tisa/api/tidefs.h>
+
+#ifndef TITYPES_H
+#define TITYPES_H
+
+/*****************************************************************************
+ * SHARED TYPES
+ *****************************************************************************/
+
+typedef struct tiPortalContext
+{
+  void    *osData;
+  void    *tdData;
+} tiPortalContext_t;
+
+typedef struct tiDeviceHandle
+{
+  void    *osData;
+  void    *tdData;
+} tiDeviceHandle_t;
+
+typedef struct tiRoot
+{
+  void    *osData;
+  void    *tdData;
+} tiRoot_t;
+
+typedef struct tiMem
+{
+  void    *virtPtr;
+  void    *osHandle;
+  bit32   physAddrUpper;
+  bit32   physAddrLower;
+  bit32   totalLength;
+  bit32   numElements;
+  bit32   singleElementLength;
+  bit32   alignment;
+  bit32   type;
+  bit32   reserved;
+} tiMem_t;
+
+typedef struct tiLoLevelMem
+{
+  bit32       count;
+  tiMem_t     mem[MAX_LL_LAYER_MEM_DESCRIPTORS];
+} tiLoLevelMem_t;
+
+typedef struct tiLoLevelOption
+{
+  bit32       usecsPerTick;
+  bit32       numOfQueuesPerPort;
+  bit32       mutexLockUsage;
+  bit32       pciFunctionNumber;
+  bit32       maxPortContext;
+  bit32       maxNumOSLocks;
+  agBOOLEAN   encryption;
+  bit32       maxInterruptVectors;
+  bit32       flag;
+  bit32       max_MSI_InterruptVectors;
+#ifdef SA_ENABLE_PCI_TRIGGER
+  bit32       PCI_trigger; 
+#endif /* SA_ENABLE_PCI_TRIGGER */
+
+} tiLoLevelOption_t;
+
+typedef struct tiLoLevelResource
+{
+  tiLoLevelOption_t   loLevelOption;
+  tiLoLevelMem_t      loLevelMem;
+} tiLoLevelResource_t;
+
+typedef struct tiTdSharedMem
+{
+  tiMem_t     tdSharedCachedMem1;
+} tiTdSharedMem_t;
+
+typedef struct tiIORequest
+{
+  void    *osData;
+  void    *tdData;
+} tiIORequest_t;
+
+typedef struct tiSgl_s
+{
+  bit32   lower;
+  bit32   upper;
+  bit32   len;
+  bit32   type;
+} tiSgl_t;
+
+typedef struct tiSenseData
+{
+  void    *senseData;
+  bit8    senseLen;
+} tiSenseData_t;
+
+typedef struct tiIOCTLPayload
+{
+  bit32       Signature;
+  bit16       MajorFunction;
+  bit16       MinorFunction;
+  bit16       Length;
+  bit16       Status;
+  bit32       Reserved; /* required for 64 bit alignment */
+  bit8        FunctionSpecificArea[1];
+}tiIOCTLPayload_t;
+
+
+typedef struct tiIOCTLPayload_wwn
+{
+  bit32       Signature;
+  bit16       MajorFunction;
+  bit16       MinorFunction;
+  bit16       Length;
+  bit16       Status;
+  bit32       Reserved; /* required for 64 bit alignment */
+  bit8        FunctionSpecificArea[8];
+}tiIOCTLPayload_wwn_t;
+
+typedef struct tiPortInfo
+{
+  char  *name;
+  char  *address;
+  char  *localName;
+  char  *remoteName;
+  bit32 localNameLen;
+  bit32 remoteNameLen;
+} tiPortInfo_t;
+
+typedef struct tiDif_s
+{
+  agBOOLEAN   enableDIFPerLA;
+  bit32       flags;
+  bit16       initialIOSeed;
+  bit16       reserved;
+  bit32       DIFPerLAAddrLo;
+  bit32       DIFPerLAAddrHi;
+  bit16       DIFPerLARegion0SecCount;
+  bit16       DIFPerLANumOfRegions;
+  bit8        udtArray[DIF_UDT_SIZE];
+  bit8        udtrArray[DIF_UDT_SIZE];
+} tiDif_t;
+
+#define DIF_INSERT                  0
+#define DIF_VERIFY_FORWARD          1
+#define DIF_VERIFY_DELETE           2
+#define DIF_VERIFY_REPLACE          3
+#define DIF_VERIFY_UDT_REPLACE_CRC  5
+#define DIF_REPLACE_UDT_REPLACE_CRC 7
+
+#define DIF_BLOCK_SIZE_512          0x00
+#define DIF_BLOCK_SIZE_520          0x01
+#define DIF_BLOCK_SIZE_4096         0x02
+#define DIF_BLOCK_SIZE_4160         0x03
+
+#define DIF_ACTION_FLAG_MASK        0x00000007 /* 0 - 2 */
+#define DIF_CRC_VERIFICATION        0x00000008 /* 3 */
+#define DIF_CRC_INVERSION           0x00000010 /* 4 */
+#define DIF_CRC_IO_SEED             0x00000020 /* 5 */
+#define DIF_UDT_REF_BLOCK_COUNT     0x00000040 /* 6 */
+#define DIF_UDT_APP_BLOCK_COUNT     0x00000080 /* 7 */
+#define DIF_UDTR_REF_BLOCK_COUNT    0x00000100 /* 8 */
+#define DIF_UDTR_APP_BLOCK_COUNT    0x00000200 /* 9 */
+#define DIF_CUST_APP_TAG            0x00000C00 /* 10 - 11 */
+#define DIF_FLAG_RESERVED           0x0000F000 /* 12 - 15 */
+#define DIF_DATA_BLOCK_SIZE_MASK    0x000F0000 /* 16 - 19 */
+#define DIF_DATA_BLOCK_SIZE_SHIFT   16
+#define DIF_TAG_VERIFY_MASK         0x03F00000 /* 20 - 25 */
+#define DIF_TAG_UPDATE_MASK         0xFC000000 /* 26 - 31 */
+
+
+#define NORMAL_BLOCK_SIZE_512       512
+#define NORMAL_BLOCK_SIZE_4K        4096
+
+#define DIF_PHY_BLOCK_SIZE_512      512
+#define DIF_PHY_BLOCK_SIZE_520      520
+#define DIF_PHY_BLOCK_SIZE_4096     4096
+#define DIF_PHY_BLOCK_SIZE_4160     4160
+
+#define DIF_LOGIC_BLOCK_SIZE_520    520
+#define DIF_LOGIC_BLOCK_SIZE_528    528
+#define DIF_LOGIC_BLOCK_SIZE_4104   4104
+#define DIF_LOGIC_BLOCK_SIZE_4168   4168
+
+
+
+
+typedef struct tiDetailedDeviceInfo
+{
+  bit8    devType_S_Rate;
+    /* Bit 6-7: reserved
+       Bit 4-5: Two bits flag to specify a SAS or SATA (STP) device:
+                00: SATA or STP device
+                01: SSP or SMP device
+                10: Direct SATA device
+       Bit 0-3: Connection Rate field when opening the device.
+                Code Description:
+        00h:  Device has not been registered
+                08h:  1,5 Gbps
+                09h:  3,0 Gbps
+                0ah:  6.0 Gbps
+                All others Reserved
+    */
+  bit8    reserved1;
+  bit16   reserved2;
+} tiDetailedDeviceInfo_t;
+
+typedef struct tiDeviceInfo
+{
+  char                   *localName;
+  char                   *localAddress;
+  char                   *remoteName;
+  char                   *remoteAddress;
+  bit16                  osAddress1;
+  bit16                  osAddress2;
+  bit32                  loginState;
+  tiDetailedDeviceInfo_t info;
+} tiDeviceInfo_t;
+
+
+#define KEK_BLOB_SIZE           48
+#define KEK_AUTH_SIZE           40
+#define KEK_MAX_TABLE_ENTRIES   8
+
+#define DEK_MAX_TABLES          2
+#define DEK_MAX_TABLE_ENTRIES   (1024*4)
+
+#define DEK_BLOB_SIZE_07        72
+#define DEK_BLOB_SIZE_08        80
+
+#define OPERATOR_ROLE_ID_SIZE   1024
+
+#define HMAC_SECRET_KEY_SIZE    72
+
+typedef struct tiEncryptKekBlob
+{
+  bit8    kekBlob[KEK_BLOB_SIZE];
+} tiEncryptKekBlob_t;
+
+typedef struct tiEncryptDekBlob
+{
+  bit8    dekBlob[DEK_BLOB_SIZE_08];
+} tiEncryptDekBlob_t;
+
+typedef struct DEK_Table_s {
+  tiEncryptDekBlob_t  Dek[DEK_MAX_TABLE_ENTRIES];
+}tiDEK_Table_t;
+
+typedef struct DEK_Tables_s {
+  tiDEK_Table_t  DekTable[DEK_MAX_TABLES];
+} tiDEK_Tables_t;
+
+/*sTSDK  4.38  */
+#define OPR_MGMT_ID_STRING_SIZE 31
+
+typedef struct tiID_s {
+   bit8   ID[OPR_MGMT_ID_STRING_SIZE];
+} tiID_t;
+
+typedef struct tiEncryptInfo
+{
+  bit32   securityCipherMode;
+  bit32   status;
+  bit32   sectorSize[6];
+} tiEncryptInfo_t;
+
+typedef struct tiEncryptPort
+{
+  bit32   encryptEvent;
+  bit32   subEvent;
+  void    *pData;
+} tiEncryptPort_t;
+
+typedef struct tiEncryptDek
+{
+  bit32    dekTable;
+  bit32    dekIndex;
+} tiEncryptDek_t;
+
+typedef struct tiEncrypt
+{
+    tiEncryptDek_t dekInfo;
+    bit32          kekIndex;
+    agBOOLEAN      keyTagCheck;
+    agBOOLEAN      enableEncryptionPerLA;
+    bit32          sectorSizeIndex;
+    bit32          encryptMode;
+    bit32          keyTag_W0;
+    bit32          keyTag_W1;
+    bit32          tweakVal_W0;
+    bit32          tweakVal_W1;
+    bit32          tweakVal_W2;
+    bit32          tweakVal_W3;
+    bit32          EncryptionPerLAAddrLo;
+    bit32          EncryptionPerLAAddrHi;
+    bit16          EncryptionPerLRegion0SecCount;
+    bit16          reserved;
+} tiEncrypt_t;
+
+typedef struct tiHWEventMode_s
+{
+    bit32          modePageOperation;
+    bit32          status;
+    bit32          modePageLen;
+    void           *modePage;
+    void           *context;
+} tiHWEventMode_t;
+
+/*****************************************************************************
+ * INITIATOR TYPES
+ *****************************************************************************/
+
+typedef struct tiInitiatorMem
+{
+  bit32       count;
+  tiMem_t     tdCachedMem[6];
+} tiInitiatorMem_t;
+
+typedef struct tiInitiatorOption
+{
+  bit32       usecsPerTick;
+  bit32       pageSize;
+  tiMem_t     dynamicDmaMem;
+  tiMem_t     dynamicCachedMem;
+  bit32       ioRequestBodySize;
+} tiInitiatorOption_t;
+
+
+typedef struct tiInitiatorResource
+{
+  tiInitiatorOption_t     initiatorOption;
+  tiInitiatorMem_t        initiatorMem;
+} tiInitiatorResource_t;
+
+typedef struct tiLUN
+{
+  bit8    lun[8];
+} tiLUN_t;
+
+typedef struct tiIniScsiCmnd
+{
+  tiLUN_t     lun;
+  bit32       expDataLength;
+  bit32       taskAttribute;
+  bit32       crn;
+  bit8        cdb[16];
+} tiIniScsiCmnd_t;
+
+typedef struct tiScsiInitiatorRequest
+{
+  void                *sglVirtualAddr;
+  tiIniScsiCmnd_t     scsiCmnd;
+  tiSgl_t             agSgl1;
+  tiDataDirection_t   dataDirection;
+} tiScsiInitiatorRequest_t;
+
+/* This is the standard request body for I/O that requires DIF or encryption. */
+typedef struct tiSuperScsiInitiatorRequest
+{
+  void                *sglVirtualAddr;
+  tiIniScsiCmnd_t     scsiCmnd;
+  tiSgl_t             agSgl1;
+  tiDataDirection_t   dataDirection;
+  bit32               flags;
+#ifdef CCBUILD_INDIRECT_CDB
+  bit32               IndCDBLowAddr;       /* The low physical address of indirect CDB buffer in host memory */
+  bit32               IndCDBHighAddr;      /* The high physical address of indirect CDB buffer in host memory */
+  bit32               IndCDBLength;        /* Indirect CDB length */
+  void                *IndCDBBuffer;       /* Indirect SSPIU buffer */
+#endif
+  tiDif_t             Dif;
+  tiEncrypt_t         Encrypt;
+} tiSuperScsiInitiatorRequest_t;
+
+typedef struct tiSMPFrame
+{
+  void        *outFrameBuf;
+  bit32       outFrameAddrUpper32;
+  bit32       outFrameAddrLower32;
+  bit32       outFrameLen;
+  bit32       inFrameAddrUpper32;
+  bit32       inFrameAddrLower32;
+  bit32       inFrameLen;
+  bit32       expectedRespLen;
+  bit32       flag;
+} tiSMPFrame_t;
+typedef struct tiEVTData
+{
+  bit32   SequenceNo;
+  bit32   TimeStamp;
+  bit32   Source;
+  bit32   Code;
+  bit8    Reserved;
+  bit8    BinaryDataLength;
+  bit8    DataAndMessage[EVENTLOG_MAX_MSG_LEN];
+} tiEVTData_t;
+
+typedef bit32 (*IsrHandler_t)(
+                        tiRoot_t    *tiRoot,
+                        bit32       channelNum
+                        );
+typedef void (*DeferedHandler_t)(
+                        tiRoot_t    *tiRoot,
+                        bit32       channelNum,
+                        bit32       count,
+                        bit32       context
+                        );
+
+/*****************************************************************************
+ * TARGET TYPES
+ *****************************************************************************/
+
+typedef struct tiTargetMem {
+  bit32     count;
+  tiMem_t   tdMem[10];
+} tiTargetMem_t;
+
+typedef struct tiTargetOption {
+  bit32     usecsPerTick;
+  bit32     pageSize;
+  bit32     numLgns;
+  bit32     numSessions;
+  bit32     numXchgs;
+  tiMem_t   dynamicDmaMem;
+  tiMem_t   dynamicCachedMem;
+} tiTargetOption_t;
+
+typedef struct
+{
+  tiTargetOption_t     targetOption;
+  tiTargetMem_t        targetMem;
+} tiTargetResource_t;
+
+typedef struct
+{
+  bit8      *reqCDB;
+  bit8      *scsiLun;
+  bit32     taskAttribute;
+  bit32     taskId;
+  bit32     crn;
+} tiTargetScsiCmnd_t;
+
+typedef struct tiSuperScsiTargetRequest
+{
+  bit32               flags;
+  tiDif_t             Dif;
+  tiEncrypt_t         Encrypt;
+  tiSgl_t             agSgl;
+  void                *sglVirtualAddr;
+  tiSgl_t             agSglMirror;
+  void                *sglVirtualAddrMirror;
+  bit32               Offset;
+  bit32               DataLength;
+} tiSuperScsiTargetRequest_t;
+
+/* SPCv controller mode page definitions */
+typedef struct tiEncryptGeneralPage_s {
+  bit32             pageCode;           /* 0x20 */
+  bit32             numberOfDeks;
+} tiEncryptGeneralPage_t;
+
+#define TD_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00
+#define TD_ENC_CONFIG_PAGE_KEK_SHIFT  8
+
+typedef struct tiEncryptDekConfigPage
+{
+  bit32 pageCode;                      /* 0x21 */
+  bit32 table0AddrLo;
+  bit32 table0AddrHi;
+  bit32 table0Entries;
+  bit32 table0Config;
+  bit32 table1AddrLo;
+  bit32 table1AddrHi;
+  bit32 table1Entries;
+  bit32 table1Config;
+} tiEncryptDekConfigPage_t;
+
+#define TD_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000
+#define TD_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAYS   0x0F000000
+#define TD_ENC_DEK_CONFIG_PAGE_DPR              0x00000200
+#define TD_ENC_DEK_CONFIG_PAGE_DER              0x00000100
+#define TD_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT  24
+#define TD_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT  28
+#define TD_ENC_DEK_CONFIG_PAGE_DEK_HDP_SHIFT    8
+
+
+/* CCS (Current Crypto Services)  and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */
+/* NAR, CORCAP and USRCAP are valid only when AUT==1 */
+typedef struct tiEncryptControlParamPage_s {
+  bit32          PageCode;           /* 0x22 */
+  bit32          CORCAP;             /* Crypto Officer Role Capabilities */
+  bit32          USRCAP;             /* User Role Capabilities */
+  bit32          CCS;                /* Current Crypto Services */
+  bit32          NOPR;               /* Number of Operators */
+} tiEncryptControlParamPage_t;
+
+typedef struct tiEncryptHMACConfigPage_s
+{
+  bit32  PageCode;
+  bit32  CustomerTag;
+  bit32  KeyAddrLo;
+  bit32  KeyAddrHi;
+} tiEncryptHMACConfigPage_t;
+
+typedef struct tiInterruptConfigPage_s {
+   bit32  pageCode;                        /* 0x05 */
+   bit32  vectorMask;
+   bit32  reserved;
+   bit32  ICTC0;
+   bit32  ICTC1;
+   bit32  ICTC2;
+   bit32  ICTC3;
+   bit32  ICTC4;
+   bit32  ICTC5;
+   bit32  ICTC6;
+   bit32  ICTC7;
+} tiInterruptConfigPage_t;
+
+/* brief data structure for SAS protocol timer configuration page. */
+typedef struct  tiSASProtocolTimerConfigurationPage_s{
+  bit32 pageCode;                       /* 0x04 */
+  bit32 MST_MSI;
+  bit32 STP_SSP_MCT_TMO;
+  bit32 STP_FRM_TMO;
+  bit32 STP_IDLE_TMO;
+  bit32 OPNRJT_RTRY_INTVL;
+  bit32 Data_Cmd_OPNRJT_RTRY_TMO;
+  bit32 Data_Cmd_OPNRJT_RTRY_THR;
+} tiSASProtocolTimerConfigurationPage_t;
+
+/*sTSDK 4.19   */
+
+/* The command is for an operator to login to/logout from SPCve. */
+/* Only when all IOs are quiesced, can an operator logout. */
+typedef struct tiOperatorCommandSet_s {
+  bit32 OPRIDX_PIN_ACS;    /* Access type (ACS) [4 bits] */
+                          /* KEYopr pinned in the KEK RAM (PIN) [1 bit] */
+                          /* KEYopr Index in the KEK RAM (OPRIDX) [8 bits] */
+  bit8   cert[40];          /* Operator Certificate (CERT) [40 bytes] */
+  bit32 reserved[3];       /* reserved */
+} tiOperatorCommandSet_t;
+
+#define FIPS_SELFTEST_MAX_MSG_LEN       (128*1024)
+#define FIPS_SELFTEST_MAX_DIGEST_SIZE   64
+
+typedef struct tiEncryptSelfTestDescriptor_s {
+  bit32         AESNTC_AESPTC;       /* AES Negative/Positive Test Case Bit Map */
+  bit32         KWPNTC_PKWPPTC;      /* Key Wrap Negative/Positive Test Case Bit Map */
+  bit32         HMACNTC_HMACPTC;     /* HMAC Negative Test Case Bit Map */
+} tiEncryptSelfTestDescriptor_t;
+
+typedef struct  tiEncryptSelfTestResult_s{
+  bit32         AESNTCS_AESPTCS;       /* AES Negative/Positive Test Case Status */
+  bit32         KWPNTCS_PKWPPTCS;      /* Key Wrap Negative/Positive Test Case Status */
+  bit32         HMACNTCS_HMACPTCS;     /* HMAC Negative Test Case Status */
+} tiEncryptSelfTestResult_t;
+
+/*
+   Tell SPCve controller the underlying SHA algorithm, where to fetch the message,
+   the size of the message, where to store the digest, where to fetch the secret key and the size of the key.
+*/
+typedef struct tiEncryptHMACTestDescriptor_s
+{
+   bit32    Tlen_SHAAlgo;
+   bit32    MsgAddrLo;
+   bit32    MsgAddrHi;
+   bit32    MsgLen;
+   bit32    DigestAddrLo;
+   bit32    DigestAddrHi;
+   bit32    KeyAddrLo;
+   bit32    KeyAddrHi;
+   bit32    KeyLen;
+} tiEncryptHMACTestDescriptor_t;
+
+typedef struct tiEncryptHMACTestResult_s
+{
+  bit32  Tlen_SHAAlgo;
+   bit32    Reserved[12];
+} tiEncryptHMACTestResult_t;
+
+typedef struct tiEncryptSHATestDescriptor_s
+{
+   bit32    Dword0;
+   bit32    MsgAddrLo;
+   bit32    MsgAddrHi;
+   bit32    MsgLen;
+   bit32    DigestAddrLo;
+   bit32    DigestAddrHi;
+} tiEncryptSHATestDescriptor_t;
+
+typedef struct tiEncryptSHATestResult_s
+{
+   bit32    Dword0;
+   bit32    Dword[12];
+} tiEncryptSHATestResult_t;
+
+
+#endif  /* TITYPES_H */

sys/dev/pms/RefTisa/tisa/sassata/common/ossa.h

@@ -0,0 +1,87 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ * The file defines the declaration of OS types
+ *
+ */
+
+#ifndef __OS_SA_H__
+#define __OS_SA_H__
+
+#define DEBUG_LEVEL   OSSA_DEBUG_LEVEL_1
+#define ossaLogDebugString    TIDEBUG_MSG
+#define ossaAssert OS_ASSERT
+
+#define tddmLogDebugString TIDEBUG_MSG
+#define DM_ASSERT OS_ASSERT
+
+#define tdsmLogDebugString TIDEBUG_MSG
+#define SM_ASSERT OS_ASSERT
+
+#ifdef NOT_YET /* no longer valid */
+#define ossaLogDebugString(agRoot, level, string, ptr1, ptr2, value1, value2) \
+  do { \
+    if ( level <= DEBUG_LEVEL ) \
+    {                          \
+      printk("%s:", __FUNCTION__); \
+      if ( agNULL != string )  \
+      {                        \
+        printk("%s:", string); \
+      }                        \
+      if ( agNULL != ptr1 )    \
+      {                        \
+        printk("ptr1=%p,", ptr1); \
+      }                           \
+      if ( agNULL != ptr2 )       \
+      {                           \
+        printk("ptr2=%p,", ptr2); \
+      }                           \
+      if ( OSSA_DEBUG_PRINT_INVALID_NUMBER != value1 ) \
+      {                                   \
+        printk("value1=0x%08x ", value1); \
+      }                                   \
+      if ( OSSA_DEBUG_PRINT_INVALID_NUMBER != value2 ) \
+      {                                                \
+        printk("value2=0x%08x ", value2);              \
+      } \
+      printk("\n"); \
+    }        \
+  } while (0); 
+
+#ifndef ossaAssert
+#define ossaAssert(agRoot, expr, message) \
+  do {                                                              \
+    if (agFALSE == (expr))                                            \
+    {                                                       \
+      printk("ossaAssert: %s", (message));                        \
+      printk(" - file %s, line %d\n", __FILE__, __LINE__);  \
+    }                                                       \
+  } while (0);
+#endif
+#endif /* 0 */
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#endif  /* __OS_SA_H__ */

sys/dev/pms/RefTisa/tisa/sassata/common/tdesgl.c

@@ -0,0 +1,543 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+**
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ *
+ * This file contains ESGL realted functions
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+#include <dev/pms/RefTisa/tisa/api/ostiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiglobal.h>
+
+#ifdef FDS_SM
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+#endif
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h>
+#include <dev/pms/freebsd/driver/common/osstring.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdutil.h>
+
+#ifdef INITIATOR_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdtypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdglobl.h>
+#endif
+
+#ifdef TARGET_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdxchg.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtypes.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdproto.h>
+
+/* no more esgl related functions */
+#ifdef REMOVED
+/*****************************************************************************
+*! \brief  tdsaEsglInit
+*
+*  Purpose: This function initializes the linked list of ESGL pool
+*
+*  \param  tiRoot:  Pointer to root data structure.
+*
+*  \return: None
+*
+*  \note 
+*
+*****************************************************************************/
+osGLOBAL void 
+tdsaEsglInit(
+             tiRoot_t *tiRoot
+             )
+{
+  tdsaRoot_t               *tdsaRoot    = (tdsaRoot_t *)tiRoot->tdData;
+  tdsaContext_t            *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared;
+  tdsaEsglAllInfo_t        *pEsglAllInfo = (tdsaEsglAllInfo_t *)&(tdsaAllShared->EsglAllInfo);
+  tdsaEsglPagePool_t       *pEsglPagePool;
+
+  bit32 pageno;
+  bit32 PagePhysAddrUpper;
+  bit32 PagePhysAddrLower;
+  bit32 prev_PagePhysAddrLower;
+  tdsaEsglPageInfo_t *pEsglPageInfo;
+  void *PageVirtAddr;
+  bit32 PageSizeInBytes;
+  
+  /* for memory index requirement */
+  agsaRoot_t          agRoot;
+  bit32               maxSALocks = 0;
+  bit32               usecsPerTick = 0;
+  agsaSwConfig_t      SwConfig;
+  agsaMemoryRequirement_t memRequirement;
+  agsaQueueConfig_t   *QueueConfig;
+  bit32                i;
+
+  TI_DBG6(("tdsaEsglInit: start\n"));
+  
+  tdsaGetSwConfigParams(tiRoot);
+  QueueConfig = &tdsaAllShared->QueueConfig;
+
+  for(i=0;i<QueueConfig->numInboundQueues;i++)
+  {
+    QueueConfig->inboundQueues[i].elementCount = tdsaAllShared->InboundQueueSize;
+    QueueConfig->inboundQueues[i].elementSize = tdsaAllShared->InboundQueueEleSize;
+    QueueConfig->inboundQueues[i].priority = tdsaAllShared->InboundQueuePriority[i];
+    QueueConfig->inboundQueues[i].reserved = 0;
+  }
+  for(i=0;i<QueueConfig->numOutboundQueues;i++)
+  {
+    QueueConfig->outboundQueues[i].elementCount = tdsaAllShared->OutboundQueueSize;
+    QueueConfig->outboundQueues[i].elementSize = tdsaAllShared->OutboundQueueEleSize;
+    QueueConfig->outboundQueues[i].interruptDelay = tdsaAllShared->OutboundQueueInterruptDelay[i]; /* default 0; no interrupt delay */
+    QueueConfig->outboundQueues[i].interruptCount = tdsaAllShared->OutboundQueueInterruptCount[i]; /* default 1*/
+    QueueConfig->outboundQueues[i].interruptVectorIndex = 0;
+  }
+  
+  /*
+    hardcoded Queue numbers
+  */
+  QueueConfig->sasHwEventQueue = 0;
+  QueueConfig->sataNCQErrorEventQueue = 0;
+  SwConfig.sizefEventLog1 = HOST_EVENT_LOG_SIZE;
+  SwConfig.sizefEventLog2 = HOST_EVENT_LOG_SIZE;
+  SwConfig.eventLog1Option = 0;
+  SwConfig.eventLog2Option = 0;
+  SwConfig.fatalErrorInterrtuptEnable = 1;
+  SwConfig.fatalErrorInterruptVector = 1;
+  SwConfig.reserved = 0;
+   
+  
+  SwConfig.param3 = (void *)&(tdsaAllShared->QueueConfig);
+  /* to find out memRequirement */
+  saGetRequirements(&agRoot, &SwConfig, &memRequirement, &usecsPerTick, &maxSALocks);
+
+  /* initializes tdsaEsglAllInfo_t */
+  pEsglAllInfo->physAddrUpper = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].physAddrUpper;
+  pEsglAllInfo->physAddrLower = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].physAddrLower;
+  pEsglAllInfo->virtPtr       = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].virtPtr;
+  pEsglAllInfo->NumEsglPages  = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].numElements; /*   NUM_ESGL_PAGES;  number of esgl pages; configurable */
+  pEsglAllInfo->EsglPageSize  = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].singleElementLength; /* sizeof(agsaEsgl_t) */
+  pEsglAllInfo->NumFreeEsglPages = pEsglAllInfo->NumEsglPages;
+  pEsglPagePool = pEsglAllInfo->EsglPagePool;
+
+  TI_DBG6(("tdsaEsglInit: pEsglPagePool %p\n", pEsglPagePool));
+  TI_DBG6(("tdsaEsglInit: tdsaAllShared->loResource.loLevelMem.mem[18].singleElementLength %d\n", tdsaAllShared->loResource.loLevelMem.mem[18].singleElementLength));
+  TI_DBG6(("tdsaEsglInit: NumEsglPage %d EsglPageSize %d\n", pEsglAllInfo->NumEsglPages, pEsglAllInfo->EsglPageSize)); /* ?, 128 */
+  TI_DBG6(("tdsaEsglInit: NumFreeEsglPages %d\n", pEsglAllInfo->NumFreeEsglPages));  
+  /* initialize the linked lists */
+  TDLIST_INIT_HDR(&pEsglAllInfo->freelist);
+
+  
+  PageVirtAddr      = pEsglAllInfo->virtPtr;
+  PagePhysAddrUpper = pEsglAllInfo->physAddrUpper;
+  PagePhysAddrLower = pEsglAllInfo->physAddrLower;
+  PageSizeInBytes   = pEsglAllInfo->EsglPageSize;
+
+  TI_DBG6(("tdsaEsglInit:  PageSizeInBytes 0x%x\n",  PageSizeInBytes));
+  for (pageno = 0 ; pageno < pEsglAllInfo->NumEsglPages ; pageno++)
+  {
+    pEsglPageInfo = &(pEsglPagePool->EsglPages[pageno]);
+    OSSA_WRITE_LE_32(agRoot, pEsglPageInfo, OSSA_OFFSET_OF(pEsglPageInfo, physAddressUpper), PagePhysAddrUpper);
+    OSSA_WRITE_LE_32(agRoot, pEsglPageInfo, OSSA_OFFSET_OF(pEsglPageInfo, physAddressLower), PagePhysAddrLower);
+    pEsglPageInfo->len = PageSizeInBytes;
+    /* for debugging onlye*/
+    pEsglPageInfo->id = pageno+123;
+    pEsglPageInfo->agEsgl = (agsaEsgl_t *)PageVirtAddr;
+    
+    /* for debugging only */
+    TI_DBG6(("tdsaEsglInit: index %d upper 0x%8x lower 0x%8x PageVirtAddr %p\n", pageno, PagePhysAddrUpper, PagePhysAddrLower, PageVirtAddr));
+    
+    
+    /* updates addresses */
+    prev_PagePhysAddrLower = PagePhysAddrLower;
+    PagePhysAddrLower += pEsglAllInfo->EsglPageSize;
+    /* if lower wraps around, increment upper */
+    if (PagePhysAddrLower <= prev_PagePhysAddrLower)
+    {
+      PagePhysAddrUpper++;
+    }
+    
+    if (pageno == pEsglAllInfo->NumEsglPages - 1) /* last page */
+    {
+      pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = 0;
+      /* set bit31 to zero */
+      CLEAR_ESGL_EXTEND(pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved);
+    }
+    else
+    {
+      /* first and so on */
+      pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = PagePhysAddrLower;
+      pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = PagePhysAddrUpper;
+      pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = PageSizeInBytes; /* sizeof (agsaEsgl_t)*/
+      /* set bit31 to one */
+      SET_ESGL_EXTEND(pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved);
+    }
+    
+    TDLIST_INIT_ELEMENT(&pEsglPageInfo->tdlist);
+    tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
+    TDLIST_ENQUEUE_AT_TAIL(&pEsglPageInfo->tdlist, &pEsglAllInfo->freelist);
+    tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
+
+    PageVirtAddr = (bit8 *)PageVirtAddr + PageSizeInBytes;
+  } /* end for */
+
+  
+  
+#ifdef TD_INTERNAL_DEBUG /* for debugging only, for keep now */
+  for (pageno = 0 ; pageno < pEsglAllInfo->NumEsglPages ; pageno++)
+  {
+    TI_DBG6(("tdsaEsglInit: index %d EsglPages %p\n", pageno, &pEsglPagePool->EsglPages[pageno]));
+    TI_DBG6(("tdsaEsglInit: nextupper 0x%8x nextlower 0x%8x\n", pEsglPagePool->EsglPages[pageno].agEsgl->nextPageUpper, pEsglPagePool->EsglPages[pageno].agEsgl->nextPageLower));
+  }
+  TI_DBG6(("tdsaEsglInit:  tdsaEsglPageInfo_t size %d 0x%x\n", sizeof(tdsaEsglPageInfo_t), sizeof(tdsaEsglPageInfo_t)));
+  TI_DBG6(("tdsaEsglInit: sizeof(SASG_DESCRIPTOR) %d 0x%x\n", sizeof(SASG_DESCRIPTOR), sizeof(SASG_DESCRIPTOR)));
+#endif
+  
+  return;
+}
+
+
+/*****************************************************************************
+*! \brief  tdsaGetEsglPages
+*
+*  Purpose: This function prepares linked list of ESGL pages from
+*           the given scatter-gather list.
+*
+*  \param tiRoot:       Pointer to root data structure.
+*  \param EsglListHdr:  pointer to list header where the list needs to be stored.
+*  \param ptiSgl:       Pointer to scatter-gather list.
+*  \param virtSgl:      virtual pointer to scatter-gather list.
+*
+*  \return None
+*  
+*  \note - 
+*       1. If we are out of ESGL pages, then no pages will be added to the list
+*          pointed to by EsglListHdr. The list should be empty before calling 
+*          this function, so that after returning from this function, the 
+*          function can check for the emptyness of the list and find out if
+*          any pages were added or not.
+*
+*****************************************************************************/
+osGLOBAL void
+tdsaGetEsglPages(
+                 tiRoot_t *tiRoot,
+                 tdList_t *EsglListHdr,
+                 tiSgl_t  *ptiSgl,
+                 tiSgl_t  *virtSgl
+                 )
+{
+  tdsaRoot_t        *tdsaRoot        = (tdsaRoot_t *) tiRoot->tdData;
+  tdsaContext_t     *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared;
+
+  tdsaEsglAllInfo_t *pEsglAllInfo = &(tdsaAllShared->EsglAllInfo);
+  bit32 numSgElements = ptiSgl->len;
+  bit32 numEntriesPerPage = MAX_ESGL_ENTRIES;
+  bit32 numPagesRequired = ((numSgElements - 1) / numEntriesPerPage) + 1;
+  bit32 i, j;
+  tdList_t *tdlist_to_fill;
+  tdsaEsglPageInfo_t *page_to_fill;
+  tiSgl_t *tmp_tiSgl = (tiSgl_t *)virtSgl;
+  agsaSgl_t *pDesc;
+  agsaEsgl_t *agEsgl, *PrevagEsgl = agNULL;
+
+  TI_DBG6(("tdsaGetEsglPages: start\n"));
+  TI_DBG6(("tdsaGetEsglPages: pEsglPagePool %p\n", pEsglAllInfo->EsglPagePool));
+  TI_DBG6(("tdsaGetEsglPages: &(pEsglAllInfo->freelist) %p\n", &pEsglAllInfo->freelist));
+  TI_DBG6(("tdsaGetEsglPages: numSgElements %d numEntriesPerPage %d\n", numSgElements, numEntriesPerPage)); /* ?,  10 */
+  TI_DBG6(("tdsaGetEsglPages: numPagesRequired %d NumFreeEsglPages %d\n", numPagesRequired, pEsglAllInfo->NumFreeEsglPages)); /* 1, 2 */
+  TI_DBG6(("tdsaGetEsglPages: free Pages %d\n", pEsglAllInfo->NumFreeEsglPages));
+
+  if (numPagesRequired > pEsglAllInfo->NumFreeEsglPages)
+  {
+    TI_DBG1(("tdsaGetEsglPages:don't have enough freepages. required %d free %d\n", numPagesRequired, pEsglAllInfo->NumFreeEsglPages));
+    return;
+  }
+  tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
+  pEsglAllInfo->NumFreeEsglPages -= numPagesRequired;
+  tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
+
+
+
+#ifdef TD_INTERNAL_DEBUG  /* for debugging only */
+  for (i=0; i < 2; i++)
+  {
+    /* remove one page from freelist */
+    tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
+    TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist);
+    tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
+  
+    /* get the pointer to the page from list pointer */
+    page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill);
+    /* for debugging */
+    TI_DBG6(("tdsaGetEsglPages:page ID %d\n", page_to_fill->id));
+    agEsgl = page_to_fill->agEsgl;
+    
+    pDesc = (SASG_DESCRIPTOR *)agEsgl;
+  
+    for (j=0; j <numEntriesPerPage; j++)
+    {
+      TI_DBG6(("tdsaGetEsglPages: lower %d  upper %d\n", pDesc->sgLower, pDesc->sgUpper));
+      TI_DBG6(("tdsaGetEsglPages: len %d\n", pDesc->len));
+      pDesc++;
+    }
+    TI_DBG6(("tdsaGetEsglPages: next lower %d next upper %d\n", agEsgl->nextPageLower, agEsgl->nextPageUpper));
+    
+  }
+#endif /* for debugging only  */  
+  
+  for (i = 0 ; i < numPagesRequired; i++)
+  {
+    /* remove one page from freelist */
+    tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
+    TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist);
+    tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
+    
+    /* get the pointer to the page from list pointer */
+    page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill);
+    /* for debugging */
+    TI_DBG6(("tdsaGetEsglPages:page ID %d\n", page_to_fill->id));
+    
+    agEsgl = page_to_fill->agEsgl;
+    pDesc = (agsaSgl_t *)agEsgl;
+    
+    /*
+      adjust next page's address in the followings so that
+      the last entry must be (0,0,0)
+    */
+    if (i == numPagesRequired - 1) /* only one page of last page */
+    {
+      for (j=0; j < numSgElements; j++)
+      {
+        OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgLower), tmp_tiSgl->lower);
+        OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgUpper), tmp_tiSgl->upper);
+        OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, len), tmp_tiSgl->len);
+        CLEAR_ESGL_EXTEND(pDesc->extReserved);
+        pDesc++;
+        tmp_tiSgl++;
+      }
+      for (j=numSgElements; j < numEntriesPerPage; j++) 
+      {
+        /* left over(unused) in the page */
+        pDesc->sgLower = 0x0;
+        pDesc->sgUpper = 0x0;
+        pDesc->len = 0x0;
+        CLEAR_ESGL_EXTEND(pDesc->extReserved);
+        pDesc++;
+      }
+    }
+    else 
+    {
+      /* in case of muliple pages, first and later, except one page only or last page */
+      for (j=0; j <numEntriesPerPage - 1; j++) /* else */
+      {
+        /* do this till (last - 1) */
+        OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgLower), tmp_tiSgl->lower);
+        OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgUpper), tmp_tiSgl->upper);
+        OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, len), tmp_tiSgl->len);
+        CLEAR_ESGL_EXTEND(pDesc->extReserved);
+        pDesc++;
+        tmp_tiSgl++;
+      }
+      numSgElements -= (numEntriesPerPage - 1);
+    }
+    if (PrevagEsgl != agNULL)
+    {
+      /* subsequent pages (second or later pages) */
+      PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = page_to_fill->physAddressLower;
+      PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = page_to_fill->physAddressUpper;
+      PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = numSgElements; 
+      /* set bit31 to one */
+      SET_ESGL_EXTEND(PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved);
+    }
+    PrevagEsgl = agEsgl;
+    /* put ESGL onto the EsglListHdr */
+    tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
+    TDLIST_ENQUEUE_AT_TAIL(tdlist_to_fill, EsglListHdr);
+    tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
+    
+    
+  } /* end for */
+  return;
+}
+
+
+/*****************************************************************************
+*! \brief  tdsaFreeEsglPages
+*
+*  Purpose: This function frees the ESGL pages pointed to by EsglListHdr
+*           and puts them back onto the free list.
+*
+*  \param  tiRoot:       Pointer to root data structure.
+*  \param  EsglListHdr:  pointer to list header where the pages to be freed
+*                        are stored.
+*
+*  \return:     None
+*  
+*  \note -
+*   1. This function removes all the pages from the list until the list 
+*      empty and chains them at the end of the free list.
+*****************************************************************************/
+osGLOBAL void
+tdsaFreeEsglPages(
+                  tiRoot_t *tiRoot,
+                  tdList_t *EsglListHdr
+                  )
+{
+  tdsaRoot_t         *tdsaRoot        = (tdsaRoot_t *) tiRoot->tdData;
+  tdsaContext_t      *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared;
+  tdsaEsglAllInfo_t  *pEsglAllInfo = (tdsaEsglAllInfo_t *)&(tdsaAllShared->EsglAllInfo);
+  tdList_t           *tdlist_to_free;
+
+  TI_DBG6(("tdsaFreeEsglPages: start\n"));
+  if (tiRoot == agNULL)
+  {
+    TI_DBG1(("tdsaFreeEsglPages: tiRoot is NULL\n"));
+    return;
+  }
+  
+  if (EsglListHdr == agNULL)
+  {
+    TI_DBG1(("tdsaFreeEsglPages: EsglListHdr is NULL\n"));
+    return;
+  }
+  
+  TI_DBG6(("tdsaFreeEsglPages: EsglListHdr %p\n", EsglListHdr));
+  tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
+  while (TDLIST_NOT_EMPTY(EsglListHdr))
+  {
+    TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_free, EsglListHdr);
+    TDLIST_ENQUEUE_AT_TAIL(tdlist_to_free, &pEsglAllInfo->freelist);
+    pEsglAllInfo->NumFreeEsglPages++;
+  }
+  tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
+  TI_DBG6(("tdsaFreeEsglPages: NumFreeEsglPages  %d\n", pEsglAllInfo->NumFreeEsglPages));
+  return;  
+}
+
+
+/*****************************************************************************
+*! \brief  tdsaGetEsglPagesInfo
+*
+*  Purpose: This function gets the information about the size of ESGL pages
+*           and number pages to be configured.
+*
+*  \param tiRoot:     Pointer to root data structure.
+*  \param pPageSize:  pointer to bit32 where pagesize information is to be
+*                     stored
+*  \param pNumPages:  Pointer to bit32 where number of pages information is
+*                     to be stored
+*
+*  \return:     None
+*
+*  \note -
+*
+*****************************************************************************/
+osGLOBAL void
+tdsaGetEsglPagesInfo(
+                     tiRoot_t *tiRoot, 
+                     bit32    *pPageSize,
+                     bit32    *pNumPages
+                     )
+{
+  char    *buffer;
+  bit32   buffLen;
+  bit32   lenRecv = 0;
+  char    *pLastUsedChar = agNULL;
+  char    globalStr[]     = "Global";
+  char    SwParmsStr[]   = "ESGLParms";
+  char    tmpBuffer[DEFAULT_KEY_BUFFER_SIZE];
+  /* default value, defined in tdsatypes.h */
+  bit32   NumEsglPages = NUM_ESGL_PAGES;  
+  TI_DBG6(("tdsaGetEsglPagesInfo: start \n"));
+
+  /*
+    calls ostiGetTransportParam which parses the configuration file to get
+    parameters.
+  */
+  
+  buffer = tmpBuffer;
+  buffLen = sizeof(tmpBuffer);
+  
+  osti_memset(buffer, 0, buffLen);
+
+  
+  if ((ostiGetTransportParam(
+                             tiRoot, 
+                             globalStr,   /* key */
+                             SwParmsStr,  /* subkey1 */
+                             agNULL,      /* subkey2 */
+                             agNULL,
+                             agNULL, 
+                             agNULL,      /* subkey5 */
+                             "NumESGLPg", /* valueName */
+                             buffer, 
+                             buffLen, 
+                             &lenRecv
+                             ) == tiSuccess) && (lenRecv != 0))
+  {
+    
+    NumEsglPages = osti_strtoul(buffer, &pLastUsedChar, 10);
+  }
+  
+  osti_memset(buffer, 0, buffLen);
+  lenRecv = 0;
+
+  TI_DBG6(("tdsaGetEsglPagesInfo: esgl page number %d\n",NumEsglPages));
+  *pPageSize = ESGL_PAGES_SIZE;/* sizeof(agsaEsgl_t); defined in tdsatypes.h */
+  *pNumPages = NumEsglPages; 
+  
+  return;
+}
+#endif
+
+
+
+
+
+
+
+

sys/dev/pms/RefTisa/tisa/sassata/common/tdhw.c

@@ -0,0 +1,95 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ * This file contains hardware related functions
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+#include <dev/pms/RefTisa/tisa/api/ostiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiglobal.h>
+
+#ifdef FDS_SM
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+#endif
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h>
+#include <dev/pms/freebsd/driver/common/osstring.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdutil.h>
+
+#ifdef INITIATOR_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdtypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdglobl.h>
+#endif
+
+#ifdef TARGET_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdxchg.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtypes.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdproto.h>
+
+/*****************************************************************************
+*! \biref tdsaReadHardwareInfo
+*
+*  Purpose:  This function reads the hardware information. This includes,
+*            PCI DeviceID, PCI VendorID, PCI Chip Revision, PCI Function
+*            Number.
+*
+*  \param  tiRoot:            Pointer to driver/port instance.
+*
+*  \return: None
+*  \note - just a place holder for now
+*****************************************************************************/
+osGLOBAL void 
+tdsaReadHardwareInfo(
+                     tiRoot_t *tiRoot
+                     )
+{
+  return;
+}

sys/dev/pms/RefTisa/tisa/sassata/common/tdint.c

@@ -0,0 +1,263 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ *
+ * This file contains interrupt related functions in the SAS/SATA TD layer
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+#include <dev/pms/RefTisa/tisa/api/ostiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiglobal.h>
+
+#ifdef FDS_SM
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+#endif
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h>
+#include <dev/pms/freebsd/driver/common/osstring.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdutil.h>
+
+#ifdef INITIATOR_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdtypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdglobl.h>
+#endif
+
+#ifdef TARGET_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdxchg.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtypes.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdproto.h>
+
+/*****************************************************************************
+*! \biref  tiCOMInterruptHandler
+*
+*  Purpose: This function is called to service the hardware interrupt of the
+*           hardware.
+*
+*  \param tiRoot:   Pointer to initiator specific root data structure  for this
+*                   instance of the driver.
+*
+*  \param channelNum: The zero-base channel number of the controller.
+*                     0xFFFFFFFF indicates that the OS-App Specific layer does 
+*                     not provide the channel number. The TD/LL Layer needs to 
+*                     discover of any of its own channels that are causing the 
+*                     interrupt.
+*
+*  \return None
+*
+*  \note - The only thing that this API will do is to acknowledge and mask
+*          the necessary hardware interrupt register. The actual processing
+*          of the interrupt handler is done in tiCOMDelayedInterruptHandler().
+*
+*****************************************************************************/
+FORCEINLINE bit32 
+tiCOMInterruptHandler(
+                      tiRoot_t * tiRoot,
+                      bit32      channelNum)
+{
+  tdsaRoot_t      *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData;
+  tdsaContext_t   *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared);
+  agsaRoot_t      *agRoot = &(tdsaAllShared->agRootNonInt);
+  bit32           interruptPending = agFALSE;
+
+  interruptPending = saInterruptHandler(agRoot, channelNum);
+  
+  return interruptPending;
+  
+} /* tiCOMInterruptHandler() */
+
+
+/*****************************************************************************
+*! \brief tiCOMDelayedInterruptHandler
+*
+*  Purpose: This function is called to process the task associated with the
+*           interrupt handler. The task that this handler needs to do includes:
+*           completion of I/O, login event, error event, etc
+*
+*  \param tiRoot:     Pointer to initiator specific root data structure for
+*                     this instance of the driver.
+*  \param channelNum: The zero-base channel number of the controller.
+*                     0xFFFFFFFF indicates that the OS-App Specific layer does 
+*                     not provide the channel number. The TD/LL Layer needs to 
+*                     discover of any of its own channels that are causing the 
+*                     interrupt.
+*  \param count:      Count on how many items (such as IO completion) need to
+*                     be processed in this context.
+*  \param interruptContext: The thread/process context within which this 
+*                           function is called.
+*
+*             tiInterruptContext:     this function is called within an
+*                                     interrupt context.
+*             tiNonInterruptContext:  this function is called outside an
+*                                     interrupt context.
+*  \return None
+*
+*****************************************************************************/
+FORCEINLINE 
+bit32 
+tiCOMDelayedInterruptHandler(
+                             tiRoot_t  *tiRoot,
+                             bit32     channelNum,
+                             bit32     count, 
+                             bit32     context
+                             )
+{
+  tdsaRoot_t      *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData;
+  tdsaContext_t   *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared);
+  agsaRoot_t      *agRoot = agNULL;
+  bit32            completed = 0;
+
+  TDSA_OUT_ENTER(tiRoot);
+
+  if(context == tiInterruptContext)
+  {
+    agRoot = &(tdsaAllShared->agRootInt);
+  }
+  else
+  {
+    agRoot = &(tdsaAllShared->agRootNonInt);
+  }
+
+  completed = saDelayedInterruptHandler(agRoot, channelNum, count);
+
+  if(completed == 0)
+  {
+    TI_DBG3(("tiCOMDelayedInterruptHandler: processedMsgCount zero\n"));
+  }
+
+  
+  TDSA_OUT_LEAVE(tiRoot);
+
+  return(completed);
+} /* tiCOMDelayedInterruptHandler() */
+
+
+/*****************************************************************************
+*! \brief tiCOMSystemInterruptsActive
+*
+*  Purpose: This function is called to indicate whether interrupts are 
+*           active or not from this point in time.
+*
+*  \param tiRoot:        Pointer to initiator specific root data structure for
+*                        this instance of the driver.
+*  \param sysIntsActive: Boolean value either true or false
+*
+*  \return None
+*
+*****************************************************************************/
+osGLOBAL void
+tiCOMSystemInterruptsActive(
+                            tiRoot_t * tiRoot, 
+                            bit32 sysIntsActive
+                            )
+{
+
+  tdsaRoot_t     *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData;
+  tdsaContext_t  *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared);
+  agsaRoot_t     *agRoot;
+  agRoot = &(tdsaAllShared->agRootNonInt);
+
+#ifdef SPC_POLLINGMODE
+  if(sysIntsActive)  return;
+#endif /* SPC_POLLINGMODE */
+
+  tdsaAllShared->flags.sysIntsActive = sysIntsActive;
+
+  TI_DBG6(("tiCOMSystemInterruptsActive: start\n"));
+  /* enable low level interrupts */
+  if(agRoot->sdkData != agNULL)
+  {
+    saSystemInterruptsActive(
+                             agRoot, 
+                             (agBOOLEAN) tdsaAllShared->flags.sysIntsActive
+                             );
+  }
+  
+  TI_DBG6(("tiCOMSystemInterruptsActive: end\n"));
+} /* tiCOMSystemInterruptsActive */
+
+
+osGLOBAL void
+tiComCountActiveIORequests(
+                            tiRoot_t * tiRoot 
+                          )
+{
+  tdsaRoot_t     *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData;
+  tdsaContext_t  *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared);
+  agsaRoot_t     *agRoot;
+  agRoot = &(tdsaAllShared->agRootNonInt);
+  saCountActiveIORequests(agRoot );
+}
+
+/*****************************************************************************
+*! \brief tiCOMInterruptEnable
+*
+*  Purpose: This function is called to enable an interrupts on the specified channel 
+*           active or not from this point in time.
+*
+*  \param tiRoot:        Pointer to initiator specific root data structure for
+*                        this instance of the driver.
+*  \param : channelNum   vector number for MSIX  Zero for legacy interrupt 
+*
+*  \return None
+*
+*****************************************************************************/
+osGLOBAL FORCEINLINE 
+void
+tiCOMInterruptEnable(
+                      tiRoot_t * tiRoot,
+                      bit32      channelNum)
+{
+  tdsaRoot_t     *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData;
+  tdsaContext_t  *tdsaAllShared = (tdsaContext_t *)&(tdsaRoot->tdsaAllShared);
+  agsaRoot_t     *agRoot;
+  agRoot = &(tdsaAllShared->agRootNonInt);
+
+  saSystemInterruptsEnable(agRoot, channelNum);
+}

sys/dev/pms/RefTisa/tisa/sassata/common/tdioctl.h

@@ -0,0 +1,687 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+*******************************************************************************/
+/*****************************************************************************
+*
+*   tdioctl.h
+*
+*   Abstract:   This module contains data structure definition used
+*               by the Transport Dependent (TD) Layer IOCTL.
+*
+*
+*   Notes:
+*
+*
+** MODIFICATION HISTORY ******************************************************
+*
+* NAME        DATE        DESCRIPTION
+* ----        ----        -----------
+* IWN         12/11/02     Initial creation.
+*
+*
+*****************************************************************************/
+
+
+#ifndef TD_IOCTL_H
+
+#define TD_IOCTL_H
+
+//#include "global.h"
+
+/*
+ * PMC-Sierra IOCTL signature
+ */
+#define PMC_SIERRA_SIGNATURE                0x1234
+#define PMC_SIERRA_IOCTL_SIGNATURE          "PMC-STRG"
+
+/*
+ * Major function code of IOCTL functions, common to target and initiator.
+ */
+#define IOCTL_MJ_CARD_PARAMETER             0x01
+#define IOCTL_MJ_FW_CONTROL                 0x02
+#define IOCTL_MJ_NVMD_GET                   0x03
+#define IOCTL_MJ_NVMD_SET                   0x04
+#define IOCTL_MJ_GET_EVENT_LOG1             0x05
+#define IOCTL_MJ_GET_EVENT_LOG2             0x06
+#define IOCTL_MJ_GET_CORE_DUMP              0x07
+#define IOCTL_MJ_LL_TRACING                 0x08
+#define IOCTL_MJ_FW_PROFILE                 0x09
+#define IOCTL_MJ_MNID                       0x0A
+#define IOCTL_MJ_ENCRYPTION_CTL             0x0B
+
+#define IOCTL_MJ_FW_INFO                    0x0C
+
+#define IOCTL_MJ_LL_API_TEST                0x11
+#define IOCTL_MJ_CHECK_DPMC_EVENT           0x16
+#define IOCTL_MJ_GET_FW_REV                 0x1A
+#define IOCTL_MJ_GET_DEVICE_INFO            0x1B
+#define IOCTL_MJ_GET_IO_ERROR_STATISTIC     0x1C
+#define IOCTL_MJ_GET_IO_EVENT_STATISTIC     0x1D
+#define IOCTL_MJ_GET_FORENSIC_DATA          0x1E
+#define IOCTL_MJ_GET_DEVICE_LIST            0x1F
+#define IOCTL_MJ_SMP_REQUEST				0x6D
+#define IOCTL_MJ_GET_DEVICE_LUN               0x7A1
+#define IOCTL_MJ_PHY_GENERAL_STATUS           0x7A6
+#define IOCTL_MJ_PHY_DETAILS           	      0x7A7
+#define IOCTL_MJ_SEND_BIST                  0x20
+#define IOCTL_MJ_CHECK_FATAL_ERROR          0x70
+#define IOCTL_MJ_FATAL_ERROR_DUMP_COMPLETE  0x71
+#define IOCTL_MJ_GPIO                       0x41
+#define IOCTL_MJ_SGPIO                      0x42
+#define IOCTL_MJ_SEND_TMF					0x6E
+#define	IOCTL_MJ_FATAL_ERROR_SOFT_RESET_TRIG 0x72
+#define	IOCTL_MJ_FATAL_ERR_CHK_RET_FALSE    0x76
+#define	IOCTL_MJ_FATAL_ERR_CHK_SEND_FALSE   0x76
+#define	IOCTL_MJ_FATAL_ERR_CHK_SEND_TRUE    0x77
+
+
+/*
+ * Major function code of IOCTL functions, specific to initiator.
+ */
+#define IOCTL_MJ_INI_ISCSI_DISCOVERY        0x21
+#define IOCTL_MJ_INI_SESSION_CONTROL        0x22
+#define IOCTL_MJ_INI_SNIA_IMA               0x23
+#define IOCTL_MJ_INI_SCSI                   0x24
+#define IOCTL_MJ_INI_WMI                    0x25
+#define IOCTL_MJ_INI_DRIVER_EVENT_LOG       0x26
+#define IOCTL_MJ_INI_PERSISTENT_BINDING     0x27
+#define IOCTL_MJ_INI_DRIVER_IDENTIFY        0x28
+
+/* temp */
+#define IOCTL_MJ_PORT_STOP        0x29
+#define IOCTL_MJ_PORT_START       0x30
+
+/* SPCv controller configuration page commands */
+#define IOCTL_MJ_MODE_CTL_PAGE              0x40
+
+#define IOCTL_MJ_SET_OR_GET_REGISTER        0x41
+
+#define IOCTL_MJ_GET_PHY_PROFILE            0x44
+#define IOCTL_MJ_SET_PHY_PROFILE            0x43
+
+#define IOCTL_MJ_GET_DRIVER_VERSION         0x101
+
+#define IOCTL_MN_PHY_PROFILE_COUNTERS        0x01
+#define IOCTL_MN_PHY_PROFILE_COUNTERS_CLR    0x02
+#define IOCTL_MN_PHY_PROFILE_BW_COUNTERS     0x03
+#define IOCTL_MN_PHY_PROFILE_ANALOG_SETTINGS 0x04
+
+/* 
+ * Minor functions for Card parameter IOCTL functions.
+ */
+#define IOCTL_MN_CARD_GET_VPD_INFO              0x01
+#define IOCTL_MN_CARD_GET_PORTSTART_INFO        0x02
+#define IOCTL_MN_CARD_GET_INTERRUPT_CONFIG      0x03
+#define IOCTL_MN_CARD_GET_PHY_ANALOGSETTING     0x04
+#define IOCTL_MN_CARD_GET_TIMER_CONFIG          0x05
+#define IOCTL_MN_CARD_GET_TYPE_FATAL_DUMP       0x06
+
+/*
+ * Minor functions for FW control IOCTL functions.
+ */
+
+/* Send FW data requests.
+ */
+#define IOCTL_MN_FW_DOWNLOAD_DATA         0x01
+
+/* Send the request for burning the new firmware.
+ */
+#define IOCTL_MN_FW_DOWNLOAD_BURN         0x02
+
+/* Poll for the flash burn phases. Sequences of poll function calls are
+ * needed following the IOCTL_MN_FW_DOWNLOAD_BURN, IOCTL_MN_FW_BURN_OSPD
+ * and IOCTL_MN_FW_ROLL_BACK_FW functions.
+ */
+#define IOCTL_MN_FW_BURN_POLL             0x03
+
+/* Instruct the FW to roll back FW to prior revision.
+ */
+#define IOCTL_MN_FW_ROLL_BACK_FW          0x04
+
+/* Instruct the FW to return the current firmware revision number.
+ */
+#define IOCTL_MN_FW_VERSION               0x05
+
+/* Retrieve the maximum size of the OS Persistent Data stored on the card.
+ */
+#define IOCTL_MN_FW_GET_OSPD_SIZE   0x06
+
+/*  Retrieve the OS Persistent Data from the card.
+ */
+#define IOCTL_MN_FW_GET_OSPD              0x07
+
+/* Send a new OS Persistent Data to the card and burn in flash.
+ */
+#define IOCTL_MN_FW_BURN_OSPD           0x08
+
+/* Retrieve the trace buffer from the card FW. Only available on the debug
+ * version of the FW.
+ */
+#define IOCTL_MN_FW_GET_TRACE_BUFFER            0x0f
+
+#define IOCTL_MN_NVMD_GET_CONFIG                0x0A
+#define IOCTL_MN_NVMD_SET_CONFIG                0x0B
+
+#define IOCTL_MN_FW_GET_CORE_DUMP_AAP1          0x0C
+#define IOCTL_MN_FW_GET_CORE_DUMP_IOP           0x0D
+#define IOCTL_MN_FW_GET_CORE_DUMP_FLASH_AAP1    0x12
+#define IOCTL_MN_FW_GET_CORE_DUMP_FLASH_IOP     0x13
+
+#define IOCTL_MN_LL_RESET_TRACE_INDEX           0x0e
+#define IOCTL_MN_LL_GET_TRACE_BUFFER_INFO       0x0f
+#define IOCTL_MN_LL_GET_TRACE_BUFFER            0x10
+
+#define IOCTL_MN_ENCRYPTION_GET_INFO          0x13
+#define IOCTL_MN_ENCRYPTION_SET_MODE          0x14
+#define IOCTL_MN_ENCRYPTION_KEK_ADD           0x15
+#define IOCTL_MN_ENCRYPTION_DEK_ADD           0x16
+#define IOCTL_MN_ENCRYPTION_DEK_INVALID       0x17
+#define IOCTL_MN_ENCRYPTION_KEK_NVRAM         0x18
+#define IOCTL_MN_ENCRYPTION_DEK_ASSIGN        0x19
+#define IOCTL_MN_ENCRYPTION_LUN_QUERY         0x1A
+#define IOCTL_MN_ENCRYPTION_KEK_LOAD_NVRAM    0x1B
+#define IOCTL_MN_ENCRYPTION_ERROR_QUERY       0x1C
+#define IOCTL_MN_ENCRYPTION_DEK_TABLE_INIT    0x1D
+#define IOCTL_MN_ENCRYPT_LUN_VERIFY           0x1E
+#define IOCTL_MN_ENCRYPT_OPERATOR_MGMT        0x1F
+#define IOCTL_MN_ENCRYPT_SET_DEK_CONFIG_PAGE  0x21
+#define IOCTL_MN_ENCRYPT_SET_CONTROL_PAGE     0x22
+#define IOCTL_MN_ENCRYPT_SET_OPERATOR_CMD     0x23
+#define IOCTL_MN_ENCRYPT_TEST_EXECUTE         0x24
+#define IOCTL_MN_ENCRYPT_SET_HMAC_CONFIG_PAGE 0x25
+#define IOCTL_MN_ENCRYPT_GET_OPERATOR_CMD     0x26
+#define IOCTL_MN_ENCRYPT_RESCAN               0x27
+#ifdef SOFT_RESET_TEST
+#define IOCTL_MN_SOFT_RESET                   0x28
+#endif
+/* SPCv configuration pages */
+#define IOCTL_MN_MODE_SENSE                   0x30
+#define IOCTL_MN_MODE_SELECT                  0x31
+
+#define IOCTL_MN_TISA_TEST_ENCRYPT_DEK_DUMP   0x51
+
+#define IOCTL_MN_FW_GET_EVENT_FLASH_LOG1        0x5A
+#define IOCTL_MN_FW_GET_EVENT_FLASH_LOG2        0x6A
+#define IOCTL_MN_GET_EVENT_LOG1                 0x5B
+#define IOCTL_MN_GET_EVENT_LOG2                 0x6B
+
+#define IOCTL_MN_GPIO_PINSETUP	            	0x01
+#define IOCTL_MN_GPIO_EVENTSETUP             	0x02
+#define IOCTL_MN_GPIO_READ 		                0x03
+#define IOCTL_MN_GPIO_WRITE	                	0x04
+
+#define IOCTL_MN_TMF_DEVICE_RESET				0x6F
+#define IOCTL_MN_TMF_LUN_RESET					0x70
+typedef struct tdFWControl
+{
+  bit32   retcode;    /* ret code (status) = (bit32)oscmCtrlEvnt_e      */
+  bit32   phase;      /* ret code phase    = (bit32)agcmCtrlFwPhase_e   */
+  bit32   phaseCmplt; /* percent complete for the current update phase  */
+  bit32   version;    /* Hex encoded firmware version number            */
+  bit32   offset;     /* Used for downloading firmware                  */
+  bit32   len;        /* len of buffer                                  */
+  bit32   size;       /* Used in OS VPD and Trace get size operations.  */
+  bit32   reserved;   /* padding required for 64 bit alignment          */
+  bit8    buffer[1];  /* Start of buffer                                */
+} tdFWControl_t;
+
+
+typedef struct tdFWControlEx
+{
+  tdFWControl_t *tdFWControl;
+  bit8    *buffer;    // keep buffer pointer to be freed when the responce comes
+  bit8    *virtAddr;  /* keep virtual address of the data */
+  bit8    *usrAddr;   /* keep virtual address of the user data */
+  bit32   len;        /* len of buffer                                  */
+  void    *payload;   /* pointer to IOCTL Payload */
+  bit8    inProgress;  /* if 1 - the IOCTL request is in progress */
+  void    *param1;
+  void    *param2;
+  void    *param3;
+} tdFWControlEx_t;
+
+/************************************************************/
+//This flag and datastructure are specific for fw profiling, Now defined as
+// compiler flag
+//#define SPC_ENABLE_PROFILE
+
+#ifdef SPC_ENABLE_PROFILE
+typedef struct tdFWProfile
+{
+    bit32   status;
+    bit32   tcid;
+    bit32   processor;  /* processor name "iop/aap1"      */
+    bit32   cmd;        /* cmd to fw   */
+    bit32   len;        /* len of buffer                                  */
+    bit32   codeStartAdd;
+    bit32   codeEndAdd;
+    bit32   reserved;   /* padding required for 64 bit alignment          */
+    bit8    buffer[1];  /* Start of buffer                                */
+} tdFWProfile_t;
+
+/************************************************/
+/**Definations for FW profile*/
+#define FW_PROFILE_PROCESSOR_ID_IOP  0x00
+#define FW_PROFILE_PROCESSOR_ID_AAP1 0x02
+/* definitions for sub operation */
+#define START_TIMER_PROFILE          0x01
+#define START_CODE_PROFILE           0x02
+#define STOP_TIMER_PROFILE           0x81
+#define STOP_CODE_PROFILE            0x82
+/************************************************/
+
+typedef struct tdFWProfileEx
+{
+  tdFWProfile_t *tdFWProfile;
+  bit8    *buffer;    // keep buffer pointer to be freed when the responce comes
+  bit8    *virtAddr;  /* keep virtual address of the data */
+  bit8    *usrAddr;   /* keep virtual address of the user data */
+  bit32   len;        /* len of buffer                                  */
+  void    *payload;   /* pointer to IOCTL Payload */
+  bit8    inProgress;  /* if 1 - the IOCTL request is in progress */
+  void    *param1;
+  void    *param2;
+  void    *param3;
+} tdFWProfileEx_t;
+#endif
+/************************************************************/
+typedef struct tdVPDControl
+{
+  bit32   retcode;    /* ret code (status)                              */
+  bit32   phase;      /* ret code phase                                 */
+  bit32   phaseCmplt; /* percent complete for the current update phase  */
+  bit32   version;    /* Hex encoded firmware version number            */
+  bit32   offset;     /* Used for downloading firmware                  */
+  bit32   len;        /* len of buffer                                  */
+  bit32   size;       /* Used in OS VPD and Trace get size operations.  */
+  bit8    deviceID;   /* padding required for 64 bit alignment          */
+  bit8    reserved1;
+  bit16   reserved2;
+  bit32   signature;
+  bit8    buffer[1];  /* Start of buffer                                */
+} tdVPDControl_t;
+
+typedef struct tdDeviceInfoIOCTL_s
+{
+  bit8       deviceType;   // TD_SATA_DEVICE or TD_SAS_DEVICE
+  bit8       linkRate;     // 0x08: 1.5 Gbit/s; 0x09: 3.0; 0x0A: 6.0 Gbit/s.
+  bit8       phyId;
+  bit8       reserved;
+  bit32      sasAddressHi; // SAS address high
+  bit32      sasAddressLo; // SAS address low
+  bit32      up_sasAddressHi; // upstream SAS address high
+  bit32      up_sasAddressLo; // upstream SAS address low
+  bit32      ishost;
+  bit32      isEncryption;    // is encryption enabled
+  bit32      isDIF;           // is DIF enabled
+  unsigned long DeviceHandle;
+  bit32      host_num;
+  bit32      channel;
+  bit32      id;
+  bit32      lun;
+}tdDeviceInfoIOCTL_t;
+
+/* Payload of IOCTL dump device list at OS layer */
+typedef struct tdDeviceInfoPayload_s
+{
+  bit32      PathId;
+  bit32      TargetId;
+  bit32      Lun;
+  bit32      Reserved;         /* Had better aligned to 64-bit. */
+
+  /* output */
+  tdDeviceInfoIOCTL_t  devInfo;
+}tdDeviceInfoPayload_t;
+
+typedef struct tdDeviceListPayload_s
+{
+  bit32  realDeviceCount;// the real device out in the array, returned by driver
+  bit32  deviceLength;   // the length of tdDeviceInfoIOCTL_t array
+  bit8   pDeviceInfo[1]; // point to tdDeviceInfoIOCTL_t array
+}tdDeviceListPayload_t;
+
+// Payload of IO error and event statistic IOCTL.
+typedef struct tdIoErrorEventStatisticIOCTL_s
+{
+  bit32  agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS;
+  bit32  agOSSA_IO_ABORTED;
+  bit32  agOSSA_IO_OVERFLOW;
+  bit32  agOSSA_IO_UNDERFLOW;
+  bit32  agOSSA_IO_FAILED;
+  bit32  agOSSA_IO_ABORT_RESET;
+  bit32  agOSSA_IO_NOT_VALID;
+  bit32  agOSSA_IO_NO_DEVICE;
+  bit32  agOSSA_IO_ILLEGAL_PARAMETER;
+  bit32  agOSSA_IO_LINK_FAILURE;
+  bit32  agOSSA_IO_PROG_ERROR;
+  bit32  agOSSA_IO_DIF_IN_ERROR;
+  bit32  agOSSA_IO_DIF_OUT_ERROR;
+  bit32  agOSSA_IO_ERROR_HW_TIMEOUT;
+  bit32  agOSSA_IO_XFER_ERROR_BREAK;
+  bit32  agOSSA_IO_XFER_ERROR_PHY_NOT_READY;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_BREAK;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR;
+  bit32  agOSSA_IO_XFER_ERROR_NAK_RECEIVED;
+  bit32  agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT;
+  bit32  agOSSA_IO_XFER_ERROR_PEER_ABORTED;
+  bit32  agOSSA_IO_XFER_ERROR_RX_FRAME;
+  bit32  agOSSA_IO_XFER_ERROR_DMA;
+  bit32  agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT;
+  bit32  agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT;
+  bit32  agOSSA_IO_XFER_ERROR_SATA;
+  bit32  agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST;
+  bit32  agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE;
+  bit32  agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE;
+  bit32  agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT;
+  bit32  agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR;
+  bit32  agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE;
+  bit32  agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN;
+  bit32  agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED;
+  bit32  agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT;
+  bit32  agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK;
+  bit32  agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK;
+  bit32  agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH;
+  bit32  agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN;
+  bit32  agOSSA_IO_XFER_CMD_FRAME_ISSUED;
+  bit32  agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE;
+  bit32  agOSSA_IO_PORT_IN_RESET;
+  bit32  agOSSA_IO_DS_NON_OPERATIONAL;
+  bit32  agOSSA_IO_DS_IN_RECOVERY;
+  bit32  agOSSA_IO_TM_TAG_NOT_FOUND;
+  bit32  agOSSA_IO_XFER_PIO_SETUP_ERROR;
+  bit32  agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR;
+  bit32  agOSSA_IO_DS_IN_ERROR;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY;
+  bit32  agOSSA_IO_ABORT_IN_PROGRESS;
+  bit32  agOSSA_IO_ABORT_DELAYED;
+  bit32  agOSSA_IO_INVALID_LENGTH;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED;
+  bit32  agOSSA_IO_DS_INVALID;
+  bit32  agOSSA_IO_XFER_READ_COMPL_ERR;
+  bit32  agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR;
+  bit32  agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR;
+  bit32  agOSSA_MPI_IO_RQE_BUSY_FULL;
+  bit32  agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE;
+  bit32  agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY;
+  bit32  agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS;
+  bit32  agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH;
+  bit32  agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID;
+  bit32  agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH;
+  bit32  agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR;
+  bit32  agOSSA_IO_XFR_ERROR_INTERNAL_RAM;
+  bit32  agOSSA_IO_XFR_ERROR_DIF_MISMATCH;
+  bit32  agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH;
+  bit32  agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH;
+  bit32  agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH;
+  bit32  agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME;
+  bit32  agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN;
+  bit32  agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS;
+  bit32  agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED;
+  bit32  agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE;
+  bit32  agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR;
+  bit32  agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED;
+  bit32  agOSSA_IO_UNKNOWN_ERROR;
+
+} tdIoErrorEventStatisticIOCTL_t;
+
+/*
+01: soft error
+02: not ready
+03: medium error
+04: hardware error
+05: illegal request
+06: unit attention
+0b: abort command
+*/
+typedef struct tdSenseKeyCount_s{
+  bit32     SoftError;
+  bit32     MediumNotReady;
+  bit32     MediumError;
+  bit32     HardwareError;
+  bit32     IllegalRequest;
+  bit32     UnitAttention;
+  bit32     AbortCommand;
+  bit32     OtherKeyType;
+}tdSenseKeyCount_t;
+
+/*
+Code Status Command  completed Service response
+00h GOOD Yes COMMAND COMPLETE
+02h CHECK CONDITION Yes COMMAND COMPLETE
+04h CONDITION MET Yes COMMAND COMPLETE
+08h BUSY Yes COMMAND COMPLETE
+10h Obsolete
+14h Obsolete
+18h RESERVATION CONFLICT Yes COMMAND COMPLETE
+22h Obsolete
+28h TASK SET FULL Yes COMMAND COMPLETE
+30h ACA ACTIVE Yes COMMAND COMPLETE
+40h TASK ABORTED Yes COMMAND COMPLETE
+*/
+typedef struct tdSCSIStatusCount_s{
+  bit32     GoodStatus;
+  bit32     CheckCondition;
+  bit32     ConditionMet;
+  bit32     BusyStatus;
+  bit32     ResvConflict;
+  bit32     TaskSetFull;
+  bit32     AcaActive;
+  bit32     TaskAborted;
+  bit32     ObsoleteStatus;
+}tdSCSIStatusCount_t;
+
+/* Payload of Io Error Statistic IOCTL. */
+typedef struct tdIoErrorStatisticPayload_s
+{
+  bit32         flag;
+  bit32         Reserved;         /* Had better aligned to 64-bit. */
+
+  /* output */
+  tdIoErrorEventStatisticIOCTL_t  IoError;
+  tdSCSIStatusCount_t             ScsiStatusCounter;
+  tdSenseKeyCount_t               SenseKeyCounter;
+} tdIoErrorStatisticPayload_t;
+
+/* Payload of Io Error Statistic IOCTL. */
+typedef struct tdIoEventStatisticPayload_s
+{
+  bit32         flag;
+  bit32         Reserved;         /* Had better aligned to 64-bit. */
+
+  /* output */
+  tdIoErrorEventStatisticIOCTL_t  IoEvent;
+} tdIoEventStatisticPayload_t;
+
+/* Payload of Register IOCTL. */
+typedef struct tdRegisterPayload_s
+{
+  bit32         flag;
+  bit32         busNum;
+  bit32         RegAddr;         /* Register address */
+  bit32         RegValue;        /* Register value */
+
+} tdRegisterPayload_t;
+
+
+#define FORENSIC_DATA_TYPE_GSM_SPACE        1
+#define FORENSIC_DATA_TYPE_QUEUE            2
+#define FORENSIC_DATA_TYPE_FATAL            3
+#define FORENSIC_DATA_TYPE_NON_FATAL        4
+#define FORENSIC_DATA_TYPE_IB_QUEUE         5
+#define FORENSIC_DATA_TYPE_OB_QUEUE          6
+#define FORENSIC_DATA_TYPE_CHECK_FATAL      0x70
+
+#define FORENSIC_Q_TYPE_INBOUND          1
+#define FORENSIC_Q_TYPE_OUTBOUND         2
+
+/* get forensic data IOCTL payload */
+typedef struct tdForensicDataPayload_s
+{
+  bit32   DataType;
+  union
+  {
+    struct
+    {
+      bit32   directLen;
+      bit32   directOffset;
+      bit32   readLen;
+      bit8   directData[1]; 
+    } gsmBuffer;
+
+    struct
+    {
+      bit16  queueType;
+      bit16  queueIndex;
+      bit32  directLen;
+      bit8   directData[1];
+    } queueBuffer;
+
+    struct
+    {
+      bit32 directLen;
+      bit32 directOffset;
+      bit32 readLen;
+      bit8  directData[1];
+    } dataBuffer;
+  }; 
+}tdForensicDataPayload_t;
+
+typedef struct tdBistPayload_s
+{
+  bit32  testType;
+  bit32  testLength;
+  bit32  testData[29];
+}tdBistPayload_t;
+
+typedef struct _TSTMTID_CARD_LOCATION_INFO
+{
+  bit32               CardNo;
+  bit32               Bus;
+  bit32               Slot;
+  bit32               Device;
+  bit32               Function;
+  bit32               IOLower;
+  bit32               IO_Upper;
+  bit32               VidDid;
+  bit32               PhyMem;
+  bit32               Flag;
+
+} TSTMTID_CARD_LOCATION_INFO;
+
+typedef struct _TSTMTID_TRACE_BUFFER_INFO
+{
+  bit32               CardNo;
+  bit32               TraceCompiled;
+  bit32               BufferSize;
+  bit32               CurrentIndex;
+  bit32               TraceWrap;
+  bit32               CurrentTraceIndexWrapCount;
+  bit32               TraceMask;
+  bit32               Flag;
+
+} TSTMTID_TRACE_BUFFER_INFO;
+
+#define FetchBufferSIZE  32
+#define LowFence32Bits   0xFCFD1234
+#define HighFence32Bits  0x5678ABDC
+
+typedef struct _TSTMTID_TRACE_BUFFER_FETCH
+{
+  bit32               CardNo;
+  bit32               BufferOffsetBegin;
+  bit32               LowFence;
+  bit8                Data[FetchBufferSIZE];
+  bit32               HighFence;
+  bit32               Flag;
+
+} TSTMTID_TRACE_BUFFER_FETCH;
+
+
+typedef struct _TSTMTID_TRACE_BUFFER_RESET
+{
+  bit32               CardNo;
+  bit32               Reset;
+  bit32               TraceMask;
+  bit32               Flag;
+
+} TSTMTID_TRACE_BUFFER_RESET;
+
+
+
+typedef struct tdPhyCount_s{
+  bit32 Phy;
+  bit32 BW_tx;
+  bit32 BW_rx;
+  bit32 InvalidDword;
+  bit32 runningDisparityError;
+  bit32 codeViolation;
+  bit32 LossOfSyncDW;
+  bit32 phyResetProblem;
+  bit32 inboundCRCError;
+}tdPhyCount_t;
+
+
+typedef struct _PHY_GENERAL_STATE
+{
+	bit32 Dword0;
+	bit32 Dword1;
+
+}GetPhyGenState_t;
+typedef struct agsaPhyGeneralState_s
+{
+  GetPhyGenState_t  PhyGenData[16];
+  bit32 Reserved1;
+  bit32 Reserved2;
+} agsaPhyGeneralState_t;
+
+typedef struct _PHY_DETAILS_
+{       
+  bit8    sasAddressLo[4];
+  bit8    sasAddressHi[4];
+  bit8    attached_sasAddressLo[4];
+  bit8    attached_sasAddressHi[4];
+  bit8    attached_phy;
+  bit8    attached_dev_type ;
+}PhyDetails_t;
+
+enum SAS_SATA_DEVICE_TYPE {
+  SAS_PHY_NO_DEVICE ,
+  SAS_PHY_END_DEVICE,
+  SAS_PHY_EXPANDER_DEVICE,
+  SAS_PHY_SATA_DEVICE = 0x11,
+};
+#define PHY_SETTINGS_LEN   1024
+
+#endif  /* TD_IOCTL_H */

sys/dev/pms/RefTisa/tisa/sassata/common/tdlist.h

@@ -0,0 +1,168 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ * The file defines list data structures for SAS/SATA TD layer
+ *
+ */
+
+#ifndef __TDLIST_H__
+#define __TDLIST_H__
+
+
+typedef struct tdList_s tdList_t;
+
+struct tdList_s {
+  tdList_t  *flink;
+  tdList_t  *blink;
+};
+
+#define TDLIST_NEXT_ENTRY(ptr, type, member)        \
+  container_of((ptr)->flink, type, member)  
+
+#define TDLIST_INIT_HDR(hdr)                        \
+  do {                                              \
+    ((tdList_t *)(hdr))->flink = (tdList_t *)(hdr); \
+    ((tdList_t *)(hdr))->blink = (tdList_t *)(hdr); \
+  } while (0)
+
+#define TDLIST_INIT_ELEMENT(hdr)                     \
+  do {                                               \
+    ((tdList_t *)(hdr))->flink = (tdList_t *)agNULL; \
+    ((tdList_t *)(hdr))->blink = (tdList_t *)agNULL; \
+  } while (0)
+
+#define TDLIST_ENQUEUE_AT_HEAD(toAddHdr,listHdr)                                \
+  do {                                                                          \
+    ((tdList_t *)(toAddHdr))->flink           = ((tdList_t *)(listHdr))->flink; \
+    ((tdList_t *)(toAddHdr))->blink           = (tdList_t *)(listHdr) ;         \
+    ((tdList_t *)(listHdr))->flink->blink     = (tdList_t *)(toAddHdr);         \
+    ((tdList_t *)(listHdr))->flink            = (tdList_t *)(toAddHdr);         \
+  } while (0)
+
+#define TDLIST_ENQUEUE_AT_TAIL(toAddHdr,listHdr)                                \
+  do {                                                                          \
+    ((tdList_t *)(toAddHdr))->flink           = (tdList_t *)(listHdr);          \
+    ((tdList_t *)(toAddHdr))->blink           = ((tdList_t *)(listHdr))->blink; \
+    ((tdList_t *)(listHdr))->blink->flink     = (tdList_t *)(toAddHdr);         \
+    ((tdList_t *)(listHdr))->blink            = (tdList_t *)(toAddHdr);         \
+  } while (0)
+
+#define TDLIST_EMPTY(listHdr) \
+  (((tdList_t *)(listHdr))->flink == ((tdList_t *)(listHdr)))
+
+#define TDLIST_NOT_EMPTY(listHdr) \
+  (!TDLIST_EMPTY(listHdr))
+
+#define TDLIST_DEQUEUE_THIS(hdr)                                      \
+  do {                                                                \
+    ((tdList_t *)(hdr))->blink->flink = ((tdList_t *)(hdr))->flink;   \
+    ((tdList_t *)(hdr))->flink->blink = ((tdList_t *)(hdr))->blink;   \
+    ((tdList_t *)(hdr))->flink = ((tdList_t *)(hdr))->blink = agNULL; \
+  } while (0)
+
+#define TDLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr)                              \
+  do {                                                                                \
+    *((tdList_t **)(atHeadHdr))                 = ((tdList_t *)(listHdr))->flink;     \
+    (*((tdList_t **)(atHeadHdr)))->flink->blink = (tdList_t *)(listHdr);              \
+    ((tdList_t *)(listHdr))->flink              = (*(tdList_t **)(atHeadHdr))->flink; \
+  } while (0)
+
+#define TDLIST_DEQUEUE_FROM_HEAD(atHeadHdr,listHdr)             \
+do {                                                            \
+  if (TDLIST_NOT_EMPTY((listHdr)))                              \
+  {                                                             \
+    TDLIST_DEQUEUE_FROM_HEAD_FAST(atHeadHdr,listHdr);           \
+  }                                                             \
+  else                                                          \
+  {                                                             \
+    (*((tdList_t **)(atHeadHdr))) = (tdList_t *)agNULL;         \
+  }                                                             \
+} while (0)
+  
+#define TDLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr)                                \
+  do {                                                                                  \
+    (*((tdList_t **)(atTailHdr)))               = ((tdList_t *)(listHdr))->blink;       \
+    (*((tdList_t **)(atTailHdr)))->blink->flink = (tdList_t *)(listHdr);                \
+    ((tdList_t *)(listHdr))->blink              = (*((tdList_t **)(atTailHdr)))->blink; \
+  } while (0)
+
+#define TDLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr)               \
+  do {                                                            \
+    if (TDLIST_NOT_EMPTY((listHdr)))                              \
+    {                                                             \
+      TDLIST_DEQUEUE_FROM_TAIL_FAST(atTailHdr,listHdr);           \
+    }                                                             \
+    else                                                          \
+    {                                                             \
+      (*((tdList_t **)(atTailHdr))) = (tdList_t *)agNULL;         \
+    }                                                             \
+  } while (0)
+
+#define TDLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr)               \
+  do {                                                                        \
+    ((tdList_t *)toAddListHdr)->blink->flink = ((tdList_t *)listHdr);         \
+    ((tdList_t *)toAddListHdr)->flink->blink = ((tdList_t *)listHdr)->blink;  \
+    ((tdList_t *)listHdr)->blink->flink = ((tdList_t *)toAddListHdr)->flink;  \
+    ((tdList_t *)listHdr)->blink = ((tdList_t *)toAddListHdr)->blink;         \
+    TDLIST_INIT_HDR(toAddListHdr);                                            \
+  } while (0)
+
+#define TDLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr)                    \
+  do {                                                                        \
+    if (TDLIST_NOT_EMPTY(toAddListHdr))                                       \
+    {                                                                         \
+      TDLIST_ENQUEUE_LIST_AT_TAIL_FAST(toAddListHdr, listHdr);                \
+    }                                                                         \
+  } while (0)
+
+#define TDLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr)               \
+  do {                                                                        \
+    ((tdList_t *)toAddListHdr)->blink->flink = ((tdList_t *)listHdr)->flink;  \
+    ((tdList_t *)toAddListHdr)->flink->blink = ((tdList_t *)listHdr);         \
+    ((tdList_t *)listHdr)->flink->blink = ((tdList_t *)toAddListHdr)->blink;  \
+    ((tdList_t *)listHdr)->flink = ((tdList_t *)toAddListHdr)->flink;         \
+    TDLIST_INIT_HDR(toAddListHdr);                                            \
+  } while (0)
+
+#define TDLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr)                    \
+  do {                                                                        \
+    if (TDLIST_NOT_EMPTY(toAddListHdr))                                       \
+    {                                                                         \
+      TDLIST_ENQUEUE_LIST_AT_HEAD_FAST(toAddListHdr, listHdr);                \
+    }                                                                         \
+  } while (0)
+
+#define TD_FIELD_OFFSET(baseType,fieldName) \
+                    ((bit32)((bitptr)(&(((baseType *)0)->fieldName))))
+
+#define TDLIST_OBJECT_BASE(baseType,fieldName,fieldPtr)         \
+                    (void *)fieldPtr == (void *)0 ? (baseType *)0 :             \
+                    ((baseType *)((bit8 *)(fieldPtr) - ((bitptr)(&(((baseType *)0)->fieldName)))))
+
+
+
+#endif /* __TDLIST_H__ */
+

sys/dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h

@@ -0,0 +1,387 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ *
+ * The file defines data structures for SAS/SATA TD layer
+ *
+ */
+
+#ifndef __TDSATYPES_H
+#define __TDSATYPES_H
+
+#define ESGL_PAGES_SIZE sizeof(agsaEsgl_t) /** the esgl page size */
+#define NUM_ESGL_PAGES 0 /* old value 512 */  /**< the default number of esgl pages */
+
+
+/**< target device type */
+#define TD_DEFAULT_DEVICE 0
+#define TD_SAS_DEVICE 1
+#define TD_SATA_DEVICE 2
+
+#include <dev/pms/RefTisa/tisa/sassata/common/tdioctl.h>
+
+
+/** \brief data structure for SATA Host
+ *
+ * to be developed
+ *
+ */
+typedef struct itdstHost_s
+{
+  int i;
+} itdstHost_t;
+
+/** \brief data structure for SATA Device
+ *
+ * to be developed
+ *
+ */
+typedef struct ttdstDevice_s
+{
+  int i;
+} ttdstDevice_t;
+
+#ifdef INITIATOR_DRIVER
+typedef struct itdsaIni_s {
+  /**< point to the shared structure bothe SAS and SATA */
+  struct tdsaContext_s           *tdsaAllShared;
+  itdssOperatingOption_t         OperatingOption;
+  tdSCSIStatusCount_t            ScsiStatusCounts;
+  tdSenseKeyCount_t              SenseKeyCounter;
+  bit32                          NumIOsActive;
+  /* the list of initiator timer; upon expiration timer CB fn is called
+     eg) itdProcessTimers()
+   */
+  tdList_t                       timerlist;
+} itdsaIni_t;
+#endif
+
+struct ttdsaXchgAllocFreeInfoList_s;
+
+#ifdef TARGET_DRIVER
+typedef struct ttdsaTgt_s {
+  /* point to the shared across SAS and SATA */
+  struct tdsaContext_s              *tdsaAllShared;
+  ttdssOperatingOption_t            OperatingOption;
+  tiTargetOption_t                  tiOperatingOption;
+  ttdsaXchgData_t                   ttdsaXchgData;
+#ifdef PASSTHROUGH
+  /* registered passthrough CB */
+  ostiProcessPassthroughCmnd_t      PasthroughCB;
+#endif
+} ttdsaTgt_t;
+#endif
+
+
+/** \brief data structure for SATA Device
+ *
+ * not in use yet. just a place holderto be develped
+ *
+ */
+typedef struct tdHardwareInfo_s {
+  bit16         DeviceID;
+  bit16         VendorID;
+  bit8          ChipRev;
+  bit32         PciFunctionNumber;
+  bit32         FlashRomPresent;
+} tdHardwareInfo_t;
+
+
+/** \brief data structure for ESLG page
+ *
+ * This data structure describes the ESGL page maintained in TD layer.
+ * One important field is agEsgl which is pointer to assaEsgl_t data structure,
+ * which describes ESGL used in lower layer.
+ * Memory for this data structure is allocated using tiTdSharedMem_t data
+ * structure. However, Memory for agsaEsgl_t data structure is allocated using
+ * tiLoLevelResource_t.
+ *
+ */
+typedef struct tdsaEsglPageInfo_s {
+  tdList_t   tdlist;            /**< pointers to next and previous pages */
+  bit32      physAddressUpper;  /**< upper physical address of the page */
+  bit32      physAddressLower;  /**< lower physical address of the page */
+  bit32      len;
+  agsaEsgl_t *agEsgl;
+  bit32      id;                /**< for debugging only */
+} tdsaEsglPageInfo_t;
+
+/** \brief data structure for ESLG page pool
+ *
+ * This data structure describes the pool of esgl pages
+ *
+ */
+typedef struct tdsaEsglPagePool_s {
+  tdsaEsglPageInfo_t EsglPages[1];  /**< variable size array */
+} tdsaEsglPagePool_t;
+
+
+/** \brief data structure for ESGL pool information
+ *
+ * This data structure maintains information about ESGL pool. For example, this
+ * data structure maintains the number of free and total ESGL pages and uses
+ * tdList_t data structure for listing of ESGL pages.
+ *
+ */
+typedef struct tdsaEsglAllInfo_s {
+  /*
+     used in tdGetEsglPages()
+   */
+  tdList_t             mainlist; /* not used */
+  tdList_t             freelist;
+  bit32                NumEsglPages;
+  bit32                NumFreeEsglPages;
+  bit32                EsglPageSize;
+  bit32                physAddrUpper;
+  bit32                physAddrLower;
+  void                 *virtPtr;
+  tdsaEsglPagePool_t   *EsglPagePool;
+} tdsaEsglAllInfo_t;
+
+typedef struct smp_pass_through_req
+{
+		bit8 exp_sas_addr[8];			//Storing the 16 digit expander SAS-address
+		bit32 smp_req_len;				//Length of the request frame
+		bit32 smp_resp_len; 			//Length of the response frame
+		bit8 smp_req_resp[1]; 				//Pointer to the request-response frame
+}smp_pass_through_req_t;
+
+#ifdef TD_INT_COALESCE
+typedef struct tdsaIntCoalesceContext_s {
+  tdList_t                  MainLink;   /* free */
+  tdList_t                  FreeLink; /* in use */
+  struct tdsaContext_s      *tdsaAllShared;
+#ifdef OS_INT_COALESCE
+  tiIntCoalesceContext_t    *tiIntCoalesceCxt;
+#endif
+  agsaIntCoalesceContext_t  agIntCoalCxt;
+  /* for debug */
+  bit32                     id;
+
+} tdsaIntCoalesceContext_t;
+#endif
+
+typedef struct tdsaHwEventSource_s {
+  bit32                 EventValid;
+  agsaEventSource_t     Source;
+} tdsaHwEventSource_t;
+
+/** \brief data structure for SAS/SATA context at TD layer
+ *
+ * This data structure is used for both SAS and SATA.
+ * In addition, this is the data structure used mainly to communicate with
+ * lower layer.
+ *
+ */
+typedef struct tdsaContext_s {
+  bit32                 currentOperation;
+
+  /**< agsaRoot_t->osData points to this */
+  struct tdsaRootOsData_s      agRootOsDataForInt;     /* for interrupt */
+  struct tdsaRootOsData_s      agRootOsDataForNonInt;  /* for non-interrupt */
+
+  agsaRoot_t            agRootInt;          /* for interrupt */
+  agsaRoot_t            agRootNonInt;       /* for non-interrupt */
+
+  /* flags values commonly used for both SAS and SATA */
+  struct tdsaComMemFlags_s       flags;
+
+
+  /**< software-related initialization params used in saInitialize() */
+  agsaSwConfig_t        SwConfig;
+
+  /**< Queue-related initialization params used in saInitialize() */
+  agsaQueueConfig_t     QueueConfig;
+
+  /**< hardware-related initialization params used in saInitialize() */
+  agsaHwConfig_t        HwConfig;
+
+
+  /**< Copy of TI low level resoure */
+  tiLoLevelResource_t   loResource;
+
+  /* information of ESGL pages allocated
+  tdsaEsglAllInfo_t          EsglAllInfo;
+  */
+
+  /*  hardware information; just place holder
+  tdHardwareInfo_t      hwInfo;
+  */
+
+  bit32                 currentInterruptDelay;
+
+  /**< timers used commonly in SAS/SATA */
+  tdList_t                      timerlist;
+  /***********************************************************************/
+  /* used to be in tdssContext_t  tdssSASShared;*/
+  struct itdsaIni_s          *itdsaIni; /* Initiator; */
+  struct ttdsaTgt_s          *ttdsaTgt; /* Target */
+  /**< pointer to PortContext memory;  */
+  tdsaPortContext_t          *PortContextMem;
+  /**< pointer to Device memory */
+  tdsaDeviceData_t           *DeviceMem;
+
+  tdList_t                   FreePortContextList;
+  tdList_t                   MainPortContextList;
+  tdList_t                   FreeDeviceList;
+  tdList_t                   MainDeviceList;
+
+  /**< actual storage for jump table */
+  tdsaJumpTable_t            tdJumpTable;
+  /**< Local SAS port start information such as ID addr */
+  tdsaPortStartInfo_t        Ports[TD_MAX_NUM_PHYS];
+  /***********************************************************************/
+  /**< storage for FW download contents */
+  tdFWControlEx_t              tdFWControlEx;
+#ifdef SPC_ENABLE_PROFILE
+  tdFWProfileEx_t              tdFWProfileEx;
+#endif
+#ifdef TD_INT_COALESCE
+  tdsaIntCoalesceContext_t   *IntCoalesce;
+#endif
+
+  /* first time a card is processed set this true */
+  bit32 first_process;
+
+  /* expander list */
+  tdsaExpander_t             *ExpanderHead;
+  //  tdList_t                   discoveringExpanderList;
+  tdList_t                   freeExpanderList;
+    bit32                      phyCount;
+  bit32                      IBQnumber;
+  bit32                      OBQnumber;
+  bit32                      InboundQueueSize[AGSA_MAX_OUTBOUND_Q];
+  bit32                      InboundQueueEleSize[AGSA_MAX_OUTBOUND_Q];
+  bit32                      OutboundQueueSize[AGSA_MAX_OUTBOUND_Q];
+  bit32                      OutboundQueueEleSize[AGSA_MAX_OUTBOUND_Q];
+  bit32                      OutboundQueueInterruptDelay[AGSA_MAX_OUTBOUND_Q];
+  bit32                      OutboundQueueInterruptCount[AGSA_MAX_OUTBOUND_Q];
+  bit32                      OutboundQueueInterruptEnable[AGSA_MAX_OUTBOUND_Q];
+  bit32                      InboundQueuePriority[AGSA_MAX_INBOUND_Q];
+  bit32                      QueueOption;
+  bit32                      tdDeviceIdVendId;
+  bit32                      tdSubVendorId;
+  /* instance number */
+  bit8                  CardIDString[TD_CARD_ID_LEN];
+  bit32                 CardID;
+#ifdef VPD_TESTING
+  /* temp; for testing VPD indirect */
+  bit32                 addrUpper;
+  bit32                 addrLower;
+#endif
+
+  bit32                 resetCount;
+  tdsaHwEventSource_t   eventSource[TD_MAX_NUM_PHYS];
+  bit32                 portTMO; /* in 100ms */
+  bit32                 phyCalibration; /* enables or disables phy calibration */
+  bit32                 FCA; /* force to clear affiliation by sending SMP HARD RESET */
+  bit32                 SMPQNum; /* first high priority queue number for SMP */
+  bit32                 ResetInDiscovery; /* hard/link reset in discovery */
+  bit32                 FWMaxPorts;
+  bit32                 IDRetry; /* SATA ID failurs are retired */
+  bit32                 RateAdjust; /* allow retry open with lower connection rate */
+#ifdef AGTIAPI_CTL
+  bit16                 SASConnectTimeLimit; /* used by tdsaCTLSet() */
+#endif
+  bit32                 MaxNumOSLocks; /* max number of OS layer locks */
+  bit32                 MaxNumLLLocks; /* max num of LL locks */
+  bit32                 MaxNumLocks;   /* max num of locks for layers and modules (LL, TDM, SATM, DM) */
+#ifdef FDS_DM
+  bit32                 MaxNumDMLocks; /* max num of DM locks */
+  dmRoot_t              dmRoot; /* discovery root */
+  dmSwConfig_t          dmSwConfig;
+#endif
+#ifdef FDS_SM
+  bit32                 MaxNumSMLocks; /* max num of SM locks */
+  smRoot_t              smRoot; /* SATM root */
+  smSwConfig_t          smSwConfig;
+#endif
+  bit32                 MCN; /* temp; only for testing and to be set by registry or adj file */
+  bit32                 sflag; /* Sflag bit */
+#ifdef CCFLAGS_PHYCONTROL_COUNTS
+  agsaPhyAnalogSetupRegisters_t analog[TD_MAX_NUM_PHYS];
+#endif /* CCFLAGS_PHYCONTROL_COUNTS */
+  bit32                 stp_idle_time; /* stp idle time for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 STP_MCT_TMO; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 SSP_MCT_TMO; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 MAX_OPEN_TIME; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 SMP_MAX_CONN_TIMER; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 STP_FRM_TMO; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 MFD; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 OPNRJT_RTRY_INTVL; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 DOPNRJT_RTRY_TMO; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 COPNRJT_RTRY_TMO; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 DOPNRJT_RTRY_THR; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 COPNRJT_RTRY_THR; /*  for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  bit32                 itNexusTimeout;   /*  set by registry */
+  bit32                 MAX_AIP;   /* for agsaSASProtocolTimerConfigurationPage_t; set by registry or adj file */
+  agsaMPIContext_t MpiOverride;
+#ifdef TI_GETFOR_ONRESET
+  bit8   FatalErrorData[(5 * (1024 * 1024))];
+#endif /* TI_GETFOR_ONRESET */
+  bit32	 sgpioResponseSet;    /*Used to sync between SGPIO Req and Resp */
+  volatile  NvmdResponseSet;
+}  tdsaContext_t;
+
+#ifdef FAST_IO_TEST
+#define CMDS_PER_IO_IOPS  1
+#define CMDS_PER_IO_DUP   1 //4
+#endif
+
+/** \brief the root data structure for TD layer
+ *
+ * This data structure is the main data structure used in communicating
+ * with OS layer. For example, tiRoot_t->tdData points to this data structure
+ * From this data structure, SATA host/Device and SAS initiator/target are found.
+ *
+ */
+typedef struct tdsaRoot_s
+{
+  /**<< common data structure for SAS/SATA */
+  tdsaContext_t          tdsaAllShared;
+  bit32                  autoGoodRSP;
+#ifdef INITIATOR_DRIVER
+  itdsaIni_t             *itdsaIni; /**< SAS/SATA initiator */
+#endif
+#ifdef TARGET_DRIVER
+  ttdsaTgt_t             *ttdsaTgt; /**< SAS/SATA target    */
+#endif
+}  tdsaRoot_t;
+
+typedef struct tmf_pass_through_req
+{
+    bit8    pathId;
+    bit8    targetId;
+    bit8    lun;
+}tmf_pass_through_req_t;
+
+/* Context Field accessors */
+#define TD_GET_TIROOT(sa_root)         (((tdsaRootOsData_t *)(sa_root)->osData)->tiRoot)
+#define TD_GET_TDROOT(ti_root)         ((tdsaRoot_t *)(ti_root)->tdData)
+#define TD_GET_TICONTEXT(ti_root)      ((tdsaContext_t *)&TD_GET_TDROOT(ti_root)->tdsaAllShared)
+#define TD_GET_TIINI_CONTEXT(ti_root)  ((itdsaIni_t *)TD_GET_TICONTEXT(ti_root)->itdsaIni)
+#define TD_GET_TITGT_CONTEXT(ti_root)  ((ttdsaTgt_t *)TD_GET_TICONTEXT(ti_root)->ttdsaTgt)
+#endif /* __TDSATYPES_H */

sys/dev/pms/RefTisa/tisa/sassata/common/tdtimers.c

@@ -0,0 +1,302 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ * This file contains timer functions in TD layer
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <dev/pms/config.h>
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+#include <dev/pms/RefTisa/tisa/api/ostiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiapi.h>
+#include <dev/pms/RefTisa/tisa/api/tiglobal.h>
+
+#ifdef FDS_SM
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/api/smapi.h>
+#include <dev/pms/RefTisa/sat/api/tdsmapi.h>
+#endif
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#include <dev/pms/RefTisa/discovery/api/dmapi.h>
+#include <dev/pms/RefTisa/discovery/api/tddmapi.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h>
+#include <dev/pms/freebsd/driver/common/osstring.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdutil.h>
+
+#ifdef INITIATOR_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdtypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/ini/itdglobl.h>
+#endif
+
+#ifdef TARGET_DRIVER
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdxchg.h>
+#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdtypes.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdproto.h>
+
+/*****************************************************************************
+*! \brief  tiCOMTimerTick
+*
+*  Purpose: This function is called to every usecsPerTick interval
+*
+*  \param tiRoot:   Pointer to initiator specific root data structure  for this
+*                   instance of the driver.
+*
+*  \return:         None
+*
+*
+*****************************************************************************/
+osGLOBAL void 
+tiCOMTimerTick (
+                tiRoot_t * tiRoot
+                )
+{
+  tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)(tiRoot->tdData);
+  agsaRoot_t *agRoot = &tdsaRoot->tdsaAllShared.agRootNonInt;
+#ifdef FDS_DM  
+  dmRoot_t   *dmRoot = &tdsaRoot->tdsaAllShared.dmRoot;
+#endif
+
+#ifdef FDS_SM_NOT_YET
+  smRoot_t   *smRoot = &tdsaRoot->tdsaAllShared.smRoot;
+#endif
+  /* checking the lower layer */
+  saTimerTick(agRoot);
+  
+#ifdef FDS_DM  
+  /* checking the DM */
+  dmTimerTick(dmRoot);
+#endif
+
+#ifdef FDS_SM_NOT_YET  
+  /* checking the SM */
+  smTimerTick(smRoot);
+#endif
+    
+  /*
+    timers for discovery 
+    checking tdsaRoot_t timers 
+  */
+  
+  tdsaProcessTimers(tiRoot);
+ 
+}
+
+/*****************************************************************************
+*! \brief  tdsaInitTimerRequest
+*
+*  Purpose: This function initiallizes timer request
+*
+*  \param tiRoot:       Pointer to initiator specific root data structure
+*                       for this instance of the driver.
+*  \param timerrequest  Pointer to timer request
+*
+*  \return:             None
+*
+*
+*****************************************************************************/
+osGLOBAL void
+tdsaInitTimerRequest(
+                     tiRoot_t                *tiRoot,
+                     tdsaTimerRequest_t      *timerRequest
+                     )
+{
+  timerRequest->timeout       = 0;
+  timerRequest->timerCBFunc   = agNULL;
+  timerRequest->timerData1     = agNULL;
+  timerRequest->timerData2     = agNULL;
+  timerRequest->timerData3     = agNULL;
+  TDLIST_INIT_ELEMENT((&timerRequest->timerLink));
+}
+
+/*****************************************************************************
+*! \brief  tdsaSetTimerRequest
+*
+*  Purpose: This function sets timer request
+*
+*  \param tiRoot:       Pointer to initiator specific root data structure
+*                       for this instance of the driver.
+*  \param timerrequest  Pointer to timer request
+*  \param timeout       timeout value
+*  \param CBFunc        timer CB function
+*  \param timerData1     Data associated with the timer
+*  \param timerData2     Data associated with the timer
+*  \param timerData3     Data associated with the timer
+*
+*  \return:             None
+*
+*
+*****************************************************************************/
+osGLOBAL void
+tdsaSetTimerRequest(
+                  tiRoot_t            *tiRoot,
+                  tdsaTimerRequest_t  *timerRequest,
+                  bit32               timeout,
+                  tdsaTimerCBFunc_t   CBFunc,
+                  void                *timerData1,
+                  void                *timerData2,
+                  void                *timerData3
+                  )
+{
+  timerRequest->timeout     = timeout;
+  timerRequest->timerCBFunc = CBFunc;
+  timerRequest->timerData1   = timerData1;
+  timerRequest->timerData2   = timerData2;
+  timerRequest->timerData3   = timerData3;
+}
+
+/*****************************************************************************
+*! \brief  tdsaAddTimer
+*
+*  Purpose: This function adds timer request to timer list
+*
+*  \param tiRoot:       Pointer to initiator specific root data structure
+*                       for this instance of the driver.
+*  \param timerListHdr  Pointer to the timer list
+*  \param timerrequest  Pointer to timer request
+*
+*  \return:             None
+*
+*
+*****************************************************************************/
+osGLOBAL void
+tdsaAddTimer(
+             tiRoot_t            *tiRoot,
+             tdList_t            *timerListHdr, 
+             tdsaTimerRequest_t  *timerRequest
+            )
+{
+  tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK);
+  TDLIST_ENQUEUE_AT_TAIL(&(timerRequest->timerLink), timerListHdr);
+  timerRequest->timerRunning = agTRUE;
+  tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK);
+}
+
+/*****************************************************************************
+*! \brief  tdsaKillTimer
+*
+*  Purpose: This function kills timer request.
+*
+*  \param tiRoot:       Pointer to initiator specific root data structure
+*                       for this instance of the driver.
+*  \param timerrequest  Pointer to timer request
+*
+*  \return:             None
+*
+*
+*****************************************************************************/
+osGLOBAL void
+tdsaKillTimer(
+              tiRoot_t            *tiRoot,
+              tdsaTimerRequest_t  *timerRequest
+              )
+{
+  tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK);
+  timerRequest->timerRunning = agFALSE;
+  TDLIST_DEQUEUE_THIS(&(timerRequest->timerLink));
+  tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK);
+}
+
+/*****************************************************************************
+*! \brief  tdsaProcessTimers
+*
+*  Purpose: This function processes timer request.
+*
+*  \param tiRoot:       Pointer to initiator specific root data structure
+*                       for this instance of the driver.
+*
+*  \return:             None
+*
+*
+*****************************************************************************/
+osGLOBAL void 
+tdsaProcessTimers(
+                  tiRoot_t *tiRoot
+                  )
+{
+  tdsaRoot_t     *tdsaRoot = (tdsaRoot_t *)(tiRoot->tdData);
+  tdsaContext_t  *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared;
+  tdsaTimerRequest_t *timerRequest_to_process = agNULL;
+  tdList_t *timerlist_to_process, *nexttimerlist = agNULL;
+
+  
+  timerlist_to_process = &tdsaAllShared->timerlist;
+  
+  timerlist_to_process = timerlist_to_process->flink;
+
+  while ((timerlist_to_process != agNULL) && (timerlist_to_process != &tdsaAllShared->timerlist))
+  {
+    nexttimerlist = timerlist_to_process->flink;
+    
+    tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK);
+    timerRequest_to_process = TDLIST_OBJECT_BASE(tdsaTimerRequest_t, timerLink, timerlist_to_process);
+    tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK);
+
+    if (timerRequest_to_process == agNULL)
+    {
+      TI_DBG1(("tdsaProcessTimers: timerRequest_to_process is NULL! Error!!!\n"));
+      return;      
+    }
+    
+    timerRequest_to_process->timeout--;
+    
+    if (timerRequest_to_process->timeout == 0)
+    {
+      tdsaSingleThreadedEnter(tiRoot, TD_TIMER_LOCK);
+      if (timerRequest_to_process->timerRunning == agTRUE)
+      {
+        timerRequest_to_process->timerRunning = agFALSE;
+        TDLIST_DEQUEUE_THIS(timerlist_to_process);
+      }
+      tdsaSingleThreadedLeave(tiRoot, TD_TIMER_LOCK);
+      /* calling call back function */
+      (timerRequest_to_process->timerCBFunc)(tiRoot, 
+                                             timerRequest_to_process->timerData1, 
+                                             timerRequest_to_process->timerData2, 
+                                             timerRequest_to_process->timerData3 
+                                             );
+    }
+    timerlist_to_process = nexttimerlist;
+  }
+  return;
+}
+

sys/dev/pms/RefTisa/tisa/sassata/common/tdutil.h

@@ -0,0 +1,105 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ * The file defines utilities for SAS/SATA TD layer
+ *
+ */
+
+#ifndef __TDUTIL_H__
+#define __TDUTIL_H__
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/tisa/api/tidefs.h>
+#include <dev/pms/RefTisa/tisa/api/titypes.h>
+#include <dev/pms/RefTisa/tisa/api/tiapi.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdlist.h>
+
+
+#define HEXDIGIT2CHAR(x)     (((x) < 10) ? ('0' + (x)) : ('A' + ((x) - 10)))
+/*****************************************************************************
+*! \brief tdDecimal2String
+*
+*  Purpose:  This function converts a given number into a decimal string.
+*            
+*  \param s:                  string to be generated
+*  \param num:                number to be converted
+*
+*  \return None
+*
+*  \note - string s should be large enough to store decimal string of
+*        num and a '\0' character
+*
+*****************************************************************************/
+void 
+tdDecimal2String(
+  char *s, 
+  bit32 num
+  );
+
+void
+tdHexToString (
+  char  *String,
+  bit32  Value1,
+  bit32  Value2,
+  bit32  Strlength
+  );
+
+bit8 tdStr2Bit8 (char *buffer);
+
+bit32 tdStr2ALPA (char *buffer);
+
+void tdStr2WWN (char *buffer, bit8 * NodeName);
+
+void tdWWN2Str (char *buffer, bit8 * NodeName);
+
+/*****************************************************************************
+*! \brief tdNextPowerOf2
+*
+*  Purpose:  This function is called to calculate the next power of 2
+*            value of given value.
+*            
+*
+*  \param  Value:             The value for which next power of 2 is requested
+*
+*  \return: The next power of 2 value of given Value
+*
+*****************************************************************************/
+bit32 
+tdNextPowerOf2 (
+  bit32 Value
+  );
+
+osGLOBAL agBOOLEAN
+tdListElementOnList(
+    tdList_t *toFindHdr,
+    tdList_t *listHdr
+    );
+
+
+#endif /* __TDUTIL_H__ */
+
+
+

sys/dev/pms/RefTisa/tisa/sassata/sas/common/tdtypes.h

@@ -0,0 +1,737 @@
+/*******************************************************************************
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ * The file defines data structures for SAS/SATA TD layer
+ *
+ */
+#ifndef __TDTYPES_H__
+#define __TDTYPES_H__
+
+#include <dev/pms/freebsd/driver/common/osenv.h>
+#include <dev/pms/freebsd/driver/common/ostypes.h>
+#include <dev/pms/freebsd/driver/common/osdebug.h>
+
+#include <dev/pms/RefTisa/sallsdk/api/sa.h>
+#include <dev/pms/RefTisa/sallsdk/api/saapi.h>
+#include <dev/pms/RefTisa/sallsdk/api/saosapi.h>
+
+#ifdef FDS_SM
+#include <dev/pms/RefTisa/sat/api/sm.h>
+#include <dev/pms/RefTisa/sat/src/smtypes.h>
+#endif
+
+#ifdef FDS_DM
+#include <dev/pms/RefTisa/discovery/api/dm.h>
+#endif
+
+#include <dev/pms/RefTisa/tisa/sassata/common/tddefs.h>
+#include <dev/pms/RefTisa/tisa/sassata/common/tdlist.h>
+#include <dev/pms/RefTisa/tisa/api/tiscsi.h>
+
+
+/* function definitions */
+typedef void (*tdssSSPReqReceived_t) (
+                                      agsaRoot_t *,
+                                      agsaDevHandle_t *,
+                                      agsaFrameHandle_t,
+                                      bit32,
+                                      bit32,
+                                      bit32
+                                      );
+typedef void (*tdssSMPReqReceived_t) (
+                                      agsaRoot_t            *,
+                                      agsaDevHandle_t       *,
+                                      agsaSMPFrameHeader_t  *,
+                                      agsaFrameHandle_t,
+                                      bit32,
+                                      bit32
+                                      );
+                                      
+typedef bit32 (*tdssGetSGLChunk_t) (agsaRoot_t      *agRoot,
+                                    agsaIORequest_t *agIORequest,
+                                    bit32           agChunkOffset,
+                                    bit32           *agChunkUpper32,
+                                    bit32           *agChunkLower32,
+                                    bit32           *agChunkLen);
+/* for SSP only */
+typedef void (*tdssIOCompleted_t) (agsaRoot_t *,
+                                   agsaIORequest_t *,
+                                   bit32,
+                                   bit32,
+                                   agsaFrameHandle_t,
+                                   bit32);
+/* for SMP only */
+typedef void (*tdssSMPCompleted_t) (
+                                    agsaRoot_t            *,
+                                    agsaIORequest_t       *,
+                                    bit32                 ,
+                                    bit32                 ,
+                                    agsaFrameHandle_t     
+                                    );
+
+
+/** \brief data structure for callback function jumptableESLG page
+ *
+ * This data structure defines callback fucntions for SSP, SMP and SATA
+ * This is used for jump table used for instance specific function callback jump
+ *
+ */
+typedef struct tdsaJumpTable_s {
+  /**< function that called to process received SSP frame */
+  tdssSSPReqReceived_t pSSPReqReceived;
+  /**< function that called to process received SSP frame */
+  tdssSMPReqReceived_t pSMPReqReceived;
+  /**< SSP IO completion callback function eg) ossaSSPcompleted() */
+  tdssIOCompleted_t         pSSPIOCompleted;
+  /**< SMP IO completion callback function eg) ossaSMPcompleted() */
+  tdssSMPCompleted_t        pSMPCompleted;
+  /* callback function for LL getSGL. Simple place holder for now */
+  tdssGetSGLChunk_t         pGetSGLChunk;
+}  tdsaJumpTable_t;
+
+/* timer functions ; both I and T */
+typedef void (*tdsaTimerCBFunc_t)(tiRoot_t *tiRoot, void *timerData1, void *timerData2, void *timerData3);
+
+/** \brief data structure for timer request
+ *  Timer requests are enqueued and dequeued using tdList_t
+ *  and have a callback function
+ */
+typedef struct tdsaTimerRequest_s {
+  /* the number of ticks */
+  bit32             timeout;
+  void              *timerData1;
+  void              *timerData2;
+  void              *timerData3;
+  tdsaTimerCBFunc_t timerCBFunc;
+  tdList_t          timerLink;
+  bit32             timerRunning;
+}  tdsaTimerRequest_t;
+
+
+/** \brief data structure for IO request data
+ *  used at target only in ttdtxchg_t structure
+ *  just a place holder for now
+ */
+typedef struct tdssIORequestData_s {
+  /* jump table has to be the first */
+  tdsaJumpTable_t *pJumpTable;    /* this is just a pointer */
+}  tdssIORequestData_t;
+
+
+
+/** \brief data structure OS root from the view of lower layer.
+ * TD Layer interrupt/non-interrupt context support structure for agsaRoot_t.
+ * The osData part of agsaRoot points to this tdsaRootOsData_t structure.
+ * In other words, agsaRoot_t->osData points to this structure and used for
+ * both SAS and SATA
+ */
+typedef struct tdsaRootOsData_s {
+  tiRoot_t  *tiRoot;            /**< Pointer back to tiRoot                 */
+  void      *tdsaAllShared;     /**< Pointer to tdsaContext_t               */
+  void      *itdsaIni;           /**< Pointer to SAS/SATA initiator               */
+  void      *ttdsaTgt;           /**< Pointer to SAS/SATA target                  */
+  /* for sata */
+  void      *tdstHost;          /**< Pointer to SATA Host                   */
+  void      *tdstDevice;        /**< Pointer to SATA Device                 */
+  agBOOLEAN IntContext;         /**< Interrupt context                      */
+}  tdsaRootOsData_t;
+
+/** \brief data structure for port/phy related flags
+ *  Some fields are just place holders and not used yet
+ */
+typedef struct tdssPortFlags_s {
+  /**< port started flag */
+  agBOOLEAN             portStarted;
+
+  /**< port initialized flag */
+  agBOOLEAN             portInitialized;
+
+  agBOOLEAN             portReadyForDiscoverySent;
+
+  /**< port stopped by oslayer */
+  agBOOLEAN             portStoppedByOSLayer;
+
+  /**< fail portinit/start */
+  agBOOLEAN             failPortInit;
+  
+  agBOOLEAN             pseudoPortInitDone;
+  agBOOLEAN             pseudoPortStartDone;  
+}  tdssPortFlags_t;
+
+/** \brief data structure for both SAS/SATA related flags
+ *  Some fields are just place holders and not used yet
+ * 
+ */
+typedef struct tdsaComMemFlags_s {
+  /**< current interrupt setting */
+  agBOOLEAN             sysIntsActive;      
+
+  /**< reset in progress */
+  agBOOLEAN             resetInProgress;
+
+  /**< reset status */
+  agBOOLEAN             resetFailed;
+
+}  tdsaComMemFlags_t;
+
+
+/* 
+ * SAT related structure 
+ */
+typedef struct satInternalIo_s
+{
+  tdList_t                    satIntIoLink;
+  tiIORequest_t               satIntTiIORequest;
+  void                        *satIntRequestBody;
+  tiScsiInitiatorRequest_t   satIntTiScsiXchg;
+  tiMem_t                     satIntDmaMem;
+  tiMem_t                     satIntReqBodyMem;
+  bit32                       satIntFlag;
+  tiIORequest_t               *satOrgTiIORequest;
+  bit32                       id;
+} satInternalIo_t;
+
+
+
+/*
+ * SAT specific structure per SATA drive 
+ */
+#define SAT_NONNCQ_MAX  1
+#define SAT_NCQ_MAX     32
+#define SAT_MAX_INT_IO  16
+
+typedef struct TDSASAddressID_s 
+{
+  bit32   sasAddressLo;     /**< HOST SAS address lower part */
+  bit32   sasAddressHi;     /**< HOST SAS address higher part */
+  bit8    phyIdentifier;    /**< PHY IDENTIFIER of the PHY */
+} TDSASAddressID_t;
+
+
+struct tdsaExpander_s;
+
+
+typedef struct tdsaDiscovery_s 
+{
+  tdList_t                   discoveringExpanderList;
+  tdList_t                   UpdiscoveringExpanderList;
+  //  tdList_t                   freeExpanderList;
+  bit32                   status;
+  TDSASAddressID_t        sasAddressIDDiscoverError;
+  agsaSATAIdentifyData_t  *pSataIdentifyData;
+  struct tdsaExpander_s   *RootExp; /* Root expander of discovery */
+  bit32                   NumOfUpExp;
+  bit32                   type; /* discovery type: TDSA_DISCOVERY_OPTION_FULL_START 
+                                   or TDSA_DISCOVERY_OPTION_INCREMENTAL_START*/
+  bit32                   retries;                                   
+  bit32                   configureRouteRetries; 
+  bit32                   deviceRetistrationRetries; 
+  tdsaTimerRequest_t      discoveryTimer;
+  tdsaTimerRequest_t      configureRouteTimer;
+  tdsaTimerRequest_t      deviceRegistrationTimer;
+  tdsaTimerRequest_t      BCTimer; /* Broadcast Change timer for ResetTriggerred */
+  smpRespDiscover_t       SMPDiscoverResp;
+  bit32                   pendingSMP; /* the number of pending SMP for this discovery */
+  bit32                   SeenBC; /* received Broadcast change */
+  bit32                   forcedOK; /* report DiscOK when chance is missed */ 
+  tdsaTimerRequest_t      SMPBusyTimer; /* SMP retry timer for saSMPStart busy */
+  bit32                   SMPRetries; /* number of SMP retries when LL returns busy for saSMPStart*/
+  bit32                   ResetTriggerred; /* Hard/Link reset triggerred by discovery */
+  tdsaTimerRequest_t      DiscoverySMPTimer; /* discovery-related SMP application Timer */
+} tdsaDiscovery_t;
+
+
+typedef struct 
+{
+  tdList_t                satIoLinkList;            /* Normal I/O from TISA         */
+  tdList_t                satFreeIntIoLinkList;     /* SAT internal I/O free list   */
+  tdList_t                satActiveIntIoLinkList;   /* SAT internal I/O active list */
+  satInternalIo_t         satIntIo[SAT_MAX_INT_IO]; /* Internal I/O resource        */
+  agsaSATAIdentifyData_t  satIdentifyData;          /* Copy of SATA Id Dev data     */
+  bit8                    SN_id_limit[25];          /* temporary serial number id info */
+  bit32                   satNCQ;                   /* Flag for NCQ support         */ 
+  bit32                   sat48BitSupport;          /* Flag for 48-bit addressing   */
+  bit32                   satSMARTSelfTest;         /* Flag for SMART self test     */
+  bit32                   satSMARTFeatureSet;       /* Flag for SMART feature set   */
+  bit32                   satSMARTEnabled;          /* Flag for SMART enabled       */
+  bit32                   satRemovableMedia;        /* Flag for Removable Media     */
+  bit32                   satRemovableMediaEnabled; /* Flag for Removable Media Enabled */
+  bit32                   satDMASupport;            /* Flag for DMA Support         */
+  bit32                   satDMAEnabled;            /* Flag for DMA Enabled         */
+  bit32                   satDMADIRSupport;         /* Flag in PACKET command for DMA transfer */
+  bit32                   satWWNSupport;            /* Flag for DMA Enabled         */
+  bit32                   satPendingIO;             /* Number of pending I/O        */
+  bit32                   satPendingNCQIO;          /* Number of pending NCQ I/O    */
+  bit32                   satPendingNONNCQIO;       /* Number of pending NON NCW I/O*/
+  bit32                   satNCQMaxIO;              /* Max NCQ I/O in SAT or drive  */
+  bit32                   satDriveState;            /* State of SAT/drive           */
+  bit32                   satAbortAfterReset;       /* Flag: abort after SATA reset */
+  bit32                   satAbortCalled;           /* Flag: abort called indication*/
+  bit32                   satVerifyState;           /* Flag: Read Vrf state for diag*/
+  bit32                   satMaxUserAddrSectors;    /* max user addressable setctors*/
+  bit32                   satWriteCacheEnabled;     /* Flag for write cache enabled */
+  bit32                   satLookAheadEnabled;      /* Flag for look ahead enabled  */
+  bit32                   satDeviceFaultState;      /* State of DF                  */
+  bit32                   satStopState;             /* State of Start and Stop      */
+  bit32                   satFormatState;           /* State of format              */
+  bit32                   satPMField;               /* PM field, first 4 bits       */
+  bit8                    satSignature[8];          /* Signature                    */
+  bit32                   satDeviceType;            /* ATA device type              */
+  bit32                   satSectorDone;            /* Number of Sector done by Cmnd*/
+  bit32                   freeSATAFDMATagBitmap;    /* SATA NCQ tag bit map         */
+  bit32                   IDDeviceValid;            /* ID DeviceData valid bit      */
+  bit8                    satMaxLBA[8];             /* MAXLBA is from read capacity */
+  bit32                   satBGPendingDiag;         /* Pending Diagnostic in backgound */
+  bit32                   NumOfFCA;                 /* number of SMP HARD RESET on this device */   
+  bit32                   NumOfIDRetries;           /* number of SMP HARD RESET after ID retries */   
+  tiIORequest_t           *satTmTaskTag;            /* TM Task Tag                  */
+  void                    *satSaDeviceData;         /* Pointer back to sa dev data  */
+  bit32                   ID_Retries;               /* identify device data retries */
+  bit32                   IDPending;                /* number of pending identify device data */
+} satDeviceData_t;
+
+
+/** \brief data structure for SAS device list
+ *  This structure maintains the device as a list and information about
+ *  the device such as the device type and ID address frame.
+ *  agsaDeviceHandle_t->osData points to this structure.
+ */
+typedef struct tdsaDeviceData_s  {
+  /* in tdtypes.h */
+  tdsaJumpTable_t        *pJumpTable; /**< a pointer to callback function jumptable */
+  tiDeviceHandle_t       tiDeviceHandle; 
+
+  tdList_t                FreeLink; /* free dev list */
+  tdList_t                MainLink; /* main(in use) dev list */
+  tdList_t                IncDisLink; /* Used for incremental Discovery only */
+  bit32                   id; /* for debugging only */
+  bit32                   InQID; /* Inbound queue ID */
+  bit32                   OutQID; /* Outbound queue ID */
+  bit8                    DeviceType;
+  /* used in tiINIIOStart() */
+  agsaRoot_t              *agRoot;
+  agsaDevHandle_t         *agDevHandle;
+  
+  /* for SAS; remote device */
+  //  agsaSASDeviceInfo_t     agSASDeviceInfo;
+  /* device's sas address */
+  TDSASAddressID_t        SASAddressID;
+  bit8                    initiator_ssp_stp_smp;
+  bit8                    target_ssp_stp_smp;
+  bit8                    numOfPhys;
+  /* SATA specific data */
+  satDeviceData_t         satDevData;
+
+  /**< pointer to tdsaPortcontext which the device belongs to */
+  struct tdsaPortContext_s *tdPortContext;
+  /* validity of device */
+  bit8                    valid;
+  bit8                    valid2;
+  bit8                    processed; /* used in TD discovery */
+#ifdef AGTIAPI_CTL
+  bit8                    discovered;
+#endif
+  agsaDeviceInfo_t        agDeviceInfo;
+  agsaContext_t           agContext; /* used in saRegisterNewDevice()*/
+  /**< pointer to tdsaExpander if Device is expander */
+  struct tdsaExpander_s   *tdExpander;
+  struct tdsaDeviceData_s *ExpDevice; /* Expander device which this device is attached to */
+  
+  bit8                    phyID;      /* PhyID this device is attached to SPC or expander */
+  agsaSASIdentify_t     sasIdentify; /* used only in TD discovery */
+  bit8                  connectionRate;
+  bit8                  registered;
+  bit8                  directlyAttached;
+  bit8                  SASSpecDeviceType; /* 0 - 3; SAS_NO_DEVICE - SAS_FANOUT_EXPANDER_DEVICE */
+  bit32                 IOStart;
+  bit32                 IOResponse;
+  agsaContext_t         agDeviceResetContext; /* used in saLocalPhyControl() */
+  tiIORequest_t         TransportRecoveryIO;
+  bit32                 TRflag; /* transport recovery flag; used only for tiINITransportRecovery */
+  bit32                 ResetCnt; /* number of reset to the device */  
+  tdsaTimerRequest_t    SATAIDDeviceTimer; /* ID Device Data timer for SATA device */
+  bit32                 OSAbortAll;
+#ifdef FDS_DM
+  bit32                 devMCN; /* MCN reported by DM */
+  bit32                 finalMCN; /* final MCN using devMCN and local MCN */
+#endif
+#ifdef FDS_SM
+  smDeviceHandle_t      smDeviceHandle; /* for SATM */
+  bit32                 SMNumOfFCA;
+  bit32                 SMNumOfID;
+  tdsaTimerRequest_t    tdIDTimer; /* ID Device Data timer for SATA device */
+#endif 
+}  tdsaDeviceData_t;
+
+/*
+  this field is used to add or remove SAS device from sharedcontext
+*/
+typedef struct tdsaSASSubID_s
+{
+  bit32        sasAddressHi;
+  bit32        sasAddressLo;
+  bit8         initiator_ssp_stp_smp;
+  bit8         target_ssp_stp_smp;
+
+} tdsaSASSubID_t;
+
+
+struct tdsaDeviceData_s;
+//struct itdssDiscoveryData_s;
+
+/** \brief data structure for TD port context
+ *  This structure maintains information about the port such as ID address frame
+ *  and the discovery status and the list of devices discovered by this port.
+ *  itdsaIni_t->PortContext[] points to this structure.
+ *  agsaPortContext->osData points to this structure, too.
+ */
+typedef struct tdsaPortContext_s
+{
+  /**< current number of devices in this PortContext */
+  bit32                         Count;
+ 
+  bit32                   DiscoveryState;   
+  
+  bit32                   discoveryOptions;
+  /* Discovery ready is given? */ 
+  bit32                   DiscoveryRdyGiven; 
+  /* Port has received link up */
+  bit32                   SeenLinkUp;
+  /* statistics */
+  bit32                   numAvailableTargets;
+  /* flag: indicates that discovery is trigggered by tiINIDiscoverTargets */
+  bit32                   osInitiatedDiscovery;
+  
+  bit32                         id; /* for debugging only */
+  tdList_t                      FreeLink; /**< free portcontext list */
+  tdList_t                      MainLink; /**< in-use portcontext list */
+  /**< SAS address of the remote device */
+  bit32                         sasRemoteAddressHi; /**< SAS address high part */
+  bit32                         sasRemoteAddressLo; /**< SAS address low part */
+  /**< SAS ID frame of the remote device */
+  agsaSASIdentify_t             sasIDframe;
+  
+  /**< SAS address of the local device*/
+  bit32                         sasLocalAddressHi; /**< SAS address high part */
+  bit32                         sasLocalAddressLo; /**< SAS address low part */
+
+  /**< the list of PhyID belonging to this port */
+  bit8                          PhyIDList[TD_MAX_NUM_PHYS];
+  tiPortalContext_t             *tiPortalContext;
+  /* used in tiINIDiscoverTarget() */
+  agsaRoot_t                    *agRoot;
+  agsaPortContext_t             *agPortContext;
+  /* maybe needs timers for saPhyStart() */
+
+  bit8                  nativeSATAMode; /* boolean flag: whether the port is in Native SATA mode */
+  bit8                remoteSignature[8]; /* the remote signature of the port is the port is in native SATA mode */
+  bit8                 directAttatchedSAS; /* boolean flag: whether the port connected directly to SAS end device*/
+  /* SAS/SATA discovery information such as discoveringExpanderList */
+  tdsaDiscovery_t            discovery;
+  bit32                      valid;
+  bit8                       LinkRate;
+  bit32                      RegisteredDevNums; /* registered number of devices */
+  bit32                      eventPhyID; /* used for saHwEventAck() */
+  bit32                      Transient; /* transient period between link up and link down/port recovery */
+  agsaContext_t              agContext; /* used in tiCOMPortStop()*/
+  bit32                      PortRecoverPhyID; /* used to remember PhyID in Port_Recover event; used in ossaDeviceRegistrationCB() */
+  bit32                      DiscFailNSeenBC; /* used to remember broadcast change after discovery failure */
+  bit8                       remoteName[68];
+#ifdef FDS_DM
+  dmPortContext_t            dmPortContext;
+  bit32                      DMDiscoveryState; /* DM discovery state returned by tddmDiscoverCB or tddmQueryDiscoveryCB */
+  bit32                      UseDM; /* set only when the directly attached target is SMP target(expander) */
+  bit32                      UpdateMCN; /* flag for inidicating update MCN */    
+#endif  
+}  tdsaPortContext_t;
+
+/** \brief data structure for TD port information
+ *  This structure contains information in order to start the port
+ *  The most of fields are filled in by OS layer and there can be up to
+ *  8 of these structures
+ *  tiPortalContext_t->tdData points to this structure.
+ */
+typedef struct tdsaPortStartInfo_s {
+  tiPortalContext_t  *tiPortalContext; 
+  tdsaPortContext_t  *portContext; /* tdsaportcontext */
+  agsaSASIdentify_t  SASID;        /* SAS ID of the local */
+  tdssPortFlags_t    flags;
+  agsaPhyConfig_t    agPhyConfig;
+}  tdsaPortStartInfo_t;
+/*
+  expander data structure
+*/
+
+#define REPORT_LUN_LEN             16
+#define REPORT_LUN_OPCODE          0xa0
+typedef struct tdDeviceLUNInfo_s
+{
+  unsigned long 	    tiDeviceHandle; 
+  bit32                  numOfLun; 
+}tdDeviceLUNInfoIOCTL_t;
+
+typedef struct tdsaExpander_s 
+{
+  tdList_t                  linkNode; /**< the link node data structure of the expander */
+  tdList_t                  upNode; /**< the link node data structure of the expander */
+  tdsaDeviceData_t          *tdDevice; /**< the pointer to the device */
+  struct tdsaExpander_s     *tdUpStreamExpander; /**< the pointer to the upstream expander device */
+  bit8                      hasUpStreamDevice;
+  bit8                      discoveringPhyId;
+  bit16                     routingIndex; /* maximum routing table index reported by expander */
+  bit16                     currentIndex[TD_MAX_EXPANDER_PHYS]; /* routing table index in use */
+  tdsaDeviceData_t          *tdDeviceToProcess;    /* on some callbacks, this is a link to the device of interest */
+  bit32                     configSASAddressHi;
+  bit32                     configSASAddressLo;
+  struct tdsaExpander_s     *tdCurrentDownStreamExpander; 
+  bit8                      upStreamPhys[TD_MAX_EXPANDER_PHYS];
+  bit16                     numOfUpStreamPhys;
+  bit16                     currentUpStreamPhyIndex;
+  bit32                     upStreamSASAddressHi; 
+  bit32                     upStreamSASAddressLo;  
+  bit32                     underDiscovering;
+  bit32                     configRouteTable: 1;
+  bit32                     configuring: 1;
+  bit32                     configReserved: 30;
+  bit32                     id; /* for debugging */
+  struct tdsaExpander_s     *tdReturnginExpander;
+  bit8                      downStreamPhys[TD_MAX_EXPANDER_PHYS];
+  bit16                     numOfDownStreamPhys;
+  bit16                     currentDownStreamPhyIndex;
+  bit32                     discoverSMPAllowed; /* used only for configurable routers */
+  bit8                      routingAttribute[TD_MAX_EXPANDER_PHYS];
+  bit32                     configSASAddressHiTable[DEFAULT_MAX_DEV];
+  bit32                     configSASAddressLoTable[DEFAULT_MAX_DEV];
+  bit32                     configSASAddrTableIndex;  
+  
+} tdsaExpander_t;
+
+/* 
+ * SATA SAT specific function pointer for SATA completion for SAT commands.
+ */
+typedef void (*satCompleteCbPtr_t  )(
+                          agsaRoot_t        *agRoot,
+                          agsaIORequest_t   *agIORequest,
+                          bit32             agIOStatus,
+                          agsaFisHeader_t   *agFirstDword,
+                          bit32             agIOInfoLen,
+                          agsaFrameHandle_t agFrameHandle,
+                          void              *satIOContext
+                       );
+
+/* 
+ * SATA SAT specific function for I/O context
+ */
+typedef struct satIOContext_s 
+{
+  tdList_t                    satIoContextLink;
+  satDeviceData_t             *pSatDevData;
+  agsaFisRegHostToDevice_t    *pFis;
+  tiIniScsiCmnd_t             *pScsiCmnd;
+  scsiRspSense_t              *pSense;
+  tiSenseData_t               *pTiSenseData;
+  void                        *tiRequestBody;
+  void                        *tiScsiXchg; /* for writesame10() */
+  bit32                       reqType;
+  bit32                       interruptContext;
+  satCompleteCbPtr_t          satCompleteCB;
+  satInternalIo_t             *satIntIoContext;
+  tiDeviceHandle_t            *ptiDeviceHandle;
+  bit8                        sataTag;
+  bit8                        superIOFlag;/* Flag indicating type for tiScsiXchg */
+  bit8                        reserved1;  /* Padding for allignment */
+  bit8                        reserved2;  /* Padding for allignment */
+  bit32                       currentLBA; /* current LBA for read and write */
+  bit32                       ATACmd;     /* ATA command */
+  bit32                       OrgTL;      /* original tranfer length(tl) */
+  bit32                       LoopNum;    /* denominator tl */
+  bit32                       LoopNum2;    /* denominator tl */
+  bit8                        LBA[8];     /* for reassign blocks; current LBA */
+  bit32                       ParmIndex;  /* for reassign blocks;current idx in defective LBA LIST */
+  bit32                       ParmLen;    /* for reassign blocks; defective LBA list length */
+  bit32                       NotifyOS;   /* only for task management */
+  bit32                       TMF;        /* task management function */
+  struct satIOContext_s       *satToBeAbortedIOContext; 
+  struct satIOContext_s       *satOrgIOContext;
+  bit32                       pid;        /* port id; used to protect double completion */
+} satIOContext_t;
+
+
+/** \brief data structure for SAS SSP IO reuqest body
+ *  This structure contains IO related fields.
+ *  agsaIORequest->osData points to this 
+ */
+typedef struct tdIORequestBody_s {
+  tdssIOCompleted_t              IOCompletionFunc; 
+  tiDeviceHandle_t               *tiDevHandle;
+  tiIORequest_t                  *tiIORequest; /* for ini */
+  agsaIORequest_t                agIORequest; /* for command and task and tm response and response */
+  tiIORequest_t                  *tiIOToBeAbortedRequest; /* IO to be aborted */
+  agsaContext_t                  agContext;  
+#ifdef FDS_SM
+  smIORequestBody_t              smIORequestBody;    /*SATA IO request body*/
+  smIORequest_t                  smIORequest; /* for SATM */
+  void                           *osMemHandle; /* for ID data */
+  bit32                          pid;  /* port id for SATA completion */
+  bit32                          superIOFlag; /* Super IO or not */ 
+  union {
+    smScsiInitiatorRequest_t       smSCSIRequest;
+    smSuperScsiInitiatorRequest_t  smSuperSCSIRequest;      
+  } SM;
+#endif 
+  union {
+    struct {
+      agsaSASRequestBody_t           agSASRequestBody;
+      //      agsaSASRequestBody_t           agSASResponseBody;
+      /* SSP response */
+      //      agsaSSPResponseInfoUnit_t      agSSPRspIU;
+    } SAS;
+    struct {
+      agsaSATAInitiatorRequest_t    agSATARequestBody;
+      scsiRspSense_t                sensePayload;
+      tiSenseData_t                 tiSenseData;
+      satIOContext_t                satIOContext;
+    } SATA;
+  } transport;  
+  bit32                          ioStarted;
+  bit32                          ioCompleted;
+  bit32                          reTries;
+  /**< for ESGL */
+  tdList_t                       EsglPageList;
+  bit32                          agRequestType;
+  union {
+    struct {
+      bit32                     expDataLength;
+      tiSgl_t                   tiSgl1;
+      tiSgl_t                   tiSgl2;
+      void                      *sglVirtualAddr;
+    } InitiatorRegIO;  /* regular IO */
+    struct {
+      void                      *osMemHandle;
+      tiIORequest_t             *CurrentTaskTag;
+      tiIORequest_t             *TaskTag;
+    } InitiatorTMIO;  /* task management */
+
+    struct {
+      tiIORequest_t   tiIORequest; /* for target */
+      
+      union {
+        struct {
+          tiSgl_t         tiSgl1;
+          void          * sglVirtualAddr;
+        } RegIO;
+        
+        struct {
+          tiSgl_t         tiSgl1;
+          void          * sglVirtualAddr;
+          tiSgl_t         tiSglMirror;
+          void          * sglMirrorVirtualAddr;
+          tdList_t        EsglMirrorPageList;
+        } MirrorIO;
+        
+      } TargetIOType;
+      
+    } TargetIO;    /* target regular IO */
+    
+    
+  } IOType;
+}  tdIORequestBody_t;
+
+/** \brief data structure for SAS SMP reuqest body
+ *  This structure contains IO related fields.
+ *  agsaIORequest->osData points to this
+ *  
+ */
+typedef struct tdssSMPRequestBody_s {
+  tdIORequestBody_t              IORequestBody;    /* for combo, must be the first */
+  tdssSMPCompleted_t             SMPCompletionFunc;/* must be the second */
+  
+  tiDeviceHandle_t               *tiDevHandle;    /* not used for TD generated SMP */
+  agsaIORequest_t                agIORequest;
+  agsaSASRequestBody_t           agSASRequestBody;
+  agsaSATAInitiatorRequest_t     agSATARequestBody; 
+  void                           *osMemHandle;
+  tdsaDeviceData_t               *tdDevice;
+  tiIORequest_t                  *CurrentTaskTag; /* SMP is used for simulate target reset */
+  tdsaPortContext_t              *tdPortContext; /* portcontext where SMP is sent from */
+  bit8                           smpPayload[SMP_DIRECT_PAYLOAD_LIMIT]; /* for smp retries; 
+                                                                          only for direct SMP */
+  bit32                          retries; /* number of retries */
+  bit32                          queueNumber; /* number of retries */
+  /* for indirect SMP req/rsp */
+  void                           *IndirectSMPReqosMemHandle;
+  void                           *IndirectSMPReq;
+  bit32                          IndirectSMPReqLen;
+  void                           *IndirectSMPResposMemHandle;
+  void                           *IndirectSMPResp;
+  bit32                          IndirectSMPRespLen;
+  
+}  tdssSMPRequestBody_t;
+
+#ifdef AGTIAPI_CTL
+typedef struct tdIORequest_s
+{
+  tiIORequest_t             tiIORequest;
+  tdIORequestBody_t         tdIORequestBody;
+  void                      *osMemHandle;
+
+  void                      *osMemHandle2;
+  bit32                     physUpper32;
+  bit32                     physLower32;
+  void                      *virtAddr;
+
+  tiIntrEventType_t         eventType;
+  bit32                     eventStatus;
+} tdIORequest_t;
+#endif
+
+#ifdef PASSTHROUGH
+/* this is allocated by OS layer but used in TD layer just like tdIORequestBody */
+typedef struct tdPassthroughCmndBody_s
+{
+  ostiPassthroughCmndEvent_t     EventCB;
+  tiPassthroughRequest_t         *tiPassthroughRequest;
+  tiDeviceHandle_t           *tiDevHandle;
+  bit32                          tiPassthroughCmndType; /* used in local abort */
+  union {
+    struct {
+#ifdef TO_DO      
+      tiSMPFunction_t            SMPFn;
+      tiSMPFunctionResult_t      SMPFnResult;  /* for SMP target only */
+      bit32                      IT; /* 0: initiator 1: target */
+      tiSMPFrameHeader_t         SMPHeader;
+#endif      
+      tdssSMPRequestBody_t       SMPBody;
+    } SMP;
+    struct {
+      tiDataDirection_t          dataDirection;
+    } RMC;
+  } protocol;
+} tdPassthroughCmndBody_t;
+
+#endif
+
+#endif                          /* __TDTYPES_H__ */

sys/dev/pms/RefTisa/tisa/sassata/sas/ini/itddefs.h

@@ -0,0 +1,48 @@
+/*******************************************************************************
+**
+*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved. 
+*
+*Redistribution and use in source and binary forms, with or without modification, are permitted provided 
+*that the following conditions are met: 
+*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
+*following disclaimer. 
+*2. Redistributions in binary form must reproduce the above copyright notice, 
+*this list of conditions and the following disclaimer in the documentation and/or other materials provided
+*with the distribution. 
+*
+*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+*
+* $FreeBSD$
+*
+********************************************************************************/
+/*******************************************************************************/
+/** \file
+ *
+ *
+ * #define for SAS intiator in SAS/SATA TD layer
+ *
+ */
+
+
+#ifndef __ITDDEFS_H__
+#define __ITDDEFS_H__
+/* discovery related state */
+#define ITD_DSTATE_NOT_STARTED                 0 
+#define ITD_DSTATE_STARTED                     1
+#define ITD_DSTATE_COMPLETED                   2
+
+/* SAS/SATA discovery status */
+#define DISCOVERY_NOT_START                       0                       /**< status indicates discovery not started */
+#define DISCOVERY_UP_STREAM                       1                       /**< status indicates discover upstream */
+#define DISCOVERY_DOWN_STREAM                     2                       /**< status indicates discover downstream */
+#define DISCOVERY_CONFIG_ROUTING                  3                       /**< status indicates discovery config routing table */
+#define DISCOVERY_SAS_DONE                        4                       /**< status indicates discovery done */
+#define DISCOVERY_REPORT_PHY_SATA                 5                       /**< status indicates discovery report phy sata */
+#endif /* __ITDDEFS_H__ */