Substantial rewrite of bxe(4) to add support for the BCM57712 and
BCM578XX controllers. Approved by: re MFC after: 4 weeks
This commit is contained in:
David Christensen
parent
bf0834df2d
commit
4e4007688c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=255736
@ -126,6 +126,7 @@ They have been applied to the following hardware drivers:
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.Xr bce 4 ,
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.Xr bfe 4 ,
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.Xr bge 4 ,
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.Xr bxe 4 ,
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.Xr cas 4 ,
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.Xr cxgbe 4 ,
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.Xr dc 4 ,
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@ -1,35 +1,41 @@
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.\" Copyright (c) 2012 Edward Tomasz Napierala <trasz@FreeBSD.org>
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.\" All rights reserved.
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.\" Copyright (c) 2013 Broadcom Corporation. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\"
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\" 3. Neither the name of Broadcom Corporation nor the name of its contributors
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.\" may be used to endorse or promote products derived from this software
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.\" without specific prior written consent.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
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.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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.\" THE POSSIBILITY OF SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd June 25, 2012
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.Dd April 29, 2012
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.Dt BXE 4
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.Os
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.Sh NAME
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.Nm bxe
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.Nd "Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet adapter driver"
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.Nd "Broadcom NetXtreme II Ethernet adapter driver for BCM57710 / BCM57711 /
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BCM57711E / BCM57712 / BCM57712-MF / BCM57800 / BCM57800-MF / BCM57810 /
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BCM57810-MF / BCM57840 / BCM57840-MF 10Gb PCIE Ethernet Network Controllers
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and Broadcom NetXtreme II BCM57840 10Gb/20Gb PCIE Ethernet Network Controllers.
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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@ -38,8 +44,8 @@ kernel configuration file:
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.Cd "device bxe"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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Alternatively, to load the driver as a module at boot time, place the
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following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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if_bxe_load="YES"
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@ -47,76 +53,240 @@ if_bxe_load="YES"
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.Sh DESCRIPTION
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The
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.Nm
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driver provides support for PCIe 10GbE Ethernet adapters based on
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BCM5771x chips.
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The driver supports Jumbo Frames, VLAN tagging, IP, UDP and TCP checksum
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offload, MSI-X, TCP Segmentation Offload (TSO), Large Receive Offload (LRO),
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and Receive Side Steering (RSS).
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.Pp
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For more information on configuring this device, see
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.Xr ifconfig 8 .
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driver provides support for PCIe 10Gb Ethernet adapters based on the Broadcom
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NetXtreme II family of 10Gb chips. The driver supports Jumbo Frames, VLAN
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tagging, checksum offload (IPv4, TCP, UDP, IPv6-TCP, IPv6-UDP), MSI-X
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interrupts, TCP Segmentation Offload (TSO), Large Receive Offload (LRO), and
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Receive Side Scaling (RSS).
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.Sh HARDWARE
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The
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.Nm
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driver provides support for various NICs based on the Broadcom BCM5771x
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family of 10GbE Ethernet controller chips, including the
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following:
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driver provides support for various NICs based on the Broadcom NetXtreme II
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family of 10Gb Ethernet controller chips, including the following:
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.Pp
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.Bl -bullet -compact
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.It
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Broadcom NetXtreme II BCM57710 10GbE
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Broadcom NetXtreme II BCM57710 10Gb
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.It
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Broadcom NetXtreme II BCM57711 10GbE
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Broadcom NetXtreme II BCM57711 10Gb
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.It
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Broadcom NetXtreme II BCM57711E 10GbE
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Broadcom NetXtreme II BCM57711E 10Gb
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.It
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Broadcom NetXtreme II BCM57712 10Gb
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.It
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Broadcom NetXtreme II BCM57712-MF 10Gb
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.It
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Broadcom NetXtreme II BCM57800 10Gb
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.It
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Broadcom NetXtreme II BCM57800-MF 10Gb
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.It
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Broadcom NetXtreme II BCM57810 10Gb
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.It
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Broadcom NetXtreme II BCM57810-MF 10Gb
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.It
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Broadcom NetXtreme II BCM57840 10Gb / 20Gb
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.It
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Broadcom NetXtreme II BCM57840-MF 10Gb
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.El
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.Sh SYSCTL VARIABLES
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The following variables are available as both
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.Xr sysctl 8
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variables and
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.Xr loader 8
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tunables:
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.Sh CONFIGURATION
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There a number of configuration parameters that can be set to tweak the
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driver's behavior. These parameters can be set via the
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.Xr loader.conf 5
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file to take affect during the next system boot. The following parameters affect
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ALL instances of the driver.
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.Bl -tag -width indent
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.It Va hw.bxe.dcc_enable
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Enable HP Flex-10 support.
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Allowed values are 0 to disable and 1 to enable.
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The default value is 0.
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.It Va hw.bxe.tso_enable
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Enable TCP Segmentation Offload.
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The default value is 1.
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.It Va hw.bxe.int_mode
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Set interrupt mode.
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Allowed values are 0 for IRQ, 1 for MSI/IRQ and 2 for MSI-X/MSI/IRQ.
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The default value is 2.
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.It Va hw.bxe.debug
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DEFAULT = 0
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.br
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Sets the default logging level of the driver. See the Diagnostics and Debugging
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section below for more details.
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.It Va hw.bxe.interrupt_mode
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DEFAULT = 2
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.br
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Sets the default interrupt mode: 0=IRQ, 1=MSI, 2=MSIX. If set to MSIX and
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allocation fails, the driver will roll back and attempt MSI allocation. If MSI
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allocation fails, the driver will roll back and attempt fixed level IRQ
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allocation. If IRQ allocation fails, then the driver load fails. With MSI/MSIX,
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the driver attempts to allocate a vector for each queue in addition to one more
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for default processing.
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.It Va hw.bxe.queue_count
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Specify the number of queues that will be used when a multi-queue
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RSS mode is selected using bxe_multi_mode.
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Allowed values are 0 for Auto or 1 to 16 for fixed number of queues.
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The default value is 0.
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.It Va hw.bxe.multi_mode
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Enable Receive Side Steering.
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Allowed values are 0, which disables all multi-queue/packet sorting
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algorithms, and 1, which assigns incoming frames to receive queues
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according to RSS.
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The default value is 0.
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.It Va hw.bxe.rx_ticks
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Control interrupt coalescing for received frames.
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The first frame always causes an interrupt, but subsequent frames
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are coalesced until the RX/TX ticks timer value expires and another
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interrupt occurs.
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The default value is 25.
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.It Va hw.bxe.tx_ticks
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Control interrupt coalescing for trasmitted frames.
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The first frame always causes an interrupt, but subsequent frames
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are coalesced until the RX/TX ticks timer value expires and another
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interrupt occurs.
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The default value is 50.
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DEFAULT = 4
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.br
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Sets the default number of fast path packet processing queues. Note that one
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MSI/MSIX interrupt vector is allocated per-queue.
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.It Va hw.bxe.max_rx_bufs
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DEFAULT = 0
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.br
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Sets the maximum number of receive buffers to allocate per-queue. Zero(0) means
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to allocate a receive buffer for every buffer descriptor. By default this
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equates to 4080 buffers per-queue which is the maximum value for this config
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parameter.
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.It Va hw.bxe.hc_rx_ticks
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DEFAULT = 25
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.br
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Sets the number of ticks for host interrupt coalescing in the receive path.
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.It Va hw.bxe.hc_tx_ticks
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DEFAULT = 50
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.br
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Sets the number of ticks for host interrupt coalescing in the transmit path.
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.It Va hw.bxe.rx_budget
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DEFAULT = 0xffffffff
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.br
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Sets the maximum number of receive packets to process in an interrupt. If the
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budget is reached then the remaining/pending packets will be processed in a
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scheduled taskqueue.
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.It Va hw.bxe.max_aggregation_size
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DEFAULT = 32768
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.br
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Sets the maximum LRO aggregration byte size. The higher the value the more
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packets the hardware will aggregate. Maximum is 65K.
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.It Va hw.bxe.mrrs
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Allows to set the PCIe maximum read request size.
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Allowed values are -1 for Auto, 0 for 128B, 1 for 256B, 2 for 512B,
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and 3 for 1kB.
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The default value is -1.
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DEFAULT = -1
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.br
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Sets the PCI MRRS: -1=Auto, 0=128B, 1=256B, 2=512B, 3=1KB
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.It Va hw.bxe.autogreeen
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DEFAULT = 0
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.br
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Set AutoGrEEEN: 0=HW_DEFAULT, 1=FORCE_ON, 2=FORCE_OFF
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.It Va hw.bxe.udp_rss
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DEFAULT = 0
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.br
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Enable/Disable 4-tuple RSS for UDP: 0=DISABLED, 1=ENABLED
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.El
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.Pp
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Special care must be taken when modifying the number of queues and receive
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buffers. FreeBSD imposes a limit on the maximum number of
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.Xr mbuf 9
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allocations. If buffer allocations fail, the interface initialization will fail
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and the interface will not be usable. The driver does not make a best effort
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for buffer allocations. It is an all or nothing effort.
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.Pp
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You can tweak the
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.Xr mbuf 9
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allocation limit using
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.Xr sysctl 8
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and view the current usage with
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.Xr netstat 1
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as follows:
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.Bd -literal -offset indent
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# netstat -m
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# sysctl kern.ipc.nmbclusters
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# sysctl kern.ipc.nmbclusters=<#>
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.Ed
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.Pp
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There are additional configuration parameters that can be set on a per-instance
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basis to dynamically override the default configuration. The '#' below must be
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replaced with the driver instance / interface unit number:
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.Bl -tag -width indent
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.It Va dev.bxe.#.debug
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DEFAULT = 0
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.br
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Sets the default logging level of the driver instance. See hw.bxe.debug above and
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the Diagnostics and Debugging section below for more details.
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.It Va dev.bxe.#.rx_budget
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DEFAULT = 0xffffffff
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.br
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Sets the maximum number of receive packets to process in an interrupt for the
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driver instance. See hw.bxe.rx_budget above for more details.
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.El
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.Pp
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Additional items can be configured using
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.Xr ifconfig 8 :
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.Bl -tag -width indent
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.It Va MTU - Maximum Transmission Unit
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DEFAULT = 1500
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.br
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RANGE = 46-9184
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.br
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# ifconfig bxe# mtu <n>
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.It Va Promiscuous Mode
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DEFAULT = OFF
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.br
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# ifconfig bxe# [ promisc | -promisc ]
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.It Va Rx/Tx Checksum Offload
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DEFAULT = RX/TX CSUM ON
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.br
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Note that the Rx and Tx settings are not independent.
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.br
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# ifconfig bxe# [ rxcsum | -rxcsum | txcsum | -txcsum ]
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.It Va TSO - TCP Segmentation Offload
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DEFAULT = ON
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.br
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# ifconfig bxe# [ tso | -tso | tso6 | -tso6 ]
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.It Va LRO - TCP Large Receive Offload
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DEFAULT = ON
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.br
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# ifconfig bxe# [ lro | -lro ]
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.El
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.Sh DIAGNOSTICS AND DEBUGGING
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There are many statistics exposed by
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.Nm
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via sysctl.
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.Pp
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To dump the default driver configuration:
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.Bd -literal -offset indent
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# sysctl -a | grep hw.bxe
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.Ed
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.Pp
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To dump every instance's configuration and detailed statistics:
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.Bd -literal -offset indent
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# sysctl -a | grep dev.bxe
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.Ed
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.Pp
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To dump information for a single instance (replace the '#' with the driver
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instance / interface unit number):
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.Bd -literal -offset indent
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# sysctl -a | grep dev.bxe.#
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.Ed
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.Pp
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To dump information for all the queues of a single instance:
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.Bd -literal -offset indent
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# sysctl -a | grep dev.bxe.#.queue
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.Ed
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.Pp
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To dump information for a single queue of a single instance (replace the
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additional '#' with the queue number):
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.Bd -literal -offset indent
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# sysctl -a | grep dev.bxe.#.queue.#
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.Ed
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.Pp
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The
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.Nm
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driver has the ability to dump a ton of debug messages to the system
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log. The default level of logging can be set with the 'hw.bxe.debug'
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configuration parameter. Take care with this setting as it can result in too
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many logs being dumped. Since this parameter is the default one, it affects
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every instance and will dramatically change the timing in the driver. A better
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alternative to aid in debugging is to dynamically change the debug level of a
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specific instance with the 'dev.bxe.#.debug' configuration parameter. This allows
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you to turn on/off logging of various debug groups on-the-fly.
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.Pp
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The different debug groups that can be toggled are:
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.Bd -literal -offset indent
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DBG_LOAD 0x00000001 /* load and unload */
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DBG_INTR 0x00000002 /* interrupt handling */
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DBG_SP 0x00000004 /* slowpath handling */
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DBG_STATS 0x00000008 /* stats updates */
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DBG_TX 0x00000010 /* packet transmit */
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DBG_RX 0x00000020 /* packet receive */
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DBG_PHY 0x00000040 /* phy/link handling */
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DBG_IOCTL 0x00000080 /* ioctl handling */
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DBG_MBUF 0x00000100 /* dumping mbuf info */
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DBG_REGS 0x00000200 /* register access */
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DBG_LRO 0x00000400 /* lro processing */
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DBG_ASSERT 0x80000000 /* debug assert */
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DBG_ALL 0xFFFFFFFF /* flying monkeys */
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.Ed
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.Pp
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For example, to debug an issue in the receive path on bxe0:
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.Bd -literal -offset indent
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# sysctl dev.bxe.0.debug=0x22
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.Ed
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.Pp
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When finished turn the logging back off:
|
||||
.Bd -literal -offset indent
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||||
# sysctl dev.bxe.0.debug=0
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.Ed
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.Sh SEE ALSO
|
||||
.Xr altq 4 ,
|
||||
.Xr arp 4 ,
|
||||
@ -124,6 +294,7 @@ The default value is -1.
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.Xr ng_ether 4 ,
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.Xr vlan 4 ,
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.Xr ifconfig 8
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||||
.Xr netstat 1
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.Sh HISTORY
|
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The
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.Nm
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@ -133,6 +304,7 @@ device driver first appeared in
|
||||
The
|
||||
.Nm
|
||||
driver was written by
|
||||
.An Gary Zambrano Aq zambrano@broadcom.com
|
||||
.An Eric Davis Aq edavis@broadcom.com ,
|
||||
.An David Christensen Aq davidch@broadcom.com ,
|
||||
and
|
||||
.An David Christensen Aq davidch@broadcom.com .
|
||||
.An Gary Zambrano Aq zambrano@broadcom.com .
|
||||
|
||||
@ -127,6 +127,7 @@ in hardware:
|
||||
.Xr ale 4 ,
|
||||
.Xr bce 4 ,
|
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.Xr bge 4 ,
|
||||
.Xr bxe 4 ,
|
||||
.Xr cxgb 4 ,
|
||||
.Xr cxgbe 4 ,
|
||||
.Xr em 4 ,
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||||
|
||||
@ -204,7 +204,7 @@ device ppi # Parallel port interface device
|
||||
device puc # Multi I/O cards and multi-channel UARTs
|
||||
|
||||
# PCI Ethernet NICs.
|
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device bxe # Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
|
||||
device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
|
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device de # DEC/Intel DC21x4x (``Tulip'')
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device em # Intel PRO/1000 Gigabit Ethernet Family
|
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device igb # Intel PRO/1000 PCIE Server Gigabit Family
|
||||
@ -341,8 +341,5 @@ device virtio_blk # VirtIO Block device
|
||||
device virtio_scsi # VirtIO SCSI device
|
||||
device virtio_balloon # VirtIO Memory Balloon device
|
||||
|
||||
# HyperV drivers
|
||||
device hyperv # HyperV drivers
|
||||
|
||||
# VMware support
|
||||
device vmx # VMware VMXNET3 Ethernet
|
||||
|
||||
@ -294,6 +294,8 @@ options DRM_DEBUG # Include debug printfs (slow)
|
||||
# Network interfaces:
|
||||
#
|
||||
|
||||
# bxe: Broadcom NetXtreme II (BCM5771X/BCM578XX) PCIe 10Gb Ethernet
|
||||
# adapters.
|
||||
# ed: Western Digital and SMC 80xx; Novell NE1000 and NE2000; 3Com 3C503
|
||||
# HP PC Lan+, various PC Card devices
|
||||
# (requires miibus)
|
||||
@ -313,6 +315,7 @@ options DRM_DEBUG # Include debug printfs (slow)
|
||||
# wpi: Intel 3945ABG Wireless LAN controller
|
||||
# Requires the wpi firmware module
|
||||
|
||||
device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
|
||||
device ed # NE[12]000, SMC Ultra, 3c503, DS8390 cards
|
||||
options ED_3C503
|
||||
options ED_HPP
|
||||
|
||||
@ -1895,7 +1895,7 @@ device xmphy # XaQti XMAC II
|
||||
# BCM570x family of controllers, including the 3Com 3c996-T,
|
||||
# the Netgear GA302T, the SysKonnect SK-9D21 and SK-9D41, and
|
||||
# the embedded gigE NICs on Dell PowerEdge 2550 servers.
|
||||
# bxe: Broadcom NetXtreme II (BCM57710/57711/57711E) PCIe 10b Ethernet
|
||||
# bxe: Broadcom NetXtreme II (BCM5771X/BCM578XX) PCIe 10Gb Ethernet
|
||||
# adapters.
|
||||
# bwi: Broadcom BCM430* and BCM431* family of wireless adapters.
|
||||
# bwn: Broadcom BCM43xx family of wireless adapters.
|
||||
@ -2080,7 +2080,6 @@ device wb # Winbond W89C840F
|
||||
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
|
||||
|
||||
# PCI Ethernet NICs.
|
||||
device bxe # Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
|
||||
device cxgbe # Chelsio T4 10GbE PCIe adapter
|
||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||
device em # Intel Pro/1000 Gigabit Ethernet
|
||||
|
||||
@ -1116,8 +1116,6 @@ dev/bwi/if_bwi_pci.c optional bwi pci
|
||||
# XXX Work around clang warning, until maintainer approves fix.
|
||||
dev/bwn/if_bwn.c optional bwn siba_bwn \
|
||||
compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}"
|
||||
dev/bxe/if_bxe.c optional bxe
|
||||
dev/bxe/bxe_link.c optional bxe
|
||||
dev/cardbus/cardbus.c optional cardbus
|
||||
dev/cardbus/cardbus_cis.c optional cardbus
|
||||
dev/cardbus/cardbus_device.c optional cardbus
|
||||
|
||||
@ -166,6 +166,14 @@ dev/atkbdc/atkbdc.c optional atkbdc
|
||||
dev/atkbdc/atkbdc_isa.c optional atkbdc isa
|
||||
dev/atkbdc/atkbdc_subr.c optional atkbdc
|
||||
dev/atkbdc/psm.c optional psm atkbdc
|
||||
dev/bxe/bxe.c optional bxe pci
|
||||
dev/bxe/bxe_stats.c optional bxe pci
|
||||
dev/bxe/bxe_debug.c optional bxe pci
|
||||
dev/bxe/ecore_sp.c optional bxe pci
|
||||
dev/bxe/bxe_elink.c optional bxe pci
|
||||
dev/bxe/57710_init_values.c optional bxe pci
|
||||
dev/bxe/57711_init_values.c optional bxe pci
|
||||
dev/bxe/57712_init_values.c optional bxe pci
|
||||
dev/coretemp/coretemp.c optional coretemp
|
||||
dev/cpuctl/cpuctl.c optional cpuctl
|
||||
dev/dpms/dpms.c optional dpms
|
||||
|
||||
@ -156,6 +156,14 @@ dev/atkbdc/atkbdc.c optional atkbdc
|
||||
dev/atkbdc/atkbdc_isa.c optional atkbdc isa
|
||||
dev/atkbdc/atkbdc_subr.c optional atkbdc
|
||||
dev/atkbdc/psm.c optional psm atkbdc
|
||||
dev/bxe/bxe.c optional bxe pci
|
||||
dev/bxe/bxe_stats.c optional bxe pci
|
||||
dev/bxe/bxe_debug.c optional bxe pci
|
||||
dev/bxe/ecore_sp.c optional bxe pci
|
||||
dev/bxe/bxe_elink.c optional bxe pci
|
||||
dev/bxe/57710_init_values.c optional bxe pci
|
||||
dev/bxe/57711_init_values.c optional bxe pci
|
||||
dev/bxe/57712_init_values.c optional bxe pci
|
||||
dev/ce/ceddk.c optional ce
|
||||
dev/ce/if_ce.c optional ce
|
||||
dev/ce/tau32-ddk.c optional ce \
|
||||
|
||||
@ -711,10 +711,6 @@ ED_SIC opt_ed.h
|
||||
BCE_DEBUG opt_bce.h
|
||||
BCE_NVRAM_WRITE_SUPPORT opt_bce.h
|
||||
|
||||
# bxe driver
|
||||
BXE_DEBUG opt_bxe.h
|
||||
BXE_NVRAM_WRITE_SUPPORT opt_bxe.h
|
||||
|
||||
SOCKBUF_DEBUG opt_global.h
|
||||
|
||||
|
||||
|
||||
29161
sys/dev/bxe/57710_init_values.c
Normal file
29161
sys/dev/bxe/57710_init_values.c
Normal file
File diff suppressed because it is too large
Load Diff
418
sys/dev/bxe/57710_int_offsets.h
Normal file
418
sys/dev/bxe/57710_int_offsets.h
Normal file
@ -0,0 +1,418 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
|
||||
static const struct iro e1_iro_arr[379] = {
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
|
||||
{ 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
|
||||
{ 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVENT_ID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_MASK
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_MASK
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_MASK
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_AGG_INT
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_EVENTID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_PCI_READ_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_INCVAL
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_REGION
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_CID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_RUN_PBF_ECHO_TEST
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_QM_PAUSE_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_SUCCESS_OPCODE_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_OPCODE_VALUE
|
||||
{ 0x3320, 0x10, 0x0, 0x0, 0x8}, // XSTORM_SPQ_PAGE_BASE_OFFSET(funcId)
|
||||
{ 0x3328, 0x10, 0x0, 0x0, 0x2}, // XSTORM_SPQ_PROD_OFFSET(funcId)
|
||||
{ 0x3320, 0x10, 0x0, 0x0, 0x10}, // XSTORM_SPQ_DATA_OFFSET(funcId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId)
|
||||
{ 0x3358, 0x1, 0x4, 0x0, 0x1}, // XSTORM_JUMBO_SUPPORT_OFFSET(pfId)
|
||||
{ 0x3360, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_IP_ID_MASK_OFFSET
|
||||
{ 0x3368, 0x0, 0x0, 0x0, 0x8}, // XSTORM_COMMON_RTC_PARAMS_OFFSET
|
||||
{ 0x336c, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_RTC_RESOLUTION_OFFSET
|
||||
{ 0x3920, 0x0, 0x0, 0x0, 0x8}, // XSTORM_FW_VERSION_OFFSET
|
||||
{ 0x3af8, 0x40, 0x0, 0x0, 0x40}, // XSTORM_LICENSE_VALUES_OFFSET(pfId)
|
||||
{ 0x3938, 0x80, 0x0, 0x0, 0x48}, // XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId)
|
||||
{ 0x3a38, 0x40, 0x0, 0x0, 0x8}, // XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId)
|
||||
{ 0x3a48, 0x40, 0x0, 0x0, 0x18}, // XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId)
|
||||
{ 0x3370, 0x28, 0x0, 0x0, 0x28}, // XSTORM_PER_QUEUE_STATS_OFFSET(xStatQueueId)
|
||||
{ 0x3c20, 0x8, 0x0, 0x0, 0x1}, // XSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x3c21, 0x8, 0x0, 0x0, 0x1}, // XSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x3c22, 0x8, 0x0, 0x0, 0x1}, // XSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // XSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // XSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PCI_READ_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // LOAD_CONTEXT_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // QM_PAUSE_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TEST_UNUSED_FOCS_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PBF_ECHO_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // IGU_TEST_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_INITIAL_CLEANUP_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_OPPORTUNISTIC_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_SIDE_INFO_INPUT_LSB_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_VLAN_ID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_VLAN_ID_EN_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_LINE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_OP_GEN_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DPM_BUFFER_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_QUEUE_MASK_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_GROUP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_PORT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_INCVAL
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_REGION
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_RUN_PBF_ECHO_TEST
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_CID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_SUCCESS_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TIME_SYNC_FLG_OFFSET(funcId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INDIRECTION_TABLE_ENTRY_SIZE
|
||||
{ 0x19c8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_COMMON_RTC_PARAMS_OFFSET
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // TSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // TSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x4870, 0x8, 0x0, 0x0, 0x1}, // TSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x4871, 0x8, 0x0, 0x0, 0x1}, // TSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x4872, 0x8, 0x0, 0x0, 0x1}, // TSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x4040, 0x38, 0x0, 0x0, 0x38}, // TSTORM_PER_QUEUE_STATS_OFFSET(tStatQueueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RSS_KEY_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_E2_INTEG_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_LSB_SIDE_BAND_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MSB_SIDE_BAND_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_LINE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_OP_GEN_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET
|
||||
{ 0x4000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_OFFSET(sbId)
|
||||
{ 0x4800, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId)
|
||||
{ 0x482e, 0x40, 0x0, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId)
|
||||
{ 0x4800, 0x40, 0x2, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId,hcIndex)
|
||||
{ 0x4801, 0x40, 0x2, 0x0, 0x0}, // CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId,hcIndex)
|
||||
{ 0x3000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_SYNC_BLOCK_OFFSET(sbId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex,sbId)
|
||||
{ 0x3000, 0x8, 0x40, 0x0, 0x4}, // CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex,sbId)
|
||||
{ 0x3004, 0x8, 0x40, 0x0, 0x4}, // CSTORM_HC_SYNC_LINE_DHC_OFFSET(sbSyncLines,sbId)
|
||||
{ 0x3b80, 0x28, 0x0, 0x0, 0x28}, // CSTORM_SP_STATUS_BLOCK_OFFSET(pfId)
|
||||
{ 0x3bd0, 0x10, 0x0, 0x0, 0x10}, // CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId)
|
||||
{ 0x3bda, 0x10, 0x0, 0x0, 0x1}, // CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId)
|
||||
{ 0x3800, 0x80, 0x0, 0x0, 0x80}, // CSTORM_SP_SYNC_BLOCK_OFFSET(pfId)
|
||||
{ 0x3800, 0x8, 0x80, 0x0, 0x2}, // CSTORM_SP_HC_SYNC_LINE_INDEX_OFFSET(hcSpIndex,pfId)
|
||||
{ 0x3900, 0x40, 0x0, 0x0, 0x40}, // CSTORM_DYNAMIC_HC_CONFIG_OFFSET(pfId)
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // CSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // CSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x5198, 0x8, 0x0, 0x0, 0x1}, // CSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x5199, 0x8, 0x0, 0x0, 0x1}, // CSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x519a, 0x8, 0x0, 0x0, 0x1}, // CSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x3980, 0x10, 0x4, 0x0, 0x4}, // CSTORM_BYTE_COUNTER_OFFSET(sbId,dhcIndex)
|
||||
{ 0x51a8, 0x30, 0x18, 0x0, 0x10}, // CSTORM_EVENT_RING_DATA_OFFSET(pfId)
|
||||
{ 0x51b0, 0x30, 0x18, 0x0, 0x2}, // CSTORM_EVENT_RING_PROD_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_MODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_PF_ID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_VF_ID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_VF_VALID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_IGU_COMMAND_OFFSET
|
||||
{ 0x23e8, 0x80, 0x0, 0x0, 0x80}, // USTORM_INDIRECTION_TABLE_OFFSET(portId)
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // USTORM_INDIRECTION_TABLE_ENTRY_SIZE
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // USTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // USTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x2e70, 0x8, 0x0, 0x0, 0x1}, // USTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x2e71, 0x8, 0x0, 0x0, 0x1}, // USTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x2e72, 0x8, 0x0, 0x0, 0x1}, // USTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x24e8, 0x38, 0x0, 0x0, 0x38}, // USTORM_PER_QUEUE_STATS_OFFSET(uStatQueueId)
|
||||
{ 0x2dd0, 0x8, 0x0, 0x0, 0x8}, // USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_ETH_PAUSE_ENABLED_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_PAUSE_ENABLED_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_MAX_PAUSE_TIME_USEC_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET
|
||||
{ 0x2500, 0x40, 0x0, 0x0, 0x8}, // TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId)
|
||||
{ 0x2508, 0x40, 0x0, 0x0, 0x20}, // TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CQE_PAGE_NEXT_OFFSET(portId,clientId)
|
||||
{ 0x3000, 0x0, 0x0, 0x0, 0x1000}, // USTORM_AGG_DATA_OFFSET
|
||||
{ 0x50a1, 0x0, 0x0, 0x0, 0x1}, // USTORM_TPA_BTR_OFFSET
|
||||
{ 0x50b8, 0x0, 0x0, 0x0, 0x2}, // USTORM_ETH_DYNAMIC_HC_PARAM_OFFSET
|
||||
{ 0x50c8, 0x90, 0x8, 0x0, 0x8}, // USTORM_RX_PRODS_E1X_OFFSET(portId,clientId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_RX_PRODS_E2_OFFSET(qzoneId)
|
||||
{ 0x2960, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId)
|
||||
{ 0x2961, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId)
|
||||
{ 0x2970, 0x8, 0x4, 0x0, 0x2}, // XSTORM_TCP_IPID_OFFSET(pfId)
|
||||
{ 0x2978, 0x8, 0x4, 0x0, 0x4}, // XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TCP_TX_SWITCHING_EN_OFFSET(portId)
|
||||
{ 0x2fb0, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_DUPLICATE_ACK_THRESHOLD_OFFSET(pfId)
|
||||
{ 0x2fb4, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_MAX_CWND_OFFSET(pfId)
|
||||
{ 0x2fc0, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_GLOBAL_PARAMS_OFFSET
|
||||
{ 0x2fc8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_ISLES_ARRAY_DESCRIPTOR_OFFSET
|
||||
{ 0x3000, 0x0, 0x0, 0x0, 0x10}, // TSTORM_TCP_ISLES_ARRAY_OFFSET
|
||||
{ 0x5040, 0x1, 0x1, 0x0, 0x1}, // XSTORM_TOE_LLC_SNAP_ENABLED_OFFSET(pfId)
|
||||
{ 0x5000, 0x0, 0x0, 0x0, 0x20}, // XSTORM_OUT_OCTETS_OFFSET
|
||||
{ 0x808, 0x10, 0x0, 0x0, 0x4}, // TSTORM_TOE_MAX_SEG_RETRANSMIT_OFFSET(pfId)
|
||||
{ 0x80c, 0x10, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOUBT_REACHABILITY_OFFSET(pfId)
|
||||
{ 0x8b7, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_MAX_DOMINANCE_VALUE_OFFSET
|
||||
{ 0x8b6, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOMINANCE_THRESHOLD_OFFSET
|
||||
{ 0x1000, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0x1004, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0x1008, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0x100a, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0x100c, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId)
|
||||
{ 0x100d, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId)
|
||||
{ 0x100e, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId)
|
||||
{ 0x1010, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId)
|
||||
{ 0x1014, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId)
|
||||
{ 0x1018, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_PROD_OFFSET(rssId,portId)
|
||||
{ 0x101c, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_CONS_OFFSET(rssId,portId)
|
||||
{ 0x3000, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_LO_OFFSET(rssId,portId,grqBdId)
|
||||
{ 0x3004, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_HI_OFFSET(rssId,portId,grqBdId)
|
||||
{ 0xa, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_CACHE_NUM_BDS
|
||||
{ 0x3068, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_PROD_OFFSET(rssId,portId)
|
||||
{ 0x3069, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_CONS_OFFSET(rssId,portId)
|
||||
{ 0x306c, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0x306e, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0x3070, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0x3074, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0x3066, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_BUF_SIZE_OFFSET(rssId,portId)
|
||||
{ 0x3064, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId)
|
||||
{ 0x3060, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0x3062, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0x3050, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId)
|
||||
{ 0x3054, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId)
|
||||
{ 0x3058, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0x305c, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0x307c, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId)
|
||||
{ 0x307d, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId)
|
||||
{ 0x1c18, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_TCP_PUSH_TIMER_TICKS_OFFSET(pfId)
|
||||
{ 0x1c30, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_GRQ_XOFF_COUNTER_OFFSET(pfId)
|
||||
{ 0x1c38, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_RCQ_XOFF_COUNTER_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_CQ_THR_LOW_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_THR_LOW_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_CQ_THR_HIGH_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_THR_HIGH_OFFSET
|
||||
{ 0x4c10, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId)
|
||||
{ 0x4c12, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x4c14, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x4c16, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x4c20, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId)
|
||||
{ 0x4c00, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x4c02, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x4c04, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x4c30, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId)
|
||||
{ 0x4c40, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId)
|
||||
{ 0x4c44, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId)
|
||||
{ 0x4c50, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId)
|
||||
{ 0x4c54, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_RX_BDS_THRSHLD_OFFSET(pfId)
|
||||
{ 0x4c52, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_CONS_OFFSET(pfId)
|
||||
{ 0x4c60, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId)
|
||||
{ 0x1400, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x1402, 0x8, 0x0, 0x0, 0x1}, // USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x1404, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x1410, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId)
|
||||
{ 0x1414, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SIZE_OFFSET(pfId)
|
||||
{ 0x1416, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId)
|
||||
{ 0x19b8, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId)
|
||||
{ 0x1420, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId)
|
||||
{ 0x1424, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_SIZE_OFFSET(pfId)
|
||||
{ 0x19c8, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId)
|
||||
{ 0x2c10, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId)
|
||||
{ 0x2c11, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId)
|
||||
{ 0x2c12, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId)
|
||||
{ 0x2c13, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId)
|
||||
{ 0x2c00, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x2c02, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x2c04, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x2c30, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId)
|
||||
{ 0x2c32, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId)
|
||||
{ 0x2c34, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId)
|
||||
{ 0x2c20, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId)
|
||||
{ 0x2c21, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId)
|
||||
{ 0x2c22, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId)
|
||||
{ 0x2c23, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId)
|
||||
{ 0x2c24, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId)
|
||||
{ 0x2c25, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId)
|
||||
{ 0x2c26, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId)
|
||||
{ 0x1480, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x1482, 0x8, 0x0, 0x0, 0x1}, // CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x1484, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x1492, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_PROD_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x1490, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_CONS_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x149c, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x1494, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x14a7, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x14a4, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x14a6, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x1610, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId)
|
||||
{ 0x1620, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId)
|
||||
{ 0x1630, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_EQ_PROD_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_TIMER_PARAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TIMER_ARRAY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FC_CRC_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_EOFA_DEL_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_MISS_FRAME_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_SEQ_TIMEOUT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_DROP_SEQ_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FCP_RX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_DROP_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_ONE_OFFSET(cached_tbl_size)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_TWO_OFFSET(cached_tbl_size)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_ENTRY_TCE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_ENTRY_MNG_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_CACHED_TCE_TBL_BIT_MAP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAIT_4_BD_READ_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_DATA_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_NON_DATA_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_ERR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_GLOBAL_TIMER_TASK_IN_USE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_DEL_CACHED_TASK_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_SILENT_DROP_CACHED_TASK_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_DROP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_CRC_ERROR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_ERROR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_PREVIOUS_THREAD_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DATA_IN_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_READ_TCE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DROP_ERR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_ERRORS_NUMBER_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_NUMBER_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_BITMAP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_ENABLE_CONN_RACE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_TASK_IN_USE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_CRC_ERROR_TASK_IN_USE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FCOE_TIMER_PARAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIMER_ARRAY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCOE_TX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCOE_TX_BYTE_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCP_TX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_ABTS_BLOCK_SQ_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_CLEANUP_BLOCK_SQ_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_VER_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_BYTE_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_WAIT_FOR_YOUR_TURN_SP_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_AFEX_ERROR_PACKETS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_DATA_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_WAITING_TABLE_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_WAITING_LIST_SIZE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_WAITING_ENTRY_OFFSET
|
||||
};
|
||||
30457
sys/dev/bxe/57711_init_values.c
Normal file
30457
sys/dev/bxe/57711_init_values.c
Normal file
File diff suppressed because it is too large
Load Diff
418
sys/dev/bxe/57711_int_offsets.h
Normal file
418
sys/dev/bxe/57711_int_offsets.h
Normal file
@ -0,0 +1,418 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
|
||||
static const struct iro e1h_iro_arr[379] = {
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
|
||||
{ 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
|
||||
{ 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVENT_ID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_MASK
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_MASK
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_MASK
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_AGG_INT
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_EVENTID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_PCI_READ_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_INCVAL
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_REGION
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_CID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_RUN_PBF_ECHO_TEST
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_QM_PAUSE_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_SUCCESS_OPCODE_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_OPCODE_VALUE
|
||||
{ 0x9000, 0x10, 0x0, 0x0, 0x8}, // XSTORM_SPQ_PAGE_BASE_OFFSET(funcId)
|
||||
{ 0x9008, 0x10, 0x0, 0x0, 0x2}, // XSTORM_SPQ_PROD_OFFSET(funcId)
|
||||
{ 0x9000, 0x10, 0x0, 0x0, 0x10}, // XSTORM_SPQ_DATA_OFFSET(funcId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId)
|
||||
{ 0x93b8, 0x1, 0x4, 0x0, 0x1}, // XSTORM_JUMBO_SUPPORT_OFFSET(pfId)
|
||||
{ 0x93c0, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_IP_ID_MASK_OFFSET
|
||||
{ 0x93c8, 0x0, 0x0, 0x0, 0x8}, // XSTORM_COMMON_RTC_PARAMS_OFFSET
|
||||
{ 0x93cc, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_RTC_RESOLUTION_OFFSET
|
||||
{ 0x93d0, 0x0, 0x0, 0x0, 0x8}, // XSTORM_FW_VERSION_OFFSET
|
||||
{ 0x9720, 0x40, 0x0, 0x0, 0x40}, // XSTORM_LICENSE_VALUES_OFFSET(pfId)
|
||||
{ 0x93e0, 0x80, 0x0, 0x0, 0x48}, // XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId)
|
||||
{ 0x94e0, 0x40, 0x0, 0x0, 0x8}, // XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId)
|
||||
{ 0x94f0, 0x40, 0x0, 0x0, 0x18}, // XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId)
|
||||
{ 0xa000, 0x28, 0x0, 0x0, 0x28}, // XSTORM_PER_QUEUE_STATS_OFFSET(xStatQueueId)
|
||||
{ 0xc0c0, 0x8, 0x0, 0x0, 0x1}, // XSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0xc0c1, 0x8, 0x0, 0x0, 0x1}, // XSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0xc0c2, 0x8, 0x0, 0x0, 0x1}, // XSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // XSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // XSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PCI_READ_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // LOAD_CONTEXT_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // QM_PAUSE_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TEST_UNUSED_FOCS_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // PBF_ECHO_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // IGU_TEST_KUKUE_CODE_OPPCOE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_INITIAL_CLEANUP_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_OPPORTUNISTIC_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_SIDE_INFO_INPUT_LSB_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_VLAN_ID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_VLAN_ID_EN_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_LINE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_OP_GEN_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DPM_BUFFER_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_QUEUE_MASK_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_GROUP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QM_PAUSE_TEST_PORT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_OPCODE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_INCVAL
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_REGION
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_RUN_PBF_ECHO_TEST
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_CID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_SUCCESS_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TIME_SYNC_FLG_OFFSET(funcId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INDIRECTION_TABLE_ENTRY_SIZE
|
||||
{ 0x1ec8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_COMMON_RTC_PARAMS_OFFSET
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // TSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // TSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0xa080, 0x8, 0x0, 0x0, 0x1}, // TSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0xa081, 0x8, 0x0, 0x0, 0x1}, // TSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0xa082, 0x8, 0x0, 0x0, 0x1}, // TSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x9070, 0x38, 0x0, 0x0, 0x38}, // TSTORM_PER_QUEUE_STATS_OFFSET(tStatQueueId)
|
||||
{ 0x1ed8, 0x0, 0x0, 0x0, 0x2}, // TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET
|
||||
{ 0x1eda, 0x0, 0x0, 0x0, 0x2}, // TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RSS_KEY_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_E2_INTEG_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_LSB_SIDE_BAND_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MSB_SIDE_BAND_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_LINE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_OP_GEN_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET
|
||||
{ 0xc000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_OFFSET(sbId)
|
||||
{ 0xc800, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId)
|
||||
{ 0xc82e, 0x40, 0x0, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId)
|
||||
{ 0xc800, 0x40, 0x2, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId,hcIndex)
|
||||
{ 0xc801, 0x40, 0x2, 0x0, 0x0}, // CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId,hcIndex)
|
||||
{ 0x8000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_SYNC_BLOCK_OFFSET(sbId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex,sbId)
|
||||
{ 0x8000, 0x8, 0x40, 0x0, 0x4}, // CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex,sbId)
|
||||
{ 0x8004, 0x8, 0x40, 0x0, 0x4}, // CSTORM_HC_SYNC_LINE_DHC_OFFSET(sbSyncLines,sbId)
|
||||
{ 0xb000, 0x28, 0x0, 0x0, 0x28}, // CSTORM_SP_STATUS_BLOCK_OFFSET(pfId)
|
||||
{ 0xb140, 0x10, 0x0, 0x0, 0x10}, // CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId)
|
||||
{ 0xb14a, 0x10, 0x0, 0x0, 0x1}, // CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId)
|
||||
{ 0x8800, 0x80, 0x0, 0x0, 0x80}, // CSTORM_SP_SYNC_BLOCK_OFFSET(pfId)
|
||||
{ 0x8800, 0x8, 0x80, 0x0, 0x2}, // CSTORM_SP_HC_SYNC_LINE_INDEX_OFFSET(hcSpIndex,pfId)
|
||||
{ 0x8c00, 0x40, 0x0, 0x0, 0x40}, // CSTORM_DYNAMIC_HC_CONFIG_OFFSET(pfId)
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // CSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // CSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x1250, 0x8, 0x0, 0x0, 0x1}, // CSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x1251, 0x8, 0x0, 0x0, 0x1}, // CSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x1252, 0x8, 0x0, 0x0, 0x1}, // CSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x8e00, 0x10, 0x4, 0x0, 0x4}, // CSTORM_BYTE_COUNTER_OFFSET(sbId,dhcIndex)
|
||||
{ 0x1290, 0x30, 0x18, 0x0, 0x10}, // CSTORM_EVENT_RING_DATA_OFFSET(pfId)
|
||||
{ 0x1298, 0x30, 0x18, 0x0, 0x2}, // CSTORM_EVENT_RING_PROD_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_MODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_PF_ID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_VF_ID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_VF_VALID_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_IGU_TEST_IGU_COMMAND_OFFSET
|
||||
{ 0x8308, 0x80, 0x0, 0x0, 0x80}, // USTORM_INDIRECTION_TABLE_OFFSET(portId)
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // USTORM_INDIRECTION_TABLE_ENTRY_SIZE
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // USTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // USTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x8500, 0x8, 0x0, 0x0, 0x1}, // USTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x8501, 0x8, 0x0, 0x0, 0x1}, // USTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x8502, 0x8, 0x0, 0x0, 0x1}, // USTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x6000, 0x38, 0x0, 0x0, 0x38}, // USTORM_PER_QUEUE_STATS_OFFSET(uStatQueueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId)
|
||||
{ 0x8454, 0x8, 0x0, 0x0, 0x2}, // USTORM_ETH_PAUSE_ENABLED_OFFSET(portId)
|
||||
{ 0x8456, 0x8, 0x0, 0x0, 0x2}, // USTORM_TOE_PAUSE_ENABLED_OFFSET(portId)
|
||||
{ 0x8464, 0x10, 0x0, 0x0, 0x4}, // USTORM_MAX_PAUSE_TIME_USEC_OFFSET(portId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_OP_GEN_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET
|
||||
{ 0x3000, 0x40, 0x0, 0x0, 0x8}, // TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId)
|
||||
{ 0x3008, 0x40, 0x0, 0x0, 0x20}, // TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId)
|
||||
{ 0x3200, 0x20, 0x0, 0x0, 0x20}, // TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId)
|
||||
{ 0x37a8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CQE_PAGE_NEXT_OFFSET(portId,clientId)
|
||||
{ 0xa000, 0x0, 0x0, 0x0, 0x2000}, // USTORM_AGG_DATA_OFFSET
|
||||
{ 0x3ec1, 0x0, 0x0, 0x0, 0x1}, // USTORM_TPA_BTR_OFFSET
|
||||
{ 0x3ee0, 0x0, 0x0, 0x0, 0x2}, // USTORM_ETH_DYNAMIC_HC_PARAM_OFFSET
|
||||
{ 0x1e00, 0xe0, 0x8, 0x0, 0x8}, // USTORM_RX_PRODS_E1X_OFFSET(portId,clientId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_RX_PRODS_E2_OFFSET(qzoneId)
|
||||
{ 0x4000, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId)
|
||||
{ 0x4001, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId)
|
||||
{ 0x4040, 0x8, 0x4, 0x0, 0x2}, // XSTORM_TCP_IPID_OFFSET(pfId)
|
||||
{ 0x4060, 0x8, 0x4, 0x0, 0x4}, // XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TCP_TX_SWITCHING_EN_OFFSET(portId)
|
||||
{ 0x4000, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_DUPLICATE_ACK_THRESHOLD_OFFSET(pfId)
|
||||
{ 0x4004, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_MAX_CWND_OFFSET(pfId)
|
||||
{ 0x4040, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_GLOBAL_PARAMS_OFFSET
|
||||
{ 0x4048, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_ISLES_ARRAY_DESCRIPTOR_OFFSET
|
||||
{ 0x8000, 0x0, 0x0, 0x0, 0x10}, // TSTORM_TCP_ISLES_ARRAY_OFFSET
|
||||
{ 0x5040, 0x1, 0x4, 0x0, 0x1}, // XSTORM_TOE_LLC_SNAP_ENABLED_OFFSET(pfId)
|
||||
{ 0x5000, 0x0, 0x0, 0x0, 0x20}, // XSTORM_OUT_OCTETS_OFFSET
|
||||
{ 0x5008, 0x10, 0x0, 0x0, 0x4}, // TSTORM_TOE_MAX_SEG_RETRANSMIT_OFFSET(pfId)
|
||||
{ 0x500c, 0x10, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOUBT_REACHABILITY_OFFSET(pfId)
|
||||
{ 0x52c7, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_MAX_DOMINANCE_VALUE_OFFSET
|
||||
{ 0x52c6, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOMINANCE_THRESHOLD_OFFSET
|
||||
{ 0x3000, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0x3004, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0x3008, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0x300a, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0x300c, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId)
|
||||
{ 0x300d, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId)
|
||||
{ 0x300e, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId)
|
||||
{ 0x3010, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId)
|
||||
{ 0x3014, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId)
|
||||
{ 0x3018, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_PROD_OFFSET(rssId,portId)
|
||||
{ 0x301c, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_CONS_OFFSET(rssId,portId)
|
||||
{ 0x5000, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_LO_OFFSET(rssId,portId,grqBdId)
|
||||
{ 0x5004, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_HI_OFFSET(rssId,portId,grqBdId)
|
||||
{ 0xa, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_CACHE_NUM_BDS
|
||||
{ 0x5068, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_PROD_OFFSET(rssId,portId)
|
||||
{ 0x5069, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_CONS_OFFSET(rssId,portId)
|
||||
{ 0x506c, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0x506e, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0x5070, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0x5074, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0x5066, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_BUF_SIZE_OFFSET(rssId,portId)
|
||||
{ 0x5064, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId)
|
||||
{ 0x5060, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0x5062, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0x5050, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId)
|
||||
{ 0x5054, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId)
|
||||
{ 0x5058, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0x505c, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0x507c, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId)
|
||||
{ 0x507d, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId)
|
||||
{ 0x4018, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_TCP_PUSH_TIMER_TICKS_OFFSET(pfId)
|
||||
{ 0x4090, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_GRQ_XOFF_COUNTER_OFFSET(pfId)
|
||||
{ 0x4098, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_RCQ_XOFF_COUNTER_OFFSET(pfId)
|
||||
{ 0x4110, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_CQ_THR_LOW_OFFSET
|
||||
{ 0x4112, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_GRQ_THR_LOW_OFFSET
|
||||
{ 0x4114, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_CQ_THR_HIGH_OFFSET
|
||||
{ 0x4116, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_GRQ_THR_HIGH_OFFSET
|
||||
{ 0x6040, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId)
|
||||
{ 0x6042, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x6044, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x6046, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x6080, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId)
|
||||
{ 0x6000, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x6002, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x6004, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x60c0, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId)
|
||||
{ 0x6100, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId)
|
||||
{ 0x6104, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId)
|
||||
{ 0x6140, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId)
|
||||
{ 0x6144, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_RX_BDS_THRSHLD_OFFSET(pfId)
|
||||
{ 0x6142, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_CONS_OFFSET(pfId)
|
||||
{ 0x6180, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId)
|
||||
{ 0x7000, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x7002, 0x8, 0x0, 0x0, 0x1}, // USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x7004, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x7040, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId)
|
||||
{ 0x7044, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SIZE_OFFSET(pfId)
|
||||
{ 0x7046, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId)
|
||||
{ 0x7660, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId)
|
||||
{ 0x7080, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId)
|
||||
{ 0x7084, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_SIZE_OFFSET(pfId)
|
||||
{ 0x76a0, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId)
|
||||
{ 0x8040, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId)
|
||||
{ 0x8041, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId)
|
||||
{ 0x8042, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId)
|
||||
{ 0x8043, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId)
|
||||
{ 0x8000, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x8002, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x8004, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x80c0, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId)
|
||||
{ 0x80c2, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId)
|
||||
{ 0x80c4, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId)
|
||||
{ 0x8080, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId)
|
||||
{ 0x8081, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId)
|
||||
{ 0x8082, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId)
|
||||
{ 0x8083, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId)
|
||||
{ 0x8084, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId)
|
||||
{ 0x8085, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId)
|
||||
{ 0x8086, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId)
|
||||
{ 0x6000, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x6002, 0x8, 0x0, 0x0, 0x1}, // CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x6004, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x6042, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_PROD_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6040, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_CONS_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x604c, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6044, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6057, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6054, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6056, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6640, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId)
|
||||
{ 0x6680, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId)
|
||||
{ 0x66c0, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_EQ_PROD_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_TIMER_PARAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_TIMER_ARRAY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FC_CRC_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_EOFA_DEL_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_MISS_FRAME_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_SEQ_TIMEOUT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_DROP_SEQ_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_FCP_RX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_STAT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_DROP_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_ONE_OFFSET(cached_tbl_size)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_TWO_OFFSET(cached_tbl_size)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_ENTRY_TCE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_CACHED_TCE_ENTRY_MNG_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_CACHED_TCE_TBL_BIT_MAP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAIT_4_BD_READ_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_DATA_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_NON_DATA_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_ERR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_GLOBAL_TIMER_TASK_IN_USE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_DEL_CACHED_TASK_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_SILENT_DROP_CACHED_TASK_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_DEBUG_CACHED_TCE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_DROP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_CRC_ERROR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_ERROR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_PREVIOUS_THREAD_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DATA_IN_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_READ_TCE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DROP_ERR_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_ERRORS_NUMBER_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_NUMBER_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_BITMAP_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_ENABLE_CONN_RACE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_TASK_IN_USE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_DEBUG_PARAMS_CRC_ERROR_TASK_IN_USE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FCOE_TIMER_PARAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIMER_ARRAY_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCOE_TX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCOE_TX_BYTE_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_FCP_TX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_STAT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_ABTS_BLOCK_SQ_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_CLEANUP_BLOCK_SQ_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_DEBUG_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_VER_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_BYTE_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_STAT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_WAIT_FOR_YOUR_TURN_SP_CNT_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_AFEX_ERROR_PACKETS_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_PORT_DEBUG_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_DATA_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_WAITING_TABLE_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_WAITING_LIST_SIZE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_REORDER_WAITING_ENTRY_OFFSET
|
||||
};
|
||||
56200
sys/dev/bxe/57712_init_values.c
Normal file
56200
sys/dev/bxe/57712_init_values.c
Normal file
File diff suppressed because it is too large
Load Diff
418
sys/dev/bxe/57712_int_offsets.h
Normal file
418
sys/dev/bxe/57712_int_offsets.h
Normal file
@ -0,0 +1,418 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
|
||||
static const struct iro e2_iro_arr[379] = {
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
|
||||
{ 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
|
||||
{ 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
|
||||
{ 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
|
||||
{ 0x3d, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
|
||||
{ 0x3c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVENT_ID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_OFFSET
|
||||
{ 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_OFFSET
|
||||
{ 0xc, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_RESULT_OFFSET
|
||||
{ 0xe, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_RESULT_OFFSET
|
||||
{ 0x4, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_RESULT_OFFSET
|
||||
{ 0x18, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_MASK
|
||||
{ 0x1c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_MASK
|
||||
{ 0x1c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_MASK
|
||||
{ 0x13, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_AGG_INT
|
||||
{ 0x3e, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_EVENTID
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_PCI_READ_OPCODE
|
||||
{ 0x2, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_OPCODE
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_INCVAL
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_REGION
|
||||
{ 0x50, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_CID
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_LOAD_CONTEXT_RUN_PBF_ECHO_TEST
|
||||
{ 0x3, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_QM_PAUSE_OPCODE
|
||||
{ 0xab, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_SUCCESS_OPCODE_VALUE
|
||||
{ 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_KUKU_TEST_UNUSED_FOCS_OPCODE_VALUE
|
||||
{ 0xc000, 0x10, 0x0, 0x0, 0x8}, // XSTORM_SPQ_PAGE_BASE_OFFSET(funcId)
|
||||
{ 0xc008, 0x10, 0x0, 0x0, 0x2}, // XSTORM_SPQ_PROD_OFFSET(funcId)
|
||||
{ 0xc000, 0x10, 0x0, 0x0, 0x10}, // XSTORM_SPQ_DATA_OFFSET(funcId)
|
||||
{ 0x9c08, 0x4, 0x0, 0x0, 0x4}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId)
|
||||
{ 0xc080, 0x10, 0x0, 0x0, 0x4}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId)
|
||||
{ 0xc088, 0x10, 0x0, 0x0, 0x2}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId)
|
||||
{ 0xc080, 0x10, 0x0, 0x0, 0x10}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId)
|
||||
{ 0x9338, 0x1, 0x4, 0x0, 0x1}, // XSTORM_JUMBO_SUPPORT_OFFSET(pfId)
|
||||
{ 0x9340, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_IP_ID_MASK_OFFSET
|
||||
{ 0x9348, 0x0, 0x0, 0x0, 0x8}, // XSTORM_COMMON_RTC_PARAMS_OFFSET
|
||||
{ 0x934c, 0x0, 0x0, 0x0, 0x2}, // XSTORM_COMMON_RTC_RESOLUTION_OFFSET
|
||||
{ 0x9350, 0x0, 0x0, 0x0, 0x8}, // XSTORM_FW_VERSION_OFFSET
|
||||
{ 0x9698, 0x40, 0x0, 0x0, 0x40}, // XSTORM_LICENSE_VALUES_OFFSET(pfId)
|
||||
{ 0x9358, 0x80, 0x0, 0x0, 0x48}, // XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId)
|
||||
{ 0x9458, 0x40, 0x0, 0x0, 0x8}, // XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId)
|
||||
{ 0x9468, 0x40, 0x0, 0x0, 0x18}, // XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId)
|
||||
{ 0x63010, 0x28, 0x0, 0x0, 0x28}, // XSTORM_PER_QUEUE_STATS_OFFSET(xStatQueueId)
|
||||
{ 0x9950, 0x8, 0x0, 0x0, 0x1}, // XSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x9951, 0x8, 0x0, 0x0, 0x1}, // XSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x9952, 0x8, 0x0, 0x0, 0x1}, // XSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // XSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // XSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x9bb8, 0x0, 0x0, 0x0, 0x8}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // PCI_READ_KUKUE_CODE_OPPCOE
|
||||
{ 0x2, 0x0, 0x0, 0x0, 0x0}, // LOAD_CONTEXT_KUKUE_CODE_OPPCOE
|
||||
{ 0x3, 0x0, 0x0, 0x0, 0x0}, // QM_PAUSE_KUKUE_CODE_OPPCOE
|
||||
{ 0x4, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x5, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0x6, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XOFF_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x7, 0x0, 0x0, 0x0, 0x0}, // PAUSE_TEST_XON_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0x8, 0x0, 0x0, 0x0, 0x0}, // TEST_UNUSED_FOCS_KUKUE_CODE_OPPCOE
|
||||
{ 0x9, 0x0, 0x0, 0x0, 0x0}, // PBF_ECHO_KUKUE_CODE_OPPCOE
|
||||
{ 0xa, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT0_KUKUE_CODE_OPPCOE
|
||||
{ 0xb, 0x0, 0x0, 0x0, 0x0}, // TIME_SYNC_PORT1_KUKUE_CODE_OPPCOE
|
||||
{ 0xc, 0x0, 0x0, 0x0, 0x0}, // IGU_TEST_KUKUE_CODE_OPPCOE
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_INITIAL_CLEANUP_INDEX
|
||||
{ 0x9, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
|
||||
{ 0x2, 0x0, 0x0, 0x0, 0x0}, // XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
|
||||
{ 0xc4c0, 0x0, 0x0, 0x0, 0x20}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{ 0xc4e6, 0x0, 0x0, 0x0, 0x1}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET
|
||||
{ 0x6000, 0x20, 0x0, 0x0, 0x20}, // XSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{ 0x7300, 0x8, 0x0, 0x0, 0x8}, // XSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x9bf0, 0x0, 0x0, 0x0, 0x1}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET
|
||||
{ 0x9b90, 0x0, 0x0, 0x0, 0x8}, // XSTORM_E2_INTEG_RAM_OFFSET
|
||||
{ 0x9b93, 0x0, 0x0, 0x0, 0x1}, // XSTORM_QM_OPPORTUNISTIC_RAM_OFFSET
|
||||
{ 0x9b91, 0x0, 0x0, 0x0, 0x1}, // XSTORM_SIDE_INFO_INPUT_LSB_OFFSET
|
||||
{ 0x9b96, 0x0, 0x0, 0x0, 0x1}, // XSTORM_E2_INTEG_VLAN_ID_OFFSET
|
||||
{ 0x9b97, 0x0, 0x0, 0x0, 0x0}, // XSTORM_E2_INTEG_VLAN_ID_EN_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_LINE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_OP_GEN_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{ 0x60000, 0x0, 0x0, 0x0, 0x20}, // XSTORM_DPM_BUFFER_OFFSET
|
||||
{ 0x9b98, 0x0, 0x0, 0x0, 0x1}, // XSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{ 0x9bd8, 0x0, 0x0, 0x0, 0x8}, // XSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x53, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_OP_GEN_VALUE
|
||||
{ 0x9be0, 0x0, 0x0, 0x0, 0x2}, // XSTORM_QM_PAUSE_TEST_QUEUE_MASK_OFFSET
|
||||
{ 0x9be4, 0x0, 0x0, 0x0, 0x1}, // XSTORM_QM_PAUSE_TEST_GROUP_OFFSET
|
||||
{ 0x9be5, 0x0, 0x0, 0x0, 0x1}, // XSTORM_QM_PAUSE_TEST_PORT_OFFSET
|
||||
{ 0x9, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_OPCODE
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_INCVAL
|
||||
{ 0x44, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_REGION
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_RUN_PBF_ECHO_TEST
|
||||
{ 0x50, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_CID
|
||||
{ 0x89, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_PBF_ECHO_SUCCESS_VALUE
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TIME_SYNC_FLG_OFFSET(funcId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INDIRECTION_TABLE_ENTRY_SIZE
|
||||
{ 0x16c8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_COMMON_RTC_PARAMS_OFFSET
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // TSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // TSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x17e0, 0x8, 0x0, 0x0, 0x1}, // TSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x17e1, 0x8, 0x0, 0x0, 0x1}, // TSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x17e2, 0x8, 0x0, 0x0, 0x1}, // TSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x62078, 0x38, 0x0, 0x0, 0x38}, // TSTORM_PER_QUEUE_STATS_OFFSET(tStatQueueId)
|
||||
{ 0x16f0, 0x0, 0x0, 0x0, 0x2}, // TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET
|
||||
{ 0x16f2, 0x0, 0x0, 0x0, 0x2}, // TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET
|
||||
{ 0xa040, 0x0, 0x0, 0x0, 0x20}, // TSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RSS_KEY_OFFSET(portId)
|
||||
{ 0xe000, 0x20, 0x0, 0x0, 0x20}, // TSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{ 0xf300, 0x8, 0x0, 0x0, 0x8}, // TSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x1708, 0x0, 0x0, 0x0, 0xd8}, // TSTORM_E2_INTEG_RAM_OFFSET
|
||||
{ 0x174f, 0x0, 0x0, 0x0, 0x1}, // TSTORM_LSB_SIDE_BAND_INFO_OFFSET
|
||||
{ 0x1727, 0x0, 0x0, 0x0, 0x1}, // TSTORM_MSB_SIDE_BAND_INFO_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_LINE_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RESULT_OFFSET
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_OP_GEN_VALUE
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{ 0x1788, 0x0, 0x0, 0x0, 0x1}, // TSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{ 0x17c8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x51, 0x0, 0x0, 0x0, 0x0}, // TSTORM_KUKU_OP_GEN_VALUE
|
||||
{ 0x17b0, 0x0, 0x0, 0x0, 0x4}, // TSTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET
|
||||
{ 0x17b4, 0x0, 0x0, 0x0, 0x4}, // TSTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET
|
||||
{ 0x17b8, 0x0, 0x0, 0x0, 0x4}, // TSTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET
|
||||
{ 0x17bc, 0x0, 0x0, 0x0, 0x8}, // TSTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET
|
||||
{ 0x17a8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
|
||||
{ 0x17d8, 0x0, 0x0, 0x0, 0x2}, // TSTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET
|
||||
{ 0x60000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_OFFSET(sbId)
|
||||
{ 0xc000, 0x40, 0x0, 0x0, 0x40}, // CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId)
|
||||
{ 0xc02e, 0x40, 0x0, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId)
|
||||
{ 0xc000, 0x40, 0x2, 0x0, 0x1}, // CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId,hcIndex)
|
||||
{ 0xc001, 0x40, 0x2, 0x0, 0x0}, // CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId,hcIndex)
|
||||
{ 0xe200, 0x20, 0x0, 0x0, 0x20}, // CSTORM_SYNC_BLOCK_OFFSET(sbId)
|
||||
{ 0xe204, 0x2, 0x8, 0x20, 0x2}, // CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex,sbId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex,sbId)
|
||||
{ 0xe200, 0x8, 0x20, 0x0, 0x4}, // CSTORM_HC_SYNC_LINE_DHC_OFFSET(sbSyncLines,sbId)
|
||||
{ 0xf500, 0x28, 0x0, 0x0, 0x28}, // CSTORM_SP_STATUS_BLOCK_OFFSET(pfId)
|
||||
{ 0xf640, 0x10, 0x0, 0x0, 0x10}, // CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId)
|
||||
{ 0xf64a, 0x10, 0x0, 0x0, 0x1}, // CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId)
|
||||
{ 0xf6c0, 0x20, 0x0, 0x0, 0x20}, // CSTORM_SP_SYNC_BLOCK_OFFSET(pfId)
|
||||
{ 0xf6c0, 0x2, 0x20, 0x0, 0x2}, // CSTORM_SP_HC_SYNC_LINE_INDEX_OFFSET(hcSpIndex,pfId)
|
||||
{ 0xf300, 0x40, 0x0, 0x0, 0x40}, // CSTORM_DYNAMIC_HC_CONFIG_OFFSET(pfId)
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // CSTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // CSTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x11a8, 0x8, 0x0, 0x0, 0x1}, // CSTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x11a9, 0x8, 0x0, 0x0, 0x1}, // CSTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x11aa, 0x8, 0x0, 0x0, 0x1}, // CSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x4000, 0x20, 0x4, 0x0, 0x10}, // CSTORM_BYTE_COUNTER_OFFSET(sbId,dhcIndex)
|
||||
{ 0x5900, 0x30, 0x18, 0x0, 0x10}, // CSTORM_EVENT_RING_DATA_OFFSET(pfId)
|
||||
{ 0x5908, 0x30, 0x18, 0x0, 0x2}, // CSTORM_EVENT_RING_PROD_OFFSET(pfId)
|
||||
{ 0x5700, 0x8, 0x0, 0x0, 0x1}, // CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId)
|
||||
{ 0x5701, 0x8, 0x0, 0x0, 0x1}, // CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId)
|
||||
{ 0x1158, 0x0, 0x0, 0x0, 0x1}, // CSTORM_IGU_MODE_OFFSET
|
||||
{ 0x1160, 0x0, 0x0, 0x0, 0x10}, // CSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{ 0x11ac, 0x8, 0x0, 0x0, 0x4}, // CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId)
|
||||
{ 0x4000, 0x20, 0x0, 0x0, 0x20}, // CSTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{ 0x5300, 0x10, 0x0, 0x0, 0x10}, // CSTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{ 0x1470, 0x0, 0x0, 0x0, 0x1}, // CSTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{ 0x14b0, 0x0, 0x0, 0x0, 0x8}, // CSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x50, 0x0, 0x0, 0x0, 0x0}, // CSTORM_KUKU_OP_GEN_VALUE
|
||||
{ 0x1478, 0x0, 0x0, 0x0, 0x4}, // CSTORM_IGU_TEST_PF_ID_OFFSET
|
||||
{ 0x147c, 0x0, 0x0, 0x0, 0x4}, // CSTORM_IGU_TEST_VF_ID_OFFSET
|
||||
{ 0x1480, 0x0, 0x0, 0x0, 0x4}, // CSTORM_IGU_TEST_VF_VALID_OFFSET
|
||||
{ 0x1484, 0x0, 0x0, 0x0, 0x4}, // CSTORM_IGU_TEST_ADDRESS_OFFSET
|
||||
{ 0x1488, 0x0, 0x0, 0x0, 0x8}, // CSTORM_IGU_TEST_IGU_COMMAND_OFFSET
|
||||
{ 0x2af0, 0x80, 0x0, 0x0, 0x80}, // USTORM_INDIRECTION_TABLE_OFFSET(portId)
|
||||
{ 0x1, 0x0, 0x0, 0x0, 0x0}, // USTORM_INDIRECTION_TABLE_ENTRY_SIZE
|
||||
{ 0x2008, 0x10, 0x0, 0x0, 0x10}, // USTORM_ASSERT_LIST_OFFSET(assertListEntry)
|
||||
{ 0x2000, 0x0, 0x0, 0x0, 0x8}, // USTORM_ASSERT_LIST_INDEX_OFFSET
|
||||
{ 0x2c70, 0x8, 0x0, 0x0, 0x1}, // USTORM_FUNC_EN_OFFSET(funcId)
|
||||
{ 0x2c71, 0x8, 0x0, 0x0, 0x1}, // USTORM_VF_TO_PF_OFFSET(funcId)
|
||||
{ 0x2c72, 0x8, 0x0, 0x0, 0x1}, // USTORM_RECORD_SLOW_PATH_OFFSET(funcId)
|
||||
{ 0x4158, 0x38, 0x0, 0x0, 0x38}, // USTORM_PER_QUEUE_STATS_OFFSET(uStatQueueId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId)
|
||||
{ 0x2c44, 0x8, 0x0, 0x0, 0x2}, // USTORM_ETH_PAUSE_ENABLED_OFFSET(portId)
|
||||
{ 0x2c46, 0x8, 0x0, 0x0, 0x2}, // USTORM_TOE_PAUSE_ENABLED_OFFSET(portId)
|
||||
{ 0x2c54, 0x10, 0x0, 0x0, 0x4}, // USTORM_MAX_PAUSE_TIME_USEC_OFFSET(portId)
|
||||
{ 0x2eb0, 0x0, 0x0, 0x0, 0x20}, // USTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
|
||||
{ 0x6000, 0x20, 0x0, 0x0, 0x20}, // USTORM_QUEUE_ZONE_OFFSET(queueId)
|
||||
{ 0x7300, 0x8, 0x0, 0x0, 0x8}, // USTORM_VF_ZONE_OFFSET(vfId)
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX
|
||||
{ 0x0, 0x0, 0x0, 0x0, 0x0}, // USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX
|
||||
{ 0x2f58, 0x0, 0x0, 0x0, 0x1}, // USTORM_KUKU_TEST_OPCODE_OFFSET
|
||||
{ 0x2f98, 0x0, 0x0, 0x0, 0x8}, // USTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET
|
||||
{ 0x50, 0x0, 0x0, 0x0, 0x0}, // USTORM_KUKU_OP_GEN_VALUE
|
||||
{ 0x2f80, 0x0, 0x0, 0x0, 0x4}, // USTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET
|
||||
{ 0x2f84, 0x0, 0x0, 0x0, 0x4}, // USTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET
|
||||
{ 0x2f88, 0x0, 0x0, 0x0, 0x4}, // USTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET
|
||||
{ 0x2f8c, 0x0, 0x0, 0x0, 0x8}, // USTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET
|
||||
{ 0x2fa8, 0x0, 0x0, 0x0, 0x2}, // USTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId)
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId)
|
||||
{ 0x3128, 0x0, 0x0, 0x0, 0x8}, // TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
|
||||
{ 0x62a20, 0x2600, 0x40, 0x0, 0x8}, // USTORM_CQE_PAGE_NEXT_OFFSET(portId,clientId)
|
||||
{ 0xa000, 0x0, 0x0, 0x0, 0x2000}, // USTORM_AGG_DATA_OFFSET
|
||||
{ 0x40c1, 0x0, 0x0, 0x0, 0x1}, // USTORM_TPA_BTR_OFFSET
|
||||
{ 0x40f0, 0x0, 0x0, 0x0, 0x2}, // USTORM_ETH_DYNAMIC_HC_PARAM_OFFSET
|
||||
{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_RX_PRODS_E1X_OFFSET(portId,clientId)
|
||||
{ 0x6000, 0x20, 0x0, 0x0, 0x8}, // USTORM_RX_PRODS_E2_OFFSET(qzoneId)
|
||||
{ 0x4000, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId)
|
||||
{ 0x4001, 0x8, 0x0, 0x0, 0x1}, // XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId)
|
||||
{ 0x4040, 0x8, 0x4, 0x0, 0x2}, // XSTORM_TCP_IPID_OFFSET(pfId)
|
||||
{ 0x4060, 0x8, 0x4, 0x0, 0x4}, // XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId)
|
||||
{ 0x4080, 0x8, 0x0, 0x0, 0x4}, // XSTORM_TCP_TX_SWITCHING_EN_OFFSET(portId)
|
||||
{ 0x4000, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_DUPLICATE_ACK_THRESHOLD_OFFSET(pfId)
|
||||
{ 0x4004, 0x8, 0x0, 0x0, 0x4}, // TSTORM_TCP_MAX_CWND_OFFSET(pfId)
|
||||
{ 0x4040, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_GLOBAL_PARAMS_OFFSET
|
||||
{ 0x4048, 0x0, 0x0, 0x0, 0x8}, // TSTORM_TCP_ISLES_ARRAY_DESCRIPTOR_OFFSET
|
||||
{ 0x8000, 0x0, 0x0, 0x0, 0x10}, // TSTORM_TCP_ISLES_ARRAY_OFFSET
|
||||
{ 0x5040, 0x1, 0x4, 0x0, 0x1}, // XSTORM_TOE_LLC_SNAP_ENABLED_OFFSET(pfId)
|
||||
{ 0x5000, 0x0, 0x0, 0x0, 0x20}, // XSTORM_OUT_OCTETS_OFFSET
|
||||
{ 0x5008, 0x10, 0x0, 0x0, 0x4}, // TSTORM_TOE_MAX_SEG_RETRANSMIT_OFFSET(pfId)
|
||||
{ 0x500c, 0x10, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOUBT_REACHABILITY_OFFSET(pfId)
|
||||
{ 0x52c7, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_MAX_DOMINANCE_VALUE_OFFSET
|
||||
{ 0x52c6, 0x0, 0x0, 0x0, 0x1}, // TSTORM_TOE_DOMINANCE_THRESHOLD_OFFSET
|
||||
{ 0x3000, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0x3004, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0x3008, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0x300a, 0x40, 0x20, 0x0, 0x2}, // CSTORM_TOE_CQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0x300c, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId)
|
||||
{ 0x300d, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId)
|
||||
{ 0x300e, 0x40, 0x20, 0x0, 0x1}, // CSTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId)
|
||||
{ 0x3010, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId)
|
||||
{ 0x3014, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId)
|
||||
{ 0x3018, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_PROD_OFFSET(rssId,portId)
|
||||
{ 0x301c, 0x40, 0x20, 0x0, 0x4}, // CSTORM_TOE_DYNAMIC_HC_CONS_OFFSET(rssId,portId)
|
||||
{ 0xc000, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_LO_OFFSET(rssId,portId,grqBdId)
|
||||
{ 0xc004, 0x100, 0x80, 0x8, 0x4}, // USTORM_GRQ_CACHE_BD_HI_OFFSET(rssId,portId,grqBdId)
|
||||
{ 0xa, 0x0, 0x0, 0x0, 0x0}, // USTORM_TOE_GRQ_CACHE_NUM_BDS
|
||||
{ 0xc068, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_PROD_OFFSET(rssId,portId)
|
||||
{ 0xc069, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_GRQ_LOCAL_CONS_OFFSET(rssId,portId)
|
||||
{ 0xc06c, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0xc06e, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0xc070, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0xc074, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_GRQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0xc066, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_GRQ_BUF_SIZE_OFFSET(rssId,portId)
|
||||
{ 0xc064, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId)
|
||||
{ 0xc060, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_CONS_OFFSET(rssId,portId)
|
||||
{ 0xc062, 0x100, 0x80, 0x0, 0x2}, // USTORM_TOE_CQ_PROD_OFFSET(rssId,portId)
|
||||
{ 0xc050, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId)
|
||||
{ 0xc054, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId)
|
||||
{ 0xc058, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId)
|
||||
{ 0xc05c, 0x100, 0x80, 0x0, 0x4}, // USTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId)
|
||||
{ 0xc07c, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId)
|
||||
{ 0xc07d, 0x100, 0x80, 0x0, 0x1}, // USTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId)
|
||||
{ 0x1018, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_TCP_PUSH_TIMER_TICKS_OFFSET(pfId)
|
||||
{ 0x1090, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_GRQ_XOFF_COUNTER_OFFSET(pfId)
|
||||
{ 0x1098, 0x10, 0x0, 0x0, 0x4}, // USTORM_TOE_RCQ_XOFF_COUNTER_OFFSET(pfId)
|
||||
{ 0x1110, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_CQ_THR_LOW_OFFSET
|
||||
{ 0x1112, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_GRQ_THR_LOW_OFFSET
|
||||
{ 0x1114, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_CQ_THR_HIGH_OFFSET
|
||||
{ 0x1116, 0x0, 0x0, 0x0, 0x2}, // USTORM_TOE_GRQ_THR_HIGH_OFFSET
|
||||
{ 0x6040, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId)
|
||||
{ 0x6042, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x6044, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x6046, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId)
|
||||
{ 0x6080, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId)
|
||||
{ 0x6000, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x6002, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x6004, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x60c0, 0x8, 0x0, 0x0, 0x8}, // TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId)
|
||||
{ 0x6100, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId)
|
||||
{ 0x6104, 0x8, 0x0, 0x0, 0x1}, // TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId)
|
||||
{ 0x6140, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId)
|
||||
{ 0x6144, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_RX_BDS_THRSHLD_OFFSET(pfId)
|
||||
{ 0x6142, 0x8, 0x0, 0x0, 0x2}, // TSTORM_ISCSI_L2_ISCSI_OOO_CONS_OFFSET(pfId)
|
||||
{ 0x6180, 0x8, 0x0, 0x0, 0x4}, // TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId)
|
||||
{ 0x3000, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x3002, 0x8, 0x0, 0x0, 0x1}, // USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x3004, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x3040, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId)
|
||||
{ 0x3044, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SIZE_OFFSET(pfId)
|
||||
{ 0x3046, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId)
|
||||
{ 0x3660, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId)
|
||||
{ 0x3080, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId)
|
||||
{ 0x3084, 0x8, 0x0, 0x0, 0x2}, // USTORM_ISCSI_RQ_SIZE_OFFSET(pfId)
|
||||
{ 0x36a0, 0x8, 0x0, 0x0, 0x8}, // USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId)
|
||||
{ 0x8040, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId)
|
||||
{ 0x8041, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId)
|
||||
{ 0x8042, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId)
|
||||
{ 0x8043, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId)
|
||||
{ 0x8000, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x8002, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x8004, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x80c0, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId)
|
||||
{ 0x80c2, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId)
|
||||
{ 0x80c4, 0x8, 0x0, 0x0, 0x2}, // XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId)
|
||||
{ 0x8080, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId)
|
||||
{ 0x8081, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId)
|
||||
{ 0x8082, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId)
|
||||
{ 0x8083, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId)
|
||||
{ 0x8084, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId)
|
||||
{ 0x8085, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId)
|
||||
{ 0x8086, 0x8, 0x0, 0x0, 0x1}, // XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId)
|
||||
{ 0x6000, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId)
|
||||
{ 0x6002, 0x8, 0x0, 0x0, 0x1}, // CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId)
|
||||
{ 0x6004, 0x8, 0x0, 0x0, 0x2}, // CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId)
|
||||
{ 0x6042, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_PROD_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6040, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_CONS_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x604c, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6044, 0xc0, 0x18, 0x0, 0x8}, // CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6057, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6054, 0xc0, 0x18, 0x0, 0x2}, // CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6056, 0xc0, 0x18, 0x0, 0x1}, // CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId,iscsiEqId)
|
||||
{ 0x6640, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId)
|
||||
{ 0x6680, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId)
|
||||
{ 0x66c0, 0x8, 0x0, 0x0, 0x8}, // CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId)
|
||||
{ 0xda82, 0x18, 0x0, 0x0, 0x2}, // USTORM_FCOE_EQ_PROD_OFFSET(pfId)
|
||||
{ 0xdba0, 0x0, 0x0, 0x0, 0x0}, // USTORM_FCOE_TIMER_PARAM_OFFSET
|
||||
{ 0xe000, 0x0, 0x0, 0x0, 0x4}, // USTORM_TIMER_ARRAY_OFFSET
|
||||
{ 0xd100, 0x0, 0x0, 0x0, 0x4}, // USTORM_STAT_FC_CRC_CNT_OFFSET
|
||||
{ 0xd104, 0x0, 0x0, 0x0, 0x4}, // USTORM_STAT_EOFA_DEL_CNT_OFFSET
|
||||
{ 0xd108, 0x0, 0x0, 0x0, 0x4}, // USTORM_STAT_MISS_FRAME_CNT_OFFSET
|
||||
{ 0xd10c, 0x0, 0x0, 0x0, 0x4}, // USTORM_STAT_SEQ_TIMEOUT_CNT_OFFSET
|
||||
{ 0xd110, 0x0, 0x0, 0x0, 0x4}, // USTORM_STAT_DROP_SEQ_CNT_OFFSET
|
||||
{ 0xd114, 0x0, 0x0, 0x0, 0x4}, // USTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET
|
||||
{ 0xd118, 0x0, 0x0, 0x0, 0x4}, // USTORM_STAT_FCP_RX_PKT_CNT_OFFSET
|
||||
{ 0xd100, 0x0, 0x0, 0x0, 0x20}, // USTORM_STAT_OFFSET
|
||||
{ 0x9280, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_DROP_PKT_CNT_OFFSET
|
||||
{ 0x9280, 0x0, 0x0, 0x0, 0x28}, // USTORM_DEBUG_OFFSET
|
||||
{ 0x8050, 0xa8, 0x0, 0x0, 0x1}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_ONE_OFFSET(cached_tbl_size)
|
||||
{ 0x8054, 0xa8, 0x0, 0x0, 0x1}, // USTORM_CACHED_TCE_MNG_INFO_DWORD_TWO_OFFSET(cached_tbl_size)
|
||||
{ 0x8000, 0x0, 0x0, 0x0, 0x50}, // USTORM_CACHED_TCE_ENTRY_TCE_OFFSET
|
||||
{ 0x8050, 0x0, 0x0, 0x0, 0x10}, // USTORM_CACHED_TCE_ENTRY_MNG_INFO_OFFSET
|
||||
{ 0x9600, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_CACHED_TCE_TBL_BIT_MAP_OFFSET
|
||||
{ 0x9400, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_CACHED_TCE_WAIT_4_BD_READ_OFFSET
|
||||
{ 0x9404, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_DATA_OFFSET
|
||||
{ 0x9408, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_NON_DATA_OFFSET
|
||||
{ 0x940c, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_ERR_OFFSET
|
||||
{ 0x9410, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_CACHED_TCE_GLOBAL_TIMER_TASK_IN_USE_OFFSET
|
||||
{ 0x9414, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_CACHED_TCE_DEL_CACHED_TASK_OFFSET
|
||||
{ 0x9418, 0x0, 0x0, 0x0, 0x4}, // USTORM_DEBUG_CACHED_TCE_SILENT_DROP_CACHED_TASK_OFFSET
|
||||
{ 0x9400, 0x0, 0x0, 0x0, 0x40}, // USTORM_DEBUG_CACHED_TCE_OFFSET
|
||||
{ 0x9420, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_DROP_OFFSET
|
||||
{ 0x9424, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_CRC_ERROR_OFFSET
|
||||
{ 0x9428, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_ERROR_OFFSET
|
||||
{ 0x941c, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_CACHED_TCE_PREVIOUS_THREAD_OFFSET
|
||||
{ 0x9430, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DATA_IN_OFFSET
|
||||
{ 0x942c, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_READ_TCE_OFFSET
|
||||
{ 0x9434, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DROP_ERR_OFFSET
|
||||
{ 0x9284, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_PARAMS_ERRORS_NUMBER_OFFSET
|
||||
{ 0x9280, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_NUMBER_OFFSET
|
||||
{ 0x9290, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_BITMAP_OFFSET
|
||||
{ 0x92a4, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_PARAMS_ENABLE_CONN_RACE_OFFSET
|
||||
{ 0x9438, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_PARAMS_TASK_IN_USE_OFFSET
|
||||
{ 0x943c, 0x0, 0x0, 0x0, 0x4}, // USTORM_FCOE_DEBUG_PARAMS_CRC_ERROR_TASK_IN_USE_OFFSET
|
||||
{ 0xb988, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FCOE_TIMER_PARAM_OFFSET
|
||||
{ 0xd000, 0x0, 0x0, 0x0, 0x4}, // XSTORM_TIMER_ARRAY_OFFSET
|
||||
{ 0xb100, 0x0, 0x0, 0x0, 0x4}, // XSTORM_STAT_FCOE_TX_PKT_CNT_OFFSET
|
||||
{ 0xb104, 0x0, 0x0, 0x0, 0x4}, // XSTORM_STAT_FCOE_TX_BYTE_CNT_OFFSET
|
||||
{ 0xb108, 0x0, 0x0, 0x0, 0x4}, // XSTORM_STAT_FCP_TX_PKT_CNT_OFFSET
|
||||
{ 0xb100, 0x0, 0x0, 0x0, 0x10}, // XSTORM_STAT_OFFSET
|
||||
{ 0xbcb0, 0x0, 0x0, 0x0, 0x4}, // XSTORM_DEBUG_ABTS_BLOCK_SQ_CNT_OFFSET
|
||||
{ 0xbcb4, 0x0, 0x0, 0x0, 0x4}, // XSTORM_DEBUG_CLEANUP_BLOCK_SQ_CNT_OFFSET
|
||||
{ 0xbcb0, 0x0, 0x0, 0x0, 0x48}, // XSTORM_DEBUG_OFFSET
|
||||
{ 0xd858, 0x0, 0x0, 0x0, 0x4}, // TSTORM_STAT_FCOE_VER_CNT_OFFSET
|
||||
{ 0xd850, 0x0, 0x0, 0x0, 0x4}, // TSTORM_STAT_FCOE_RX_PKT_CNT_OFFSET
|
||||
{ 0xd854, 0x0, 0x0, 0x0, 0x4}, // TSTORM_STAT_FCOE_RX_BYTE_CNT_OFFSET
|
||||
{ 0xd85c, 0x0, 0x0, 0x0, 0x4}, // TSTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET
|
||||
{ 0xd850, 0x0, 0x0, 0x0, 0x10}, // TSTORM_STAT_OFFSET
|
||||
{ 0xd840, 0x0, 0x0, 0x0, 0x4}, // TSTORM_PORT_DEBUG_WAIT_FOR_YOUR_TURN_SP_CNT_OFFSET
|
||||
{ 0xd844, 0x0, 0x0, 0x0, 0x4}, // TSTORM_PORT_DEBUG_AFEX_ERROR_PACKETS_OFFSET
|
||||
{ 0xd840, 0x0, 0x0, 0x0, 0x8}, // TSTORM_PORT_DEBUG_OFFSET
|
||||
{ 0xd4c8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_REORDER_DATA_OFFSET
|
||||
{ 0xd4d8, 0x0, 0x0, 0x0, 0x80}, // TSTORM_REORDER_WAITING_TABLE_OFFSET
|
||||
{ 0x10, 0x0, 0x0, 0x0, 0x0}, // TSTORM_WAITING_LIST_SIZE
|
||||
{ 0xd4d8, 0x0, 0x0, 0x0, 0x8}, // TSTORM_REORDER_WAITING_ENTRY_OFFSET
|
||||
};
|
||||
18843
sys/dev/bxe/bxe.c
Normal file
18843
sys/dev/bxe/bxe.c
Normal file
File diff suppressed because it is too large
Load Diff
2497
sys/dev/bxe/bxe.h
Normal file
2497
sys/dev/bxe/bxe.h
Normal file
File diff suppressed because it is too large
Load Diff
287
sys/dev/bxe/bxe_dcb.h
Normal file
287
sys/dev/bxe/bxe_dcb.h
Normal file
@ -0,0 +1,287 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#ifndef BXE_DCB_H
|
||||
#define BXE_DCB_H
|
||||
|
||||
#define LLFC_DRIVER_TRAFFIC_TYPE_MAX 3 /* NW, iSCSI, FCoE */
|
||||
struct bxe_dcbx_app_params {
|
||||
uint32_t enabled;
|
||||
uint32_t traffic_type_priority[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
|
||||
};
|
||||
|
||||
#define DCBX_COS_MAX_NUM_E2 DCBX_E2E3_MAX_NUM_COS
|
||||
/* bxe currently limits numbers of supported COSes to 3 to be extended to 6 */
|
||||
#define BXE_MAX_COS_SUPPORT 3
|
||||
#define DCBX_COS_MAX_NUM_E3B0 BXE_MAX_COS_SUPPORT
|
||||
#define DCBX_COS_MAX_NUM BXE_MAX_COS_SUPPORT
|
||||
|
||||
struct bxe_dcbx_cos_params {
|
||||
uint32_t bw_tbl;
|
||||
uint32_t pri_bitmask;
|
||||
/*
|
||||
* strict priority: valid values are 0..5; 0 is highest priority.
|
||||
* There can't be two COSes with the same priority.
|
||||
*/
|
||||
uint8_t strict;
|
||||
#define BXE_DCBX_STRICT_INVALID DCBX_COS_MAX_NUM
|
||||
#define BXE_DCBX_STRICT_COS_HIGHEST 0
|
||||
#define BXE_DCBX_STRICT_COS_NEXT_LOWER_PRI(sp) ((sp) + 1)
|
||||
uint8_t pauseable;
|
||||
};
|
||||
|
||||
struct bxe_dcbx_pg_params {
|
||||
uint32_t enabled;
|
||||
uint8_t num_of_cos; /* valid COS entries */
|
||||
struct bxe_dcbx_cos_params cos_params[DCBX_COS_MAX_NUM];
|
||||
};
|
||||
|
||||
struct bxe_dcbx_pfc_params {
|
||||
uint32_t enabled;
|
||||
uint32_t priority_non_pauseable_mask;
|
||||
};
|
||||
|
||||
struct bxe_dcbx_port_params {
|
||||
struct bxe_dcbx_pfc_params pfc;
|
||||
struct bxe_dcbx_pg_params ets;
|
||||
struct bxe_dcbx_app_params app;
|
||||
};
|
||||
|
||||
#define BXE_DCBX_CONFIG_INV_VALUE (0xFFFFFFFF)
|
||||
#define BXE_DCBX_OVERWRITE_SETTINGS_DISABLE 0
|
||||
#define BXE_DCBX_OVERWRITE_SETTINGS_ENABLE 1
|
||||
#define BXE_DCBX_OVERWRITE_SETTINGS_INVALID (BXE_DCBX_CONFIG_INV_VALUE)
|
||||
#define BXE_IS_ETS_ENABLED(sc) \
|
||||
((sc)->dcb_state == BXE_DCB_STATE_ON && \
|
||||
(sc)->dcbx_port_params.ets.enabled)
|
||||
|
||||
struct bxe_config_lldp_params {
|
||||
uint32_t overwrite_settings;
|
||||
uint32_t msg_tx_hold;
|
||||
uint32_t msg_fast_tx;
|
||||
uint32_t tx_credit_max;
|
||||
uint32_t msg_tx_interval;
|
||||
uint32_t tx_fast;
|
||||
};
|
||||
|
||||
struct bxe_lldp_params_get {
|
||||
uint32_t ver_num;
|
||||
#define LLDP_PARAMS_VER_NUM 2
|
||||
struct bxe_config_lldp_params config_lldp_params;
|
||||
/* The reserved field should follow in case the struct above will increase*/
|
||||
uint32_t _reserved[20];
|
||||
uint32_t admin_status;
|
||||
#define LLDP_TX_ONLY 0x01
|
||||
#define LLDP_RX_ONLY 0x02
|
||||
#define LLDP_TX_RX 0x03
|
||||
#define LLDP_DISABLED 0x04
|
||||
uint32_t remote_chassis_id[REM_CHASSIS_ID_STAT_LEN];
|
||||
uint32_t remote_port_id[REM_PORT_ID_STAT_LEN];
|
||||
uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
|
||||
uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
|
||||
};
|
||||
|
||||
struct bxe_admin_priority_app_table {
|
||||
uint32_t valid;
|
||||
uint32_t priority;
|
||||
#define INVALID_TRAFFIC_TYPE_PRIORITY (0xFFFFFFFF)
|
||||
uint32_t traffic_type;
|
||||
#define TRAFFIC_TYPE_ETH 0
|
||||
#define TRAFFIC_TYPE_PORT 1
|
||||
uint32_t app_id;
|
||||
};
|
||||
|
||||
#define DCBX_CONFIG_MAX_APP_PROTOCOL 4
|
||||
struct bxe_config_dcbx_params {
|
||||
uint32_t overwrite_settings;
|
||||
uint32_t admin_dcbx_version;
|
||||
uint32_t admin_ets_enable;
|
||||
uint32_t admin_pfc_enable;
|
||||
uint32_t admin_tc_supported_tx_enable;
|
||||
uint32_t admin_ets_configuration_tx_enable;
|
||||
uint32_t admin_ets_recommendation_tx_enable;
|
||||
uint32_t admin_pfc_tx_enable;
|
||||
uint32_t admin_application_priority_tx_enable;
|
||||
uint32_t admin_ets_willing;
|
||||
uint32_t admin_ets_reco_valid;
|
||||
uint32_t admin_pfc_willing;
|
||||
uint32_t admin_app_priority_willing;
|
||||
uint32_t admin_configuration_bw_precentage[8];
|
||||
uint32_t admin_configuration_ets_pg[8];
|
||||
uint32_t admin_recommendation_bw_precentage[8];
|
||||
uint32_t admin_recommendation_ets_pg[8];
|
||||
uint32_t admin_pfc_bitmap;
|
||||
struct bxe_admin_priority_app_table
|
||||
admin_priority_app_table[DCBX_CONFIG_MAX_APP_PROTOCOL];
|
||||
uint32_t admin_default_priority;
|
||||
};
|
||||
|
||||
//#define DCBX_PARAMS_VER_NUM 3 /* XXX conflict with common_uif.h */
|
||||
struct bxe_dcbx_params_get {
|
||||
uint32_t ver_num;
|
||||
uint32_t dcb_state;
|
||||
uint32_t dcbx_enabled;
|
||||
struct bxe_config_dcbx_params config_dcbx_params;
|
||||
/* The reserved field should follow in case the struct above will increase*/
|
||||
uint32_t _reserved[19];
|
||||
|
||||
uint32_t dcb_current_state;
|
||||
#define BXE_DCBX_CURRENT_STATE_IS_SYNC (1 << 0)
|
||||
#define BXE_PFC_IS_CURRENTLY_OPERATIONAL (1 << 1)
|
||||
#define BXE_ETS_IS_CURRENTLY_OPERATIONAL (1 << 2)
|
||||
#define BXE_PRIORITY_TAGGING_IS_CURRENTLY_OPERATIONAL (1 << 3)
|
||||
|
||||
uint32_t local_tc_supported;
|
||||
uint32_t local_pfc_caps;
|
||||
uint32_t remote_tc_supported;
|
||||
uint32_t remote_pfc_cap;
|
||||
uint32_t remote_ets_willing;
|
||||
uint32_t remote_ets_reco_valid;
|
||||
uint32_t remote_pfc_willing;
|
||||
uint32_t remote_app_priority_willing;
|
||||
uint32_t remote_configuration_bw_precentage[8];
|
||||
uint32_t remote_configuration_ets_pg[8];
|
||||
uint32_t remote_recommendation_bw_precentage[8];
|
||||
uint32_t remote_recommendation_ets_pg[8];
|
||||
uint32_t remote_pfc_bitmap;
|
||||
struct bxe_admin_priority_app_table
|
||||
remote_priority_app_table[DCBX_MAX_APP_PROTOCOL];
|
||||
uint32_t local_ets_enable;
|
||||
uint32_t local_pfc_enable;
|
||||
uint32_t local_configuration_bw_precentage[8];
|
||||
uint32_t local_configuration_ets_pg[8];
|
||||
uint32_t local_pfc_bitmap;
|
||||
struct bxe_admin_priority_app_table
|
||||
local_priority_app_table[DCBX_MAX_APP_PROTOCOL];
|
||||
uint32_t pfc_mismatch;
|
||||
uint32_t priority_app_mismatch;
|
||||
uint32_t dcbx_frames_sent;
|
||||
uint32_t dcbx_frames_received;
|
||||
uint32_t pfc_frames_sent[2];
|
||||
uint32_t pfc_frames_received[2];
|
||||
};
|
||||
|
||||
struct bxe_dcbx_params_set {
|
||||
uint32_t ver_num;
|
||||
uint32_t dcb_state;
|
||||
uint32_t dcbx_enabled;
|
||||
struct bxe_config_dcbx_params config_dcbx_params;
|
||||
};
|
||||
|
||||
#define GET_FLAGS(flags, bits) ((flags) & (bits))
|
||||
#define SET_FLAGS(flags, bits) ((flags) |= (bits))
|
||||
#define RESET_FLAGS(flags, bits) ((flags) &= ~(bits))
|
||||
|
||||
enum {
|
||||
DCBX_READ_LOCAL_MIB,
|
||||
DCBX_READ_REMOTE_MIB
|
||||
};
|
||||
|
||||
#define ETH_TYPE_FCOE (0x8906)
|
||||
#define TCP_PORT_ISCSI (0xCBC)
|
||||
|
||||
#define PFC_VALUE_FRAME_SIZE (512)
|
||||
#define PFC_QUANTA_IN_NANOSEC_FROM_SPEED_MEGA(mega_speed) \
|
||||
((1000 * PFC_VALUE_FRAME_SIZE)/(mega_speed))
|
||||
|
||||
#define PFC_BRB1_REG_HIGH_LLFC_LOW_THRESHOLD 130
|
||||
#define PFC_BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD 170
|
||||
|
||||
struct cos_entry_help_data {
|
||||
uint32_t pri_join_mask;
|
||||
uint32_t cos_bw;
|
||||
uint8_t strict;
|
||||
uint8_t pausable;
|
||||
};
|
||||
|
||||
struct cos_help_data {
|
||||
struct cos_entry_help_data data[DCBX_COS_MAX_NUM];
|
||||
uint8_t num_of_cos;
|
||||
};
|
||||
|
||||
#define DCBX_ILLEGAL_PG (0xFF)
|
||||
#define DCBX_PFC_PRI_MASK (0xFF)
|
||||
#define DCBX_STRICT_PRIORITY (15)
|
||||
#define DCBX_INVALID_COS_BW (0xFFFFFFFF)
|
||||
#define DCBX_PFC_PRI_NON_PAUSE_MASK(sc) \
|
||||
((sc)->dcbx_port_params.pfc.priority_non_pauseable_mask)
|
||||
#define DCBX_PFC_PRI_PAUSE_MASK(sc) \
|
||||
((uint8_t)~DCBX_PFC_PRI_NON_PAUSE_MASK(sc))
|
||||
#define DCBX_PFC_PRI_GET_PAUSE(sc, pg_pri) \
|
||||
((pg_pri) & (DCBX_PFC_PRI_PAUSE_MASK(sc)))
|
||||
#define DCBX_PFC_PRI_GET_NON_PAUSE(sc, pg_pri) \
|
||||
(DCBX_PFC_PRI_NON_PAUSE_MASK(sc) & (pg_pri))
|
||||
#define DCBX_IS_PFC_PRI_SOME_PAUSE(sc, pg_pri) \
|
||||
(0 != DCBX_PFC_PRI_GET_PAUSE(sc, pg_pri))
|
||||
#define IS_DCBX_PFC_PRI_ONLY_PAUSE(sc, pg_pri) \
|
||||
(pg_pri == DCBX_PFC_PRI_GET_PAUSE((sc), (pg_pri)))
|
||||
#define IS_DCBX_PFC_PRI_ONLY_NON_PAUSE(sc, pg_pri) \
|
||||
((pg_pri) == DCBX_PFC_PRI_GET_NON_PAUSE((sc), (pg_pri)))
|
||||
#define IS_DCBX_PFC_PRI_MIX_PAUSE(sc, pg_pri) \
|
||||
(!(IS_DCBX_PFC_PRI_ONLY_NON_PAUSE((sc), (pg_pri)) || \
|
||||
IS_DCBX_PFC_PRI_ONLY_PAUSE((sc), (pg_pri))))
|
||||
|
||||
struct pg_entry_help_data {
|
||||
uint8_t num_of_dif_pri;
|
||||
uint8_t pg;
|
||||
uint32_t pg_priority;
|
||||
};
|
||||
|
||||
struct pg_help_data {
|
||||
struct pg_entry_help_data data[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
|
||||
uint8_t num_of_pg;
|
||||
};
|
||||
|
||||
/* forward DCB/PFC related declarations */
|
||||
struct bxe_softc;
|
||||
/* void bxe_dcbx_update(struct work_struct *work); */
|
||||
void bxe_dcbx_init_params(struct bxe_softc *sc);
|
||||
void bxe_dcbx_set_state(struct bxe_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled);
|
||||
int bxe_dcb_get_lldp_params_ioctl(struct bxe_softc *sc, void *uaddr);
|
||||
int bxe_dcb_get_dcbx_params_ioctl(struct bxe_softc *sc, void *uaddr);
|
||||
int bxe_dcb_set_dcbx_params_ioctl(struct bxe_softc *sc, void *uaddr);
|
||||
|
||||
enum {
|
||||
BXE_DCBX_STATE_NEG_RECEIVED = 0x1,
|
||||
BXE_DCBX_STATE_TX_PAUSED,
|
||||
BXE_DCBX_STATE_TX_RELEASED
|
||||
};
|
||||
|
||||
void bxe_dcbx_set_params(struct bxe_softc *sc, uint32_t state);
|
||||
void bxe_dcbx_pmf_update(struct bxe_softc *sc);
|
||||
|
||||
#endif /* BXE_DCB_H */
|
||||
|
||||
375
sys/dev/bxe/bxe_debug.c
Normal file
375
sys/dev/bxe/bxe_debug.c
Normal file
@ -0,0 +1,375 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include "bxe.h"
|
||||
|
||||
#include "ddb/ddb.h"
|
||||
#include "ddb/db_sym.h"
|
||||
#include "ddb/db_lex.h"
|
||||
|
||||
#ifdef BXE_REG_NO_INLINE
|
||||
|
||||
/*
|
||||
* Debug versions of the 8/16/32 bit OS register read/write functions to
|
||||
* capture/display values read/written from/to the controller.
|
||||
*/
|
||||
|
||||
void
|
||||
bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val)
|
||||
{
|
||||
BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%02x\n", offset, val);
|
||||
bus_space_write_1(sc->bar[BAR0].tag,
|
||||
sc->bar[BAR0].handle,
|
||||
offset,
|
||||
val);
|
||||
}
|
||||
|
||||
void
|
||||
bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val)
|
||||
{
|
||||
if ((offset % 2) != 0) {
|
||||
BLOGD(sc, DBG_REGS, "Unaligned 16-bit write to 0x%08lx\n", offset);
|
||||
}
|
||||
|
||||
BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%04x\n", offset, val);
|
||||
bus_space_write_2(sc->bar[BAR0].tag,
|
||||
sc->bar[BAR0].handle,
|
||||
offset,
|
||||
val);
|
||||
}
|
||||
|
||||
void
|
||||
bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val)
|
||||
{
|
||||
if ((offset % 4) != 0) {
|
||||
BLOGD(sc, DBG_REGS, "Unaligned 32-bit write to 0x%08lx\n", offset);
|
||||
}
|
||||
|
||||
BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%08x\n", offset, val);
|
||||
bus_space_write_4(sc->bar[BAR0].tag,
|
||||
sc->bar[BAR0].handle,
|
||||
offset,
|
||||
val);
|
||||
}
|
||||
|
||||
uint8_t
|
||||
bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset)
|
||||
{
|
||||
uint8_t val;
|
||||
|
||||
val = bus_space_read_1(sc->bar[BAR0].tag,
|
||||
sc->bar[BAR0].handle,
|
||||
offset);
|
||||
BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%02x\n", offset, val);
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
uint16_t
|
||||
bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset)
|
||||
{
|
||||
uint16_t val;
|
||||
|
||||
if ((offset % 2) != 0) {
|
||||
BLOGD(sc, DBG_REGS, "Unaligned 16-bit read from 0x%08lx\n", offset);
|
||||
}
|
||||
|
||||
val = bus_space_read_2(sc->bar[BAR0].tag,
|
||||
sc->bar[BAR0].handle,
|
||||
offset);
|
||||
BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%08x\n", offset, val);
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
if ((offset % 4) != 0) {
|
||||
BLOGD(sc, DBG_REGS, "Unaligned 32-bit read from 0x%08lx\n", offset);
|
||||
}
|
||||
|
||||
val = bus_space_read_4(sc->bar[BAR0].tag,
|
||||
sc->bar[BAR0].handle,
|
||||
offset);
|
||||
BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%08x\n", offset, val);
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
#endif /* BXE_REG_NO_INLINE */
|
||||
|
||||
#ifdef ELINK_DEBUG
|
||||
|
||||
void
|
||||
elink_cb_dbg(struct bxe_softc *sc,
|
||||
char *fmt)
|
||||
{
|
||||
char buf[128];
|
||||
if (__predict_false(sc->debug & DBG_PHY)) {
|
||||
snprintf(buf, sizeof(buf), "ELINK: %s", fmt);
|
||||
device_printf(sc->dev, "%s", buf);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
elink_cb_dbg1(struct bxe_softc *sc,
|
||||
char *fmt,
|
||||
uint32_t arg1)
|
||||
{
|
||||
char tmp[128], buf[128];
|
||||
if (__predict_false(sc->debug & DBG_PHY)) {
|
||||
snprintf(tmp, sizeof(tmp), "ELINK: %s", fmt);
|
||||
snprintf(buf, sizeof(buf), tmp, arg1);
|
||||
device_printf(sc->dev, "%s", buf);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
elink_cb_dbg2(struct bxe_softc *sc,
|
||||
char *fmt,
|
||||
uint32_t arg1,
|
||||
uint32_t arg2)
|
||||
{
|
||||
char tmp[128], buf[128];
|
||||
if (__predict_false(sc->debug & DBG_PHY)) {
|
||||
snprintf(tmp, sizeof(tmp), "ELINK: %s", fmt);
|
||||
snprintf(buf, sizeof(buf), tmp, arg1, arg2);
|
||||
device_printf(sc->dev, "%s", buf);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
elink_cb_dbg3(struct bxe_softc *sc,
|
||||
char *fmt,
|
||||
uint32_t arg1,
|
||||
uint32_t arg2,
|
||||
uint32_t arg3)
|
||||
{
|
||||
char tmp[128], buf[128];
|
||||
if (__predict_false(sc->debug & DBG_PHY)) {
|
||||
snprintf(tmp, sizeof(tmp), "ELINK: %s", fmt);
|
||||
snprintf(buf, sizeof(buf), tmp, arg1, arg2, arg3);
|
||||
device_printf(sc->dev, "%s", buf);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* ELINK_DEBUG */
|
||||
|
||||
extern struct mtx bxe_prev_mtx;
|
||||
|
||||
void
|
||||
bxe_dump_mem(struct bxe_softc *sc,
|
||||
char *tag,
|
||||
uint8_t *mem,
|
||||
uint32_t len)
|
||||
{
|
||||
char buf[256];
|
||||
char c[32];
|
||||
int xx;
|
||||
|
||||
mtx_lock(&bxe_prev_mtx);
|
||||
|
||||
BLOGI(sc, "++++++++++++ %s\n", tag);
|
||||
strcpy(buf, "** 000: ");
|
||||
|
||||
for (xx = 0; xx < len; xx++)
|
||||
{
|
||||
if ((xx != 0) && (xx % 16 == 0))
|
||||
{
|
||||
BLOGI(sc, "%s\n", buf);
|
||||
strcpy(buf, "** ");
|
||||
snprintf(c, sizeof(c), "%03x", xx);
|
||||
strcat(buf, c);
|
||||
strcat(buf, ": ");
|
||||
}
|
||||
|
||||
snprintf(c, sizeof(c), "%02x ", *mem);
|
||||
strcat(buf, c);
|
||||
|
||||
mem++;
|
||||
}
|
||||
|
||||
BLOGI(sc, "%s\n", buf);
|
||||
BLOGI(sc, "------------ %s\n", tag);
|
||||
|
||||
mtx_unlock(&bxe_prev_mtx);
|
||||
}
|
||||
|
||||
void
|
||||
bxe_dump_mbuf_data(struct bxe_softc *sc,
|
||||
char *tag,
|
||||
struct mbuf *m,
|
||||
uint8_t contents)
|
||||
{
|
||||
char buf[256];
|
||||
char c[32];
|
||||
uint8_t *memp;
|
||||
int i, xx = 0;
|
||||
|
||||
mtx_lock(&bxe_prev_mtx);
|
||||
|
||||
BLOGI(sc, "++++++++++++ %s\n", tag);
|
||||
|
||||
while (m)
|
||||
{
|
||||
memp = m->m_data;
|
||||
strcpy(buf, "** > ");
|
||||
snprintf(c, sizeof(c), "%03x", xx);
|
||||
strcat(buf, c);
|
||||
strcat(buf, ": ");
|
||||
|
||||
if (contents)
|
||||
{
|
||||
for (i = 0; i < m->m_len; i++)
|
||||
{
|
||||
if ((xx != 0) && (xx % 16 == 0))
|
||||
{
|
||||
BLOGI(sc, "%s\n", buf);
|
||||
strcpy(buf, "** ");
|
||||
snprintf(c, sizeof(c), "%03x", xx);
|
||||
strcat(buf, c);
|
||||
strcat(buf, ": ");
|
||||
}
|
||||
|
||||
snprintf(c, sizeof(c), "%02x ", *memp);
|
||||
strcat(buf, c);
|
||||
|
||||
memp++;
|
||||
xx++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
snprintf(c, sizeof(c), "%d", m->m_len);
|
||||
strcat(buf, c);
|
||||
xx += m->m_len;
|
||||
}
|
||||
|
||||
BLOGI(sc, "%s\n", buf);
|
||||
m = m->m_next;
|
||||
}
|
||||
|
||||
BLOGI(sc, "------------ %s\n", tag);
|
||||
|
||||
mtx_unlock(&bxe_prev_mtx);
|
||||
}
|
||||
|
||||
#ifdef DDB
|
||||
|
||||
static void bxe_ddb_usage()
|
||||
{
|
||||
db_printf("Usage: bxe[/hpv] <instance> [<address>]\n");
|
||||
}
|
||||
|
||||
static db_cmdfcn_t bxe_ddb;
|
||||
_DB_SET(_cmd, bxe, bxe_ddb, db_cmd_table, CS_OWN, NULL);
|
||||
|
||||
static void bxe_ddb(db_expr_t blah1,
|
||||
boolean_t blah2,
|
||||
db_expr_t blah3,
|
||||
char *blah4)
|
||||
{
|
||||
char if_xname[IFNAMSIZ];
|
||||
struct ifnet *ifp = NULL;
|
||||
struct bxe_softc *sc;
|
||||
db_expr_t next_arg;
|
||||
int index;
|
||||
int tok;
|
||||
int mod_phys_addr = FALSE;
|
||||
int mod_virt_addr = FALSE;
|
||||
db_addr_t addr;
|
||||
|
||||
tok = db_read_token();
|
||||
if (tok == tSLASH) {
|
||||
tok = db_read_token();
|
||||
if (tok != tIDENT) {
|
||||
db_printf("ERROR: bad modifier\n");
|
||||
bxe_ddb_usage();
|
||||
goto bxe_ddb_done;
|
||||
}
|
||||
if (strcmp(db_tok_string, "h") == 0) {
|
||||
bxe_ddb_usage();
|
||||
goto bxe_ddb_done;
|
||||
} else if (strcmp(db_tok_string, "p") == 0) {
|
||||
mod_phys_addr = TRUE;
|
||||
} else if (strcmp(db_tok_string, "v") == 0) {
|
||||
mod_virt_addr = TRUE;
|
||||
}
|
||||
} else {
|
||||
db_unread_token(tok);
|
||||
}
|
||||
|
||||
if (!db_expression((db_expr_t *)&index)) {
|
||||
db_printf("ERROR: bxe index missing\n");
|
||||
bxe_ddb_usage();
|
||||
goto bxe_ddb_done;
|
||||
}
|
||||
|
||||
snprintf(if_xname, sizeof(if_xname), "bxe%d", index);
|
||||
if ((ifp = ifunit_ref(if_xname)) == NULL)
|
||||
{
|
||||
db_printf("ERROR: Invalid interface %s\n", if_xname);
|
||||
goto bxe_ddb_done;
|
||||
}
|
||||
|
||||
sc = (struct bxe_softc *)ifp->if_softc;
|
||||
db_printf("ifnet=%p (%s)\n", ifp, if_xname);
|
||||
db_printf("softc=%p\n", sc);
|
||||
db_printf(" dev=%p\n", sc->dev);
|
||||
db_printf(" BDF=%d:%d:%d\n",
|
||||
sc->pcie_bus, sc->pcie_device, sc->pcie_func);
|
||||
|
||||
if (mod_phys_addr || mod_virt_addr) {
|
||||
if (!db_expression((db_addr_t *)&addr)) {
|
||||
db_printf("ERROR: Invalid address\n");
|
||||
bxe_ddb_usage();
|
||||
goto bxe_ddb_done;
|
||||
}
|
||||
|
||||
db_printf("addr=%p", addr);
|
||||
}
|
||||
|
||||
bxe_ddb_done:
|
||||
|
||||
db_flush_lex();
|
||||
if (ifp) if_rele(ifp);
|
||||
}
|
||||
|
||||
#endif /* DDB */
|
||||
|
||||
@ -1,364 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
#ifndef _BXE_DEBUG_H
|
||||
#define _BXE_DEBUG_H
|
||||
|
||||
extern uint32_t bxe_debug;
|
||||
|
||||
/*
|
||||
* Debugging macros and definitions.
|
||||
*/
|
||||
|
||||
#define BXE_CP_LOAD 0x00000001
|
||||
#define BXE_CP_SEND 0x00000002
|
||||
#define BXE_CP_RECV 0x00000004
|
||||
#define BXE_CP_INTR 0x00000008
|
||||
#define BXE_CP_UNLOAD 0x00000010
|
||||
#define BXE_CP_RESET 0x00000020
|
||||
#define BXE_CP_IOCTL 0x00000040
|
||||
#define BXE_CP_STATS 0x00000080
|
||||
#define BXE_CP_MISC 0x00000100
|
||||
#define BXE_CP_PHY 0x00000200
|
||||
#define BXE_CP_RAMROD 0x00000400
|
||||
#define BXE_CP_NVRAM 0x00000800
|
||||
#define BXE_CP_REGS 0x00001000
|
||||
#define BXE_CP_TPA 0x00002000
|
||||
#define BXE_CP_ALL 0x00FFFFFF
|
||||
#define BXE_CP_MASK 0x00FFFFFF
|
||||
|
||||
#define BXE_LEVEL_FATAL 0x00000000
|
||||
#define BXE_LEVEL_WARN 0x01000000
|
||||
#define BXE_LEVEL_INFO 0x02000000
|
||||
#define BXE_LEVEL_VERBOSE 0x03000000
|
||||
#define BXE_LEVEL_EXTREME 0x04000000
|
||||
#define BXE_LEVEL_INSANE 0x05000000
|
||||
|
||||
#define BXE_LEVEL_MASK 0xFF000000
|
||||
|
||||
#define BXE_WARN_LOAD (BXE_CP_LOAD | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_LOAD (BXE_CP_LOAD | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_LOAD (BXE_CP_LOAD | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_LOAD (BXE_CP_LOAD | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_LOAD (BXE_CP_LOAD | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_SEND (BXE_CP_SEND | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_SEND (BXE_CP_SEND | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_SEND (BXE_CP_SEND | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_SEND (BXE_CP_SEND | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_SEND (BXE_CP_SEND | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_RECV (BXE_CP_RECV | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_RECV (BXE_CP_RECV | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_RECV (BXE_CP_RECV | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_RECV (BXE_CP_RECV | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_RECV (BXE_CP_RECV | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_INTR (BXE_CP_INTR | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_INTR (BXE_CP_INTR | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_INTR (BXE_CP_INTR | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_INTR (BXE_CP_INTR | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_INTR (BXE_CP_INTR | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_UNLOAD (BXE_CP_UNLOAD | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_RESET (BXE_CP_RESET | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_RESET (BXE_CP_RESET | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_RESET (BXE_CP_RESET | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_RESET (BXE_CP_RESET | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_RESET (BXE_CP_RESET | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_IOCTL (BXE_CP_IOCTL | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_STATS (BXE_CP_STATS | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_STATS (BXE_CP_STATS | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_STATS (BXE_CP_STATS | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_STATS (BXE_CP_STATS | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_STATS (BXE_CP_STATS | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_MISC (BXE_CP_MISC | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_MISC (BXE_CP_MISC | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_MISC (BXE_CP_MISC | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_MISC (BXE_CP_MISC | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_MISC (BXE_CP_MISC | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_PHY (BXE_CP_PHY | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_PHY (BXE_CP_PHY | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_PHY (BXE_CP_PHY | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_PHY (BXE_CP_PHY | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_PHY (BXE_CP_PHY | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_RAMROD (BXE_CP_RAMROD | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_NVRAM (BXE_CP_NVRAM | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_REGS (BXE_CP_REGS | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_REGS (BXE_CP_REGS | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_REGS (BXE_CP_REGS | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_REGS (BXE_CP_REGS | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_REGS (BXE_CP_REGS | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_WARN_TPA (BXE_CP_TPA | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO_TPA (BXE_CP_TPA | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE_TPA (BXE_CP_TPA | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME_TPA (BXE_CP_TPA | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE_TPA (BXE_CP_TPA | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_FATAL (BXE_CP_ALL | BXE_LEVEL_FATAL)
|
||||
#define BXE_WARN (BXE_CP_ALL | BXE_LEVEL_WARN)
|
||||
#define BXE_INFO (BXE_CP_ALL | BXE_LEVEL_INFO)
|
||||
#define BXE_VERBOSE (BXE_CP_ALL | BXE_LEVEL_VERBOSE)
|
||||
#define BXE_EXTREME (BXE_CP_ALL | BXE_LEVEL_EXTREME)
|
||||
#define BXE_INSANE (BXE_CP_ALL | BXE_LEVEL_INSANE)
|
||||
|
||||
#define BXE_CODE_PATH(cp) ((cp & BXE_CP_MASK) & bxe_debug)
|
||||
#define BXE_MSG_LEVEL(lv) ((lv & BXE_LEVEL_MASK) <= (bxe_debug & BXE_LEVEL_MASK))
|
||||
#define BXE_LOG_MSG(m) (BXE_CODE_PATH(m) && BXE_MSG_LEVEL(m))
|
||||
|
||||
|
||||
#ifdef BXE_DEBUG
|
||||
|
||||
/* Print a message based on the logging level and code path. */
|
||||
#define DBPRINT(sc, level, format, args...) \
|
||||
do { \
|
||||
if (BXE_LOG_MSG(level)) { \
|
||||
device_printf(sc->dev, format, ## args); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* Runs a particular command when debugging is enabled. */
|
||||
#define DBRUN(args...) \
|
||||
do { \
|
||||
args; \
|
||||
} while (0)
|
||||
|
||||
/* Runs a particular command based on the logging level. */
|
||||
#define DBRUNLV(level, args...) \
|
||||
if (BXE_MSG_LEVEL(level)) { \
|
||||
args; \
|
||||
}
|
||||
|
||||
/* Runs a particular command based on the code path. */
|
||||
#define DBRUNCP(cp, args...) \
|
||||
if (BXE_CODE_PATH(cp)) { \
|
||||
args; \
|
||||
}
|
||||
|
||||
/* Runs a particular command based on a condition. */
|
||||
#define DBRUNIF(cond, args...) \
|
||||
if (cond) { \
|
||||
args; \
|
||||
}
|
||||
|
||||
/* Runs a particular command based on the logging level and code path. */
|
||||
#define DBRUNMSG(msg, args...) \
|
||||
if (BXE_LOG_MSG(msg)) { \
|
||||
args; \
|
||||
}
|
||||
|
||||
/* Announces function entry. */
|
||||
#define DBENTER(cond) \
|
||||
DBPRINT(sc, (cond), "%s(enter:%d)\n", __FUNCTION__, curcpu)
|
||||
|
||||
/* Announces function exit. */
|
||||
#define DBEXIT(cond) \
|
||||
DBPRINT(sc, (cond), "%s(exit:%d)\n", __FUNCTION__, curcpu)
|
||||
|
||||
/* Needed for random() function which is only used in debugging. */
|
||||
#include <sys/random.h>
|
||||
|
||||
/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
|
||||
#define DB_RANDOMFALSE(defects) (random() > defects)
|
||||
#define DB_OR_RANDOMFALSE(defects) || (random() > defects)
|
||||
#define DB_AND_RANDOMFALSE(defects) && (random() > defects)
|
||||
|
||||
/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
|
||||
#define DB_RANDOMTRUE(defects) (random() < defects)
|
||||
#define DB_OR_RANDOMTRUE(defects) || (random() < defects)
|
||||
#define DB_AND_RANDOMTRUE(defects) && (random() < defects)
|
||||
|
||||
#else
|
||||
|
||||
#define DBPRINT(...)
|
||||
#define DBRUN(...)
|
||||
#define DBRUNLV(...)
|
||||
#define DBRUNCP(...)
|
||||
#define DBRUNIF(...)
|
||||
#define DBRUNMSG(...)
|
||||
#define DBENTER(...)
|
||||
#define DBENTER_UNLOCKED(...)
|
||||
#define DBEXIT(...)
|
||||
#define DBEXIT_UNLOCKED(...)
|
||||
#define DB_RANDOMFALSE(...)
|
||||
#define DB_OR_RANDOMFALSE(...)
|
||||
#define DB_AND_RANDOMFALSE(...)
|
||||
#define DB_RANDOMTRUE(...)
|
||||
#define DB_OR_RANDOMTRUE(...)
|
||||
#define DB_AND_RANDOMTRUE(...)
|
||||
|
||||
#endif /* BXE_DEBUG */
|
||||
|
||||
/* Generic bit decoding for printf("%b"). */
|
||||
#define BXE_DWORD_PRINTFB \
|
||||
"\020" \
|
||||
"\40b31" \
|
||||
"\37b30" \
|
||||
"\36b29" \
|
||||
"\35b28" \
|
||||
"\34b27" \
|
||||
"\33b26" \
|
||||
"\32b25" \
|
||||
"\31b24" \
|
||||
"\30b23" \
|
||||
"\27b22" \
|
||||
"\26b21" \
|
||||
"\25b20" \
|
||||
"\24b19" \
|
||||
"\23b18" \
|
||||
"\22b17" \
|
||||
"\21b16" \
|
||||
"\20b15" \
|
||||
"\17b14" \
|
||||
"\16b13" \
|
||||
"\15b12" \
|
||||
"\14b11" \
|
||||
"\13b10" \
|
||||
"\12b9" \
|
||||
"\11b8" \
|
||||
"\10b7" \
|
||||
"\07b6" \
|
||||
"\06b5" \
|
||||
"\05b4" \
|
||||
"\04b3" \
|
||||
"\03b2" \
|
||||
"\02b1" \
|
||||
"\01b0"
|
||||
|
||||
/* Supported link settings bit decoding for printf("%b"). */
|
||||
#define BXE_SUPPORTED_PRINTFB \
|
||||
"\020" \
|
||||
"\040b31" \
|
||||
"\037b30" \
|
||||
"\036b29" \
|
||||
"\035b28" \
|
||||
"\034b27" \
|
||||
"\033b26" \
|
||||
"\032b25" \
|
||||
"\031b24" \
|
||||
"\030b23" \
|
||||
"\027b22" \
|
||||
"\026b21" \
|
||||
"\025b20" \
|
||||
"\024b19" \
|
||||
"\023b18" \
|
||||
"\022b17" \
|
||||
"\02110000BaseT-Full" \
|
||||
"\0202500BaseX-Full" \
|
||||
"\017b14" \
|
||||
"\016b13" \
|
||||
"\015b12" \
|
||||
"\014Pause" \
|
||||
"\013Asym-Pause" \
|
||||
"\012Autoneg" \
|
||||
"\011Fiber" \
|
||||
"\010TP" \
|
||||
"\0071000BaseT-Full" \
|
||||
"\0061000BaseT-Half" \
|
||||
"\005100BaseTX-Full" \
|
||||
"\004100BaseTX-Half" \
|
||||
"\00310BaseT-Full" \
|
||||
"\00210BaseT-Half" \
|
||||
"\001b0"
|
||||
|
||||
/* Transmit BD TCP flags bit decoding for printf("%b"). */
|
||||
#define BXE_ETH_TX_PARSE_BD_TCP_FLAGS_PRINTFB \
|
||||
"\020" \
|
||||
"\10CWR" \
|
||||
"\07ECE" \
|
||||
"\06URG" \
|
||||
"\05ACK" \
|
||||
"\04PSH" \
|
||||
"\03RST" \
|
||||
"\02SYN" \
|
||||
"\01FIN"
|
||||
|
||||
/* Parsing BD global data bit decoding for printf("%b"). */
|
||||
#define BXE_ETH_TX_PARSE_BD_GLOBAL_DATA_PRINTFB \
|
||||
"\020" \
|
||||
"\10NS" \
|
||||
"\07LLC_SNAP" \
|
||||
"\06PSEUDO_CS_WO_LEN" \
|
||||
"\05CS_ANY"
|
||||
|
||||
/* Transmit BD flags bit decoding for printf("%b"). */
|
||||
#define BXE_ETH_TX_BD_FLAGS_PRINTFB \
|
||||
"\020" \
|
||||
"\10IPv6" \
|
||||
"\07LSO" \
|
||||
"\06HDR_POOL" \
|
||||
"\05START" \
|
||||
"\04END" \
|
||||
"\03TCP_CSUM" \
|
||||
"\02IP_CSUM" \
|
||||
"\01VLAN"
|
||||
|
||||
/* Receive CQE error flags bit decoding for printf("%b"). */
|
||||
#define BXE_ETH_FAST_PATH_RX_CQE_ERROR_FLAGS_PRINTFB \
|
||||
"\020" \
|
||||
"\10RSRVD" \
|
||||
"\07RSRVD" \
|
||||
"\06END_FLAG" \
|
||||
"\05START_FLAG" \
|
||||
"\04L4_BAD_XSUM" \
|
||||
"\03IP_BAD_XSUM" \
|
||||
"\02PHY_DECODE_ERR" \
|
||||
"\01SP"
|
||||
|
||||
#endif /* _BXE_DEBUG_H */
|
||||
14747
sys/dev/bxe/bxe_elink.c
Normal file
14747
sys/dev/bxe/bxe_elink.c
Normal file
File diff suppressed because it is too large
Load Diff
698
sys/dev/bxe/bxe_elink.h
Normal file
698
sys/dev/bxe/bxe_elink.h
Normal file
@ -0,0 +1,698 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#ifndef ELINK_H
|
||||
#define ELINK_H
|
||||
|
||||
#define ELINK_DEBUG
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/***********************************************************/
|
||||
/* CLC Call backs functions */
|
||||
/***********************************************************/
|
||||
/* CLC device structure */
|
||||
struct bxe_softc;
|
||||
|
||||
extern uint32_t elink_cb_reg_read(struct bxe_softc *sc, uint32_t reg_addr);
|
||||
extern void elink_cb_reg_write(struct bxe_softc *sc, uint32_t reg_addr, uint32_t val);
|
||||
/* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/
|
||||
extern void elink_cb_reg_wb_write(struct bxe_softc *sc, uint32_t offset,
|
||||
uint32_t *wb_write, uint16_t len);
|
||||
extern void elink_cb_reg_wb_read(struct bxe_softc *sc, uint32_t offset,
|
||||
uint32_t *wb_write, uint16_t len);
|
||||
|
||||
/* mode - 0( LOW ) /1(HIGH)*/
|
||||
extern uint8_t elink_cb_gpio_write(struct bxe_softc *sc,
|
||||
uint16_t gpio_num,
|
||||
uint8_t mode, uint8_t port);
|
||||
extern uint8_t elink_cb_gpio_mult_write(struct bxe_softc *sc,
|
||||
uint8_t pins,
|
||||
uint8_t mode);
|
||||
|
||||
extern uint32_t elink_cb_gpio_read(struct bxe_softc *sc, uint16_t gpio_num, uint8_t port);
|
||||
extern uint8_t elink_cb_gpio_int_write(struct bxe_softc *sc,
|
||||
uint16_t gpio_num,
|
||||
uint8_t mode, uint8_t port);
|
||||
|
||||
extern uint32_t elink_cb_fw_command(struct bxe_softc *sc, uint32_t command, uint32_t param);
|
||||
|
||||
/* Delay */
|
||||
extern void elink_cb_udelay(struct bxe_softc *sc, uint32_t microsecond);
|
||||
|
||||
/* This function is called every 1024 bytes downloading of phy firmware.
|
||||
Driver can use it to print to screen indication for download progress */
|
||||
extern void elink_cb_download_progress(struct bxe_softc *sc, uint32_t cur, uint32_t total);
|
||||
|
||||
/* Each log type has its own parameters */
|
||||
typedef enum elink_log_id {
|
||||
ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */
|
||||
ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */
|
||||
ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */
|
||||
ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
|
||||
ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */
|
||||
}elink_log_id_t;
|
||||
|
||||
typedef enum elink_status {
|
||||
ELINK_STATUS_OK = 0,
|
||||
ELINK_STATUS_ERROR,
|
||||
ELINK_STATUS_TIMEOUT,
|
||||
ELINK_STATUS_NO_LINK,
|
||||
ELINK_STATUS_INVALID_IMAGE,
|
||||
ELINK_OP_NOT_SUPPORTED = 122
|
||||
} elink_status_t;
|
||||
extern void elink_cb_event_log(struct bxe_softc *sc, const elink_log_id_t log_id, ...);
|
||||
extern void elink_cb_load_warpcore_microcode(void);
|
||||
|
||||
extern uint8_t elink_cb_path_id(struct bxe_softc *sc);
|
||||
|
||||
extern void elink_cb_notify_link_changed(struct bxe_softc *sc);
|
||||
|
||||
#define ELINK_EVENT_LOG_LEVEL_ERROR 1
|
||||
#define ELINK_EVENT_LOG_LEVEL_WARNING 2
|
||||
#define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1
|
||||
#define ELINK_EVENT_ID_SFP_POWER_FAULT 2
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
|
||||
/* Debug prints */
|
||||
#ifdef ELINK_DEBUG
|
||||
|
||||
extern void elink_cb_dbg(struct bxe_softc *sc, char *fmt);
|
||||
extern void elink_cb_dbg1(struct bxe_softc *sc, char *fmt, uint32_t arg1);
|
||||
extern void elink_cb_dbg2(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2);
|
||||
extern void elink_cb_dbg3(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2,
|
||||
uint32_t arg3);
|
||||
|
||||
#define ELINK_DEBUG_P0(sc, fmt) elink_cb_dbg(sc, fmt)
|
||||
#define ELINK_DEBUG_P1(sc, fmt, arg1) elink_cb_dbg1(sc, fmt, arg1)
|
||||
#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) elink_cb_dbg2(sc, fmt, arg1, arg2)
|
||||
#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \
|
||||
elink_cb_dbg3(sc, fmt, arg1, arg2, arg3)
|
||||
#else
|
||||
#define ELINK_DEBUG_P0(sc, fmt)
|
||||
#define ELINK_DEBUG_P1(sc, fmt, arg1)
|
||||
#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2)
|
||||
#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3)
|
||||
#endif
|
||||
|
||||
/***********************************************************/
|
||||
/* Defines */
|
||||
/***********************************************************/
|
||||
#define ELINK_DEFAULT_PHY_DEV_ADDR 3
|
||||
#define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5
|
||||
|
||||
|
||||
#define DUPLEX_FULL 1
|
||||
#define DUPLEX_HALF 2
|
||||
|
||||
#define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
|
||||
#define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
|
||||
#define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
|
||||
#define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
|
||||
#define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
|
||||
|
||||
#define ELINK_NET_SERDES_IF_XFI 1
|
||||
#define ELINK_NET_SERDES_IF_SFI 2
|
||||
#define ELINK_NET_SERDES_IF_KR 3
|
||||
#define ELINK_NET_SERDES_IF_DXGXS 4
|
||||
|
||||
#define ELINK_SPEED_AUTO_NEG 0
|
||||
#define ELINK_SPEED_10 10
|
||||
#define ELINK_SPEED_100 100
|
||||
#define ELINK_SPEED_1000 1000
|
||||
#define ELINK_SPEED_2500 2500
|
||||
#define ELINK_SPEED_10000 10000
|
||||
#define ELINK_SPEED_20000 20000
|
||||
|
||||
#define ELINK_I2C_DEV_ADDR_A0 0xa0
|
||||
#define ELINK_I2C_DEV_ADDR_A2 0xa2
|
||||
|
||||
#define ELINK_SFP_EEPROM_PAGE_SIZE 16
|
||||
#define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14
|
||||
#define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16
|
||||
#define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25
|
||||
#define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3
|
||||
#define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28
|
||||
#define ELINK_SFP_EEPROM_PART_NO_SIZE 16
|
||||
#define ELINK_SFP_EEPROM_REVISION_ADDR 0x38
|
||||
#define ELINK_SFP_EEPROM_REVISION_SIZE 4
|
||||
#define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44
|
||||
#define ELINK_SFP_EEPROM_SERIAL_SIZE 16
|
||||
#define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
|
||||
#define ELINK_SFP_EEPROM_DATE_SIZE 6
|
||||
#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
|
||||
#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1
|
||||
#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
|
||||
#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
|
||||
#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1
|
||||
|
||||
#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
|
||||
#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
|
||||
|
||||
#define ELINK_PWR_FLT_ERR_MSG_LEN 250
|
||||
|
||||
#define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
|
||||
((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
|
||||
#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
|
||||
(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
|
||||
PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
|
||||
#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
|
||||
((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
|
||||
|
||||
/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
|
||||
#define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
|
||||
/* Single Media board contains single external phy */
|
||||
#define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2)
|
||||
/* Dual Media board contains two external phy with different media */
|
||||
#define ELINK_DUAL_MEDIA(params) (params->num_phys == 3)
|
||||
|
||||
#define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF
|
||||
#define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00
|
||||
#define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
|
||||
#define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16
|
||||
#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
|
||||
ELINK_FW_PARAM_PHY_ADDR_MASK)
|
||||
#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
|
||||
ELINK_FW_PARAM_PHY_TYPE_MASK)
|
||||
#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
|
||||
ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \
|
||||
ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
|
||||
#define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
|
||||
(phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
|
||||
|
||||
|
||||
#define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
|
||||
#define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250
|
||||
|
||||
#define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
|
||||
|
||||
#define ELINK_BMAC_CONTROL_RX_ENABLE 2
|
||||
/***********************************************************/
|
||||
/* Structs */
|
||||
/***********************************************************/
|
||||
#define ELINK_INT_PHY 0
|
||||
#define ELINK_EXT_PHY1 1
|
||||
#define ELINK_EXT_PHY2 2
|
||||
#define ELINK_MAX_PHYS 3
|
||||
|
||||
/* Same configuration is shared between the XGXS and the first external phy */
|
||||
#define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
|
||||
#define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
|
||||
0 : (_phy_idx - 1))
|
||||
/***********************************************************/
|
||||
/* elink_phy struct */
|
||||
/* Defines the required arguments and function per phy */
|
||||
/***********************************************************/
|
||||
struct elink_vars;
|
||||
struct elink_params;
|
||||
struct elink_phy;
|
||||
|
||||
typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,
|
||||
struct elink_vars *vars);
|
||||
typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,
|
||||
struct elink_vars *vars);
|
||||
typedef void (*link_reset_t)(struct elink_phy *phy,
|
||||
struct elink_params *params);
|
||||
typedef void (*config_loopback_t)(struct elink_phy *phy,
|
||||
struct elink_params *params);
|
||||
typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
|
||||
typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
|
||||
typedef void (*set_link_led_t)(struct elink_phy *phy,
|
||||
struct elink_params *params, uint8_t mode);
|
||||
typedef void (*phy_specific_func_t)(struct elink_phy *phy,
|
||||
struct elink_params *params, uint32_t action);
|
||||
struct elink_reg_set {
|
||||
uint8_t devad;
|
||||
uint16_t reg;
|
||||
uint16_t val;
|
||||
};
|
||||
|
||||
struct elink_phy {
|
||||
uint32_t type;
|
||||
|
||||
/* Loaded during init */
|
||||
uint8_t addr;
|
||||
uint8_t def_md_devad;
|
||||
uint16_t flags;
|
||||
/* No Over-Current detection */
|
||||
#define ELINK_FLAGS_NOC (1<<1)
|
||||
/* Fan failure detection required */
|
||||
#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2)
|
||||
/* Initialize first the XGXS and only then the phy itself */
|
||||
#define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3)
|
||||
#define ELINK_FLAGS_WC_DUAL_MODE (1<<4)
|
||||
#define ELINK_FLAGS_4_PORT_MODE (1<<5)
|
||||
#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6)
|
||||
#define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7)
|
||||
#define ELINK_FLAGS_MDC_MDIO_WA (1<<8)
|
||||
#define ELINK_FLAGS_DUMMY_READ (1<<9)
|
||||
#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10)
|
||||
#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11)
|
||||
#define ELINK_FLAGS_TX_ERROR_CHECK (1<<12)
|
||||
#define ELINK_FLAGS_EEE (1<<13)
|
||||
#define ELINK_FLAGS_TEMPERATURE (1<<14)
|
||||
#define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15)
|
||||
|
||||
/* preemphasis values for the rx side */
|
||||
uint16_t rx_preemphasis[4];
|
||||
|
||||
/* preemphasis values for the tx side */
|
||||
uint16_t tx_preemphasis[4];
|
||||
|
||||
/* EMAC address for access MDIO */
|
||||
uint32_t mdio_ctrl;
|
||||
|
||||
uint32_t supported;
|
||||
#define ELINK_SUPPORTED_10baseT_Half (1<<0)
|
||||
#define ELINK_SUPPORTED_10baseT_Full (1<<1)
|
||||
#define ELINK_SUPPORTED_100baseT_Half (1<<2)
|
||||
#define ELINK_SUPPORTED_100baseT_Full (1<<3)
|
||||
#define ELINK_SUPPORTED_1000baseT_Full (1<<4)
|
||||
#define ELINK_SUPPORTED_2500baseX_Full (1<<5)
|
||||
#define ELINK_SUPPORTED_10000baseT_Full (1<<6)
|
||||
#define ELINK_SUPPORTED_TP (1<<7)
|
||||
#define ELINK_SUPPORTED_FIBRE (1<<8)
|
||||
#define ELINK_SUPPORTED_Autoneg (1<<9)
|
||||
#define ELINK_SUPPORTED_Pause (1<<10)
|
||||
#define ELINK_SUPPORTED_Asym_Pause (1<<11)
|
||||
#define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21)
|
||||
#define ELINK_SUPPORTED_20000baseKR2_Full (1<<22)
|
||||
|
||||
uint32_t media_type;
|
||||
#define ELINK_ETH_PHY_UNSPECIFIED 0x0
|
||||
#define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1
|
||||
#define ELINK_ETH_PHY_XFP_FIBER 0x2
|
||||
#define ELINK_ETH_PHY_DA_TWINAX 0x3
|
||||
#define ELINK_ETH_PHY_BASE_T 0x4
|
||||
#define ELINK_ETH_PHY_SFP_1G_FIBER 0x5
|
||||
#define ELINK_ETH_PHY_KR 0xf0
|
||||
#define ELINK_ETH_PHY_CX4 0xf1
|
||||
#define ELINK_ETH_PHY_NOT_PRESENT 0xff
|
||||
|
||||
/* The address in which version is located*/
|
||||
uint32_t ver_addr;
|
||||
|
||||
uint16_t req_flow_ctrl;
|
||||
|
||||
uint16_t req_line_speed;
|
||||
|
||||
uint32_t speed_cap_mask;
|
||||
|
||||
uint16_t req_duplex;
|
||||
uint16_t rsrv;
|
||||
/* Called per phy/port init, and it configures LASI, speed, autoneg,
|
||||
duplex, flow control negotiation, etc. */
|
||||
config_init_t config_init;
|
||||
|
||||
/* Called due to interrupt. It determines the link, speed */
|
||||
read_status_t read_status;
|
||||
|
||||
/* Called when driver is unloading. Should reset the phy */
|
||||
link_reset_t link_reset;
|
||||
|
||||
/* Set the loopback configuration for the phy */
|
||||
config_loopback_t config_loopback;
|
||||
|
||||
/* Format the given raw number into str up to len */
|
||||
format_fw_ver_t format_fw_ver;
|
||||
|
||||
/* Reset the phy (both ports) */
|
||||
hw_reset_t hw_reset;
|
||||
|
||||
/* Set link led mode (on/off/oper)*/
|
||||
set_link_led_t set_link_led;
|
||||
|
||||
/* PHY Specific tasks */
|
||||
phy_specific_func_t phy_specific_func;
|
||||
#define ELINK_DISABLE_TX 1
|
||||
#define ELINK_ENABLE_TX 2
|
||||
#define ELINK_PHY_INIT 3
|
||||
};
|
||||
|
||||
/* Inputs parameters to the CLC */
|
||||
struct elink_params {
|
||||
|
||||
uint8_t port;
|
||||
|
||||
/* Default / User Configuration */
|
||||
uint8_t loopback_mode;
|
||||
#define ELINK_LOOPBACK_NONE 0
|
||||
#define ELINK_LOOPBACK_EMAC 1
|
||||
#define ELINK_LOOPBACK_BMAC 2
|
||||
#define ELINK_LOOPBACK_XGXS 3
|
||||
#define ELINK_LOOPBACK_EXT_PHY 4
|
||||
#define ELINK_LOOPBACK_EXT 5
|
||||
#define ELINK_LOOPBACK_UMAC 6
|
||||
#define ELINK_LOOPBACK_XMAC 7
|
||||
|
||||
/* Device parameters */
|
||||
uint8_t mac_addr[6];
|
||||
|
||||
uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE];
|
||||
uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];
|
||||
|
||||
uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
|
||||
|
||||
/* shmem parameters */
|
||||
uint32_t shmem_base;
|
||||
uint32_t shmem2_base;
|
||||
uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
|
||||
uint32_t switch_cfg;
|
||||
#define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
|
||||
#define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
|
||||
#define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
|
||||
|
||||
uint32_t lane_config;
|
||||
|
||||
/* Phy register parameter */
|
||||
uint32_t chip_id;
|
||||
|
||||
/* features */
|
||||
uint32_t feature_config_flags;
|
||||
#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
|
||||
#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1)
|
||||
#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
|
||||
#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
|
||||
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4)
|
||||
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5)
|
||||
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6)
|
||||
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7)
|
||||
#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
|
||||
#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
|
||||
#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
|
||||
#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
|
||||
#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12)
|
||||
#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13)
|
||||
#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
|
||||
|
||||
/* Will be populated during common init */
|
||||
struct elink_phy phy[ELINK_MAX_PHYS];
|
||||
|
||||
/* Will be populated during common init */
|
||||
uint8_t num_phys;
|
||||
|
||||
uint8_t rsrv;
|
||||
|
||||
/* Used to configure the EEE Tx LPI timer, has several modes of
|
||||
* operation, according to bits 29:28 -
|
||||
* 2'b00: Timer will be configured by nvram, output will be the value
|
||||
* from nvram.
|
||||
* 2'b01: Timer will be configured by nvram, output will be in
|
||||
* microseconds.
|
||||
* 2'b10: bits 1:0 contain an nvram value which will be used instead
|
||||
* of the one located in the nvram. Output will be that value.
|
||||
* 2'b11: bits 19:0 contain the idle timer in microseconds; output
|
||||
* will be in microseconds.
|
||||
* Bits 31:30 should be 2'b11 in order for EEE to be enabled.
|
||||
*/
|
||||
uint32_t eee_mode;
|
||||
#define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
|
||||
#define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
|
||||
#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
|
||||
#define ELINK_EEE_MODE_NVRAM_MASK (0x3)
|
||||
#define ELINK_EEE_MODE_TIMER_MASK (0xfffff)
|
||||
#define ELINK_EEE_MODE_OUTPUT_TIME (1<<28)
|
||||
#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29)
|
||||
#define ELINK_EEE_MODE_ENABLE_LPI (1<<30)
|
||||
#define ELINK_EEE_MODE_ADV_LPI (1<<31)
|
||||
|
||||
uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
|
||||
uint32_t multi_phy_config;
|
||||
|
||||
/* Device pointer passed to all callback functions */
|
||||
struct bxe_softc *sc;
|
||||
uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
|
||||
req_flow_ctrl is set to AUTO */
|
||||
uint16_t link_flags;
|
||||
#define ELINK_LINK_FLAGS_INT_DISABLED (1<<0)
|
||||
#define ELINK_PHY_INITIALIZED (1<<1)
|
||||
uint32_t lfa_base;
|
||||
};
|
||||
|
||||
/* Output parameters */
|
||||
struct elink_vars {
|
||||
uint8_t phy_flags;
|
||||
#define PHY_XGXS_FLAG (1<<0)
|
||||
#define PHY_SGMII_FLAG (1<<1)
|
||||
#define PHY_PHYSICAL_LINK_FLAG (1<<2)
|
||||
#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
|
||||
#define PHY_OVER_CURRENT_FLAG (1<<4)
|
||||
#define PHY_SFP_TX_FAULT_FLAG (1<<5)
|
||||
|
||||
uint8_t mac_type;
|
||||
#define ELINK_MAC_TYPE_NONE 0
|
||||
#define ELINK_MAC_TYPE_EMAC 1
|
||||
#define ELINK_MAC_TYPE_BMAC 2
|
||||
#define ELINK_MAC_TYPE_UMAC 3
|
||||
#define ELINK_MAC_TYPE_XMAC 4
|
||||
|
||||
uint8_t phy_link_up; /* internal phy link indication */
|
||||
uint8_t link_up;
|
||||
|
||||
uint16_t line_speed;
|
||||
uint16_t duplex;
|
||||
|
||||
uint16_t flow_ctrl;
|
||||
uint16_t ieee_fc;
|
||||
|
||||
/* The same definitions as the shmem parameter */
|
||||
uint32_t link_status;
|
||||
uint32_t eee_status;
|
||||
uint8_t fault_detected;
|
||||
uint8_t check_kr2_recovery_cnt;
|
||||
#define ELINK_CHECK_KR2_RECOVERY_CNT 5
|
||||
uint16_t periodic_flags;
|
||||
#define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001
|
||||
|
||||
uint32_t aeu_int_mask;
|
||||
uint8_t rx_tx_asic_rst;
|
||||
uint8_t turn_to_run_wc_rt;
|
||||
uint16_t rsrv2;
|
||||
/* The same definitions as the shmem2 parameter */
|
||||
uint32_t link_attr_sync;
|
||||
};
|
||||
|
||||
/***********************************************************/
|
||||
/* Functions */
|
||||
/***********************************************************/
|
||||
elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
|
||||
|
||||
/* Reset the link. Should be called when driver or interface goes down
|
||||
Before calling phy firmware upgrade, the reset_ext_phy should be set
|
||||
to 0 */
|
||||
elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
|
||||
uint8_t reset_ext_phy);
|
||||
elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
|
||||
/* elink_link_update should be called upon link interrupt */
|
||||
elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
|
||||
|
||||
/* use the following phy functions to read/write from external_phy
|
||||
In order to use it to read/write internal phy registers, use
|
||||
ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
|
||||
the register */
|
||||
elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
|
||||
uint8_t devad, uint16_t reg, uint16_t *ret_val);
|
||||
|
||||
elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
|
||||
uint8_t devad, uint16_t reg, uint16_t val);
|
||||
|
||||
/* Reads the link_status from the shmem,
|
||||
and update the link vars accordingly */
|
||||
void elink_link_status_update(struct elink_params *input,
|
||||
struct elink_vars *output);
|
||||
/* returns string representing the fw_version of the external phy */
|
||||
elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
|
||||
uint16_t len);
|
||||
|
||||
/* Set/Unset the led
|
||||
Basically, the CLC takes care of the led for the link, but in case one needs
|
||||
to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
|
||||
blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
|
||||
elink_status_t elink_set_led(struct elink_params *params,
|
||||
struct elink_vars *vars, uint8_t mode, uint32_t speed);
|
||||
#define ELINK_LED_MODE_OFF 0
|
||||
#define ELINK_LED_MODE_ON 1
|
||||
#define ELINK_LED_MODE_OPER 2
|
||||
#define ELINK_LED_MODE_FRONT_PANEL_OFF 3
|
||||
|
||||
/* elink_handle_module_detect_int should be called upon module detection
|
||||
interrupt */
|
||||
void elink_handle_module_detect_int(struct elink_params *params);
|
||||
|
||||
/* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,
|
||||
otherwise link is down*/
|
||||
elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
|
||||
uint8_t is_serdes);
|
||||
|
||||
|
||||
/* One-time initialization for external phy after power up */
|
||||
elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
|
||||
uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
|
||||
|
||||
/* Reset the external PHY using GPIO */
|
||||
void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port);
|
||||
|
||||
/* Reset the external of SFX7101 */
|
||||
void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy);
|
||||
|
||||
/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
|
||||
elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
|
||||
struct elink_params *params, uint8_t dev_addr,
|
||||
uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf);
|
||||
|
||||
void elink_hw_reset_phy(struct elink_params *params);
|
||||
|
||||
/* Check swap bit and adjust PHY order */
|
||||
uint32_t elink_phy_selection(struct elink_params *params);
|
||||
|
||||
/* Probe the phys on board, and populate them in "params" */
|
||||
elink_status_t elink_phy_probe(struct elink_params *params);
|
||||
|
||||
/* Checks if fan failure detection is required on one of the phys on board */
|
||||
uint8_t elink_fan_failure_det_req(struct bxe_softc *sc, uint32_t shmem_base,
|
||||
uint32_t shmem2_base, uint8_t port);
|
||||
|
||||
/* Open / close the gate between the NIG and the BRB */
|
||||
void elink_set_rx_filter(struct elink_params *params, uint8_t en);
|
||||
|
||||
/* DCBX structs */
|
||||
|
||||
/* Number of maximum COS per chip */
|
||||
#define ELINK_DCBX_E2E3_MAX_NUM_COS (2)
|
||||
#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
|
||||
#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
|
||||
#define ELINK_DCBX_E3B0_MAX_NUM_COS ( \
|
||||
ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
|
||||
ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))
|
||||
|
||||
#define ELINK_DCBX_MAX_NUM_COS ( \
|
||||
ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
|
||||
ELINK_DCBX_E2E3_MAX_NUM_COS))
|
||||
|
||||
/* PFC port configuration params */
|
||||
struct elink_nig_brb_pfc_port_params {
|
||||
/* NIG */
|
||||
uint32_t pause_enable;
|
||||
uint32_t llfc_out_en;
|
||||
uint32_t llfc_enable;
|
||||
uint32_t pkt_priority_to_cos;
|
||||
uint8_t num_of_rx_cos_priority_mask;
|
||||
uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
|
||||
uint32_t llfc_high_priority_classes;
|
||||
uint32_t llfc_low_priority_classes;
|
||||
};
|
||||
|
||||
|
||||
/* ETS port configuration params */
|
||||
struct elink_ets_bw_params {
|
||||
uint8_t bw;
|
||||
};
|
||||
|
||||
struct elink_ets_sp_params {
|
||||
/**
|
||||
* valid values are 0 - 5. 0 is highest strict priority.
|
||||
* There can't be two COS's with the same pri.
|
||||
*/
|
||||
uint8_t pri;
|
||||
};
|
||||
|
||||
enum elink_cos_state {
|
||||
elink_cos_state_strict = 0,
|
||||
elink_cos_state_bw = 1,
|
||||
};
|
||||
|
||||
struct elink_ets_cos_params {
|
||||
enum elink_cos_state state ;
|
||||
union {
|
||||
struct elink_ets_bw_params bw_params;
|
||||
struct elink_ets_sp_params sp_params;
|
||||
} params;
|
||||
};
|
||||
|
||||
struct elink_ets_params {
|
||||
uint8_t num_of_cos; /* Number of valid COS entries*/
|
||||
struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
|
||||
};
|
||||
|
||||
/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
|
||||
* when link is already up
|
||||
*/
|
||||
elink_status_t elink_update_pfc(struct elink_params *params,
|
||||
struct elink_vars *vars,
|
||||
struct elink_nig_brb_pfc_port_params *pfc_params);
|
||||
|
||||
|
||||
/* Used to configure the ETS to disable */
|
||||
elink_status_t elink_ets_disabled(struct elink_params *params,
|
||||
struct elink_vars *vars);
|
||||
|
||||
/* Used to configure the ETS to BW limited */
|
||||
void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
|
||||
const uint32_t cos1_bw);
|
||||
|
||||
/* Used to configure the ETS to strict */
|
||||
elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos);
|
||||
|
||||
|
||||
/* Configure the COS to ETS according to BW and SP settings.*/
|
||||
elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
|
||||
const struct elink_vars *vars,
|
||||
struct elink_ets_params *ets_params);
|
||||
/* Read pfc statistic*/
|
||||
void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
|
||||
uint32_t pfc_frames_sent[2],
|
||||
uint32_t pfc_frames_received[2]);
|
||||
void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
|
||||
uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
|
||||
uint8_t port);
|
||||
|
||||
elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
|
||||
struct elink_params *params);
|
||||
|
||||
void elink_period_func(struct elink_params *params, struct elink_vars *vars);
|
||||
|
||||
elink_status_t elink_check_half_open_conn(struct elink_params *params,
|
||||
struct elink_vars *vars, uint8_t notify);
|
||||
|
||||
void elink_enable_pmd_tx(struct elink_params *params);
|
||||
|
||||
|
||||
|
||||
#endif /* ELINK_H */
|
||||
|
||||
@ -1,624 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
#ifndef _BXE_FW_DEFS_H
|
||||
#define _BXE_FW_DEFS_H
|
||||
|
||||
#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x7000 : 0x1000)
|
||||
#define CSTORM_ASSERT_LIST_OFFSET(idx) \
|
||||
(IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
|
||||
#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
|
||||
(IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
|
||||
((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
|
||||
0x40) + (index * 0x4)))
|
||||
#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
|
||||
(IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
|
||||
((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
|
||||
0x80) + (index * 0x4)))
|
||||
#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
|
||||
((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
|
||||
#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
|
||||
((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
|
||||
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
|
||||
((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
|
||||
#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
|
||||
((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
|
||||
#define CSTORM_FUNCTION_MODE_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
|
||||
#define CSTORM_HC_BTR_C_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
|
||||
#define CSTORM_HC_BTR_U_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
|
||||
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
|
||||
(function * 0x8)))
|
||||
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
|
||||
(function * 0x8)))
|
||||
#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
|
||||
(IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
|
||||
(0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
|
||||
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
|
||||
(IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
|
||||
(0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
|
||||
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
|
||||
(IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
|
||||
(0x241c + (function * 0xc0) + (eqIdx * 0x18)))
|
||||
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
|
||||
(IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
|
||||
(0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
|
||||
#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
|
||||
(IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
|
||||
(0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
|
||||
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
|
||||
(IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
|
||||
(0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
|
||||
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
|
||||
(IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
|
||||
(0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
|
||||
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
|
||||
(function * 0x8)))
|
||||
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
|
||||
(function * 0x8)))
|
||||
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
|
||||
(function * 0x8)))
|
||||
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
|
||||
(function * 0x8)))
|
||||
#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
|
||||
(IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
|
||||
(index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
|
||||
(index * 0x4)))
|
||||
#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
|
||||
(IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
|
||||
(index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
|
||||
(index * 0x4)))
|
||||
#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
|
||||
(IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
|
||||
(index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
|
||||
(index * 0x4)))
|
||||
#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
|
||||
(IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
|
||||
(index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
|
||||
(index * 0x4)))
|
||||
#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
|
||||
(IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
|
||||
(0x3040 + (port * 0x280) + (cpu_id * 0x28)))
|
||||
#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
|
||||
(IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
|
||||
(0x4000 + (port * 0x800) + (cpu_id * 0x80)))
|
||||
#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
|
||||
(IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
|
||||
(0x3048 + (port * 0x280) + (cpu_id * 0x28)))
|
||||
#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
|
||||
(IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
|
||||
(0x4008 + (port * 0x800) + (cpu_id * 0x80)))
|
||||
#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
|
||||
#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
|
||||
#define CSTORM_STATS_FLAGS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
|
||||
#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0xa000 : 0x1000)
|
||||
#define TSTORM_ASSERT_LIST_OFFSET(idx) \
|
||||
(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
|
||||
#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
|
||||
(IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
|
||||
: (0x9c0 + (port * 0x120) + (client_id * 0x10)))
|
||||
#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
|
||||
#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
|
||||
#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
|
||||
(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
|
||||
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
|
||||
0x28) + (index * 0x4)))
|
||||
#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
|
||||
((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
|
||||
#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
|
||||
((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
|
||||
#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
|
||||
(function * 0x40)))
|
||||
#define TSTORM_FUNCTION_MODE_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
|
||||
#define TSTORM_HC_BTR_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
|
||||
#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
|
||||
(function * 0x80)))
|
||||
#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
|
||||
#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
|
||||
(IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
|
||||
: (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
|
||||
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
|
||||
(function * 0x40)))
|
||||
#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
|
||||
(IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
|
||||
0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
|
||||
#define TSTORM_STATS_FLAGS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
|
||||
(function * 0x8)))
|
||||
#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
|
||||
#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
|
||||
#define USTORM_ASSERT_LIST_INDEX_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x8000 : 0x1000)
|
||||
#define USTORM_ASSERT_LIST_OFFSET(idx) \
|
||||
(IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
|
||||
#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
|
||||
(IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
|
||||
(0x4010 + (port * 0x360) + (clientId * 0x30)))
|
||||
|
||||
#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
|
||||
(IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
|
||||
(0x4028 + (port * 0x360) + (clientId * 0x30)))
|
||||
|
||||
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
|
||||
#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
|
||||
(IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
|
||||
0xffffffff)
|
||||
#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_FUNCTION_MODE_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
|
||||
#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
|
||||
(IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
|
||||
(0x4018 + (port * 0x360) + (clientId * 0x30)))
|
||||
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
|
||||
(IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
|
||||
0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
|
||||
#define USTORM_RX_PRODS_OFFSET(port, client_id) \
|
||||
(IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
|
||||
: (0x4000 + (port * 0x360) + (client_id * 0x30)))
|
||||
#define USTORM_STATS_FLAGS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
|
||||
(function * 0x8)))
|
||||
#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
|
||||
#define USTORM_TPA_BTR_SIZE 0x1
|
||||
#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x9000 : 0x1000)
|
||||
#define XSTORM_ASSERT_LIST_OFFSET(idx) \
|
||||
(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
|
||||
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
|
||||
#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
|
||||
(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
|
||||
((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
|
||||
0x28) + (index * 0x4)))
|
||||
#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
|
||||
((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
|
||||
#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
|
||||
((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
|
||||
#define XSTORM_E1HOV_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
|
||||
#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
|
||||
(function * 0x90)))
|
||||
#define XSTORM_FUNCTION_MODE_OFFSET \
|
||||
(IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
|
||||
#define XSTORM_HC_BTR_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
|
||||
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
|
||||
(IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
|
||||
0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
|
||||
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
|
||||
(function * 0x90)))
|
||||
#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
|
||||
(function * 0x10)))
|
||||
#define XSTORM_SPQ_PROD_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
|
||||
(function * 0x10)))
|
||||
#define XSTORM_STATS_FLAGS_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
|
||||
(function * 0x8)))
|
||||
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
|
||||
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
|
||||
(IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
|
||||
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
|
||||
(IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
|
||||
* 0x4)) : (0x1978 + (function * 0x4)))
|
||||
#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
|
||||
|
||||
/**
|
||||
* This file defines HSI constants for the ETH flow
|
||||
*/
|
||||
#ifdef _EVEREST_MICROCODE
|
||||
#include "microcode_constants.h"
|
||||
#include "eth_rx_bd.h"
|
||||
#include "eth_tx_bd.h"
|
||||
#include "eth_rx_cqe.h"
|
||||
#include "eth_rx_sge.h"
|
||||
#include "eth_rx_cqe_next_page.h"
|
||||
#endif
|
||||
|
||||
/* RSS hash types */
|
||||
#define DEFAULT_HASH_TYPE 0
|
||||
#define IPV4_HASH_TYPE 1
|
||||
#define TCP_IPV4_HASH_TYPE 2
|
||||
#define IPV6_HASH_TYPE 3
|
||||
#define TCP_IPV6_HASH_TYPE 4
|
||||
#define VLAN_PRI_HASH_TYPE 5
|
||||
#define E1HOV_PRI_HASH_TYPE 6
|
||||
#define DSCP_HASH_TYPE 7
|
||||
|
||||
|
||||
/* Ethernet Ring parameters */
|
||||
#define X_ETH_LOCAL_RING_SIZE 13
|
||||
#define FIRST_BD_IN_PKT 0
|
||||
#define PARSE_BD_INDEX 1
|
||||
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
|
||||
#define U_ETH_NUM_OF_SGES_TO_FETCH 8
|
||||
#define U_ETH_MAX_SGES_FOR_PACKET 3
|
||||
|
||||
/* Rx ring params */
|
||||
#define U_ETH_LOCAL_BD_RING_SIZE 8
|
||||
#define U_ETH_LOCAL_SGE_RING_SIZE 10
|
||||
#define U_ETH_SGL_SIZE 8
|
||||
|
||||
|
||||
#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
|
||||
(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
|
||||
|
||||
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
|
||||
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
|
||||
#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
|
||||
|
||||
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
|
||||
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
|
||||
#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
|
||||
|
||||
#define U_ETH_UNDEFINED_Q 0xFF
|
||||
|
||||
/* values of command IDs in the ramrod message */
|
||||
#define RAMROD_CMD_ID_ETH_PORT_SETUP 80
|
||||
#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
|
||||
#define RAMROD_CMD_ID_ETH_STAT_QUERY 90
|
||||
#define RAMROD_CMD_ID_ETH_UPDATE 100
|
||||
#define RAMROD_CMD_ID_ETH_HALT 105
|
||||
#define RAMROD_CMD_ID_ETH_SET_MAC 110
|
||||
#define RAMROD_CMD_ID_ETH_CFC_DEL 115
|
||||
#define RAMROD_CMD_ID_ETH_PORT_DEL 120
|
||||
#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
|
||||
|
||||
|
||||
/* command values for set mac command */
|
||||
#define T_ETH_MAC_COMMAND_SET 0
|
||||
#define T_ETH_MAC_COMMAND_INVALIDATE 1
|
||||
|
||||
#define T_ETH_INDIRECTION_TABLE_SIZE 128
|
||||
|
||||
/*The CRC32 seed, that is used for the hash(reduction) multicast address */
|
||||
#define T_ETH_CRC32_HASH_SEED 0x00000000
|
||||
|
||||
/* Maximal L2 clients supported */
|
||||
#define ETH_MAX_RX_CLIENTS_E1 18
|
||||
#define ETH_MAX_RX_CLIENTS_E1H 26
|
||||
|
||||
/* Maximal aggregation queues supported */
|
||||
#define ETH_MAX_AGGREGATION_QUEUES_E1 32
|
||||
#define ETH_MAX_AGGREGATION_QUEUES_E1H 64
|
||||
|
||||
/* ETH RSS modes */
|
||||
#define ETH_RSS_MODE_DISABLED 0
|
||||
#define ETH_RSS_MODE_REGULAR 1
|
||||
#define ETH_RSS_MODE_VLAN_PRI 2
|
||||
#define ETH_RSS_MODE_E1HOV_PRI 3
|
||||
#define ETH_RSS_MODE_IP_DSCP 4
|
||||
|
||||
|
||||
/**
|
||||
* This file defines HSI constants common to all microcode flows
|
||||
*/
|
||||
|
||||
/* Connection types */
|
||||
#define ETH_CONNECTION_TYPE 0
|
||||
#define TOE_CONNECTION_TYPE 1
|
||||
#define RDMA_CONNECTION_TYPE 2
|
||||
#define ISCSI_CONNECTION_TYPE 3
|
||||
#define FCOE_CONNECTION_TYPE 4
|
||||
#define RESERVED_CONNECTION_TYPE_0 5
|
||||
#define RESERVED_CONNECTION_TYPE_1 6
|
||||
#define RESERVED_CONNECTION_TYPE_2 7
|
||||
|
||||
|
||||
#define PROTOCOL_STATE_BIT_OFFSET 6
|
||||
|
||||
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
|
||||
#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
|
||||
#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
|
||||
|
||||
/* microcode fixed page page size 4K (chains and ring segments) */
|
||||
#define MC_PAGE_SIZE 4096
|
||||
|
||||
|
||||
/* Host coalescing constants */
|
||||
#define HC_IGU_BC_MODE 0
|
||||
#define HC_IGU_NBC_MODE 1
|
||||
|
||||
#define HC_REGULAR_SEGMENT 0
|
||||
#define HC_DEFAULT_SEGMENT 1
|
||||
|
||||
/* index numbers */
|
||||
#define HC_USTORM_DEF_SB_NUM_INDICES 8
|
||||
#define HC_CSTORM_DEF_SB_NUM_INDICES 8
|
||||
#define HC_XSTORM_DEF_SB_NUM_INDICES 4
|
||||
#define HC_TSTORM_DEF_SB_NUM_INDICES 4
|
||||
#define HC_USTORM_SB_NUM_INDICES 4
|
||||
#define HC_CSTORM_SB_NUM_INDICES 4
|
||||
|
||||
/* index values - which counter to update */
|
||||
|
||||
#define HC_INDEX_U_TOE_RX_CQ_CONS 0
|
||||
#define HC_INDEX_U_ETH_RX_CQ_CONS 1
|
||||
#define HC_INDEX_U_ETH_RX_BD_CONS 2
|
||||
#define HC_INDEX_U_FCOE_EQ_CONS 3
|
||||
|
||||
#define HC_INDEX_C_TOE_TX_CQ_CONS 0
|
||||
#define HC_INDEX_C_ETH_TX_CQ_CONS 1
|
||||
#define HC_INDEX_C_ISCSI_EQ_CONS 2
|
||||
|
||||
#define HC_INDEX_DEF_X_SPQ_CONS 0
|
||||
|
||||
#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
|
||||
#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
|
||||
#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
|
||||
#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
|
||||
#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
|
||||
#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
|
||||
#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
|
||||
|
||||
#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
|
||||
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
|
||||
#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
|
||||
#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
|
||||
#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
|
||||
#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
|
||||
|
||||
/* used by the driver to get the SB offset */
|
||||
#define USTORM_ID 0
|
||||
#define CSTORM_ID 1
|
||||
#define XSTORM_ID 2
|
||||
#define TSTORM_ID 3
|
||||
#define ATTENTION_ID 4
|
||||
|
||||
/* max number of slow path commands per port */
|
||||
#define MAX_RAMRODS_PER_PORT 8
|
||||
|
||||
/* values for RX ETH CQE type field */
|
||||
#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
|
||||
#define RX_ETH_CQE_TYPE_ETH_RAMROD 1
|
||||
|
||||
|
||||
/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
|
||||
#define EMULATION_FREQUENCY_FACTOR 1600
|
||||
#define FPGA_FREQUENCY_FACTOR 100
|
||||
|
||||
#define TIMERS_TICK_SIZE_CHIP (1e-3)
|
||||
#define TIMERS_TICK_SIZE_EMUL \
|
||||
((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
|
||||
#define TIMERS_TICK_SIZE_FPGA \
|
||||
((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
|
||||
|
||||
#define TSEMI_CLK1_RESUL_CHIP (1e-3)
|
||||
#define TSEMI_CLK1_RESUL_EMUL \
|
||||
((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
|
||||
#define TSEMI_CLK1_RESUL_FPGA \
|
||||
((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
|
||||
|
||||
#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
|
||||
#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
|
||||
#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
|
||||
|
||||
#define XSEMI_CLK1_RESUL_CHIP (1e-3)
|
||||
#define XSEMI_CLK1_RESUL_EMUL \
|
||||
((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
|
||||
#define XSEMI_CLK1_RESUL_FPGA \
|
||||
((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
|
||||
|
||||
#define XSEMI_CLK2_RESUL_CHIP (1e-6)
|
||||
#define XSEMI_CLK2_RESUL_EMUL \
|
||||
((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
|
||||
#define XSEMI_CLK2_RESUL_FPGA \
|
||||
((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
|
||||
|
||||
#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
|
||||
#define SDM_TIMER_TICK_RESUL_EMUL \
|
||||
((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
|
||||
#define SDM_TIMER_TICK_RESUL_FPGA \
|
||||
((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
|
||||
|
||||
|
||||
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
|
||||
#define XSTORM_IP_ID_ROLL_HALF 0x8000
|
||||
#define XSTORM_IP_ID_ROLL_ALL 0
|
||||
|
||||
#define FW_LOG_LIST_SIZE 50
|
||||
|
||||
#define NUM_OF_PROTOCOLS 4
|
||||
#define NUM_OF_SAFC_BITS 16
|
||||
#define MAX_COS_NUMBER 4
|
||||
#define MAX_T_STAT_COUNTER_ID 18
|
||||
#define MAX_X_STAT_COUNTER_ID 18
|
||||
#define MAX_U_STAT_COUNTER_ID 18
|
||||
|
||||
|
||||
#define UNKNOWN_ADDRESS 0
|
||||
#define UNICAST_ADDRESS 1
|
||||
#define MULTICAST_ADDRESS 2
|
||||
#define BROADCAST_ADDRESS 3
|
||||
|
||||
#define SINGLE_FUNCTION 0
|
||||
#define MULTI_FUNCTION 1
|
||||
|
||||
#define IP_V4 0
|
||||
#define IP_V6 1
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,163 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
#ifndef _BXE_INCLUDE_H
|
||||
#define _BXE_INCLUDE_H
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/endian.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
/*
|
||||
* Convert FreeBSD byte order to match generated code usage.
|
||||
*/
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
#define __BIG_ENDIAN 1
|
||||
#undef __LITTLE_ENDIAN
|
||||
#else
|
||||
#undef __BIG_ENDIAN
|
||||
#define __LITTLE_ENDIAN 1
|
||||
#endif
|
||||
|
||||
#include "bxe_debug.h"
|
||||
#include "bxe_reg.h"
|
||||
#include "bxe_fw_defs.h"
|
||||
#include "bxe_hsi.h"
|
||||
#include "bxe_link.h"
|
||||
|
||||
/*
|
||||
* Convenience definitions used in multiple files.
|
||||
*/
|
||||
#define BXE_PRINTF(fmt, args...) \
|
||||
do { \
|
||||
device_printf(sc->dev, fmt, ##args); \
|
||||
}while(0)
|
||||
|
||||
|
||||
#ifdef BXE_DEBUG
|
||||
|
||||
#define REG_WR(sc, offset, val) \
|
||||
bxe_reg_write32(sc, offset, val)
|
||||
#define REG_WR8(sc, offset, val) \
|
||||
bxe_reg_write8(sc, offset, val)
|
||||
#define REG_WR16(sc, offset, val) \
|
||||
bxe_reg_write16(sc, offset, val)
|
||||
#define REG_WR32(sc, offset, val) \
|
||||
bxe_reg_write32(sc, offset, val)
|
||||
|
||||
#define REG_RD(sc, offset) \
|
||||
bxe_reg_read32(sc, offset)
|
||||
#define REG_RD8(sc, offset) \
|
||||
bxe_reg_read8(sc, offset)
|
||||
#define REG_RD16(sc, offset) \
|
||||
bxe_reg_read16(sc, offset)
|
||||
#define REG_RD32(sc, offset) \
|
||||
bxe_reg_read32(sc, offset)
|
||||
|
||||
#define REG_RD_IND(sc, offset) \
|
||||
bxe_reg_rd_ind(sc, offset)
|
||||
#define REG_WR_IND(sc, offset, val) \
|
||||
bxe_reg_wr_ind(sc, offset, val)
|
||||
|
||||
#else
|
||||
|
||||
#define REG_WR(sc, offset, val) \
|
||||
bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
|
||||
#define REG_WR8(sc, offset, val) \
|
||||
bus_space_write_1(sc->bxe_btag, sc->bxe_bhandle, offset, val)
|
||||
#define REG_WR16(sc, offset, val) \
|
||||
bus_space_write_2(sc->bxe_btag, sc->bxe_bhandle, offset, val)
|
||||
#define REG_WR32(sc, offset, val) \
|
||||
bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
|
||||
|
||||
#define REG_RD(sc, offset) \
|
||||
bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
|
||||
#define REG_RD8(sc, offset) \
|
||||
bus_space_read_1(sc->bxe_btag, sc->bxe_bhandle, offset)
|
||||
#define REG_RD16(sc, offset) \
|
||||
bus_space_read_2(sc->bxe_btag, sc->bxe_bhandle, offset)
|
||||
#define REG_RD32(sc, offset) \
|
||||
bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
|
||||
|
||||
#define REG_RD_IND(sc, offset) \
|
||||
bxe_reg_rd_ind(sc, offset)
|
||||
#define REG_WR_IND(sc, offset, val) \
|
||||
bxe_reg_wr_ind(sc, offset, val)
|
||||
|
||||
#endif /* BXE_DEBUG */
|
||||
|
||||
|
||||
#define REG_RD_DMAE(sc, offset, val, len32) \
|
||||
do { \
|
||||
bxe_read_dmae(sc, offset, len32); \
|
||||
memcpy(val, BXE_SP(sc, wb_data[0]), len32 * 4); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define REG_WR_DMAE(sc, offset, val, len32) \
|
||||
do { \
|
||||
memcpy(BXE_SP(sc, wb_data[0]), val, len32 * 4); \
|
||||
bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), \
|
||||
offset, len32); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define SHMEM_ADDR(sc, field) (sc->common.shmem_base + \
|
||||
offsetof(struct shmem_region, field))
|
||||
|
||||
#define SHMEM_RD(sc, field) \
|
||||
REG_RD(sc, SHMEM_ADDR(sc, field))
|
||||
#define SHMEM_RD16(sc, field) \
|
||||
REG_RD16(sc, SHMEM_ADDR(sc, field))
|
||||
|
||||
#define SHMEM_WR(sc, field, val) \
|
||||
REG_WR(sc, SHMEM_ADDR(sc, field), val)
|
||||
|
||||
#define SHMEM2_ADDR(sc, field) (sc->common.shmem2_base + \
|
||||
offsetof(struct shmem2_region, field))
|
||||
#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
|
||||
#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
|
||||
|
||||
|
||||
#define EMAC_RD(sc, reg) \
|
||||
REG_RD(sc, emac_base + (uint32_t) reg)
|
||||
#define EMAC_WR(sc, reg, val) \
|
||||
REG_WR(sc, emac_base + (uint32_t) reg, val)
|
||||
|
||||
#define BMAC_WR(sc, reg, val) \
|
||||
REG_WR(sc, GRCBASE_NIG + bmac_addr + reg, val)
|
||||
|
||||
#endif /* _BXE_INCLUDE_H */
|
||||
@ -1,177 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
#ifndef BXE_INIT_H
|
||||
#define BXE_INIT_H
|
||||
/*
|
||||
* bxe_init.h: Broadcom Everest network driver.
|
||||
* Structures and macros needed during the initialization.
|
||||
*/
|
||||
|
||||
/* RAM0 size in bytes */
|
||||
#define STORM_INTMEM_SIZE_E1 0x5800
|
||||
#define STORM_INTMEM_SIZE_E1H 0x10000
|
||||
#define STORM_INTMEM_SIZE(sc) \
|
||||
((CHIP_IS_E1(sc) ? STORM_INTMEM_SIZE_E1 : STORM_INTMEM_SIZE_E1H) / 4)
|
||||
|
||||
|
||||
/* Init operation types and structures */
|
||||
/* Common for both E1 and E1H */
|
||||
#define OP_RD 0x1 /* read single register */
|
||||
#define OP_WR 0x2 /* write single register */
|
||||
#define OP_IW 0x3 /* write single register using mailbox */
|
||||
#define OP_SW 0x4 /* copy a string to the device */
|
||||
#define OP_SI 0x5 /* copy a string using mailbox */
|
||||
#define OP_ZR 0x6 /* clear memory */
|
||||
#define OP_ZP 0x7 /* unzip then copy with DMAE */
|
||||
#define OP_WR_64 0x8 /* write 64 bit pattern */
|
||||
#define OP_WB 0x9 /* copy a string using DMAE */
|
||||
|
||||
/* FPGA and EMUL specific operations */
|
||||
#define OP_WR_EMUL 0xa /* write single register on Emulation */
|
||||
#define OP_WR_FPGA 0xb /* write single register on FPGA */
|
||||
#define OP_WR_ASIC 0xc /* write single register on ASIC */
|
||||
|
||||
/* Init stages */
|
||||
/* Never reorder stages !!! */
|
||||
#define COMMON_STAGE 0
|
||||
#define PORT0_STAGE 1
|
||||
#define PORT1_STAGE 2
|
||||
#define FUNC0_STAGE 3
|
||||
#define FUNC1_STAGE 4
|
||||
#define FUNC2_STAGE 5
|
||||
#define FUNC3_STAGE 6
|
||||
#define FUNC4_STAGE 7
|
||||
#define FUNC5_STAGE 8
|
||||
#define FUNC6_STAGE 9
|
||||
#define FUNC7_STAGE 10
|
||||
#define STAGE_IDX_MAX 11
|
||||
|
||||
#define STAGE_START 0
|
||||
#define STAGE_END 1
|
||||
|
||||
|
||||
/* Indices of blocks */
|
||||
#define PRS_BLOCK 0
|
||||
#define SRCH_BLOCK 1
|
||||
#define TSDM_BLOCK 2
|
||||
#define TCM_BLOCK 3
|
||||
#define BRB1_BLOCK 4
|
||||
#define TSEM_BLOCK 5
|
||||
#define PXPCS_BLOCK 6
|
||||
#define EMAC0_BLOCK 7
|
||||
#define EMAC1_BLOCK 8
|
||||
#define DBU_BLOCK 9
|
||||
#define MISC_BLOCK 10
|
||||
#define DBG_BLOCK 11
|
||||
#define NIG_BLOCK 12
|
||||
#define MCP_BLOCK 13
|
||||
#define UPB_BLOCK 14
|
||||
#define CSDM_BLOCK 15
|
||||
#define USDM_BLOCK 16
|
||||
#define CCM_BLOCK 17
|
||||
#define UCM_BLOCK 18
|
||||
#define USEM_BLOCK 19
|
||||
#define CSEM_BLOCK 20
|
||||
#define XPB_BLOCK 21
|
||||
#define DQ_BLOCK 22
|
||||
#define TIMERS_BLOCK 23
|
||||
#define XSDM_BLOCK 24
|
||||
#define QM_BLOCK 25
|
||||
#define PBF_BLOCK 26
|
||||
#define XCM_BLOCK 27
|
||||
#define XSEM_BLOCK 28
|
||||
#define CDU_BLOCK 29
|
||||
#define DMAE_BLOCK 30
|
||||
#define PXP_BLOCK 31
|
||||
#define CFC_BLOCK 32
|
||||
#define HC_BLOCK 33
|
||||
#define PXP2_BLOCK 34
|
||||
#define MISC_AEU_BLOCK 35
|
||||
#define PGLUE_B_BLOCK 36
|
||||
#define IGU_BLOCK 37
|
||||
|
||||
/* Returns the index of start or end of a specific block stage in ops array. */
|
||||
#define BLOCK_OPS_IDX(block, stage, end) \
|
||||
(2 * (((block) * STAGE_IDX_MAX) + (stage)) + (end))
|
||||
|
||||
struct raw_op {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t raw_data;
|
||||
};
|
||||
|
||||
struct op_read {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t pad;
|
||||
};
|
||||
|
||||
struct op_write {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
struct op_string_write {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
#ifdef __LITTLE_ENDIAN
|
||||
uint16_t data_off;
|
||||
uint16_t data_len;
|
||||
#else /* __BIG_ENDIAN */
|
||||
uint16_t data_len;
|
||||
uint16_t data_off;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct op_zero {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t len;
|
||||
};
|
||||
|
||||
union init_op {
|
||||
struct op_read read;
|
||||
struct op_write write;
|
||||
struct op_string_write str_wr;
|
||||
struct op_zero zero;
|
||||
struct raw_op raw;
|
||||
};
|
||||
|
||||
#include "bxe_init_values_e1.h"
|
||||
#include "bxe_init_values_e1h.h"
|
||||
|
||||
#endif /* BXE_INIT_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,239 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2010 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
#ifndef BXE_LINK_H
|
||||
#define BXE_LINK_H
|
||||
|
||||
/*
|
||||
* Defines
|
||||
*/
|
||||
#define DEFAULT_PHY_DEV_ADDR 3
|
||||
|
||||
|
||||
|
||||
#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
|
||||
#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
|
||||
#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
|
||||
#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
|
||||
#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
|
||||
|
||||
#define SPEED_AUTO_NEG 0
|
||||
#define SPEED_12000 12000
|
||||
#define SPEED_12500 12500
|
||||
#define SPEED_13000 13000
|
||||
#define SPEED_15000 15000
|
||||
#define SPEED_16000 16000
|
||||
|
||||
#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
|
||||
#define SFP_EEPROM_VENDOR_NAME_SIZE 16
|
||||
#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
|
||||
#define SFP_EEPROM_VENDOR_OUI_SIZE 3
|
||||
#define SFP_EEPROM_PART_NO_ADDR 0x28
|
||||
#define SFP_EEPROM_PART_NO_SIZE 16
|
||||
#define PWR_FLT_ERR_MSG_LEN 250
|
||||
|
||||
/*
|
||||
* Structs
|
||||
*/
|
||||
/* Inputs parameters to the CLC. */
|
||||
struct link_params {
|
||||
uint8_t port;
|
||||
/* Default / User Configuration */
|
||||
uint8_t loopback_mode;
|
||||
#define LOOPBACK_NONE 0
|
||||
#define LOOPBACK_EMAC 1
|
||||
#define LOOPBACK_BMAC 2
|
||||
#define LOOPBACK_XGXS_10 3
|
||||
#define LOOPBACK_EXT_PHY 4
|
||||
#define LOOPBACK_EXT 5
|
||||
|
||||
uint16_t req_duplex;
|
||||
uint16_t req_flow_ctrl;
|
||||
/* Should be set to TX / BOTH when req_flow_ctrl is set to AUTO. */
|
||||
uint16_t req_fc_auto_adv;
|
||||
/* Also determine AutoNeg. */
|
||||
uint16_t req_line_speed;
|
||||
|
||||
/* Device parameters */
|
||||
uint8_t mac_addr[6];
|
||||
|
||||
/* shmem parameters */
|
||||
uint32_t shmem_base;
|
||||
uint32_t speed_cap_mask;
|
||||
uint32_t switch_cfg;
|
||||
#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
|
||||
#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
|
||||
#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
|
||||
|
||||
/* Part of the hw_config read from the shmem. */
|
||||
uint16_t hw_led_mode;
|
||||
|
||||
/* phy_addr populated by the CLC. */
|
||||
uint8_t phy_addr;
|
||||
/* uint8_t reserved1; */
|
||||
|
||||
uint32_t lane_config;
|
||||
uint32_t ext_phy_config;
|
||||
#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
|
||||
((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
|
||||
#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
|
||||
(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
|
||||
PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
|
||||
#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
|
||||
((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
|
||||
|
||||
/* Phy register parameter */
|
||||
uint32_t chip_id;
|
||||
|
||||
uint16_t xgxs_config_rx[4]; /* preemphasis values for the rx side */
|
||||
uint16_t xgxs_config_tx[4]; /* preemphasis values for the tx side */
|
||||
|
||||
uint32_t feature_config_flags;
|
||||
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
|
||||
#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
|
||||
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
|
||||
#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
|
||||
|
||||
/* Device pointer passed to all callback functions. */
|
||||
struct bxe_softc *sc;
|
||||
};
|
||||
|
||||
/* Output parameters */
|
||||
struct link_vars {
|
||||
uint8_t phy_flags;
|
||||
|
||||
uint8_t mac_type;
|
||||
#define MAC_TYPE_NONE 0
|
||||
#define MAC_TYPE_EMAC 1
|
||||
#define MAC_TYPE_BMAC 2
|
||||
|
||||
/* Internal phy link indication. */
|
||||
uint8_t phy_link_up;
|
||||
uint8_t link_up;
|
||||
|
||||
uint16_t line_speed;
|
||||
uint16_t duplex;
|
||||
|
||||
uint16_t flow_ctrl;
|
||||
uint16_t ieee_fc;
|
||||
|
||||
uint32_t autoneg;
|
||||
#define AUTO_NEG_DISABLED 0x0
|
||||
#define AUTO_NEG_ENABLED 0x1
|
||||
#define AUTO_NEG_COMPLETE 0x2
|
||||
#define AUTO_NEG_PARALLEL_DETECTION_USED 0x4
|
||||
|
||||
/* The same definitions as the shmem parameter. */
|
||||
uint32_t link_status;
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
|
||||
/* Initialize the phy. */
|
||||
uint8_t bxe_phy_init(struct link_params *input, struct link_vars *output);
|
||||
|
||||
/*
|
||||
* Reset the link. Should be called when driver or interface goes down
|
||||
* Before calling phy firmware upgrade, the reset_ext_phy should be set
|
||||
* to 0.
|
||||
*/
|
||||
uint8_t bxe_link_reset(struct link_params *params, struct link_vars *vars,
|
||||
uint8_t reset_ext_phy);
|
||||
|
||||
/* bxe_link_update should be called upon link interrupt */
|
||||
uint8_t bxe_link_update(struct link_params *input, struct link_vars *output);
|
||||
|
||||
/*
|
||||
* Use the following cl45 functions to read/write from external_phy
|
||||
* In order to use it to read/write internal phy registers, use
|
||||
* DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
|
||||
* Use ext_phy_type of 0 in case of cl22 over cl45
|
||||
* the register.
|
||||
*/
|
||||
uint8_t bxe_cl45_read(struct bxe_softc *sc, uint8_t port, uint32_t ext_phy_type,
|
||||
uint8_t phy_addr, uint8_t devad, uint16_t reg, uint16_t *ret_val);
|
||||
|
||||
uint8_t bxe_cl45_write(struct bxe_softc *sc, uint8_t port,
|
||||
uint32_t ext_phy_type, uint8_t phy_addr, uint8_t devad, uint16_t reg,
|
||||
uint16_t val);
|
||||
|
||||
/*
|
||||
* Reads the link_status from the shmem, and update the link vars accordingly.
|
||||
*/
|
||||
void bxe_link_status_update(struct link_params *input,
|
||||
struct link_vars *output);
|
||||
/* Returns string representing the fw_version of the external phy. */
|
||||
uint8_t bxe_get_ext_phy_fw_version(struct link_params *params,
|
||||
uint8_t driver_loaded, uint8_t *version, uint16_t len);
|
||||
|
||||
/*
|
||||
* Set/Unset the led
|
||||
* Basically, the CLC takes care of the led for the link, but in case one needs
|
||||
* to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to blink
|
||||
* the led, and LED_MODE_OFF to set the led off.
|
||||
*/
|
||||
uint8_t bxe_set_led(struct link_params *params, uint8_t mode, uint32_t speed);
|
||||
#define LED_MODE_OFF 0
|
||||
#define LED_MODE_OPER 2
|
||||
|
||||
uint8_t bxe_override_led_value(struct bxe_softc *sc, uint8_t port,
|
||||
uint32_t led_idx, uint32_t value);
|
||||
|
||||
/*
|
||||
* bxe_handle_module_detect_int should be called upon module detection
|
||||
* interrupt.
|
||||
*/
|
||||
void bxe_handle_module_detect_int(struct link_params *params);
|
||||
|
||||
/*
|
||||
* Get the actual link status. In case it returns 0, link is up, otherwise
|
||||
* link is down.
|
||||
*/
|
||||
uint8_t bxe_test_link(struct link_params *input, struct link_vars *vars);
|
||||
|
||||
/* One-time initialization for external phy after power up. */
|
||||
uint8_t bxe_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base);
|
||||
|
||||
/* Reset the external PHY using GPIO. */
|
||||
void bxe_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port);
|
||||
|
||||
void bxe_sfx7101_sp_sw_reset(struct bxe_softc *sc, uint8_t port,
|
||||
uint8_t phy_addr);
|
||||
|
||||
uint8_t bxe_read_sfp_module_eeprom(struct link_params *params, uint16_t addr,
|
||||
uint8_t byte_cnt, uint8_t *o_buf);
|
||||
|
||||
#endif /* BXE_LINK_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
2032
sys/dev/bxe/bxe_stats.c
Normal file
2032
sys/dev/bxe/bxe_stats.c
Normal file
File diff suppressed because it is too large
Load Diff
687
sys/dev/bxe/bxe_stats.h
Normal file
687
sys/dev/bxe/bxe_stats.h
Normal file
@ -0,0 +1,687 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef BXE_STATS_H
|
||||
#define BXE_STATS_H
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
struct nig_stats {
|
||||
uint32_t brb_discard;
|
||||
uint32_t brb_packet;
|
||||
uint32_t brb_truncate;
|
||||
uint32_t flow_ctrl_discard;
|
||||
uint32_t flow_ctrl_octets;
|
||||
uint32_t flow_ctrl_packet;
|
||||
uint32_t mng_discard;
|
||||
uint32_t mng_octet_inp;
|
||||
uint32_t mng_octet_out;
|
||||
uint32_t mng_packet_inp;
|
||||
uint32_t mng_packet_out;
|
||||
uint32_t pbf_octets;
|
||||
uint32_t pbf_packet;
|
||||
uint32_t safc_inp;
|
||||
uint32_t egress_mac_pkt0_lo;
|
||||
uint32_t egress_mac_pkt0_hi;
|
||||
uint32_t egress_mac_pkt1_lo;
|
||||
uint32_t egress_mac_pkt1_hi;
|
||||
};
|
||||
|
||||
|
||||
enum bxe_stats_event {
|
||||
STATS_EVENT_PMF = 0,
|
||||
STATS_EVENT_LINK_UP,
|
||||
STATS_EVENT_UPDATE,
|
||||
STATS_EVENT_STOP,
|
||||
STATS_EVENT_MAX
|
||||
};
|
||||
|
||||
enum bxe_stats_state {
|
||||
STATS_STATE_DISABLED = 0,
|
||||
STATS_STATE_ENABLED,
|
||||
STATS_STATE_MAX
|
||||
};
|
||||
|
||||
struct bxe_eth_stats {
|
||||
uint32_t total_bytes_received_hi;
|
||||
uint32_t total_bytes_received_lo;
|
||||
uint32_t total_bytes_transmitted_hi;
|
||||
uint32_t total_bytes_transmitted_lo;
|
||||
uint32_t total_unicast_packets_received_hi;
|
||||
uint32_t total_unicast_packets_received_lo;
|
||||
uint32_t total_multicast_packets_received_hi;
|
||||
uint32_t total_multicast_packets_received_lo;
|
||||
uint32_t total_broadcast_packets_received_hi;
|
||||
uint32_t total_broadcast_packets_received_lo;
|
||||
uint32_t total_unicast_packets_transmitted_hi;
|
||||
uint32_t total_unicast_packets_transmitted_lo;
|
||||
uint32_t total_multicast_packets_transmitted_hi;
|
||||
uint32_t total_multicast_packets_transmitted_lo;
|
||||
uint32_t total_broadcast_packets_transmitted_hi;
|
||||
uint32_t total_broadcast_packets_transmitted_lo;
|
||||
uint32_t valid_bytes_received_hi;
|
||||
uint32_t valid_bytes_received_lo;
|
||||
|
||||
uint32_t error_bytes_received_hi;
|
||||
uint32_t error_bytes_received_lo;
|
||||
uint32_t etherstatsoverrsizepkts_hi;
|
||||
uint32_t etherstatsoverrsizepkts_lo;
|
||||
uint32_t no_buff_discard_hi;
|
||||
uint32_t no_buff_discard_lo;
|
||||
|
||||
uint32_t rx_stat_ifhcinbadoctets_hi;
|
||||
uint32_t rx_stat_ifhcinbadoctets_lo;
|
||||
uint32_t tx_stat_ifhcoutbadoctets_hi;
|
||||
uint32_t tx_stat_ifhcoutbadoctets_lo;
|
||||
uint32_t rx_stat_dot3statsfcserrors_hi;
|
||||
uint32_t rx_stat_dot3statsfcserrors_lo;
|
||||
uint32_t rx_stat_dot3statsalignmenterrors_hi;
|
||||
uint32_t rx_stat_dot3statsalignmenterrors_lo;
|
||||
uint32_t rx_stat_dot3statscarriersenseerrors_hi;
|
||||
uint32_t rx_stat_dot3statscarriersenseerrors_lo;
|
||||
uint32_t rx_stat_falsecarriererrors_hi;
|
||||
uint32_t rx_stat_falsecarriererrors_lo;
|
||||
uint32_t rx_stat_etherstatsundersizepkts_hi;
|
||||
uint32_t rx_stat_etherstatsundersizepkts_lo;
|
||||
uint32_t rx_stat_dot3statsframestoolong_hi;
|
||||
uint32_t rx_stat_dot3statsframestoolong_lo;
|
||||
uint32_t rx_stat_etherstatsfragments_hi;
|
||||
uint32_t rx_stat_etherstatsfragments_lo;
|
||||
uint32_t rx_stat_etherstatsjabbers_hi;
|
||||
uint32_t rx_stat_etherstatsjabbers_lo;
|
||||
uint32_t rx_stat_maccontrolframesreceived_hi;
|
||||
uint32_t rx_stat_maccontrolframesreceived_lo;
|
||||
uint32_t rx_stat_bmac_xpf_hi;
|
||||
uint32_t rx_stat_bmac_xpf_lo;
|
||||
uint32_t rx_stat_bmac_xcf_hi;
|
||||
uint32_t rx_stat_bmac_xcf_lo;
|
||||
uint32_t rx_stat_xoffstateentered_hi;
|
||||
uint32_t rx_stat_xoffstateentered_lo;
|
||||
uint32_t rx_stat_xonpauseframesreceived_hi;
|
||||
uint32_t rx_stat_xonpauseframesreceived_lo;
|
||||
uint32_t rx_stat_xoffpauseframesreceived_hi;
|
||||
uint32_t rx_stat_xoffpauseframesreceived_lo;
|
||||
uint32_t tx_stat_outxonsent_hi;
|
||||
uint32_t tx_stat_outxonsent_lo;
|
||||
uint32_t tx_stat_outxoffsent_hi;
|
||||
uint32_t tx_stat_outxoffsent_lo;
|
||||
uint32_t tx_stat_flowcontroldone_hi;
|
||||
uint32_t tx_stat_flowcontroldone_lo;
|
||||
uint32_t tx_stat_etherstatscollisions_hi;
|
||||
uint32_t tx_stat_etherstatscollisions_lo;
|
||||
uint32_t tx_stat_dot3statssinglecollisionframes_hi;
|
||||
uint32_t tx_stat_dot3statssinglecollisionframes_lo;
|
||||
uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
|
||||
uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
|
||||
uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
|
||||
uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
|
||||
uint32_t tx_stat_dot3statsexcessivecollisions_hi;
|
||||
uint32_t tx_stat_dot3statsexcessivecollisions_lo;
|
||||
uint32_t tx_stat_dot3statslatecollisions_hi;
|
||||
uint32_t tx_stat_dot3statslatecollisions_lo;
|
||||
uint32_t tx_stat_etherstatspkts64octets_hi;
|
||||
uint32_t tx_stat_etherstatspkts64octets_lo;
|
||||
uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
|
||||
uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
|
||||
uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
|
||||
uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
|
||||
uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
|
||||
uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
|
||||
uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
|
||||
uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
|
||||
uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
|
||||
uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
|
||||
uint32_t tx_stat_etherstatspktsover1522octets_hi;
|
||||
uint32_t tx_stat_etherstatspktsover1522octets_lo;
|
||||
uint32_t tx_stat_bmac_2047_hi;
|
||||
uint32_t tx_stat_bmac_2047_lo;
|
||||
uint32_t tx_stat_bmac_4095_hi;
|
||||
uint32_t tx_stat_bmac_4095_lo;
|
||||
uint32_t tx_stat_bmac_9216_hi;
|
||||
uint32_t tx_stat_bmac_9216_lo;
|
||||
uint32_t tx_stat_bmac_16383_hi;
|
||||
uint32_t tx_stat_bmac_16383_lo;
|
||||
uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
|
||||
uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
|
||||
uint32_t tx_stat_bmac_ufl_hi;
|
||||
uint32_t tx_stat_bmac_ufl_lo;
|
||||
|
||||
uint32_t pause_frames_received_hi;
|
||||
uint32_t pause_frames_received_lo;
|
||||
uint32_t pause_frames_sent_hi;
|
||||
uint32_t pause_frames_sent_lo;
|
||||
|
||||
uint32_t etherstatspkts1024octetsto1522octets_hi;
|
||||
uint32_t etherstatspkts1024octetsto1522octets_lo;
|
||||
uint32_t etherstatspktsover1522octets_hi;
|
||||
uint32_t etherstatspktsover1522octets_lo;
|
||||
|
||||
uint32_t brb_drop_hi;
|
||||
uint32_t brb_drop_lo;
|
||||
uint32_t brb_truncate_hi;
|
||||
uint32_t brb_truncate_lo;
|
||||
|
||||
uint32_t mac_filter_discard;
|
||||
uint32_t mf_tag_discard;
|
||||
uint32_t brb_truncate_discard;
|
||||
uint32_t mac_discard;
|
||||
|
||||
uint32_t nig_timer_max;
|
||||
|
||||
uint32_t total_tpa_aggregations_hi;
|
||||
uint32_t total_tpa_aggregations_lo;
|
||||
uint32_t total_tpa_aggregated_frames_hi;
|
||||
uint32_t total_tpa_aggregated_frames_lo;
|
||||
uint32_t total_tpa_bytes_hi;
|
||||
uint32_t total_tpa_bytes_lo;
|
||||
|
||||
/* PFC */
|
||||
uint32_t pfc_frames_received_hi;
|
||||
uint32_t pfc_frames_received_lo;
|
||||
uint32_t pfc_frames_sent_hi;
|
||||
uint32_t pfc_frames_sent_lo;
|
||||
|
||||
/* Recovery */
|
||||
uint32_t recoverable_error;
|
||||
uint32_t unrecoverable_error;
|
||||
|
||||
/* src: Clear-on-Read register; Will not survive PMF Migration */
|
||||
uint32_t eee_tx_lpi;
|
||||
|
||||
/* receive path driver statistics */
|
||||
uint32_t rx_calls;
|
||||
uint32_t rx_pkts;
|
||||
uint32_t rx_tpa_pkts;
|
||||
uint32_t rx_soft_errors;
|
||||
uint32_t rx_hw_csum_errors;
|
||||
uint32_t rx_ofld_frames_csum_ip;
|
||||
uint32_t rx_ofld_frames_csum_tcp_udp;
|
||||
uint32_t rx_budget_reached;
|
||||
|
||||
/* tx path driver statistics */
|
||||
uint32_t tx_pkts;
|
||||
uint32_t tx_soft_errors;
|
||||
uint32_t tx_ofld_frames_csum_ip;
|
||||
uint32_t tx_ofld_frames_csum_tcp;
|
||||
uint32_t tx_ofld_frames_csum_udp;
|
||||
uint32_t tx_ofld_frames_lso;
|
||||
uint32_t tx_ofld_frames_lso_hdr_splits;
|
||||
uint32_t tx_encap_failures;
|
||||
uint32_t tx_hw_queue_full;
|
||||
uint32_t tx_hw_max_queue_depth;
|
||||
uint32_t tx_dma_mapping_failure;
|
||||
uint32_t tx_max_drbr_queue_depth;
|
||||
uint32_t tx_window_violation_std;
|
||||
uint32_t tx_window_violation_tso;
|
||||
//uint32_t tx_unsupported_tso_request_ipv6;
|
||||
//uint32_t tx_unsupported_tso_request_not_tcp;
|
||||
uint32_t tx_chain_lost_mbuf;
|
||||
uint32_t tx_frames_deferred;
|
||||
uint32_t tx_queue_xoff;
|
||||
|
||||
/* mbuf driver statistics */
|
||||
uint32_t mbuf_defrag_attempts;
|
||||
uint32_t mbuf_defrag_failures;
|
||||
uint32_t mbuf_rx_bd_alloc_failed;
|
||||
uint32_t mbuf_rx_bd_mapping_failed;
|
||||
uint32_t mbuf_rx_tpa_alloc_failed;
|
||||
uint32_t mbuf_rx_tpa_mapping_failed;
|
||||
uint32_t mbuf_rx_sge_alloc_failed;
|
||||
uint32_t mbuf_rx_sge_mapping_failed;
|
||||
|
||||
/* track the number of allocated mbufs */
|
||||
uint32_t mbuf_alloc_tx;
|
||||
uint32_t mbuf_alloc_rx;
|
||||
uint32_t mbuf_alloc_sge;
|
||||
uint32_t mbuf_alloc_tpa;
|
||||
};
|
||||
|
||||
|
||||
struct bxe_eth_q_stats {
|
||||
uint32_t total_unicast_bytes_received_hi;
|
||||
uint32_t total_unicast_bytes_received_lo;
|
||||
uint32_t total_broadcast_bytes_received_hi;
|
||||
uint32_t total_broadcast_bytes_received_lo;
|
||||
uint32_t total_multicast_bytes_received_hi;
|
||||
uint32_t total_multicast_bytes_received_lo;
|
||||
uint32_t total_bytes_received_hi;
|
||||
uint32_t total_bytes_received_lo;
|
||||
uint32_t total_unicast_bytes_transmitted_hi;
|
||||
uint32_t total_unicast_bytes_transmitted_lo;
|
||||
uint32_t total_broadcast_bytes_transmitted_hi;
|
||||
uint32_t total_broadcast_bytes_transmitted_lo;
|
||||
uint32_t total_multicast_bytes_transmitted_hi;
|
||||
uint32_t total_multicast_bytes_transmitted_lo;
|
||||
uint32_t total_bytes_transmitted_hi;
|
||||
uint32_t total_bytes_transmitted_lo;
|
||||
uint32_t total_unicast_packets_received_hi;
|
||||
uint32_t total_unicast_packets_received_lo;
|
||||
uint32_t total_multicast_packets_received_hi;
|
||||
uint32_t total_multicast_packets_received_lo;
|
||||
uint32_t total_broadcast_packets_received_hi;
|
||||
uint32_t total_broadcast_packets_received_lo;
|
||||
uint32_t total_unicast_packets_transmitted_hi;
|
||||
uint32_t total_unicast_packets_transmitted_lo;
|
||||
uint32_t total_multicast_packets_transmitted_hi;
|
||||
uint32_t total_multicast_packets_transmitted_lo;
|
||||
uint32_t total_broadcast_packets_transmitted_hi;
|
||||
uint32_t total_broadcast_packets_transmitted_lo;
|
||||
uint32_t valid_bytes_received_hi;
|
||||
uint32_t valid_bytes_received_lo;
|
||||
|
||||
uint32_t etherstatsoverrsizepkts_hi;
|
||||
uint32_t etherstatsoverrsizepkts_lo;
|
||||
uint32_t no_buff_discard_hi;
|
||||
uint32_t no_buff_discard_lo;
|
||||
|
||||
uint32_t total_packets_received_checksum_discarded_hi;
|
||||
uint32_t total_packets_received_checksum_discarded_lo;
|
||||
uint32_t total_packets_received_ttl0_discarded_hi;
|
||||
uint32_t total_packets_received_ttl0_discarded_lo;
|
||||
uint32_t total_transmitted_dropped_packets_error_hi;
|
||||
uint32_t total_transmitted_dropped_packets_error_lo;
|
||||
|
||||
uint32_t total_tpa_aggregations_hi;
|
||||
uint32_t total_tpa_aggregations_lo;
|
||||
uint32_t total_tpa_aggregated_frames_hi;
|
||||
uint32_t total_tpa_aggregated_frames_lo;
|
||||
uint32_t total_tpa_bytes_hi;
|
||||
uint32_t total_tpa_bytes_lo;
|
||||
|
||||
/* receive path driver statistics */
|
||||
uint32_t rx_calls;
|
||||
uint32_t rx_pkts;
|
||||
uint32_t rx_tpa_pkts;
|
||||
uint32_t rx_soft_errors;
|
||||
uint32_t rx_hw_csum_errors;
|
||||
uint32_t rx_ofld_frames_csum_ip;
|
||||
uint32_t rx_ofld_frames_csum_tcp_udp;
|
||||
uint32_t rx_budget_reached;
|
||||
|
||||
/* tx path driver statistics */
|
||||
uint32_t tx_pkts;
|
||||
uint32_t tx_soft_errors;
|
||||
uint32_t tx_ofld_frames_csum_ip;
|
||||
uint32_t tx_ofld_frames_csum_tcp;
|
||||
uint32_t tx_ofld_frames_csum_udp;
|
||||
uint32_t tx_ofld_frames_lso;
|
||||
uint32_t tx_ofld_frames_lso_hdr_splits;
|
||||
uint32_t tx_encap_failures;
|
||||
uint32_t tx_hw_queue_full;
|
||||
uint32_t tx_hw_max_queue_depth;
|
||||
uint32_t tx_dma_mapping_failure;
|
||||
uint32_t tx_max_drbr_queue_depth;
|
||||
uint32_t tx_window_violation_std;
|
||||
uint32_t tx_window_violation_tso;
|
||||
//uint32_t tx_unsupported_tso_request_ipv6;
|
||||
//uint32_t tx_unsupported_tso_request_not_tcp;
|
||||
uint32_t tx_chain_lost_mbuf;
|
||||
uint32_t tx_frames_deferred;
|
||||
uint32_t tx_queue_xoff;
|
||||
|
||||
/* mbuf driver statistics */
|
||||
uint32_t mbuf_defrag_attempts;
|
||||
uint32_t mbuf_defrag_failures;
|
||||
uint32_t mbuf_rx_bd_alloc_failed;
|
||||
uint32_t mbuf_rx_bd_mapping_failed;
|
||||
uint32_t mbuf_rx_tpa_alloc_failed;
|
||||
uint32_t mbuf_rx_tpa_mapping_failed;
|
||||
uint32_t mbuf_rx_sge_alloc_failed;
|
||||
uint32_t mbuf_rx_sge_mapping_failed;
|
||||
|
||||
/* track the number of allocated mbufs */
|
||||
uint32_t mbuf_alloc_tx;
|
||||
uint32_t mbuf_alloc_rx;
|
||||
uint32_t mbuf_alloc_sge;
|
||||
uint32_t mbuf_alloc_tpa;
|
||||
};
|
||||
|
||||
struct bxe_eth_stats_old {
|
||||
uint32_t rx_stat_dot3statsframestoolong_hi;
|
||||
uint32_t rx_stat_dot3statsframestoolong_lo;
|
||||
};
|
||||
|
||||
struct bxe_eth_q_stats_old {
|
||||
/* Fields to perserve over fw reset*/
|
||||
uint32_t total_unicast_bytes_received_hi;
|
||||
uint32_t total_unicast_bytes_received_lo;
|
||||
uint32_t total_broadcast_bytes_received_hi;
|
||||
uint32_t total_broadcast_bytes_received_lo;
|
||||
uint32_t total_multicast_bytes_received_hi;
|
||||
uint32_t total_multicast_bytes_received_lo;
|
||||
uint32_t total_unicast_bytes_transmitted_hi;
|
||||
uint32_t total_unicast_bytes_transmitted_lo;
|
||||
uint32_t total_broadcast_bytes_transmitted_hi;
|
||||
uint32_t total_broadcast_bytes_transmitted_lo;
|
||||
uint32_t total_multicast_bytes_transmitted_hi;
|
||||
uint32_t total_multicast_bytes_transmitted_lo;
|
||||
uint32_t total_tpa_bytes_hi;
|
||||
uint32_t total_tpa_bytes_lo;
|
||||
|
||||
/* Fields to perserve last of */
|
||||
uint32_t total_bytes_received_hi;
|
||||
uint32_t total_bytes_received_lo;
|
||||
uint32_t total_bytes_transmitted_hi;
|
||||
uint32_t total_bytes_transmitted_lo;
|
||||
uint32_t total_unicast_packets_received_hi;
|
||||
uint32_t total_unicast_packets_received_lo;
|
||||
uint32_t total_multicast_packets_received_hi;
|
||||
uint32_t total_multicast_packets_received_lo;
|
||||
uint32_t total_broadcast_packets_received_hi;
|
||||
uint32_t total_broadcast_packets_received_lo;
|
||||
uint32_t total_unicast_packets_transmitted_hi;
|
||||
uint32_t total_unicast_packets_transmitted_lo;
|
||||
uint32_t total_multicast_packets_transmitted_hi;
|
||||
uint32_t total_multicast_packets_transmitted_lo;
|
||||
uint32_t total_broadcast_packets_transmitted_hi;
|
||||
uint32_t total_broadcast_packets_transmitted_lo;
|
||||
uint32_t valid_bytes_received_hi;
|
||||
uint32_t valid_bytes_received_lo;
|
||||
|
||||
uint32_t total_tpa_bytes_hi_old;
|
||||
uint32_t total_tpa_bytes_lo_old;
|
||||
|
||||
/* receive path driver statistics */
|
||||
uint32_t rx_calls_old;
|
||||
uint32_t rx_pkts_old;
|
||||
uint32_t rx_tpa_pkts_old;
|
||||
uint32_t rx_soft_errors_old;
|
||||
uint32_t rx_hw_csum_errors_old;
|
||||
uint32_t rx_ofld_frames_csum_ip_old;
|
||||
uint32_t rx_ofld_frames_csum_tcp_udp_old;
|
||||
uint32_t rx_budget_reached_old;
|
||||
|
||||
/* tx path driver statistics */
|
||||
uint32_t tx_pkts_old;
|
||||
uint32_t tx_soft_errors_old;
|
||||
uint32_t tx_ofld_frames_csum_ip_old;
|
||||
uint32_t tx_ofld_frames_csum_tcp_old;
|
||||
uint32_t tx_ofld_frames_csum_udp_old;
|
||||
uint32_t tx_ofld_frames_lso_old;
|
||||
uint32_t tx_ofld_frames_lso_hdr_splits_old;
|
||||
uint32_t tx_encap_failures_old;
|
||||
uint32_t tx_hw_queue_full_old;
|
||||
uint32_t tx_hw_max_queue_depth_old;
|
||||
uint32_t tx_dma_mapping_failure_old;
|
||||
uint32_t tx_max_drbr_queue_depth_old;
|
||||
uint32_t tx_window_violation_std_old;
|
||||
uint32_t tx_window_violation_tso_old;
|
||||
//uint32_t tx_unsupported_tso_request_ipv6_old;
|
||||
//uint32_t tx_unsupported_tso_request_not_tcp_old;
|
||||
uint32_t tx_chain_lost_mbuf_old;
|
||||
uint32_t tx_frames_deferred_old;
|
||||
uint32_t tx_queue_xoff_old;
|
||||
|
||||
/* mbuf driver statistics */
|
||||
uint32_t mbuf_defrag_attempts_old;
|
||||
uint32_t mbuf_defrag_failures_old;
|
||||
uint32_t mbuf_rx_bd_alloc_failed_old;
|
||||
uint32_t mbuf_rx_bd_mapping_failed_old;
|
||||
uint32_t mbuf_rx_tpa_alloc_failed_old;
|
||||
uint32_t mbuf_rx_tpa_mapping_failed_old;
|
||||
uint32_t mbuf_rx_sge_alloc_failed_old;
|
||||
uint32_t mbuf_rx_sge_mapping_failed_old;
|
||||
|
||||
/* track the number of allocated mbufs */
|
||||
int mbuf_alloc_tx_old;
|
||||
int mbuf_alloc_rx_old;
|
||||
int mbuf_alloc_sge_old;
|
||||
int mbuf_alloc_tpa_old;
|
||||
};
|
||||
|
||||
struct bxe_net_stats_old {
|
||||
uint32_t rx_dropped;
|
||||
};
|
||||
|
||||
struct bxe_fw_port_stats_old {
|
||||
uint32_t pfc_frames_tx_hi;
|
||||
uint32_t pfc_frames_tx_lo;
|
||||
uint32_t pfc_frames_rx_hi;
|
||||
uint32_t pfc_frames_rx_lo;
|
||||
|
||||
uint32_t mac_filter_discard;
|
||||
uint32_t mf_tag_discard;
|
||||
uint32_t brb_truncate_discard;
|
||||
uint32_t mac_discard;
|
||||
};
|
||||
|
||||
/* sum[hi:lo] += add[hi:lo] */
|
||||
#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
|
||||
do { \
|
||||
s_lo += a_lo; \
|
||||
s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
|
||||
} while (0)
|
||||
|
||||
#define LE32_0 ((uint32_t) 0)
|
||||
#define LE16_0 ((uint16_t) 0)
|
||||
|
||||
/* The _force is for cases where high value is 0 */
|
||||
#define ADD_64_LE(s_hi, a_hi_le, s_lo, a_lo_le) \
|
||||
ADD_64(s_hi, le32toh(a_hi_le), \
|
||||
s_lo, le32toh(a_lo_le))
|
||||
|
||||
#define ADD_64_LE16(s_hi, a_hi_le, s_lo, a_lo_le) \
|
||||
ADD_64(s_hi, le16toh(a_hi_le), \
|
||||
s_lo, le16toh(a_lo_le))
|
||||
|
||||
/* difference = minuend - subtrahend */
|
||||
#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
|
||||
do { \
|
||||
if (m_lo < s_lo) { \
|
||||
/* underflow */ \
|
||||
d_hi = m_hi - s_hi; \
|
||||
if (d_hi > 0) { \
|
||||
/* we can 'loan' 1 */ \
|
||||
d_hi--; \
|
||||
d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
|
||||
} else { \
|
||||
/* m_hi <= s_hi */ \
|
||||
d_hi = 0; \
|
||||
d_lo = 0; \
|
||||
} \
|
||||
} else { \
|
||||
/* m_lo >= s_lo */ \
|
||||
if (m_hi < s_hi) { \
|
||||
d_hi = 0; \
|
||||
d_lo = 0; \
|
||||
} else { \
|
||||
/* m_hi >= s_hi */ \
|
||||
d_hi = m_hi - s_hi; \
|
||||
d_lo = m_lo - s_lo; \
|
||||
} \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_STAT64(s, t) \
|
||||
do { \
|
||||
DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
|
||||
diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
|
||||
pstats->mac_stx[0].t##_hi = new->s##_hi; \
|
||||
pstats->mac_stx[0].t##_lo = new->s##_lo; \
|
||||
ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
|
||||
pstats->mac_stx[1].t##_lo, diff.lo); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_STAT64_NIG(s, t) \
|
||||
do { \
|
||||
DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
|
||||
diff.lo, new->s##_lo, old->s##_lo); \
|
||||
ADD_64(estats->t##_hi, diff.hi, \
|
||||
estats->t##_lo, diff.lo); \
|
||||
} while (0)
|
||||
|
||||
/* sum[hi:lo] += add */
|
||||
#define ADD_EXTEND_64(s_hi, s_lo, a) \
|
||||
do { \
|
||||
s_lo += a; \
|
||||
s_hi += (s_lo < a) ? 1 : 0; \
|
||||
} while (0)
|
||||
|
||||
#define ADD_STAT64(diff, t) \
|
||||
do { \
|
||||
ADD_64(pstats->mac_stx[1].t##_hi, new->diff##_hi, \
|
||||
pstats->mac_stx[1].t##_lo, new->diff##_lo); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_EXTEND_STAT(s) \
|
||||
do { \
|
||||
ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
|
||||
pstats->mac_stx[1].s##_lo, \
|
||||
new->s); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_EXTEND_TSTAT_X(s, t, size) \
|
||||
do { \
|
||||
diff = le##size##toh(tclient->s) - \
|
||||
le##size##toh(old_tclient->s); \
|
||||
old_tclient->s = tclient->s; \
|
||||
ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_EXTEND_TSTAT(s, t) UPDATE_EXTEND_TSTAT_X(s, t, 32)
|
||||
|
||||
#define UPDATE_EXTEND_E_TSTAT(s, t, size) \
|
||||
do { \
|
||||
UPDATE_EXTEND_TSTAT_X(s, t, size); \
|
||||
ADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_EXTEND_USTAT(s, t) \
|
||||
do { \
|
||||
diff = le32toh(uclient->s) - le32toh(old_uclient->s); \
|
||||
old_uclient->s = uclient->s; \
|
||||
ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_EXTEND_E_USTAT(s, t) \
|
||||
do { \
|
||||
UPDATE_EXTEND_USTAT(s, t); \
|
||||
ADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_EXTEND_XSTAT(s, t) \
|
||||
do { \
|
||||
diff = le32toh(xclient->s) - le32toh(old_xclient->s); \
|
||||
old_xclient->s = xclient->s; \
|
||||
ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_QSTAT(s, t) \
|
||||
do { \
|
||||
qstats->t##_hi = qstats_old->t##_hi + le32toh(s.hi); \
|
||||
qstats->t##_lo = qstats_old->t##_lo + le32toh(s.lo); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_QSTAT_OLD(f) \
|
||||
do { \
|
||||
qstats_old->f = qstats->f; \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_ESTAT_QSTAT_64(s) \
|
||||
do { \
|
||||
ADD_64(estats->s##_hi, qstats->s##_hi, \
|
||||
estats->s##_lo, qstats->s##_lo); \
|
||||
SUB_64(estats->s##_hi, qstats_old->s##_hi_old, \
|
||||
estats->s##_lo, qstats_old->s##_lo_old); \
|
||||
qstats_old->s##_hi_old = qstats->s##_hi; \
|
||||
qstats_old->s##_lo_old = qstats->s##_lo; \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_ESTAT_QSTAT(s) \
|
||||
do { \
|
||||
estats->s += qstats->s; \
|
||||
estats->s -= qstats_old->s##_old; \
|
||||
qstats_old->s##_old = qstats->s; \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_FSTAT_QSTAT(s) \
|
||||
do { \
|
||||
ADD_64(fstats->s##_hi, qstats->s##_hi, \
|
||||
fstats->s##_lo, qstats->s##_lo); \
|
||||
SUB_64(fstats->s##_hi, qstats_old->s##_hi, \
|
||||
fstats->s##_lo, qstats_old->s##_lo); \
|
||||
estats->s##_hi = fstats->s##_hi; \
|
||||
estats->s##_lo = fstats->s##_lo; \
|
||||
qstats_old->s##_hi = qstats->s##_hi; \
|
||||
qstats_old->s##_lo = qstats->s##_lo; \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_FW_STAT(s) \
|
||||
do { \
|
||||
estats->s = le32toh(tport->s) + fwstats->s; \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_FW_STAT_OLD(f) \
|
||||
do { \
|
||||
fwstats->f = estats->f; \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_ESTAT(s, t) \
|
||||
do { \
|
||||
SUB_64(estats->s##_hi, estats_old->t##_hi, \
|
||||
estats->s##_lo, estats_old->t##_lo); \
|
||||
ADD_64(estats->s##_hi, estats->t##_hi, \
|
||||
estats->s##_lo, estats->t##_lo); \
|
||||
estats_old->t##_hi = estats->t##_hi; \
|
||||
estats_old->t##_lo = estats->t##_lo; \
|
||||
} while (0)
|
||||
|
||||
/* minuend -= subtrahend */
|
||||
#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
|
||||
do { \
|
||||
DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
|
||||
} while (0)
|
||||
|
||||
/* minuend[hi:lo] -= subtrahend */
|
||||
#define SUB_EXTEND_64(m_hi, m_lo, s) \
|
||||
do { \
|
||||
SUB_64(m_hi, 0, m_lo, s); \
|
||||
} while (0)
|
||||
|
||||
#define SUB_EXTEND_USTAT(s, t) \
|
||||
do { \
|
||||
diff = le32toh(uclient->s) - le32toh(old_uclient->s); \
|
||||
SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
|
||||
} while (0)
|
||||
|
||||
struct bxe_softc;
|
||||
void bxe_stats_init(struct bxe_softc *sc);
|
||||
void bxe_stats_handle(struct bxe_softc *sc, enum bxe_stats_event event);
|
||||
void bxe_save_statistics(struct bxe_softc *sc);
|
||||
void bxe_afex_collect_stats(struct bxe_softc *sc, void *void_afex_stats, uint32_t stats_type);
|
||||
|
||||
#endif /* BXE_STATS_H */
|
||||
|
||||
@ -1,131 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
uint32_t regs_count_e1=319;
|
||||
|
||||
struct reg_addr reg_addrs_e1[319] = {
|
||||
{0x00002000,341}, {0x00002800,103}, {0x00003000,287}, {0x00003800,331},
|
||||
{0x00008800,6}, {0x0000a000,223}, {0x0000a388,1}, {0x0000a398,1},
|
||||
{0x0000a400,69}, {0x0000a518,1}, {0x0000a520,1}, {0x0000a528,1},
|
||||
{0x0000a530,1}, {0x0000a538,1}, {0x0000a540,1}, {0x0000a548,1},
|
||||
{0x0000a550,1}, {0x0000a558,1}, {0x0000a560,1}, {0x0000a568,1},
|
||||
{0x0000a570,1}, {0x0000a580,1}, {0x0000a590,1}, {0x0000a5a0,1},
|
||||
{0x0000a5c0,1}, {0x0000c000,35}, {0x0000c098,1}, {0x0000c0a8,1},
|
||||
{0x0000c100,11}, {0x0000c130,2}, {0x0000c140,2}, {0x0000c160,4},
|
||||
{0x0000c180,4}, {0x0000c1a0,4}, {0x0000c800,4}, {0x00010000,236},
|
||||
{0x000103bc,1}, {0x000103cc,1}, {0x000103dc,1}, {0x00010400,57},
|
||||
{0x000104e8,2}, {0x000104f4,2}, {0x00010500,146}, {0x00010750,2},
|
||||
{0x00010760,2}, {0x00010770,2}, {0x00010780,2}, {0x00010790,2},
|
||||
{0x000107a0,2}, {0x000107b0,2}, {0x000107c0,2}, {0x000107d0,2},
|
||||
{0x000107e0,2}, {0x00010880,2}, {0x00010900,2}, {0x00010c00,2},
|
||||
{0x00011000,2}, {0x00012000,1}, {0x00014000,1}, {0x00020000,170},
|
||||
{0x000202b4,1}, {0x000202c4,1}, {0x00020400,2}, {0x0002040c,8},
|
||||
{0x00020480,1}, {0x00020500,1}, {0x00020600,1}, {0x00028000,24674},
|
||||
{0x00040194,1}, {0x000401a4,1}, {0x00040200,4}, {0x00040400,43},
|
||||
{0x000404b8,1}, {0x000404c8,1}, {0x00040500,2}, {0x00040510,2},
|
||||
{0x00040520,2}, {0x00040530,2}, {0x00040540,2}, {0x00042000,164},
|
||||
{0x0004229c,1}, {0x000422ac,1}, {0x000422bc,1}, {0x00042400,49},
|
||||
{0x000424c8,38}, {0x00042568,2}, {0x00042800,1}, {0x00050000,116},
|
||||
{0x000501dc,1}, {0x000501ec,1}, {0x00050200,2}, {0x0005020c,7},
|
||||
{0x00050240,1}, {0x00050280,1}, {0x00052000,1}, {0x00054000,3328},
|
||||
{0x00058000,8263}, {0x00060128,1}, {0x00060138,1}, {0x00060200,1},
|
||||
{0x00061000,512}, {0x00070000,32768}, {0x000a0000,16384},
|
||||
{0x000c1000,7}, {0x000c1028,1}, {0x000c1038,1}, {0x000c1800,2},
|
||||
{0x000c2000,164}, {0x000c229c,1}, {0x000c22ac,1}, {0x000c22bc,1},
|
||||
{0x000c2400,49}, {0x000c24c8,38}, {0x000c2568,2}, {0x000c2600,1},
|
||||
{0x000c4000,165}, {0x000c42a0,1}, {0x000c42b0,1}, {0x000c42c0,1},
|
||||
{0x000c4400,51}, {0x000c44d0,38}, {0x000c4570,2}, {0x000c4600,1},
|
||||
{0x000d0000,118}, {0x000d01e4,1}, {0x000d01f4,1}, {0x000d0200,2},
|
||||
{0x000d020c,7}, {0x000d0280,1}, {0x000d0300,1}, {0x000d0400,1},
|
||||
{0x000d4000,2560}, {0x000d8000,8306}, {0x000e01d4,1}, {0x000e01e4,1},
|
||||
{0x000e0200,2}, {0x000e020c,8}, {0x000e0280,1}, {0x000e0300,1},
|
||||
{0x000e1000,1}, {0x000e2000,2048}, {0x000f0000,16384}, {0x00101000,12},
|
||||
{0x0010103c,1}, {0x0010104c,1}, {0x00101100,1}, {0x00101800,8},
|
||||
{0x00102000,18}, {0x00102054,1}, {0x00102064,1}, {0x00102080,17},
|
||||
{0x00102400,1}, {0x00103000,26}, {0x00103074,1}, {0x00103084,1},
|
||||
{0x00103094,1}, {0x00103800,8}, {0x00104000,63}, {0x00104108,1},
|
||||
{0x00104118,1}, {0x00104200,17}, {0x00104400,512}, {0x00105000,1024},
|
||||
{0x00108000,33}, {0x00108090,1}, {0x001080a0,1}, {0x00108100,5},
|
||||
{0x00108120,5}, {0x00108200,74}, {0x00108400,74}, {0x00108800,152},
|
||||
{0x00109000,1}, {0x00120000,347}, {0x00120578,1}, {0x00120588,1},
|
||||
{0x00120598,1}, {0x0012080c,65}, {0x00120a00,2}, {0x00122000,2},
|
||||
{0x00140000,114}, {0x001401d4,1}, {0x001401e4,1}, {0x00140200,6},
|
||||
{0x00144000,4}, {0x00148000,4}, {0x0014c000,4}, {0x00150000,4},
|
||||
{0x00154000,4}, {0x00158000,4}, {0x00161000,7}, {0x00161028,1},
|
||||
{0x00161038,1}, {0x00161800,2}, {0x00164000,60}, {0x001640fc,1},
|
||||
{0x0016410c,1}, {0x00164200,1}, {0x00164208,1}, {0x00164210,1},
|
||||
{0x00164218,1}, {0x00164220,1}, {0x00164228,1}, {0x00164230,1},
|
||||
{0x00164238,1}, {0x00164240,1}, {0x00164248,1}, {0x00164250,1},
|
||||
{0x00164258,1}, {0x00164260,1}, {0x00164270,2}, {0x00164280,2},
|
||||
{0x00164800,2}, {0x00165000,2}, {0x00166000,164}, {0x0016629c,1},
|
||||
{0x001662ac,1}, {0x001662bc,1}, {0x00166400,49}, {0x001664c8,38},
|
||||
{0x00166568,2}, {0x00166800,1}, {0x00168000,270}, {0x00168444,1},
|
||||
{0x00168454,1}, {0x00168800,19}, {0x00168900,1}, {0x00168a00,128},
|
||||
{0x0016a000,1536}, {0x0016c000,1536}, {0x00170000,93}, {0x00170180,1},
|
||||
{0x00170190,1}, {0x00170200,4}, {0x00170214,1}, {0x00178000,1},
|
||||
{0x00180000,61}, {0x00180100,1}, {0x00180110,1}, {0x00180120,1},
|
||||
{0x00180130,1}, {0x00180200,58}, {0x00180340,4}, {0x00180400,1},
|
||||
{0x00181000,1024}, {0x001a0000,5632}, {0x001a8000,64},
|
||||
{0x001b1800,128}, {0x001b1c00,128}, {0x001b2000,1}, {0x001b8200,1},
|
||||
{0x001b8240,1}, {0x001b8280,1}, {0x001b82c0,1}, {0x001b8a00,1},
|
||||
{0x001b8a80,1}, {0x001c0000,2}, {0x00200000,65}, {0x00200110,1},
|
||||
{0x00200120,1}, {0x00200130,1}, {0x00200140,1}, {0x00200200,58},
|
||||
{0x00200340,4}, {0x00200400,1}, {0x00202000,2048}, {0x00220000,5632},
|
||||
{0x00228000,64}, {0x00231800,128}, {0x00231c00,128}, {0x00232000,1},
|
||||
{0x00238200,1}, {0x00238240,1}, {0x00238280,1}, {0x002382c0,1},
|
||||
{0x00238a00,1}, {0x00238a80,1}, {0x00240000,2}, {0x00280000,65},
|
||||
{0x00280110,1}, {0x00280120,1}, {0x00280130,1}, {0x00280140,1},
|
||||
{0x00280200,58}, {0x00280340,4}, {0x00280400,1}, {0x00282000,2048},
|
||||
{0x002a0000,5632}, {0x002a8000,64}, {0x002b1800,128}, {0x002b1c00,128},
|
||||
{0x002b2000,1}, {0x002b8200,1}, {0x002b8240,1}, {0x002b8280,1},
|
||||
{0x002b82c0,1}, {0x002b8a00,1}, {0x002b8a80,1}, {0x002c0000,2},
|
||||
{0x00300000,65}, {0x00300110,1}, {0x00300120,1}, {0x00300130,1},
|
||||
{0x00300140,1}, {0x00300200,58}, {0x00300340,4}, {0x00300400,1},
|
||||
{0x00302000,2048}, {0x00320000,5632}, {0x00328000,64},
|
||||
{0x00331800,128}, {0x00331c00,128}, {0x00332000,1}, {0x00338200,1},
|
||||
{0x00338240,1}, {0x00338280,1}, {0x003382c0,1}, {0x00338a00,1},
|
||||
{0x00338a80,1}, {0x00340000,2}};
|
||||
|
||||
|
||||
|
||||
uint32_t wregs_count_e1=1;
|
||||
|
||||
static uint32_t const_reg0_e1[1] = {0x001b1000};
|
||||
|
||||
|
||||
struct wreg_addr wreg_addrs_e1[1] = {{0x001b0c00, 192, 1, const_reg0_e1}};
|
||||
|
||||
|
||||
struct hd_param hd_param_e1={0x497e2e43, 0x00040802, 0x0000001f};
|
||||
|
||||
@ -1,140 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
uint32_t regs_count_e1h=354;
|
||||
|
||||
struct reg_addr reg_addrs_e1h[354] = {
|
||||
{0x00002000,341}, {0x00002800,103}, {0x00003000,287}, {0x00003800,331},
|
||||
{0x0000a000,223}, {0x0000a388,1}, {0x0000a398,8}, {0x0000a3c0,3},
|
||||
{0x0000a3d0,1}, {0x0000a3d8,1}, {0x0000a3e0,1}, {0x0000a3e8,1},
|
||||
{0x0000a3f0,1}, {0x0000a3f8,1}, {0x0000a400,69}, {0x0000a518,1},
|
||||
{0x0000a520,1}, {0x0000a528,1}, {0x0000a530,1}, {0x0000a538,1},
|
||||
{0x0000a540,1}, {0x0000a548,1}, {0x0000a550,1}, {0x0000a558,1},
|
||||
{0x0000a560,1}, {0x0000a568,1}, {0x0000a570,1}, {0x0000a580,1},
|
||||
{0x0000a590,1}, {0x0000a5a0,1}, {0x0000a5c0,1}, {0x0000a5e0,1},
|
||||
{0x0000a5e8,1}, {0x0000a5f0,1}, {0x0000a5f8,10}, {0x0000c000,35},
|
||||
{0x0000c098,1}, {0x0000c0a8,1}, {0x0000c100,11}, {0x0000c130,2},
|
||||
{0x0000c140,2}, {0x0000c160,4}, {0x0000c180,4}, {0x0000c1a0,4},
|
||||
{0x0000c800,4}, {0x0000d000,347}, {0x00010000,236}, {0x000103bc,1},
|
||||
{0x000103cc,1}, {0x000103dc,1}, {0x00010400,57}, {0x000104e8,2},
|
||||
{0x000104f4,2}, {0x00010500,146}, {0x00010750,2}, {0x00010760,2},
|
||||
{0x00010770,2}, {0x00010780,2}, {0x00010790,2}, {0x000107a0,2},
|
||||
{0x000107b0,2}, {0x000107c0,2}, {0x000107d0,2}, {0x000107e0,2},
|
||||
{0x00010880,2}, {0x00010900,2}, {0x00010c00,2}, {0x00011000,2},
|
||||
{0x00012000,1}, {0x00014000,1}, {0x00016000,26}, {0x00016070,18},
|
||||
{0x000160c0,27}, {0x00016140,1}, {0x00016160,1}, {0x00016180,2},
|
||||
{0x000161c0,2}, {0x00016204,5}, {0x00018000,1}, {0x00018008,1},
|
||||
{0x00020000,170}, {0x000202b4,1}, {0x000202c4,1}, {0x00020400,2},
|
||||
{0x0002040c,26}, {0x00020480,1}, {0x00020500,1}, {0x00020600,1},
|
||||
{0x00028000,24674}, {0x00040194,1}, {0x000401a4,12}, {0x00040200,4},
|
||||
{0x00040400,43}, {0x000404b8,1}, {0x000404c8,4}, {0x00040500,2},
|
||||
{0x00040510,2}, {0x00040520,2}, {0x00040530,2}, {0x00040540,2},
|
||||
{0x00042000,164}, {0x0004229c,1}, {0x000422ac,1}, {0x000422bc,1},
|
||||
{0x000422d4,5}, {0x00042400,49}, {0x000424c8,38}, {0x00042568,2},
|
||||
{0x00042800,1}, {0x00050000,116}, {0x000501dc,1}, {0x000501ec,7},
|
||||
{0x0005020c,14}, {0x00050280,1}, {0x00052000,1}, {0x00054000,3328},
|
||||
{0x00058000,8263}, {0x00060128,1}, {0x00060138,25}, {0x00060200,1},
|
||||
{0x00061000,512}, {0x00070000,32768}, {0x000a0000,32768},
|
||||
{0x000c1000,7}, {0x000c1028,1}, {0x000c1038,1}, {0x000c1800,2},
|
||||
{0x000c2000,164}, {0x000c229c,1}, {0x000c22ac,1}, {0x000c22bc,1},
|
||||
{0x000c2400,49}, {0x000c24c8,38}, {0x000c2568,2}, {0x000c2600,1},
|
||||
{0x000c4000,165}, {0x000c42a0,1}, {0x000c42b0,1}, {0x000c42c0,1},
|
||||
{0x000c42e0,7}, {0x000c4400,51}, {0x000c44d0,38}, {0x000c4570,2},
|
||||
{0x000c4600,1}, {0x000d0000,118}, {0x000d01e4,1}, {0x000d01f4,1},
|
||||
{0x000d0200,2}, {0x000d020c,25}, {0x000d0280,1}, {0x000d0300,1},
|
||||
{0x000d0400,1}, {0x000d4000,2560}, {0x000d8000,8306}, {0x000e01d4,1},
|
||||
{0x000e01e4,1}, {0x000e0200,2}, {0x000e020c,26}, {0x000e0280,1},
|
||||
{0x000e0300,1}, {0x000e1000,1}, {0x000e2000,2048}, {0x000f0000,16384},
|
||||
{0x00101000,12}, {0x0010103c,1}, {0x0010104c,2}, {0x00101100,1},
|
||||
{0x00101800,8}, {0x00102000,18}, {0x00102054,1}, {0x00102064,1},
|
||||
{0x00102080,17}, {0x001020c8,8}, {0x00102400,1}, {0x00103000,26},
|
||||
{0x00103074,1}, {0x00103084,1}, {0x00103094,6}, {0x00103800,8},
|
||||
{0x00104000,63}, {0x00104108,1}, {0x00104118,1}, {0x00104200,17},
|
||||
{0x00104400,512}, {0x00105000,1024}, {0x00108000,33}, {0x00108090,1},
|
||||
{0x001080a0,1}, {0x001080ac,5}, {0x00108100,5}, {0x00108120,5},
|
||||
{0x00108200,74}, {0x00108400,74}, {0x00108800,152}, {0x00109000,1},
|
||||
{0x00120000,347}, {0x00120578,1}, {0x00120588,1}, {0x00120598,24},
|
||||
{0x00120614,1}, {0x0012061c,30}, {0x0012080c,65}, {0x00120a00,2},
|
||||
{0x00122000,2}, {0x00128000,2}, {0x00140000,114}, {0x001401d4,1},
|
||||
{0x001401e4,1}, {0x00140200,6}, {0x00144000,4}, {0x00148000,4},
|
||||
{0x0014c000,4}, {0x00150000,4}, {0x00154000,4}, {0x00158000,4},
|
||||
{0x0015c000,7}, {0x00161000,7}, {0x00161028,1}, {0x00161038,1},
|
||||
{0x00161800,2}, {0x00164000,60}, {0x001640fc,1}, {0x0016410c,3},
|
||||
{0x00164200,1}, {0x00164208,1}, {0x00164210,1}, {0x00164218,1},
|
||||
{0x00164220,1}, {0x00164228,1}, {0x00164230,1}, {0x00164238,1},
|
||||
{0x00164240,1}, {0x00164248,1}, {0x00164250,1}, {0x00164258,1},
|
||||
{0x00164260,1}, {0x00164270,2}, {0x00164280,2}, {0x00164800,2},
|
||||
{0x00165000,2}, {0x00166000,164}, {0x0016629c,1}, {0x001662ac,1},
|
||||
{0x001662bc,1}, {0x00166400,49}, {0x001664c8,38}, {0x00166568,2},
|
||||
{0x00166800,1}, {0x00168000,270}, {0x00168444,1}, {0x00168454,1},
|
||||
{0x00168800,19}, {0x00168900,1}, {0x00168a00,128}, {0x0016a000,1536},
|
||||
{0x0016c000,1536}, {0x0016e000,16}, {0x0016e100,1}, {0x0016e200,2},
|
||||
{0x0016e400,183}, {0x00170000,93}, {0x00170180,1}, {0x00170190,1},
|
||||
{0x00170200,4}, {0x00170214,1}, {0x00178000,1}, {0x00180000,61},
|
||||
{0x00180100,1}, {0x00180110,1}, {0x00180120,1}, {0x00180130,1},
|
||||
{0x0018013c,2}, {0x00180200,58}, {0x00180340,4}, {0x00180400,1},
|
||||
{0x00181000,1024}, {0x001a0000,16896}, {0x001b1800,128},
|
||||
{0x001b1c00,128}, {0x001b2000,1}, {0x001b2400,64}, {0x001b8200,1},
|
||||
{0x001b8240,1}, {0x001b8280,1}, {0x001b82c0,1}, {0x001b8a00,1},
|
||||
{0x001b8a80,1}, {0x001c0000,2}, {0x00200000,65}, {0x00200110,1},
|
||||
{0x00200120,1}, {0x00200130,1}, {0x00200140,1}, {0x0020014c,2},
|
||||
{0x00200200,58}, {0x00200340,4}, {0x00200400,1}, {0x00202000,2048},
|
||||
{0x00220000,16896}, {0x00231800,128}, {0x00231c00,128}, {0x00232000,1},
|
||||
{0x00232400,64}, {0x00238200,1}, {0x00238240,1}, {0x00238280,1},
|
||||
{0x002382c0,1}, {0x00238a00,1}, {0x00238a80,1}, {0x00240000,2},
|
||||
{0x00280000,65}, {0x00280110,1}, {0x00280120,1}, {0x00280130,1},
|
||||
{0x00280140,1}, {0x0028014c,2}, {0x00280200,58}, {0x00280340,4},
|
||||
{0x00280400,1}, {0x00282000,2048}, {0x002a0000,16896},
|
||||
{0x002b1800,128}, {0x002b1c00,128}, {0x002b2000,1}, {0x002b2400,64},
|
||||
{0x002b8200,1}, {0x002b8240,1}, {0x002b8280,1}, {0x002b82c0,1},
|
||||
{0x002b8a00,1}, {0x002b8a80,1}, {0x002c0000,2}, {0x00300000,65},
|
||||
{0x00300110,1}, {0x00300120,1}, {0x00300130,1}, {0x00300140,1},
|
||||
{0x0030014c,2}, {0x00300200,58}, {0x00300340,4}, {0x00300400,1},
|
||||
{0x00302000,2048}, {0x00320000,16896}, {0x00331800,128},
|
||||
{0x00331c00,128}, {0x00332000,1}, {0x00332400,64}, {0x00338200,1},
|
||||
{0x00338240,1}, {0x00338280,1}, {0x003382c0,1}, {0x00338a00,1},
|
||||
{0x00338a80,1}, {0x00340000,2}};
|
||||
|
||||
|
||||
|
||||
uint32_t wregs_count_e1h=1;
|
||||
|
||||
static uint32_t const_reg0_e1h[2] = {0x001b1040, 0x001b1000};
|
||||
|
||||
|
||||
struct wreg_addr wreg_addrs_e1h[1] = {{0x001b0c00, 256, 2, const_reg0_e1h}};
|
||||
|
||||
|
||||
struct hd_param hd_param_e1h={0x497e2efb, 0x00040802, 0x0000001f};
|
||||
|
||||
433
sys/dev/bxe/ecore_fw_defs.h
Normal file
433
sys/dev/bxe/ecore_fw_defs.h
Normal file
@ -0,0 +1,433 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#ifndef ECORE_FW_DEFS_H
|
||||
#define ECORE_FW_DEFS_H
|
||||
|
||||
|
||||
#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
|
||||
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
|
||||
(IRO[147].base + ((assertListEntry) * IRO[147].m1))
|
||||
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
|
||||
(IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
|
||||
IRO[153].m2))
|
||||
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
|
||||
(IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
|
||||
IRO[154].m2))
|
||||
#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
|
||||
(IRO[159].base + ((funcId) * IRO[159].m1))
|
||||
#define CSTORM_FUNC_EN_OFFSET(funcId) \
|
||||
(IRO[149].base + ((funcId) * IRO[149].m1))
|
||||
#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
|
||||
(IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))
|
||||
#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
|
||||
(IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \
|
||||
* IRO[138].m2) + ((sbId) * IRO[138].m3))
|
||||
#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
|
||||
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[317].base + ((pfId) * IRO[317].m1))
|
||||
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
|
||||
(IRO[318].base + ((pfId) * IRO[318].m1))
|
||||
#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
|
||||
(IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
|
||||
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
|
||||
(IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
|
||||
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
|
||||
(IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
|
||||
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
|
||||
(IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
|
||||
#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
|
||||
(IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
|
||||
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
|
||||
(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
|
||||
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
|
||||
(IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))
|
||||
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[316].base + ((pfId) * IRO[316].m1))
|
||||
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
|
||||
(IRO[308].base + ((pfId) * IRO[308].m1))
|
||||
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
|
||||
(IRO[307].base + ((pfId) * IRO[307].m1))
|
||||
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
|
||||
(IRO[306].base + ((pfId) * IRO[306].m1))
|
||||
#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
|
||||
(IRO[151].base + ((funcId) * IRO[151].m1))
|
||||
#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
|
||||
(IRO[142].base + ((pfId) * IRO[142].m1))
|
||||
#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
|
||||
(IRO[143].base + ((pfId) * IRO[143].m1))
|
||||
#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
|
||||
(IRO[141].base + ((pfId) * IRO[141].m1))
|
||||
#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)
|
||||
#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
|
||||
(IRO[144].base + ((pfId) * IRO[144].m1))
|
||||
#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)
|
||||
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
|
||||
(IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))
|
||||
#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
|
||||
(IRO[133].base + ((sbId) * IRO[133].m1))
|
||||
#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
|
||||
(IRO[134].base + ((sbId) * IRO[134].m1))
|
||||
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
|
||||
(IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))
|
||||
#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
|
||||
(IRO[132].base + ((sbId) * IRO[132].m1))
|
||||
#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)
|
||||
#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
|
||||
(IRO[137].base + ((sbId) * IRO[137].m1))
|
||||
#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)
|
||||
#define CSTORM_VF_TO_PF_OFFSET(funcId) \
|
||||
(IRO[150].base + ((funcId) * IRO[150].m1))
|
||||
#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)
|
||||
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
|
||||
(IRO[203].base + ((pfId) * IRO[203].m1))
|
||||
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
|
||||
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
|
||||
(IRO[101].base + ((assertListEntry) * IRO[101].m1))
|
||||
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
|
||||
(IRO[201].base + ((pfId) * IRO[201].m1))
|
||||
#define TSTORM_FUNC_EN_OFFSET(funcId) \
|
||||
(IRO[103].base + ((funcId) * IRO[103].m1))
|
||||
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
|
||||
(IRO[272].base + ((pfId) * IRO[272].m1))
|
||||
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
|
||||
(IRO[271].base + ((pfId) * IRO[271].m1))
|
||||
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
|
||||
(IRO[270].base + ((pfId) * IRO[270].m1))
|
||||
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
|
||||
(IRO[269].base + ((pfId) * IRO[269].m1))
|
||||
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[268].base + ((pfId) * IRO[268].m1))
|
||||
#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
|
||||
(IRO[278].base + ((pfId) * IRO[278].m1))
|
||||
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
|
||||
(IRO[264].base + ((pfId) * IRO[264].m1))
|
||||
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
|
||||
(IRO[265].base + ((pfId) * IRO[265].m1))
|
||||
#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
|
||||
(IRO[266].base + ((pfId) * IRO[266].m1))
|
||||
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
|
||||
(IRO[267].base + ((pfId) * IRO[267].m1))
|
||||
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
|
||||
(IRO[202].base + ((pfId) * IRO[202].m1))
|
||||
#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
|
||||
(IRO[105].base + ((funcId) * IRO[105].m1))
|
||||
#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
|
||||
(IRO[217].base + ((pfId) * IRO[217].m1))
|
||||
#define TSTORM_VF_TO_PF_OFFSET(funcId) \
|
||||
(IRO[104].base + ((funcId) * IRO[104].m1))
|
||||
#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
|
||||
#define USTORM_AGG_DATA_SIZE (IRO[206].size)
|
||||
#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base)
|
||||
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
|
||||
(IRO[176].base + ((assertListEntry) * IRO[176].m1))
|
||||
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
|
||||
(IRO[183].base + ((portId) * IRO[183].m1))
|
||||
#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
|
||||
(IRO[319].base + ((pfId) * IRO[319].m1))
|
||||
#define USTORM_FUNC_EN_OFFSET(funcId) \
|
||||
(IRO[178].base + ((funcId) * IRO[178].m1))
|
||||
#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[283].base + ((pfId) * IRO[283].m1))
|
||||
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
|
||||
(IRO[284].base + ((pfId) * IRO[284].m1))
|
||||
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
|
||||
(IRO[288].base + ((pfId) * IRO[288].m1))
|
||||
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
|
||||
(IRO[285].base + ((pfId) * IRO[285].m1))
|
||||
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
|
||||
(IRO[281].base + ((pfId) * IRO[281].m1))
|
||||
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
|
||||
(IRO[280].base + ((pfId) * IRO[280].m1))
|
||||
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
|
||||
(IRO[279].base + ((pfId) * IRO[279].m1))
|
||||
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[282].base + ((pfId) * IRO[282].m1))
|
||||
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
|
||||
(IRO[286].base + ((pfId) * IRO[286].m1))
|
||||
#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[287].base + ((pfId) * IRO[287].m1))
|
||||
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
|
||||
(IRO[182].base + ((pfId) * IRO[182].m1))
|
||||
#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
|
||||
(IRO[180].base + ((funcId) * IRO[180].m1))
|
||||
#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
|
||||
(IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \
|
||||
IRO[209].m2))
|
||||
#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
|
||||
(IRO[210].base + ((qzoneId) * IRO[210].m1))
|
||||
#define USTORM_TPA_BTR_OFFSET (IRO[207].base)
|
||||
#define USTORM_TPA_BTR_SIZE (IRO[207].size)
|
||||
#define USTORM_VF_TO_PF_OFFSET(funcId) \
|
||||
(IRO[179].base + ((funcId) * IRO[179].m1))
|
||||
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
|
||||
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
|
||||
#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
|
||||
#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
|
||||
(IRO[50].base + ((assertListEntry) * IRO[50].m1))
|
||||
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \
|
||||
(IRO[43].base + ((portId) * IRO[43].m1))
|
||||
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \
|
||||
(IRO[45].base + ((pfId) * IRO[45].m1))
|
||||
#define XSTORM_FUNC_EN_OFFSET(funcId) \
|
||||
(IRO[47].base + ((funcId) * IRO[47].m1))
|
||||
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[296].base + ((pfId) * IRO[296].m1))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
|
||||
(IRO[299].base + ((pfId) * IRO[299].m1))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
|
||||
(IRO[300].base + ((pfId) * IRO[300].m1))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
|
||||
(IRO[301].base + ((pfId) * IRO[301].m1))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
|
||||
(IRO[302].base + ((pfId) * IRO[302].m1))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
|
||||
(IRO[303].base + ((pfId) * IRO[303].m1))
|
||||
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
|
||||
(IRO[304].base + ((pfId) * IRO[304].m1))
|
||||
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
|
||||
(IRO[305].base + ((pfId) * IRO[305].m1))
|
||||
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
|
||||
(IRO[295].base + ((pfId) * IRO[295].m1))
|
||||
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
|
||||
(IRO[294].base + ((pfId) * IRO[294].m1))
|
||||
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
|
||||
(IRO[293].base + ((pfId) * IRO[293].m1))
|
||||
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[298].base + ((pfId) * IRO[298].m1))
|
||||
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
|
||||
(IRO[297].base + ((pfId) * IRO[297].m1))
|
||||
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
|
||||
(IRO[292].base + ((pfId) * IRO[292].m1))
|
||||
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
|
||||
(IRO[291].base + ((pfId) * IRO[291].m1))
|
||||
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
|
||||
(IRO[290].base + ((pfId) * IRO[290].m1))
|
||||
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
|
||||
(IRO[289].base + ((pfId) * IRO[289].m1))
|
||||
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
|
||||
(IRO[44].base + ((pfId) * IRO[44].m1))
|
||||
#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
|
||||
(IRO[49].base + ((funcId) * IRO[49].m1))
|
||||
#define XSTORM_SPQ_DATA_OFFSET(funcId) \
|
||||
(IRO[32].base + ((funcId) * IRO[32].m1))
|
||||
#define XSTORM_SPQ_DATA_SIZE (IRO[32].size)
|
||||
#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \
|
||||
(IRO[30].base + ((funcId) * IRO[30].m1))
|
||||
#define XSTORM_SPQ_PROD_OFFSET(funcId) \
|
||||
(IRO[31].base + ((funcId) * IRO[31].m1))
|
||||
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
|
||||
(IRO[211].base + ((portId) * IRO[211].m1))
|
||||
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
|
||||
(IRO[212].base + ((portId) * IRO[212].m1))
|
||||
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
|
||||
(IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \
|
||||
IRO[214].m2))
|
||||
#define XSTORM_VF_TO_PF_OFFSET(funcId) \
|
||||
(IRO[48].base + ((funcId) * IRO[48].m1))
|
||||
#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)
|
||||
|
||||
|
||||
/* Ethernet Ring parameters */
|
||||
#define X_ETH_LOCAL_RING_SIZE 13
|
||||
#define FIRST_BD_IN_PKT 0
|
||||
#define PARSE_BD_INDEX 1
|
||||
#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
|
||||
#define U_ETH_NUM_OF_SGES_TO_FETCH 8
|
||||
#define U_ETH_MAX_SGES_FOR_PACKET 3
|
||||
|
||||
/* Rx ring params */
|
||||
#define U_ETH_LOCAL_BD_RING_SIZE 8
|
||||
#define U_ETH_LOCAL_SGE_RING_SIZE 10
|
||||
#define U_ETH_SGL_SIZE 8
|
||||
/* The fw will padd the buffer with this value, so the IP header \
|
||||
will be align to 4 Byte */
|
||||
#define IP_HEADER_ALIGNMENT_PADDING 2
|
||||
|
||||
#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
|
||||
(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
|
||||
|
||||
#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
|
||||
#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
|
||||
#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
|
||||
|
||||
#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
|
||||
#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
|
||||
#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
|
||||
|
||||
#define U_ETH_UNDEFINED_Q 0xFF
|
||||
|
||||
#define T_ETH_INDIRECTION_TABLE_SIZE 128
|
||||
#define T_ETH_RSS_KEY 10
|
||||
#define ETH_NUM_OF_RSS_ENGINES_E2 72
|
||||
|
||||
#define FILTER_RULES_COUNT 16
|
||||
#define MULTICAST_RULES_COUNT 16
|
||||
#define CLASSIFY_RULES_COUNT 16
|
||||
|
||||
/*The CRC32 seed, that is used for the hash(reduction) multicast address */
|
||||
#define ETH_CRC32_HASH_SEED 0x00000000
|
||||
|
||||
#define ETH_CRC32_HASH_BIT_SIZE (8)
|
||||
#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
|
||||
|
||||
/* Maximal L2 clients supported */
|
||||
#define ETH_MAX_RX_CLIENTS_E1 18
|
||||
#define ETH_MAX_RX_CLIENTS_E1H 28
|
||||
#define ETH_MAX_RX_CLIENTS_E2 152
|
||||
|
||||
/* Maximal statistics client Ids */
|
||||
#define MAX_STAT_COUNTER_ID_E1 36
|
||||
#define MAX_STAT_COUNTER_ID_E1H 56
|
||||
#define MAX_STAT_COUNTER_ID_E2 140
|
||||
|
||||
#define MAX_MAC_CREDIT_E1 192 /* Per Chip */
|
||||
#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
|
||||
#define MAX_MAC_CREDIT_E2 272 /* Per Path */
|
||||
#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
|
||||
#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
|
||||
#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
|
||||
|
||||
|
||||
/* Maximal aggregation queues supported */
|
||||
#define ETH_MAX_AGGREGATION_QUEUES_E1 32
|
||||
#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
|
||||
|
||||
|
||||
#define ETH_NUM_OF_MCAST_BINS 256
|
||||
#define ETH_NUM_OF_MCAST_ENGINES_E2 72
|
||||
|
||||
#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
|
||||
#define ETH_MIN_RX_CQES_WITH_TPA_E1 \
|
||||
(ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
|
||||
#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
|
||||
(ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
|
||||
|
||||
#define DISABLE_STATISTIC_COUNTER_ID_VALUE 0
|
||||
|
||||
|
||||
/* This file defines HSI constants common to all microcode flows */
|
||||
|
||||
/* offset in bits of protocol in the state context parameter */
|
||||
#define PROTOCOL_STATE_BIT_OFFSET 6
|
||||
|
||||
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
|
||||
#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
|
||||
#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
|
||||
|
||||
/* microcode fixed page page size 4K (chains and ring segments) */
|
||||
#define MC_PAGE_SIZE 4096
|
||||
|
||||
/* Number of indices per slow-path SB */
|
||||
#define HC_SP_SB_MAX_INDICES 16 /* The Maximum of all */
|
||||
|
||||
/* Number of indices per SB */
|
||||
#define HC_SB_MAX_INDICES_E1X 8 /* Multiple of 4 */
|
||||
#define HC_SB_MAX_INDICES_E2 8 /* Multiple of 4 */
|
||||
|
||||
/* Number of SB */
|
||||
#define HC_SB_MAX_SB_E1X 32
|
||||
#define HC_SB_MAX_SB_E2 136 /* include PF */
|
||||
|
||||
/* ID of slow path status block */
|
||||
#define HC_SP_SB_ID 0xde
|
||||
|
||||
/* Num of State machines */
|
||||
#define HC_SB_MAX_SM 2 /* Fixed */
|
||||
|
||||
/* Num of dynamic indices */
|
||||
#define HC_SB_MAX_DYNAMIC_INDICES 4 /* 0..3 fixed */
|
||||
|
||||
/* max number of slow path commands per port */
|
||||
#define MAX_RAMRODS_PER_PORT 8
|
||||
|
||||
|
||||
/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
|
||||
|
||||
/* chip timers frequency constants */
|
||||
#define TIMERS_TICK_SIZE_CHIP (1e-3)
|
||||
|
||||
/* used in toe: TsRecentAge, MaxRt, and temporarily RTT */
|
||||
#define TSEMI_CLK1_RESUL_CHIP (1e-3)
|
||||
|
||||
/* temporarily used for RTT */
|
||||
#define XSEMI_CLK1_RESUL_CHIP (1e-3)
|
||||
|
||||
/* used for Host Coallescing */
|
||||
#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
|
||||
|
||||
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
|
||||
|
||||
#define XSTORM_IP_ID_ROLL_HALF 0x8000
|
||||
#define XSTORM_IP_ID_ROLL_ALL 0
|
||||
|
||||
/* assert list: number of entries */
|
||||
#define FW_LOG_LIST_SIZE 50
|
||||
|
||||
#define NUM_OF_SAFC_BITS 16
|
||||
#define MAX_COS_NUMBER 4
|
||||
#define MAX_TRAFFIC_TYPES 8
|
||||
#define MAX_PFC_PRIORITIES 8
|
||||
|
||||
/* used by array traffic_type_to_priority[] to mark traffic type \
|
||||
that is not mapped to priority*/
|
||||
#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
|
||||
|
||||
/* Event Ring definitions */
|
||||
#define C_ERES_PER_PAGE \
|
||||
(PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))
|
||||
#define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)
|
||||
|
||||
/* number of statistic command */
|
||||
#define STATS_QUERY_CMD_COUNT 16
|
||||
|
||||
/* niv list table size */
|
||||
#define AFEX_LIST_TABLE_SIZE 4096
|
||||
|
||||
/* invalid VNIC Id. used in VNIC classification */
|
||||
#define INVALID_VNIC_ID 0xFF
|
||||
|
||||
/* used for indicating an undefined RAM offset in the IRO arrays */
|
||||
#define UNDEF_IRO 0x80000000
|
||||
|
||||
/* used for defining the amount of FCoE tasks supported for PF */
|
||||
#define MAX_FCOE_FUNCS_PER_ENGINE 2
|
||||
#define MAX_NUM_FCOE_TASKS_PER_ENGINE \
|
||||
4096 /*Each port can have at max 1 function*/
|
||||
|
||||
|
||||
#endif /* ECORE_FW_DEFS_H */
|
||||
|
||||
6348
sys/dev/bxe/ecore_hsi.h
Normal file
6348
sys/dev/bxe/ecore_hsi.h
Normal file
File diff suppressed because it is too large
Load Diff
853
sys/dev/bxe/ecore_init.h
Normal file
853
sys/dev/bxe/ecore_init.h
Normal file
@ -0,0 +1,853 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#ifndef ECORE_INIT_H
|
||||
#define ECORE_INIT_H
|
||||
|
||||
/* Init operation types and structures */
|
||||
enum {
|
||||
OP_RD = 0x1, /* read a single register */
|
||||
OP_WR, /* write a single register */
|
||||
OP_SW, /* copy a string to the device */
|
||||
OP_ZR, /* clear memory */
|
||||
OP_ZP, /* unzip then copy with DMAE */
|
||||
OP_WR_64, /* write 64 bit pattern */
|
||||
OP_WB, /* copy a string using DMAE */
|
||||
#ifndef FW_ZIP_SUPPORT
|
||||
OP_FW, /* copy an array from fw data (only used with unzipped FW) */
|
||||
#endif
|
||||
OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
|
||||
OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */
|
||||
OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
|
||||
OP_IF_PHASE,
|
||||
OP_RT,
|
||||
OP_DELAY,
|
||||
OP_VERIFY,
|
||||
OP_MAX
|
||||
};
|
||||
|
||||
enum {
|
||||
STAGE_START,
|
||||
STAGE_END,
|
||||
};
|
||||
|
||||
/* Returns the index of start or end of a specific block stage in ops array*/
|
||||
#define BLOCK_OPS_IDX(block, stage, end) \
|
||||
(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
|
||||
|
||||
|
||||
/* structs for the various opcodes */
|
||||
struct raw_op {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t raw_data;
|
||||
};
|
||||
|
||||
struct op_read {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
struct op_write {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
struct op_arr_write {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
#ifdef __BIG_ENDIAN
|
||||
uint16_t data_len;
|
||||
uint16_t data_off;
|
||||
#else /* __LITTLE_ENDIAN */
|
||||
uint16_t data_off;
|
||||
uint16_t data_len;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct op_zero {
|
||||
uint32_t op:8;
|
||||
uint32_t offset:24;
|
||||
uint32_t len;
|
||||
};
|
||||
|
||||
struct op_if_mode {
|
||||
uint32_t op:8;
|
||||
uint32_t cmd_offset:24;
|
||||
uint32_t mode_bit_map;
|
||||
};
|
||||
|
||||
struct op_if_phase {
|
||||
uint32_t op:8;
|
||||
uint32_t cmd_offset:24;
|
||||
uint32_t phase_bit_map;
|
||||
};
|
||||
|
||||
struct op_delay {
|
||||
uint32_t op:8;
|
||||
uint32_t reserved:24;
|
||||
uint32_t delay;
|
||||
};
|
||||
|
||||
union init_op {
|
||||
struct op_read read;
|
||||
struct op_write write;
|
||||
struct op_arr_write arr_wr;
|
||||
struct op_zero zero;
|
||||
struct raw_op raw;
|
||||
struct op_if_mode if_mode;
|
||||
struct op_if_phase if_phase;
|
||||
struct op_delay delay;
|
||||
};
|
||||
|
||||
|
||||
/* Init Phases */
|
||||
enum {
|
||||
PHASE_COMMON,
|
||||
PHASE_PORT0,
|
||||
PHASE_PORT1,
|
||||
PHASE_PF0,
|
||||
PHASE_PF1,
|
||||
PHASE_PF2,
|
||||
PHASE_PF3,
|
||||
PHASE_PF4,
|
||||
PHASE_PF5,
|
||||
PHASE_PF6,
|
||||
PHASE_PF7,
|
||||
NUM_OF_INIT_PHASES
|
||||
};
|
||||
|
||||
/* Init Modes */
|
||||
enum {
|
||||
MODE_ASIC = 0x00000001,
|
||||
MODE_FPGA = 0x00000002,
|
||||
MODE_EMUL = 0x00000004,
|
||||
MODE_E2 = 0x00000008,
|
||||
MODE_E3 = 0x00000010,
|
||||
MODE_PORT2 = 0x00000020,
|
||||
MODE_PORT4 = 0x00000040,
|
||||
MODE_SF = 0x00000080,
|
||||
MODE_MF = 0x00000100,
|
||||
MODE_MF_SD = 0x00000200,
|
||||
MODE_MF_SI = 0x00000400,
|
||||
MODE_MF_AFEX = 0x00000800,
|
||||
MODE_E3_A0 = 0x00001000,
|
||||
MODE_E3_B0 = 0x00002000,
|
||||
MODE_COS3 = 0x00004000,
|
||||
MODE_COS6 = 0x00008000,
|
||||
MODE_LITTLE_ENDIAN = 0x00010000,
|
||||
MODE_BIG_ENDIAN = 0x00020000,
|
||||
};
|
||||
|
||||
/* Init Blocks */
|
||||
enum {
|
||||
BLOCK_ATC,
|
||||
BLOCK_BRB1,
|
||||
BLOCK_CCM,
|
||||
BLOCK_CDU,
|
||||
BLOCK_CFC,
|
||||
BLOCK_CSDM,
|
||||
BLOCK_CSEM,
|
||||
BLOCK_DBG,
|
||||
BLOCK_DMAE,
|
||||
BLOCK_DORQ,
|
||||
BLOCK_HC,
|
||||
BLOCK_IGU,
|
||||
BLOCK_MISC,
|
||||
BLOCK_NIG,
|
||||
BLOCK_PBF,
|
||||
BLOCK_PGLUE_B,
|
||||
BLOCK_PRS,
|
||||
BLOCK_PXP2,
|
||||
BLOCK_PXP,
|
||||
BLOCK_QM,
|
||||
BLOCK_SRC,
|
||||
BLOCK_TCM,
|
||||
BLOCK_TM,
|
||||
BLOCK_TSDM,
|
||||
BLOCK_TSEM,
|
||||
BLOCK_UCM,
|
||||
BLOCK_UPB,
|
||||
BLOCK_USDM,
|
||||
BLOCK_USEM,
|
||||
BLOCK_XCM,
|
||||
BLOCK_XPB,
|
||||
BLOCK_XSDM,
|
||||
BLOCK_XSEM,
|
||||
BLOCK_MISC_AEU,
|
||||
NUM_OF_INIT_BLOCKS
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Vnics per mode */
|
||||
#define ECORE_PORT2_MODE_NUM_VNICS 4
|
||||
|
||||
|
||||
/* QM queue numbers */
|
||||
#define ECORE_ETH_Q 0
|
||||
#define ECORE_TOE_Q 3
|
||||
#define ECORE_TOE_ACK_Q 6
|
||||
#define ECORE_ISCSI_Q 9
|
||||
#define ECORE_ISCSI_ACK_Q 11
|
||||
#define ECORE_FCOE_Q 10
|
||||
|
||||
/* Vnics per mode */
|
||||
#define ECORE_PORT4_MODE_NUM_VNICS 2
|
||||
|
||||
/* COS offset for port1 in E3 B0 4port mode */
|
||||
#define ECORE_E3B0_PORT1_COS_OFFSET 3
|
||||
|
||||
/* QM Register addresses */
|
||||
#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\
|
||||
(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
|
||||
#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\
|
||||
(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
|
||||
#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\
|
||||
(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
|
||||
|
||||
/* extracts the QM queue number for the specified port and vnic */
|
||||
#define ECORE_PF_Q_NUM(q_num, port, vnic)\
|
||||
((((port) << 1) | (vnic)) * 16 + (q_num))
|
||||
|
||||
|
||||
/* Maps the specified queue to the specified COS */
|
||||
static inline void ecore_map_q_cos(struct bxe_softc *sc, uint32_t q_num, uint32_t new_cos)
|
||||
{
|
||||
/* find current COS mapping */
|
||||
uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);
|
||||
|
||||
/* check if queue->COS mapping has changed */
|
||||
if (curr_cos != new_cos) {
|
||||
uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;
|
||||
uint32_t reg_addr, reg_bit_map, vnic;
|
||||
|
||||
/* update parameters for 4port mode */
|
||||
if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
|
||||
num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
|
||||
if (PORT_ID(sc)) {
|
||||
curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
|
||||
new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
|
||||
}
|
||||
}
|
||||
|
||||
/* change queue mapping for each VNIC */
|
||||
for (vnic = 0; vnic < num_vnics; vnic++) {
|
||||
uint32_t pf_q_num =
|
||||
ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
|
||||
uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
|
||||
|
||||
/* overwrite queue->VOQ mapping */
|
||||
REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
|
||||
|
||||
/* clear queue bit from current COS bit map */
|
||||
reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
|
||||
reg_bit_map = REG_RD(sc, reg_addr);
|
||||
REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
|
||||
|
||||
/* set queue bit in new COS bit map */
|
||||
reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
|
||||
reg_bit_map = REG_RD(sc, reg_addr);
|
||||
REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
|
||||
|
||||
/* set/clear queue bit in command-queue bit map
|
||||
(E2/E3A0 only, valid COS values are 0/1) */
|
||||
if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) {
|
||||
reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);
|
||||
reg_bit_map = REG_RD(sc, reg_addr);
|
||||
q_bit_map = 1 << (2 * (pf_q_num & 0xf));
|
||||
reg_bit_map = new_cos ?
|
||||
(reg_bit_map | q_bit_map) :
|
||||
(reg_bit_map & (~q_bit_map));
|
||||
REG_WR(sc, reg_addr, reg_bit_map);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Configures the QM according to the specified per-traffic-type COSes */
|
||||
static inline void ecore_dcb_config_qm(struct bxe_softc *sc, enum cos_mode mode,
|
||||
struct priority_cos *traffic_cos)
|
||||
{
|
||||
ecore_map_q_cos(sc, ECORE_FCOE_Q,
|
||||
traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
|
||||
ecore_map_q_cos(sc, ECORE_ISCSI_Q,
|
||||
traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
|
||||
ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q,
|
||||
traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
|
||||
if (mode != STATIC_COS) {
|
||||
/* required only in OVERRIDE_COS mode */
|
||||
ecore_map_q_cos(sc, ECORE_ETH_Q,
|
||||
traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
|
||||
ecore_map_q_cos(sc, ECORE_TOE_Q,
|
||||
traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
|
||||
ecore_map_q_cos(sc, ECORE_TOE_ACK_Q,
|
||||
traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* congestion managment port init api description
|
||||
* the api works as follows:
|
||||
* the driver should pass the cmng_init_input struct, the port_init function
|
||||
* will prepare the required internal ram structure which will be passed back
|
||||
* to the driver (cmng_init) that will write it into the internal ram.
|
||||
*
|
||||
* IMPORTANT REMARKS:
|
||||
* 1. the cmng_init struct does not represent the contiguous internal ram
|
||||
* structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
|
||||
* offset in order to write the port sub struct and the
|
||||
* PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
|
||||
* words - don't use memcpy!).
|
||||
* 2. although the cmng_init struct is filled for the maximal vnic number
|
||||
* possible, the driver should only write the valid vnics into the internal
|
||||
* ram according to the appropriate port mode.
|
||||
*/
|
||||
#define BITS_TO_BYTES(x) ((x)/8)
|
||||
|
||||
/* CMNG constants, as derived from system spec calculations */
|
||||
|
||||
/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
|
||||
#define DEF_MIN_RATE 100
|
||||
|
||||
/* resolution of the rate shaping timer - 400 usec */
|
||||
#define RS_PERIODIC_TIMEOUT_USEC 400
|
||||
|
||||
/*
|
||||
* number of bytes in single QM arbitration cycle -
|
||||
* coefficient for calculating the fairness timer
|
||||
*/
|
||||
#define QM_ARB_BYTES 160000
|
||||
|
||||
/* resolution of Min algorithm 1:100 */
|
||||
#define MIN_RES 100
|
||||
|
||||
/*
|
||||
* how many bytes above threshold for
|
||||
* the minimal credit of Min algorithm
|
||||
*/
|
||||
#define MIN_ABOVE_THRESH 32768
|
||||
|
||||
/*
|
||||
* Fairness algorithm integration time coefficient -
|
||||
* for calculating the actual Tfair
|
||||
*/
|
||||
#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
|
||||
|
||||
/* Memory of fairness algorithm - 2 cycles */
|
||||
#define FAIR_MEM 2
|
||||
#define SAFC_TIMEOUT_USEC 52
|
||||
|
||||
#define SDM_TICKS 4
|
||||
|
||||
|
||||
static inline void ecore_init_max(const struct cmng_init_input *input_data,
|
||||
uint32_t r_param, struct cmng_init *ram_data)
|
||||
{
|
||||
uint32_t vnic;
|
||||
struct cmng_vnic *vdata = &ram_data->vnic;
|
||||
struct cmng_struct_per_port *pdata = &ram_data->port;
|
||||
/*
|
||||
* rate shaping per-port variables
|
||||
* 100 micro seconds in SDM ticks = 25
|
||||
* since each tick is 4 microSeconds
|
||||
*/
|
||||
|
||||
pdata->rs_vars.rs_periodic_timeout =
|
||||
RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
|
||||
|
||||
/* this is the threshold below which no timer arming will occur.
|
||||
* 1.25 coefficient is for the threshold to be a little bigger
|
||||
* then the real time to compensate for timer in-accuracy
|
||||
*/
|
||||
pdata->rs_vars.rs_threshold =
|
||||
(5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
|
||||
|
||||
/* rate shaping per-vnic variables */
|
||||
for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
|
||||
/* global vnic counter */
|
||||
vdata->vnic_max_rate[vnic].vn_counter.rate =
|
||||
input_data->vnic_max_rate[vnic];
|
||||
/*
|
||||
* maximal Mbps for this vnic
|
||||
* the quota in each timer period - number of bytes
|
||||
* transmitted in this period
|
||||
*/
|
||||
vdata->vnic_max_rate[vnic].vn_counter.quota =
|
||||
RS_PERIODIC_TIMEOUT_USEC *
|
||||
(uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate,
|
||||
struct rate_shaping_vars_per_vn *ram_data)
|
||||
{
|
||||
/* global vnic counter */
|
||||
ram_data->vn_counter.rate = vnic_max_rate;
|
||||
|
||||
/*
|
||||
* maximal Mbps for this vnic
|
||||
* the quota in each timer period - number of bytes
|
||||
* transmitted in this period
|
||||
*/
|
||||
ram_data->vn_counter.quota =
|
||||
RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8;
|
||||
}
|
||||
|
||||
static inline void ecore_init_min(const struct cmng_init_input *input_data,
|
||||
uint32_t r_param, struct cmng_init *ram_data)
|
||||
{
|
||||
uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
|
||||
struct cmng_vnic *vdata = &ram_data->vnic;
|
||||
struct cmng_struct_per_port *pdata = &ram_data->port;
|
||||
|
||||
/* this is the resolution of the fairness timer */
|
||||
fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
|
||||
|
||||
/*
|
||||
* fairness per-port variables
|
||||
* for 10G it is 1000usec. for 1G it is 10000usec.
|
||||
*/
|
||||
tFair = T_FAIR_COEF / input_data->port_rate;
|
||||
|
||||
/* this is the threshold below which we won't arm the timer anymore */
|
||||
pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
|
||||
|
||||
/*
|
||||
* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
|
||||
* to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
|
||||
*/
|
||||
pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
|
||||
|
||||
/* since each tick is 4 microSeconds */
|
||||
pdata->fair_vars.fairness_timeout =
|
||||
fair_periodic_timeout_usec / SDM_TICKS;
|
||||
|
||||
/* calculate sum of weights */
|
||||
vnicWeightSum = 0;
|
||||
|
||||
for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++)
|
||||
vnicWeightSum += input_data->vnic_min_rate[vnic];
|
||||
|
||||
/* global vnic counter */
|
||||
if (vnicWeightSum > 0) {
|
||||
/* fairness per-vnic variables */
|
||||
for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
|
||||
/*
|
||||
* this is the credit for each period of the fairness
|
||||
* algorithm - number of bytes in T_FAIR (this vnic
|
||||
* share of the port rate)
|
||||
*/
|
||||
vdata->vnic_min_rate[vnic].vn_credit_delta =
|
||||
((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 *
|
||||
(T_FAIR_COEF / (8 * 100 * vnicWeightSum)));
|
||||
if (vdata->vnic_min_rate[vnic].vn_credit_delta <
|
||||
pdata->fair_vars.fair_threshold +
|
||||
MIN_ABOVE_THRESH) {
|
||||
vdata->vnic_min_rate[vnic].vn_credit_delta =
|
||||
pdata->fair_vars.fair_threshold +
|
||||
MIN_ABOVE_THRESH;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
|
||||
uint32_t r_param, struct cmng_init *ram_data)
|
||||
{
|
||||
uint32_t vnic, cos;
|
||||
uint32_t cosWeightSum = 0;
|
||||
struct cmng_vnic *vdata = &ram_data->vnic;
|
||||
struct cmng_struct_per_port *pdata = &ram_data->port;
|
||||
|
||||
for (cos = 0; cos < MAX_COS_NUMBER; cos++)
|
||||
cosWeightSum += input_data->cos_min_rate[cos];
|
||||
|
||||
if (cosWeightSum > 0) {
|
||||
|
||||
for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
|
||||
/*
|
||||
* Since cos and vnic shouldn't work together the rate
|
||||
* to divide between the coses is the port rate.
|
||||
*/
|
||||
uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
|
||||
for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
|
||||
/*
|
||||
* this is the credit for each period of
|
||||
* the fairness algorithm - number of bytes
|
||||
* in T_FAIR (this cos share of the vnic rate)
|
||||
*/
|
||||
ccd[cos] =
|
||||
((uint32_t)input_data->cos_min_rate[cos] * 100 *
|
||||
(T_FAIR_COEF / (8 * 100 * cosWeightSum)));
|
||||
if (ccd[cos] < pdata->fair_vars.fair_threshold
|
||||
+ MIN_ABOVE_THRESH) {
|
||||
ccd[cos] =
|
||||
pdata->fair_vars.fair_threshold +
|
||||
MIN_ABOVE_THRESH;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void ecore_init_safc(const struct cmng_init_input *input_data,
|
||||
struct cmng_init *ram_data)
|
||||
{
|
||||
/* in microSeconds */
|
||||
ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
|
||||
}
|
||||
|
||||
/* Congestion management port init */
|
||||
static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
|
||||
struct cmng_init *ram_data)
|
||||
{
|
||||
uint32_t r_param;
|
||||
ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
|
||||
|
||||
ram_data->port.flags = input_data->flags;
|
||||
|
||||
/*
|
||||
* number of bytes transmitted in a rate of 10Gbps
|
||||
* in one usec = 1.25KB.
|
||||
*/
|
||||
r_param = BITS_TO_BYTES(input_data->port_rate);
|
||||
ecore_init_max(input_data, r_param, ram_data);
|
||||
ecore_init_min(input_data, r_param, ram_data);
|
||||
ecore_init_fw_wrr(input_data, r_param, ram_data);
|
||||
ecore_init_safc(input_data, ram_data);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* Returns the index of start or end of a specific block stage in ops array*/
|
||||
#define BLOCK_OPS_IDX(block, stage, end) \
|
||||
(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
|
||||
|
||||
|
||||
#define INITOP_SET 0 /* set the HW directly */
|
||||
#define INITOP_CLEAR 1 /* clear the HW directly */
|
||||
#define INITOP_INIT 2 /* set the init-value array */
|
||||
|
||||
/****************************************************************************
|
||||
* ILT management
|
||||
****************************************************************************/
|
||||
struct ilt_line {
|
||||
ecore_dma_addr_t page_mapping;
|
||||
void *page;
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
struct ilt_client_info {
|
||||
uint32_t page_size;
|
||||
uint16_t start;
|
||||
uint16_t end;
|
||||
uint16_t client_num;
|
||||
uint16_t flags;
|
||||
#define ILT_CLIENT_SKIP_INIT 0x1
|
||||
#define ILT_CLIENT_SKIP_MEM 0x2
|
||||
};
|
||||
|
||||
struct ecore_ilt {
|
||||
uint32_t start_line;
|
||||
struct ilt_line *lines;
|
||||
struct ilt_client_info clients[4];
|
||||
#define ILT_CLIENT_CDU 0
|
||||
#define ILT_CLIENT_QM 1
|
||||
#define ILT_CLIENT_SRC 2
|
||||
#define ILT_CLIENT_TM 3
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* SRC configuration
|
||||
****************************************************************************/
|
||||
struct src_ent {
|
||||
uint8_t opaque[56];
|
||||
uint64_t next;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Parity configuration
|
||||
****************************************************************************/
|
||||
#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
|
||||
{ \
|
||||
block##_REG_##block##_PRTY_MASK, \
|
||||
block##_REG_##block##_PRTY_STS_CLR, \
|
||||
en_mask, {m1, m1h, m2, m3}, #block \
|
||||
}
|
||||
|
||||
#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
|
||||
{ \
|
||||
block##_REG_##block##_PRTY_MASK_0, \
|
||||
block##_REG_##block##_PRTY_STS_CLR_0, \
|
||||
en_mask, {m1, m1h, m2, m3}, #block"_0" \
|
||||
}
|
||||
|
||||
#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
|
||||
{ \
|
||||
block##_REG_##block##_PRTY_MASK_1, \
|
||||
block##_REG_##block##_PRTY_STS_CLR_1, \
|
||||
en_mask, {m1, m1h, m2, m3}, #block"_1" \
|
||||
}
|
||||
|
||||
static const struct {
|
||||
uint32_t mask_addr;
|
||||
uint32_t sts_clr_addr;
|
||||
uint32_t en_mask; /* Mask to enable parity attentions */
|
||||
struct {
|
||||
uint32_t e1; /* 57710 */
|
||||
uint32_t e1h; /* 57711 */
|
||||
uint32_t e2; /* 57712 */
|
||||
uint32_t e3; /* 578xx */
|
||||
} reg_mask; /* Register mask (all valid bits) */
|
||||
char name[8]; /* Block's longest name is 7 characters long
|
||||
* (name + suffix)
|
||||
*/
|
||||
} ecore_blocks_parity_data[] = {
|
||||
/* bit 19 masked */
|
||||
/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
|
||||
/* bit 5,18,20-31 */
|
||||
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
|
||||
/* bit 5 */
|
||||
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
|
||||
/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
|
||||
/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
|
||||
|
||||
/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
|
||||
* want to handle "system kill" flow at the moment.
|
||||
*/
|
||||
BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
|
||||
0x7ffffff),
|
||||
BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
|
||||
BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
|
||||
BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
|
||||
BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
|
||||
BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
|
||||
BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
|
||||
BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
|
||||
BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
|
||||
BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
|
||||
{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
|
||||
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
|
||||
{0xf, 0xf, 0xf, 0xf}, "UPB"},
|
||||
{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
|
||||
GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
|
||||
{0xf, 0xf, 0xf, 0xf}, "XPB"},
|
||||
BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
|
||||
BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
|
||||
BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
|
||||
BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
|
||||
BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
|
||||
BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
|
||||
BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
|
||||
BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
|
||||
BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
|
||||
BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
||||
BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
|
||||
BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
|
||||
BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
|
||||
BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
|
||||
BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
|
||||
BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
|
||||
BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
|
||||
BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff),
|
||||
BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
|
||||
};
|
||||
|
||||
|
||||
/* [28] MCP Latched rom_parity
|
||||
* [29] MCP Latched ump_rx_parity
|
||||
* [30] MCP Latched ump_tx_parity
|
||||
* [31] MCP Latched scpad_parity
|
||||
*/
|
||||
#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
|
||||
(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
|
||||
|
||||
/* Below registers control the MCP parity attention output. When
|
||||
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
|
||||
* enabled, when cleared - disabled.
|
||||
*/
|
||||
static const uint32_t mcp_attn_ctl_regs[] = {
|
||||
MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
|
||||
MISC_REG_AEU_ENABLE4_NIG_0,
|
||||
MISC_REG_AEU_ENABLE4_PXP_0,
|
||||
MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
|
||||
MISC_REG_AEU_ENABLE4_NIG_1,
|
||||
MISC_REG_AEU_ENABLE4_PXP_1
|
||||
};
|
||||
|
||||
static inline void ecore_set_mcp_parity(struct bxe_softc *sc, uint8_t enable)
|
||||
{
|
||||
int i;
|
||||
uint32_t reg_val;
|
||||
|
||||
for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
|
||||
reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
|
||||
|
||||
if (enable)
|
||||
reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
|
||||
else
|
||||
reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
|
||||
|
||||
REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint32_t ecore_parity_reg_mask(struct bxe_softc *sc, int idx)
|
||||
{
|
||||
if (CHIP_IS_E1(sc))
|
||||
return ecore_blocks_parity_data[idx].reg_mask.e1;
|
||||
else if (CHIP_IS_E1H(sc))
|
||||
return ecore_blocks_parity_data[idx].reg_mask.e1h;
|
||||
else if (CHIP_IS_E2(sc))
|
||||
return ecore_blocks_parity_data[idx].reg_mask.e2;
|
||||
else /* CHIP_IS_E3 */
|
||||
return ecore_blocks_parity_data[idx].reg_mask.e3;
|
||||
}
|
||||
|
||||
static inline void ecore_disable_blocks_parity(struct bxe_softc *sc)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
|
||||
uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
|
||||
|
||||
if (dis_mask) {
|
||||
REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
|
||||
dis_mask);
|
||||
ECORE_MSG(sc, "Setting parity mask "
|
||||
"for %s to\t\t0x%x\n",
|
||||
ecore_blocks_parity_data[i].name, dis_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable MCP parity attentions */
|
||||
ecore_set_mcp_parity(sc, FALSE);
|
||||
}
|
||||
|
||||
/**
|
||||
* Clear the parity error status registers.
|
||||
*/
|
||||
static inline void ecore_clear_blocks_parity(struct bxe_softc *sc)
|
||||
{
|
||||
int i;
|
||||
uint32_t reg_val, mcp_aeu_bits =
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
|
||||
|
||||
/* Clear SEM_FAST parities */
|
||||
REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
||||
REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
||||
REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
||||
REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
||||
|
||||
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
|
||||
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
|
||||
|
||||
if (reg_mask) {
|
||||
reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
|
||||
sts_clr_addr);
|
||||
if (reg_val & reg_mask)
|
||||
ECORE_MSG(sc,
|
||||
"Parity errors in %s: 0x%x\n",
|
||||
ecore_blocks_parity_data[i].name,
|
||||
reg_val & reg_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if there were parity attentions in MCP */
|
||||
reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
|
||||
if (reg_val & mcp_aeu_bits)
|
||||
ECORE_MSG(sc, "Parity error in MCP: 0x%x\n",
|
||||
reg_val & mcp_aeu_bits);
|
||||
|
||||
/* Clear parity attentions in MCP:
|
||||
* [7] clears Latched rom_parity
|
||||
* [8] clears Latched ump_rx_parity
|
||||
* [9] clears Latched ump_tx_parity
|
||||
* [10] clears Latched scpad_parity (both ports)
|
||||
*/
|
||||
REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
|
||||
}
|
||||
|
||||
static inline void ecore_enable_blocks_parity(struct bxe_softc *sc)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
|
||||
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
|
||||
|
||||
if (reg_mask)
|
||||
REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
|
||||
ecore_blocks_parity_data[i].en_mask & reg_mask);
|
||||
}
|
||||
|
||||
/* Enable MCP parity attentions */
|
||||
ecore_set_mcp_parity(sc, TRUE);
|
||||
}
|
||||
|
||||
|
||||
#endif /* ECORE_INIT_H */
|
||||
|
||||
975
sys/dev/bxe/ecore_init_ops.h
Normal file
975
sys/dev/bxe/ecore_init_ops.h
Normal file
@ -0,0 +1,975 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#ifndef ECORE_INIT_OPS_H
|
||||
#define ECORE_INIT_OPS_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static int ecore_gunzip(struct bxe_softc *sc, const uint8_t *zbuf, int len);
|
||||
static void ecore_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val);
|
||||
static void ecore_write_dmae_phys_len(struct bxe_softc *sc,
|
||||
ecore_dma_addr_t phys_addr, uint32_t addr,
|
||||
uint32_t len);
|
||||
|
||||
static void ecore_init_str_wr(struct bxe_softc *sc, uint32_t addr,
|
||||
const uint32_t *data, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
REG_WR(sc, addr + i*4, data[i]);
|
||||
}
|
||||
|
||||
static void ecore_init_ind_wr(struct bxe_softc *sc, uint32_t addr,
|
||||
const uint32_t *data, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
ecore_reg_wr_ind(sc, addr + i*4, data[i]);
|
||||
}
|
||||
|
||||
static void ecore_write_big_buf(struct bxe_softc *sc, uint32_t addr, uint32_t len,
|
||||
uint8_t wb)
|
||||
{
|
||||
if (DMAE_READY(sc))
|
||||
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
|
||||
|
||||
/* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
|
||||
else if (wb && CHIP_IS_E1(sc))
|
||||
ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
|
||||
|
||||
/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
|
||||
else
|
||||
ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
|
||||
}
|
||||
|
||||
static void ecore_init_fill(struct bxe_softc *sc, uint32_t addr, int fill,
|
||||
uint32_t len, uint8_t wb)
|
||||
{
|
||||
uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
|
||||
uint32_t buf_len32 = buf_len/4;
|
||||
uint32_t i;
|
||||
|
||||
ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len);
|
||||
|
||||
for (i = 0; i < len; i += buf_len32) {
|
||||
uint32_t cur_len = min(buf_len32, len - i);
|
||||
|
||||
ecore_write_big_buf(sc, addr + i*4, cur_len, wb);
|
||||
}
|
||||
}
|
||||
|
||||
static void ecore_write_big_buf_wb(struct bxe_softc *sc, uint32_t addr, uint32_t len)
|
||||
{
|
||||
if (DMAE_READY(sc))
|
||||
ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
|
||||
|
||||
/* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
|
||||
else if (CHIP_IS_E1(sc))
|
||||
ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
|
||||
|
||||
/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
|
||||
else
|
||||
ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
|
||||
}
|
||||
|
||||
static void ecore_init_wr_64(struct bxe_softc *sc, uint32_t addr,
|
||||
const uint32_t *data, uint32_t len64)
|
||||
{
|
||||
uint32_t buf_len32 = FW_BUF_SIZE/4;
|
||||
uint32_t len = len64*2;
|
||||
uint64_t data64 = 0;
|
||||
uint32_t i;
|
||||
|
||||
/* 64 bit value is in a blob: first low DWORD, then high DWORD */
|
||||
data64 = HILO_U64((*(data + 1)), (*data));
|
||||
|
||||
len64 = min((uint32_t)(FW_BUF_SIZE/8), len64);
|
||||
for (i = 0; i < len64; i++) {
|
||||
uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i;
|
||||
|
||||
*pdata = data64;
|
||||
}
|
||||
|
||||
for (i = 0; i < len; i += buf_len32) {
|
||||
uint32_t cur_len = min(buf_len32, len - i);
|
||||
|
||||
ecore_write_big_buf_wb(sc, addr + i*4, cur_len);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************
|
||||
There are different blobs for each PRAM section.
|
||||
In addition, each blob write operation is divided into a few operations
|
||||
in order to decrease the amount of phys. contiguous buffer needed.
|
||||
Thus, when we select a blob the address may be with some offset
|
||||
from the beginning of PRAM section.
|
||||
The same holds for the INT_TABLE sections.
|
||||
**********************************************************/
|
||||
#define IF_IS_INT_TABLE_ADDR(base, addr) \
|
||||
if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
|
||||
|
||||
#define IF_IS_PRAM_ADDR(base, addr) \
|
||||
if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
|
||||
|
||||
static const uint8_t *ecore_sel_blob(struct bxe_softc *sc, uint32_t addr,
|
||||
const uint8_t *data)
|
||||
{
|
||||
IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
|
||||
data = INIT_TSEM_INT_TABLE_DATA(sc);
|
||||
else
|
||||
IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
|
||||
data = INIT_CSEM_INT_TABLE_DATA(sc);
|
||||
else
|
||||
IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
|
||||
data = INIT_USEM_INT_TABLE_DATA(sc);
|
||||
else
|
||||
IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
|
||||
data = INIT_XSEM_INT_TABLE_DATA(sc);
|
||||
else
|
||||
IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
|
||||
data = INIT_TSEM_PRAM_DATA(sc);
|
||||
else
|
||||
IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
|
||||
data = INIT_CSEM_PRAM_DATA(sc);
|
||||
else
|
||||
IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
|
||||
data = INIT_USEM_PRAM_DATA(sc);
|
||||
else
|
||||
IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
|
||||
data = INIT_XSEM_PRAM_DATA(sc);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static void ecore_init_wr_wb(struct bxe_softc *sc, uint32_t addr,
|
||||
const uint32_t *data, uint32_t len)
|
||||
{
|
||||
if (DMAE_READY(sc))
|
||||
VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
|
||||
|
||||
/* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
|
||||
else if (CHIP_IS_E1(sc))
|
||||
ecore_init_ind_wr(sc, addr, data, len);
|
||||
|
||||
/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
|
||||
else
|
||||
ecore_init_str_wr(sc, addr, data, len);
|
||||
}
|
||||
|
||||
#ifndef FW_ZIP_SUPPORT
|
||||
static void ecore_init_fw(struct bxe_softc *sc, uint32_t addr, uint32_t len)
|
||||
{
|
||||
const uint8_t *data = NULL;
|
||||
|
||||
data = ecore_sel_blob(sc, addr, (const uint8_t *)data);
|
||||
|
||||
if (DMAE_READY(sc))
|
||||
VIRT_WR_DMAE_LEN(sc, data, addr, len, 1);
|
||||
|
||||
/* in E1 BIOS initiated ZLR may interrupt widebus writes */
|
||||
else if (CHIP_IS_E1(sc))
|
||||
ecore_init_ind_wr(sc, addr, (const uint32_t *)data, len);
|
||||
|
||||
/* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
|
||||
else
|
||||
ecore_init_str_wr(sc, addr, (const uint32_t *)data, len);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void ecore_wr_64(struct bxe_softc *sc, uint32_t reg, uint32_t val_lo,
|
||||
uint32_t val_hi)
|
||||
{
|
||||
uint32_t wb_write[2];
|
||||
|
||||
wb_write[0] = val_lo;
|
||||
wb_write[1] = val_hi;
|
||||
REG_WR_DMAE_LEN(sc, reg, wb_write, 2);
|
||||
}
|
||||
|
||||
static void ecore_init_wr_zp(struct bxe_softc *sc, uint32_t addr, uint32_t len,
|
||||
uint32_t blob_off)
|
||||
{
|
||||
const uint8_t *data = NULL;
|
||||
int rc;
|
||||
uint32_t i;
|
||||
|
||||
data = ecore_sel_blob(sc, addr, data) + blob_off*4;
|
||||
|
||||
rc = ecore_gunzip(sc, data, len);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
/* gunzip_outlen is in dwords */
|
||||
len = GUNZIP_OUTLEN(sc);
|
||||
for (i = 0; i < len; i++)
|
||||
((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t)
|
||||
ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]);
|
||||
|
||||
ecore_write_big_buf_wb(sc, addr, len);
|
||||
}
|
||||
|
||||
static void ecore_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
|
||||
{
|
||||
uint16_t op_start =
|
||||
INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
|
||||
STAGE_START)];
|
||||
uint16_t op_end =
|
||||
INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
|
||||
STAGE_END)];
|
||||
const union init_op *op;
|
||||
uint32_t op_idx, op_type, addr, len;
|
||||
const uint32_t *data, *data_base;
|
||||
|
||||
/* If empty block */
|
||||
if (op_start == op_end)
|
||||
return;
|
||||
|
||||
data_base = INIT_DATA(sc);
|
||||
|
||||
for (op_idx = op_start; op_idx < op_end; op_idx++) {
|
||||
|
||||
op = (const union init_op *)&(INIT_OPS(sc)[op_idx]);
|
||||
/* Get generic data */
|
||||
op_type = op->raw.op;
|
||||
addr = op->raw.offset;
|
||||
/* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
|
||||
* OP_WR64 (we assume that op_arr_write and op_write have the
|
||||
* same structure).
|
||||
*/
|
||||
len = op->arr_wr.data_len;
|
||||
data = data_base + op->arr_wr.data_off;
|
||||
|
||||
switch (op_type) {
|
||||
case OP_RD:
|
||||
REG_RD(sc, addr);
|
||||
break;
|
||||
case OP_WR:
|
||||
REG_WR(sc, addr, op->write.val);
|
||||
break;
|
||||
case OP_SW:
|
||||
ecore_init_str_wr(sc, addr, data, len);
|
||||
break;
|
||||
case OP_WB:
|
||||
ecore_init_wr_wb(sc, addr, data, len);
|
||||
break;
|
||||
#ifndef FW_ZIP_SUPPORT
|
||||
case OP_FW:
|
||||
ecore_init_fw(sc, addr, len);
|
||||
break;
|
||||
#endif
|
||||
case OP_ZR:
|
||||
ecore_init_fill(sc, addr, 0, op->zero.len, 0);
|
||||
break;
|
||||
case OP_WB_ZR:
|
||||
ecore_init_fill(sc, addr, 0, op->zero.len, 1);
|
||||
break;
|
||||
case OP_ZP:
|
||||
ecore_init_wr_zp(sc, addr, len,
|
||||
op->arr_wr.data_off);
|
||||
break;
|
||||
case OP_WR_64:
|
||||
ecore_init_wr_64(sc, addr, data, len);
|
||||
break;
|
||||
case OP_IF_MODE_AND:
|
||||
/* if any of the flags doesn't match, skip the
|
||||
* conditional block.
|
||||
*/
|
||||
if ((INIT_MODE_FLAGS(sc) &
|
||||
op->if_mode.mode_bit_map) !=
|
||||
op->if_mode.mode_bit_map)
|
||||
op_idx += op->if_mode.cmd_offset;
|
||||
break;
|
||||
case OP_IF_MODE_OR:
|
||||
/* if all the flags don't match, skip the conditional
|
||||
* block.
|
||||
*/
|
||||
if ((INIT_MODE_FLAGS(sc) &
|
||||
op->if_mode.mode_bit_map) == 0)
|
||||
op_idx += op->if_mode.cmd_offset;
|
||||
break;
|
||||
/* the following opcodes are unused at the moment. */
|
||||
case OP_IF_PHASE:
|
||||
case OP_RT:
|
||||
case OP_DELAY:
|
||||
case OP_VERIFY:
|
||||
default:
|
||||
/* Should never get here! */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* PXP Arbiter
|
||||
****************************************************************************/
|
||||
/*
|
||||
* This code configures the PCI read/write arbiter
|
||||
* which implements a weighted round robin
|
||||
* between the virtual queues in the chip.
|
||||
*
|
||||
* The values were derived for each PCI max payload and max request size.
|
||||
* since max payload and max request size are only known at run time,
|
||||
* this is done as a separate init stage.
|
||||
*/
|
||||
|
||||
#define NUM_WR_Q 13
|
||||
#define NUM_RD_Q 29
|
||||
#define MAX_RD_ORD 3
|
||||
#define MAX_WR_ORD 2
|
||||
|
||||
/* configuration for one arbiter queue */
|
||||
struct arb_line {
|
||||
int l;
|
||||
int add;
|
||||
int ubound;
|
||||
};
|
||||
|
||||
/* derived configuration for each read queue for each max request size */
|
||||
static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
|
||||
/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
|
||||
{ {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
|
||||
{ {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
|
||||
{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
|
||||
/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
|
||||
{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
|
||||
};
|
||||
|
||||
/* derived configuration for each write queue for each max request size */
|
||||
static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
|
||||
/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
|
||||
{ {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
|
||||
{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
|
||||
{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
|
||||
/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
|
||||
{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
|
||||
{ {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
|
||||
{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
|
||||
};
|
||||
|
||||
/* register addresses for read queues */
|
||||
static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
|
||||
/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND0},
|
||||
{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
|
||||
PXP2_REG_PSWRQ_BW_UB1},
|
||||
{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
|
||||
PXP2_REG_PSWRQ_BW_UB2},
|
||||
{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
|
||||
PXP2_REG_PSWRQ_BW_UB3},
|
||||
{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND4},
|
||||
{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND5},
|
||||
{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
|
||||
PXP2_REG_PSWRQ_BW_UB6},
|
||||
{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
|
||||
PXP2_REG_PSWRQ_BW_UB7},
|
||||
{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
|
||||
PXP2_REG_PSWRQ_BW_UB8},
|
||||
/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
|
||||
PXP2_REG_PSWRQ_BW_UB9},
|
||||
{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
|
||||
PXP2_REG_PSWRQ_BW_UB10},
|
||||
{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
|
||||
PXP2_REG_PSWRQ_BW_UB11},
|
||||
{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND12},
|
||||
{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND13},
|
||||
{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND14},
|
||||
{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND15},
|
||||
{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND16},
|
||||
{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND17},
|
||||
{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND18},
|
||||
/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND19},
|
||||
{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND20},
|
||||
{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND22},
|
||||
{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND23},
|
||||
{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND24},
|
||||
{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND25},
|
||||
{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND26},
|
||||
{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
|
||||
PXP2_REG_RQ_BW_RD_UBOUND27},
|
||||
{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
|
||||
PXP2_REG_PSWRQ_BW_UB28}
|
||||
};
|
||||
|
||||
/* register addresses for write queues */
|
||||
static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
|
||||
/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
|
||||
PXP2_REG_PSWRQ_BW_UB1},
|
||||
{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
|
||||
PXP2_REG_PSWRQ_BW_UB2},
|
||||
{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
|
||||
PXP2_REG_PSWRQ_BW_UB3},
|
||||
{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
|
||||
PXP2_REG_PSWRQ_BW_UB6},
|
||||
{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
|
||||
PXP2_REG_PSWRQ_BW_UB7},
|
||||
{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
|
||||
PXP2_REG_PSWRQ_BW_UB8},
|
||||
{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
|
||||
PXP2_REG_PSWRQ_BW_UB9},
|
||||
{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
|
||||
PXP2_REG_PSWRQ_BW_UB10},
|
||||
{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
|
||||
PXP2_REG_PSWRQ_BW_UB11},
|
||||
/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
|
||||
PXP2_REG_PSWRQ_BW_UB28},
|
||||
{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
|
||||
PXP2_REG_RQ_BW_WR_UBOUND29},
|
||||
{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
|
||||
PXP2_REG_RQ_BW_WR_UBOUND30}
|
||||
};
|
||||
|
||||
static void ecore_init_pxp_arb(struct bxe_softc *sc, int r_order,
|
||||
int w_order)
|
||||
{
|
||||
uint32_t val, i;
|
||||
|
||||
if (r_order > MAX_RD_ORD) {
|
||||
ECORE_MSG(sc, "read order of %d order adjusted to %d\n",
|
||||
r_order, MAX_RD_ORD);
|
||||
r_order = MAX_RD_ORD;
|
||||
}
|
||||
if (w_order > MAX_WR_ORD) {
|
||||
ECORE_MSG(sc, "write order of %d order adjusted to %d\n",
|
||||
w_order, MAX_WR_ORD);
|
||||
w_order = MAX_WR_ORD;
|
||||
}
|
||||
if (CHIP_REV_IS_FPGA(sc)) {
|
||||
ECORE_MSG(sc, "write order adjusted to 1 for FPGA\n");
|
||||
w_order = 0;
|
||||
}
|
||||
ECORE_MSG(sc, "read order %d write order %d\n", r_order, w_order);
|
||||
|
||||
for (i = 0; i < NUM_RD_Q-1; i++) {
|
||||
REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
|
||||
REG_WR(sc, read_arb_addr[i].add,
|
||||
read_arb_data[i][r_order].add);
|
||||
REG_WR(sc, read_arb_addr[i].ubound,
|
||||
read_arb_data[i][r_order].ubound);
|
||||
}
|
||||
|
||||
for (i = 0; i < NUM_WR_Q-1; i++) {
|
||||
if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
|
||||
(write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
|
||||
|
||||
REG_WR(sc, write_arb_addr[i].l,
|
||||
write_arb_data[i][w_order].l);
|
||||
|
||||
REG_WR(sc, write_arb_addr[i].add,
|
||||
write_arb_data[i][w_order].add);
|
||||
|
||||
REG_WR(sc, write_arb_addr[i].ubound,
|
||||
write_arb_data[i][w_order].ubound);
|
||||
} else {
|
||||
|
||||
val = REG_RD(sc, write_arb_addr[i].l);
|
||||
REG_WR(sc, write_arb_addr[i].l,
|
||||
val | (write_arb_data[i][w_order].l << 10));
|
||||
|
||||
val = REG_RD(sc, write_arb_addr[i].add);
|
||||
REG_WR(sc, write_arb_addr[i].add,
|
||||
val | (write_arb_data[i][w_order].add << 10));
|
||||
|
||||
val = REG_RD(sc, write_arb_addr[i].ubound);
|
||||
REG_WR(sc, write_arb_addr[i].ubound,
|
||||
val | (write_arb_data[i][w_order].ubound << 7));
|
||||
}
|
||||
}
|
||||
|
||||
val = write_arb_data[NUM_WR_Q-1][w_order].add;
|
||||
val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
|
||||
val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
|
||||
REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
|
||||
|
||||
val = read_arb_data[NUM_RD_Q-1][r_order].add;
|
||||
val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
|
||||
val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
|
||||
REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
|
||||
|
||||
REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
|
||||
REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
|
||||
REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
|
||||
REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
|
||||
|
||||
if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
|
||||
REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
|
||||
|
||||
if (CHIP_IS_E3(sc))
|
||||
REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
|
||||
else if (CHIP_IS_E2(sc))
|
||||
REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
|
||||
else
|
||||
REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
|
||||
|
||||
if (!CHIP_IS_E1(sc)) {
|
||||
/* MPS w_order optimal TH presently TH
|
||||
* 128 0 0 2
|
||||
* 256 1 1 3
|
||||
* >=512 2 2 3
|
||||
*/
|
||||
/* DMAE is special */
|
||||
if (!CHIP_IS_E1H(sc)) {
|
||||
/* E2 can use optimal TH */
|
||||
val = w_order;
|
||||
REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
|
||||
} else {
|
||||
val = ((w_order == 0) ? 2 : 3);
|
||||
REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
|
||||
}
|
||||
|
||||
REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
|
||||
REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
|
||||
}
|
||||
|
||||
/* Validate number of tags suppoted by device */
|
||||
#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
|
||||
val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);
|
||||
val &= 0xFF;
|
||||
if (val <= 0x20)
|
||||
REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* ILT management
|
||||
****************************************************************************/
|
||||
/*
|
||||
* This codes hides the low level HW interaction for ILT management and
|
||||
* configuration. The API consists of a shadow ILT table which is set by the
|
||||
* driver and a set of routines to use it to configure the HW.
|
||||
*
|
||||
*/
|
||||
|
||||
/* ILT HW init operations */
|
||||
|
||||
/* ILT memory management operations */
|
||||
#define ILT_MEMOP_ALLOC 0
|
||||
#define ILT_MEMOP_FREE 1
|
||||
|
||||
/* the phys address is shifted right 12 bits and has an added
|
||||
* 1=valid bit added to the 53rd bit
|
||||
* then since this is a wide register(TM)
|
||||
* we split it into two 32 bit writes
|
||||
*/
|
||||
#define ILT_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
|
||||
#define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
|
||||
#define ILT_RANGE(f, l) (((l) << 10) | f)
|
||||
|
||||
static int ecore_ilt_line_mem_op(struct bxe_softc *sc,
|
||||
struct ilt_line *line, uint32_t size, uint8_t memop)
|
||||
{
|
||||
if (memop == ILT_MEMOP_FREE) {
|
||||
ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
|
||||
return 0;
|
||||
}
|
||||
ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);
|
||||
if (!line->page)
|
||||
return -1;
|
||||
line->size = size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int ecore_ilt_client_mem_op(struct bxe_softc *sc, int cli_num,
|
||||
uint8_t memop)
|
||||
{
|
||||
int i, rc;
|
||||
struct ecore_ilt *ilt = SC_ILT(sc);
|
||||
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
|
||||
|
||||
if (!ilt || !ilt->lines)
|
||||
return -1;
|
||||
|
||||
if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
|
||||
return 0;
|
||||
|
||||
for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
|
||||
rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
|
||||
ilt_cli->page_size, memop);
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
static inline int ecore_ilt_mem_op_cnic(struct bxe_softc *sc, uint8_t memop)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (CONFIGURE_NIC_MODE(sc))
|
||||
rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
|
||||
if (!rc)
|
||||
rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int ecore_ilt_mem_op(struct bxe_softc *sc, uint8_t memop)
|
||||
{
|
||||
int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
|
||||
if (!rc)
|
||||
rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop);
|
||||
if (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
|
||||
rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void ecore_ilt_line_wr(struct bxe_softc *sc, int abs_idx,
|
||||
ecore_dma_addr_t page_mapping)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
if (CHIP_IS_E1(sc))
|
||||
reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
|
||||
else
|
||||
reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
|
||||
|
||||
ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
|
||||
}
|
||||
|
||||
static void ecore_ilt_line_init_op(struct bxe_softc *sc,
|
||||
struct ecore_ilt *ilt, int idx, uint8_t initop)
|
||||
{
|
||||
ecore_dma_addr_t null_mapping;
|
||||
int abs_idx = ilt->start_line + idx;
|
||||
|
||||
|
||||
switch (initop) {
|
||||
case INITOP_INIT:
|
||||
/* set in the init-value array */
|
||||
case INITOP_SET:
|
||||
ecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping);
|
||||
break;
|
||||
case INITOP_CLEAR:
|
||||
null_mapping = 0;
|
||||
ecore_ilt_line_wr(sc, abs_idx, null_mapping);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void ecore_ilt_boundry_init_op(struct bxe_softc *sc,
|
||||
struct ilt_client_info *ilt_cli,
|
||||
uint32_t ilt_start, uint8_t initop)
|
||||
{
|
||||
uint32_t start_reg = 0;
|
||||
uint32_t end_reg = 0;
|
||||
|
||||
/* The boundary is either SET or INIT,
|
||||
CLEAR => SET and for now SET ~~ INIT */
|
||||
|
||||
/* find the appropriate regs */
|
||||
if (CHIP_IS_E1(sc)) {
|
||||
switch (ilt_cli->client_num) {
|
||||
case ILT_CLIENT_CDU:
|
||||
start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
|
||||
break;
|
||||
case ILT_CLIENT_QM:
|
||||
start_reg = PXP2_REG_PSWRQ_QM0_L2P;
|
||||
break;
|
||||
case ILT_CLIENT_SRC:
|
||||
start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
|
||||
break;
|
||||
case ILT_CLIENT_TM:
|
||||
start_reg = PXP2_REG_PSWRQ_TM0_L2P;
|
||||
break;
|
||||
}
|
||||
REG_WR(sc, start_reg + SC_FUNC(sc)*4,
|
||||
ILT_RANGE((ilt_start + ilt_cli->start),
|
||||
(ilt_start + ilt_cli->end)));
|
||||
} else {
|
||||
switch (ilt_cli->client_num) {
|
||||
case ILT_CLIENT_CDU:
|
||||
start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
|
||||
end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
|
||||
break;
|
||||
case ILT_CLIENT_QM:
|
||||
start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
|
||||
end_reg = PXP2_REG_RQ_QM_LAST_ILT;
|
||||
break;
|
||||
case ILT_CLIENT_SRC:
|
||||
start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
|
||||
end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
|
||||
break;
|
||||
case ILT_CLIENT_TM:
|
||||
start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
|
||||
end_reg = PXP2_REG_RQ_TM_LAST_ILT;
|
||||
break;
|
||||
}
|
||||
REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
|
||||
REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
|
||||
}
|
||||
}
|
||||
|
||||
static void ecore_ilt_client_init_op_ilt(struct bxe_softc *sc,
|
||||
struct ecore_ilt *ilt,
|
||||
struct ilt_client_info *ilt_cli,
|
||||
uint8_t initop)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
|
||||
return;
|
||||
|
||||
for (i = ilt_cli->start; i <= ilt_cli->end; i++)
|
||||
ecore_ilt_line_init_op(sc, ilt, i, initop);
|
||||
|
||||
/* init/clear the ILT boundries */
|
||||
ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line, initop);
|
||||
}
|
||||
|
||||
static void ecore_ilt_client_init_op(struct bxe_softc *sc,
|
||||
struct ilt_client_info *ilt_cli, uint8_t initop)
|
||||
{
|
||||
struct ecore_ilt *ilt = SC_ILT(sc);
|
||||
|
||||
ecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop);
|
||||
}
|
||||
|
||||
static void ecore_ilt_client_id_init_op(struct bxe_softc *sc,
|
||||
int cli_num, uint8_t initop)
|
||||
{
|
||||
struct ecore_ilt *ilt = SC_ILT(sc);
|
||||
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
|
||||
|
||||
ecore_ilt_client_init_op(sc, ilt_cli, initop);
|
||||
}
|
||||
|
||||
static inline void ecore_ilt_init_op_cnic(struct bxe_softc *sc, uint8_t initop)
|
||||
{
|
||||
if (CONFIGURE_NIC_MODE(sc))
|
||||
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
|
||||
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
|
||||
}
|
||||
|
||||
static void ecore_ilt_init_op(struct bxe_softc *sc, uint8_t initop)
|
||||
{
|
||||
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
|
||||
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop);
|
||||
if (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
|
||||
ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
|
||||
}
|
||||
|
||||
static void ecore_ilt_init_client_psz(struct bxe_softc *sc, int cli_num,
|
||||
uint32_t psz_reg, uint8_t initop)
|
||||
{
|
||||
struct ecore_ilt *ilt = SC_ILT(sc);
|
||||
struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
|
||||
|
||||
if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
|
||||
return;
|
||||
|
||||
switch (initop) {
|
||||
case INITOP_INIT:
|
||||
/* set in the init-value array */
|
||||
case INITOP_SET:
|
||||
REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12));
|
||||
break;
|
||||
case INITOP_CLEAR:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* called during init common stage, ilt clients should be initialized
|
||||
* prioir to calling this function
|
||||
*/
|
||||
static void ecore_ilt_init_page_size(struct bxe_softc *sc, uint8_t initop)
|
||||
{
|
||||
ecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU,
|
||||
PXP2_REG_RQ_CDU_P_SIZE, initop);
|
||||
ecore_ilt_init_client_psz(sc, ILT_CLIENT_QM,
|
||||
PXP2_REG_RQ_QM_P_SIZE, initop);
|
||||
ecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC,
|
||||
PXP2_REG_RQ_SRC_P_SIZE, initop);
|
||||
ecore_ilt_init_client_psz(sc, ILT_CLIENT_TM,
|
||||
PXP2_REG_RQ_TM_P_SIZE, initop);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* QM initializations
|
||||
****************************************************************************/
|
||||
#define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
|
||||
#define QM_INIT_MIN_CID_COUNT 31
|
||||
#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
|
||||
|
||||
/* called during init port stage */
|
||||
static void ecore_qm_init_cid_count(struct bxe_softc *sc, int qm_cid_count,
|
||||
uint8_t initop)
|
||||
{
|
||||
int port = SC_PORT(sc);
|
||||
|
||||
if (QM_INIT(qm_cid_count)) {
|
||||
switch (initop) {
|
||||
case INITOP_INIT:
|
||||
/* set in the init-value array */
|
||||
case INITOP_SET:
|
||||
REG_WR(sc, QM_REG_CONNNUM_0 + port*4,
|
||||
qm_cid_count/16 - 1);
|
||||
break;
|
||||
case INITOP_CLEAR:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void ecore_qm_set_ptr_table(struct bxe_softc *sc, int qm_cid_count,
|
||||
uint32_t base_reg, uint32_t reg)
|
||||
{
|
||||
int i;
|
||||
uint32_t wb_data[2] = {0, 0};
|
||||
for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
|
||||
REG_WR(sc, base_reg + i*4,
|
||||
qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
|
||||
ecore_init_wr_wb(sc, reg + i*8,
|
||||
wb_data, 2);
|
||||
}
|
||||
}
|
||||
|
||||
/* called during init common stage */
|
||||
static void ecore_qm_init_ptr_table(struct bxe_softc *sc, int qm_cid_count,
|
||||
uint8_t initop)
|
||||
{
|
||||
if (!QM_INIT(qm_cid_count))
|
||||
return;
|
||||
|
||||
switch (initop) {
|
||||
case INITOP_INIT:
|
||||
/* set in the init-value array */
|
||||
case INITOP_SET:
|
||||
ecore_qm_set_ptr_table(sc, qm_cid_count,
|
||||
QM_REG_BASEADDR, QM_REG_PTRTBL);
|
||||
if (CHIP_IS_E1H(sc))
|
||||
ecore_qm_set_ptr_table(sc, qm_cid_count,
|
||||
QM_REG_BASEADDR_EXT_A,
|
||||
QM_REG_PTRTBL_EXT_A);
|
||||
break;
|
||||
case INITOP_CLEAR:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* SRC initializations
|
||||
****************************************************************************/
|
||||
#ifdef ECORE_L5
|
||||
/* called during init func stage */
|
||||
static void ecore_src_init_t2(struct bxe_softc *sc, struct src_ent *t2,
|
||||
ecore_dma_addr_t t2_mapping, int src_cid_count)
|
||||
{
|
||||
int i;
|
||||
int port = SC_PORT(sc);
|
||||
|
||||
/* Initialize T2 */
|
||||
for (i = 0; i < src_cid_count-1; i++)
|
||||
t2[i].next = (uint64_t)(t2_mapping +
|
||||
(i+1)*sizeof(struct src_ent));
|
||||
|
||||
/* tell the searcher where the T2 table is */
|
||||
REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
|
||||
|
||||
ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
|
||||
U64_LO(t2_mapping), U64_HI(t2_mapping));
|
||||
|
||||
ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
|
||||
U64_LO((uint64_t)t2_mapping +
|
||||
(src_cid_count-1) * sizeof(struct src_ent)),
|
||||
U64_HI((uint64_t)t2_mapping +
|
||||
(src_cid_count-1) * sizeof(struct src_ent)));
|
||||
}
|
||||
#endif
|
||||
#endif /* ECORE_INIT_OPS_H */
|
||||
210
sys/dev/bxe/ecore_mfw_req.h
Normal file
210
sys/dev/bxe/ecore_mfw_req.h
Normal file
@ -0,0 +1,210 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Eric Davis <edavis@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#ifndef ECORE_MFW_REQ_H
|
||||
#define ECORE_MFW_REQ_H
|
||||
|
||||
|
||||
|
||||
#define PORT_0 0
|
||||
#define PORT_1 1
|
||||
#define PORT_MAX 2
|
||||
#define NVM_PATH_MAX 2
|
||||
|
||||
/* FCoE capabilities required from the driver */
|
||||
struct fcoe_capabilities {
|
||||
uint32_t capability1;
|
||||
/* Maximum number of I/Os per connection */
|
||||
#define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff
|
||||
#define FCOE_IOS_PER_CONNECTION_SHIFT 0
|
||||
/* Maximum number of Logins per port */
|
||||
#define FCOE_LOGINS_PER_PORT_MASK 0xffff0000
|
||||
#define FCOE_LOGINS_PER_PORT_SHIFT 16
|
||||
|
||||
uint32_t capability2;
|
||||
/* Maximum number of exchanges */
|
||||
#define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff
|
||||
#define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0
|
||||
/* Maximum NPIV WWN per port */
|
||||
#define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000
|
||||
#define FCOE_NPIV_WWN_PER_PORT_SHIFT 16
|
||||
|
||||
uint32_t capability3;
|
||||
/* Maximum number of targets supported */
|
||||
#define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff
|
||||
#define FCOE_TARGETS_SUPPORTED_SHIFT 0
|
||||
/* Maximum number of outstanding commands across all connections */
|
||||
#define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000
|
||||
#define FCOE_OUTSTANDING_COMMANDS_SHIFT 16
|
||||
|
||||
uint32_t capability4;
|
||||
#define FCOE_CAPABILITY4_STATEFUL 0x00000001
|
||||
#define FCOE_CAPABILITY4_STATELESS 0x00000002
|
||||
#define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID 0x00000004
|
||||
};
|
||||
|
||||
struct glob_ncsi_oem_data
|
||||
{
|
||||
uint32_t driver_version;
|
||||
uint32_t unused[3];
|
||||
struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];
|
||||
};
|
||||
|
||||
/* current drv_info version */
|
||||
#define DRV_INFO_CUR_VER 2
|
||||
|
||||
/* drv_info op codes supported */
|
||||
enum drv_info_opcode {
|
||||
ETH_STATS_OPCODE,
|
||||
FCOE_STATS_OPCODE,
|
||||
ISCSI_STATS_OPCODE
|
||||
};
|
||||
|
||||
#define ETH_STAT_INFO_VERSION_LEN 12
|
||||
/* Per PCI Function Ethernet Statistics required from the driver */
|
||||
struct eth_stats_info {
|
||||
/* Function's Driver Version. padded to 12 */
|
||||
uint8_t version[ETH_STAT_INFO_VERSION_LEN];
|
||||
/* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
|
||||
uint8_t mac_local[8];
|
||||
uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
|
||||
uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */
|
||||
uint32_t mtu_size; /* MTU Size. Note : Negotiated MTU */
|
||||
uint32_t feature_flags; /* Feature_Flags. */
|
||||
#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01
|
||||
#define FEATURE_ETH_LSO_MASK 0x02
|
||||
#define FEATURE_ETH_BOOTMODE_MASK 0x1C
|
||||
#define FEATURE_ETH_BOOTMODE_SHIFT 2
|
||||
#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
|
||||
#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2)
|
||||
#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2)
|
||||
#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2)
|
||||
#define FEATURE_ETH_TOE_MASK 0x20
|
||||
uint32_t lso_max_size; /* LSO MaxOffloadSize. */
|
||||
uint32_t lso_min_seg_cnt; /* LSO MinSegmentCount. */
|
||||
/* Num Offloaded Connections TCP_IPv4. */
|
||||
uint32_t ipv4_ofld_cnt;
|
||||
/* Num Offloaded Connections TCP_IPv6. */
|
||||
uint32_t ipv6_ofld_cnt;
|
||||
uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
|
||||
uint32_t txq_size; /* TX Descriptors Queue Size */
|
||||
uint32_t rxq_size; /* RX Descriptors Queue Size */
|
||||
/* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
|
||||
uint32_t txq_avg_depth;
|
||||
/* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
|
||||
uint32_t rxq_avg_depth;
|
||||
/* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
|
||||
uint32_t iov_offload;
|
||||
/* Number of NetQueue/VMQ Config'd. */
|
||||
uint32_t netq_cnt;
|
||||
uint32_t vf_cnt; /* Num VF assigned to this PF. */
|
||||
};
|
||||
|
||||
/* Per PCI Function FCOE Statistics required from the driver */
|
||||
struct fcoe_stats_info {
|
||||
uint8_t version[12]; /* Function's Driver Version. */
|
||||
uint8_t mac_local[8]; /* Locally Admin Addr. */
|
||||
uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
|
||||
uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */
|
||||
/* QoS Priority (per 802.1p). 0-7255 */
|
||||
uint32_t qos_priority;
|
||||
uint32_t txq_size; /* FCoE TX Descriptors Queue Size. */
|
||||
uint32_t rxq_size; /* FCoE RX Descriptors Queue Size. */
|
||||
/* FCoE TX Descriptor Queue Avg Depth. */
|
||||
uint32_t txq_avg_depth;
|
||||
/* FCoE RX Descriptors Queue Avg Depth. */
|
||||
uint32_t rxq_avg_depth;
|
||||
uint32_t rx_frames_lo; /* FCoE RX Frames received. */
|
||||
uint32_t rx_frames_hi; /* FCoE RX Frames received. */
|
||||
uint32_t rx_bytes_lo; /* FCoE RX Bytes received. */
|
||||
uint32_t rx_bytes_hi; /* FCoE RX Bytes received. */
|
||||
uint32_t tx_frames_lo; /* FCoE TX Frames sent. */
|
||||
uint32_t tx_frames_hi; /* FCoE TX Frames sent. */
|
||||
uint32_t tx_bytes_lo; /* FCoE TX Bytes sent. */
|
||||
uint32_t tx_bytes_hi; /* FCoE TX Bytes sent. */
|
||||
uint32_t rx_fcs_errors; /* number of receive packets with FCS errors */
|
||||
uint32_t rx_fc_crc_errors; /* number of FC frames with CRC errors*/
|
||||
uint32_t fip_login_failures; /* number of FCoE/FIP Login failures */
|
||||
};
|
||||
|
||||
/* Per PCI Function iSCSI Statistics required from the driver*/
|
||||
struct iscsi_stats_info {
|
||||
uint8_t version[12]; /* Function's Driver Version. */
|
||||
uint8_t mac_local[8]; /* Locally Admin iSCSI MAC Addr. */
|
||||
uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
|
||||
/* QoS Priority (per 802.1p). 0-7255 */
|
||||
uint32_t qos_priority;
|
||||
|
||||
uint8_t initiator_name[64]; /* iSCSI Boot Initiator Node name. */
|
||||
|
||||
uint8_t ww_port_name[64]; /* iSCSI World wide port name */
|
||||
|
||||
uint8_t boot_target_name[64];/* iSCSI Boot Target Name. */
|
||||
|
||||
uint8_t boot_target_ip[16]; /* iSCSI Boot Target IP. */
|
||||
uint32_t boot_target_portal; /* iSCSI Boot Target Portal. */
|
||||
uint8_t boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */
|
||||
uint32_t max_frame_size; /* Max Frame Size. bytes */
|
||||
uint32_t txq_size; /* PDU TX Descriptors Queue Size. */
|
||||
uint32_t rxq_size; /* PDU RX Descriptors Queue Size. */
|
||||
|
||||
uint32_t txq_avg_depth; /*PDU TX Descriptor Queue Avg Depth. */
|
||||
uint32_t rxq_avg_depth; /*PDU RX Descriptors Queue Avg Depth. */
|
||||
uint32_t rx_pdus_lo; /* iSCSI PDUs received. */
|
||||
uint32_t rx_pdus_hi; /* iSCSI PDUs received. */
|
||||
|
||||
uint32_t rx_bytes_lo; /* iSCSI RX Bytes received. */
|
||||
uint32_t rx_bytes_hi; /* iSCSI RX Bytes received. */
|
||||
uint32_t tx_pdus_lo; /* iSCSI PDUs sent. */
|
||||
uint32_t tx_pdus_hi; /* iSCSI PDUs sent. */
|
||||
|
||||
uint32_t tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */
|
||||
uint32_t tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */
|
||||
uint32_t pcp_prior_map_tbl; /*C-PCP to S-PCP Priority MapTable.
|
||||
9 nibbles, the position of each nibble
|
||||
represents the C-PCP value, the value
|
||||
of the nibble = S-PCP value.*/
|
||||
};
|
||||
|
||||
union drv_info_to_mcp {
|
||||
struct eth_stats_info ether_stat;
|
||||
struct fcoe_stats_info fcoe_stat;
|
||||
struct iscsi_stats_info iscsi_stat;
|
||||
};
|
||||
|
||||
|
||||
#endif /* ECORE_MFW_REQ_H */
|
||||
|
||||
3704
sys/dev/bxe/ecore_reg.h
Normal file
3704
sys/dev/bxe/ecore_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
6270
sys/dev/bxe/ecore_sp.c
Normal file
6270
sys/dev/bxe/ecore_sp.c
Normal file
File diff suppressed because it is too large
Load Diff
1857
sys/dev/bxe/ecore_sp.h
Normal file
1857
sys/dev/bxe/ecore_sp.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,80 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Gary Zambrano <zambrano@broadcom.com>
|
||||
* David Christensen <davidch@broadcom.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written consent.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD$*/
|
||||
|
||||
#ifndef _HW_DUMP_REG_ST_H
|
||||
#define _HW_DUMP_REG_ST_H
|
||||
|
||||
#define BXE_GRCDUMP_BUF_SIZE 0xE0000
|
||||
|
||||
#define XSTORM_WAITP_ADDRESS 0x2b8a80
|
||||
#define TSTORM_WAITP_ADDRESS 0x2b8a80
|
||||
#define USTORM_WAITP_ADDRESS 0x2b8a80
|
||||
#define CSTORM_WAITP_ADDRESS 0x2b8a80
|
||||
#define TSTORM_CAM_MODE 0x1B1440
|
||||
|
||||
/* Register address structure. */
|
||||
typedef struct reg_addr {
|
||||
uint32_t addr;
|
||||
uint32_t size;
|
||||
}*preg_addr;
|
||||
|
||||
/* Wide register address structure. */
|
||||
typedef struct wreg_addr {
|
||||
uint32_t addr;
|
||||
uint32_t size;
|
||||
uint32_t const_regs_count;
|
||||
uint32_t * const_regs;
|
||||
}*pwreg_addr;
|
||||
|
||||
/* Dump header parameters. */
|
||||
struct hd_param {
|
||||
uint32_t time_stamp;
|
||||
uint32_t diag_ver;
|
||||
uint32_t grc_dump_ver;
|
||||
};
|
||||
|
||||
/* Global parameters. */
|
||||
extern struct wreg_addr wreg_addrs_e1[];
|
||||
extern struct reg_addr reg_addrs_e1[];
|
||||
extern uint32_t regs_count_e1;
|
||||
extern uint32_t wregs_count_e1;
|
||||
extern struct hd_param hd_param_e1;
|
||||
|
||||
extern struct wreg_addr wreg_addrs_e1h[];
|
||||
extern struct reg_addr reg_addrs_e1h[];
|
||||
extern uint32_t regs_count_e1h;
|
||||
extern uint32_t wregs_count_e1h;
|
||||
extern struct hd_param hd_param_e1h;
|
||||
|
||||
#endif //_HW_DUMP_REG_ST_H
|
||||
17581
sys/dev/bxe/if_bxe.c
17581
sys/dev/bxe/if_bxe.c
File diff suppressed because it is too large
Load Diff
1831
sys/dev/bxe/if_bxe.h
1831
sys/dev/bxe/if_bxe.h
File diff suppressed because it is too large
Load Diff
@ -215,7 +215,7 @@ device ppi # Parallel port interface device
|
||||
device puc # Multi I/O cards and multi-channel UARTs
|
||||
|
||||
# PCI Ethernet NICs.
|
||||
device bxe # Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
|
||||
device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
|
||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||
device em # Intel PRO/1000 Gigabit Ethernet Family
|
||||
device igb # Intel PRO/1000 PCIE Server Gigabit Family
|
||||
|
||||
@ -553,6 +553,8 @@ hint.mse.0.irq="5"
|
||||
# Network interfaces:
|
||||
#
|
||||
|
||||
# bxe: Broadcom NetXtreme II (BCM5771X/BCM578XX) PCIe 10Gb Ethernet
|
||||
# adapters.
|
||||
# ce: Cronyx Tau-PCI/32 sync single/dual port G.703/E1 serial adaptor
|
||||
# with 32 HDLC subchannels (requires sppp (default), or NETGRAPH if
|
||||
# NETGRAPH_CRONYX is configured)
|
||||
@ -587,6 +589,7 @@ hint.mse.0.irq="5"
|
||||
|
||||
# Order for ISA/EISA devices is important here
|
||||
|
||||
device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
|
||||
device ce
|
||||
device cp
|
||||
device cs # Crystal Semiconductor CS89x0 NIC
|
||||
|
||||
@ -2,12 +2,17 @@
|
||||
BXE = ${.CURDIR}/../../dev/bxe
|
||||
.PATH: ${BXE}
|
||||
|
||||
KMOD= if_bxe
|
||||
SRCS = opt_bxe.h device_if.h bus_if.h pci_if.h
|
||||
SRCS += if_bxe.c bxe_link.c
|
||||
KMOD = if_bxe
|
||||
SRCS = device_if.h bus_if.h pci_if.h
|
||||
SRCS += bxe.c \
|
||||
bxe_stats.c \
|
||||
bxe_debug.c \
|
||||
bxe_elink.c \
|
||||
ecore_sp.c \
|
||||
57710_init_values.c \
|
||||
57711_init_values.c \
|
||||
57712_init_values.c
|
||||
|
||||
CFLAGS += -I${BXE} -DBXE_TASK
|
||||
#CFLAGS += -DBXE_DEBUG
|
||||
#CFLAGS += -DBXE_NVRAM_WRITE_SUPPORT
|
||||
CFLAGS += -I${BXE}
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user