Move USB-specific parts from rtwn(4) to rtwn_usb(4)
MFC after: 4 days
This commit is contained in:
parent
17d5fbf21b
commit
4e4bcfcfb7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=342678
@ -24,9 +24,7 @@
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/*
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* Global definitions.
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*/
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#define R88E_PUBQ_NPAGES 142
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#define R88E_TXPKTBUF_COUNT 177
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#define R88E_TX_PAGE_COUNT 169
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#define R88E_MACID_MAX 63
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#define R88E_RX_DMA_BUFFER_SIZE 0x2400
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@ -67,9 +65,8 @@ int r88e_set_pwrmode(struct rtwn_softc *, struct ieee80211vap *, int);
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#endif
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/* r88e_init.c */
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void r88e_init_bb(struct rtwn_softc *);
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void r88e_init_bb_common(struct rtwn_softc *);
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void r88e_init_rf(struct rtwn_softc *);
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int r88e_power_on(struct rtwn_softc *);
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/* r88e_led.c */
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void r88e_set_led(struct rtwn_softc *, int, int);
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@ -70,20 +70,8 @@ r88e_crystalcap_write(struct rtwn_softc *sc)
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}
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void
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r88e_init_bb(struct rtwn_softc *sc)
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r88e_init_bb_common(struct rtwn_softc *sc)
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{
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/* Enable BB and RF. */
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rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
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R92C_SYS_FUNC_EN_DIO_RF);
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
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rtwn_write_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
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R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
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r92c_init_bb_common(sc);
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rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
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@ -93,66 +81,3 @@ r88e_init_bb(struct rtwn_softc *sc)
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r88e_crystalcap_write(sc);
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}
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int
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r88e_power_on(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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int ntries;
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/* Wait for power ready bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for chip power up\n");
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return (ETIMEDOUT);
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}
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/* Reset BB. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0));
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RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
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/* Disable HWPDN. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APDM_HPDN, 0, 1));
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/* Disable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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0, R92C_APS_FSMCO_APFM_ONMAC, 1));
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000)
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return (ETIMEDOUT);
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/* Enable LDO normal mode. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
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R92C_LPLDO_CTRL_SLEEP, 0));
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
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RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
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R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
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R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
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((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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R92C_CR_CALTMR_EN));
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return (0);
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#undef RTWN_CHK
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}
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@ -24,10 +24,19 @@
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#include <dev/rtwn/rtl8188e/r88e.h>
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/*
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* Global definitions.
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*/
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#define R88EU_PUBQ_NPAGES 142
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#define R88EU_TX_PAGE_COUNT 169
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/*
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* Function declarations.
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*/
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/* r88eu_init.c */
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void r88eu_init_bb(struct rtwn_softc *);
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int r88eu_power_on(struct rtwn_softc *);
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void r88eu_power_off(struct rtwn_softc *);
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void r88eu_init_intr(struct rtwn_softc *);
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void r88eu_init_rx_agg(struct rtwn_softc *);
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@ -140,7 +140,7 @@ r88eu_attach(struct rtwn_usb_softc *uc)
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sc->sc_efuse_postread = rtwn_nop_softc;
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sc->sc_parse_rom = r88e_parse_rom;
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sc->sc_set_led = r88e_set_led;
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sc->sc_power_on = r88e_power_on;
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sc->sc_power_on = r88eu_power_on;
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sc->sc_power_off = r88eu_power_off;
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#ifndef RTWN_WITHOUT_UCODE
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sc->sc_fw_reset = r88e_fw_reset;
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@ -172,7 +172,7 @@ r88eu_attach(struct rtwn_usb_softc *uc)
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sc->sc_init_ampdu = rtwn_nop_softc;
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sc->sc_init_intr = r88eu_init_intr;
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sc->sc_init_edca = r92c_init_edca;
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sc->sc_init_bb = r88e_init_bb;
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sc->sc_init_bb = r88eu_init_bb;
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sc->sc_init_rf = r92c_init_rf;
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sc->sc_init_antsel = rtwn_nop_softc;
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sc->sc_post_init = r88eu_post_init;
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@ -190,11 +190,11 @@ r88eu_attach(struct rtwn_usb_softc *uc)
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sc->fwname = "rtwn-rtl8188eufw";
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sc->fwsig = 0x88e;
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sc->page_count = R88E_TX_PAGE_COUNT;
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sc->page_count = R88EU_TX_PAGE_COUNT;
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sc->pktbuf_count = R88E_TXPKTBUF_COUNT;
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sc->ackto = 0x40;
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sc->npubqpages = R88E_PUBQ_NPAGES;
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sc->npubqpages = R88EU_PUBQ_NPAGES;
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sc->page_size = R92C_TX_PAGE_SIZE;
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sc->txdesc_len = sizeof(struct r92cu_tx_desc);
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@ -54,6 +54,87 @@ __FBSDID("$FreeBSD$");
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#include <dev/rtwn/rtl8188e/usb/r88eu_reg.h>
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void
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r88eu_init_bb(struct rtwn_softc *sc)
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{
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/* Enable BB and RF. */
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rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
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R92C_SYS_FUNC_EN_DIO_RF);
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
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rtwn_write_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
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R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
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r88e_init_bb_common(sc);
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}
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int
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r88eu_power_on(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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int ntries;
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/* Wait for power ready bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for chip power up\n");
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return (ETIMEDOUT);
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}
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/* Reset BB. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0));
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RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
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/* Disable HWPDN. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APDM_HPDN, 0, 1));
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/* Disable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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0, R92C_APS_FSMCO_APFM_ONMAC, 1));
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000)
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return (ETIMEDOUT);
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/* Enable LDO normal mode. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
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R92C_LPLDO_CTRL_SLEEP, 0));
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
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RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
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R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
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R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
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((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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R92C_CR_CALTMR_EN));
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return (0);
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#undef RTWN_CHK
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}
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void
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r88eu_power_off(struct rtwn_softc *sc)
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{
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