diff --git a/sys/arm/xilinx/zy7_mp.c b/sys/arm/xilinx/zy7_mp.c
index d9bcf602ac10..c9dfc8dadfe2 100644
--- a/sys/arm/xilinx/zy7_mp.c
+++ b/sys/arm/xilinx/zy7_mp.c
@@ -58,7 +58,7 @@ zynq7_mp_setmaxid(platform_t plat)
 	mp_ncpus = 2;
 }
 
-void    
+void
 zynq7_mp_start_ap(platform_t plat)
 {
 	bus_space_handle_t scu_handle;
@@ -67,8 +67,8 @@ zynq7_mp_start_ap(platform_t plat)
 
 	/* Map in SCU control register. */
 	if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
-			  0, &scu_handle) != 0)
-		panic("platform_mp_start_ap: Couldn't map SCU config reg\n");
+	    0, &scu_handle) != 0)
+		panic("%s: Could not map SCU control reg.\n", __func__);
 
 	/* Set SCU enable bit. */
 	scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
@@ -80,7 +80,7 @@ zynq7_mp_start_ap(platform_t plat)
 	/* Map in magic location to give entry address to CPU1. */
 	if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
 	    0, &ocm_handle) != 0)
-		panic("platform_mp_start_ap: Couldn't map OCM\n");
+		panic("%s: Could not map OCM\n", __func__);
 
 	/* Write start address for CPU1. */
 	bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,