o Remove the com_thr, com_rhr, com_isr and com_lctl defines. They are
not used and aliases for other defines. o Add REG_DATA as an alias for com_data. Likewise for other register defines. o Add LCR_SBREAK and make CFCR_SBREAK an alias for it. Likewise for the other LCR register bits that are known with the CFCR prefix. o Add MCR_IE and make MCR_IENABLE an alias for it. o Add LSR_TEMT and make LSR_TSRE an alias for it. o Add LSR_THRE and make LSR_TXRDY as alias for it. o Add FCR_ENABLE and make FIFO_ENABLE as alias for it. Likewise for the other FCR register bits that are known with the FIFO prefix. o Add EFR_CTS and make EFR_AUTOCTS an alias for it. o Add EFR_RTS and make EFR_AUTORTS an alias for it. This is a first step in cleaning up the definitions in this file.
This commit is contained in:
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=137948
@ -37,17 +37,17 @@
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/* 8250 registers #[0-6]. */
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#define com_data 0 /* data register (R/W) */
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#define com_thr com_data /* transmitter holding register (W) */
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#define com_rhr com_data /* receiver holding register (R) */
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#define REG_DATA com_data
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#define com_ier 1 /* interrupt enable register (W) */
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#define REG_IER com_ier
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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#define com_iir 2 /* interrupt identification register (R) */
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#define com_isr com_iir /* interrupt status register (R) */
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#define REG_IIR com_iir
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_RLS 0x6
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@ -58,36 +58,52 @@
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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#define com_lcr 3 /* line control register (R/W) */
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#define com_lctl com_lcr
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#define com_cfcr com_lcr /* character format control register (R/W) */
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#define REG_LCR com_lcr
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#define LCR_DLAB 0x80
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#define CFCR_DLAB LCR_DLAB
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#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
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#define CFCR_EFR_ENABLE LCR_EFR_ENABLE
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#define CFCR_SBREAK 0x40
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#define CFCR_PZERO 0x30
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#define CFCR_PONE 0x20
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#define CFCR_PEVEN 0x10
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#define CFCR_PODD 0x00
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#define CFCR_PENAB 0x08
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#define CFCR_STOPB 0x04
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#define CFCR_8BITS 0x03
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#define CFCR_7BITS 0x02
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#define CFCR_6BITS 0x01
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#define CFCR_5BITS 0x00
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#define LCR_SBREAK 0x40
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#define CFCR_SBREAK LCR_SBREAK
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#define LCR_PZERO 0x30
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#define CFCR_PZERO LCR_PZERO
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#define LCR_PONE 0x20
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#define CFCR_PONE LCR_PONE
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#define LCR_PEVEN 0x10
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#define CFCR_PEVEN LCR_PEVEN
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#define LCR_PODD 0x00
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#define CFCR_PODD LCR_PODD
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#define LCR_PENAB 0x08
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#define CFCR_PENAB LCR_PENAB
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#define LCR_STOPB 0x04
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#define CFCR_STOPB LCR_STOPB
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#define LCR_8BITS 0x03
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#define CFCR_8BITS LCR_8BITS
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#define LCR_7BITS 0x02
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#define CFCR_7BITS LCR_7BITS
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#define LCR_6BITS 0x01
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#define CFCR_6BITS LCR_6BITS
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#define LCR_5BITS 0x00
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#define CFCR_5BITS LCR_5BITS
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#define com_mcr 4 /* modem control register (R/W) */
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#define REG_MCR com_mcr
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#define MCR_PRESCALE 0x80 /* only available on 16650 up */
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#define MCR_LOOPBACK 0x10
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#define MCR_IENABLE 0x08
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#define MCR_IE 0x08
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#define MCR_IENABLE MCR_IE
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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#define com_lsr 5 /* line status register (R/W) */
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#define REG_LSR com_lsr
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#define LSR_RCV_FIFO 0x80
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#define LSR_TSRE 0x40
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#define LSR_TXRDY 0x20
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#define LSR_TEMT 0x40
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#define LSR_TSRE LSR_TEMT
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#define LSR_THRE 0x20
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#define LSR_TXRDY LSR_THRE
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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@ -96,6 +112,7 @@
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#define LSR_RCV_MASK 0x1f
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#define com_msr 6 /* modem status register (R/W) */
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#define REG_MSR com_msr
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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@ -110,6 +127,7 @@
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#define com_dlbl com_dll
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#define com_dlm 1 /* divisor latch high (R/W) */
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#define com_dlbh com_dlm
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#define REG_DL com_dll
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/* 16450 register #7. Not multiplexed. */
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#define com_scr 7 /* scratch register (R/W) */
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@ -117,20 +135,32 @@
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/* 16550 register #2. Not multiplexed. */
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#define com_fcr 2 /* FIFO control register (W) */
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#define com_fifo com_fcr
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_RX_LOW 0x00
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#define FIFO_RX_MEDL 0x40
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#define FIFO_RX_MEDH 0x80
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#define FIFO_RX_HIGH 0xc0
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#define REG_FCR com_fcr
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#define FCR_ENABLE 0x01
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#define FIFO_ENABLE FCR_ENABLE
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#define FCR_RCV_RST 0x02
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#define FIFO_RCV_RST FCR_RCV_RST
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#define FCR_XMT_RST 0x04
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#define FIFO_XMT_RST FCR_XMT_RST
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#define FCR_DMA 0x08
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#define FIFO_DMA_MODE FCR_DMA
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#define FCR_RX_LOW 0x00
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#define FIFO_RX_LOW FCR_RX_LOW
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#define FCR_RX_MEDL 0x40
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#define FIFO_RX_MEDL FCR_RX_MEDL
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#define FCR_RX_MEDH 0x80
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#define FIFO_RX_MEDH FCR_RX_MEDH
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#define FCR_RX_HIGH 0xc0
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#define FIFO_RX_HIGH FCR_RX_HIGH
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/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
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#define com_efr 2 /* enhanced features register (R/W) */
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#define EFR_AUTOCTS 0x80
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#define EFR_AUTORTS 0x40
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#define REG_EFR com_efr
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#define EFR_CTS 0x80
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#define EFR_AUTOCTS EFR_CTS
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#define EFR_RTS 0x40
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#define EFR_AUTORTS EFR_RTS
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#define EFR_EFE 0x10 /* enhanced functions enable */
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#define com_xon1 4 /* XON 1 character (R/W) */
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@ -162,6 +192,7 @@
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* index into the Indexed Control register set.
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*/
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#define com_spr com_scr /* scratch pad (and index) register (R/W) */
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#define REG_SPR com_scr
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/*
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* 16950 indexed control registers #[0-0x13]. Access is via index in SPR,
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