This commit gives support for the Rise mP6 CPU. It has two changes:
1. Rise is recognized in identdcpu.c. 2. The TSC is not written to. A workaround for the CPU bug is being applied to clock.c (the bug being that the mP6 has TSC enabled in its CPUID-capabilities, but it only supports reading it. If we try to write to it (MSR 16), a GPF occurs.) The new behavior is that FreeBSD will _not_ zero the TSC. Instead, we do a bit of 64-bit arithmetic. Reviewed by: msmith Obtained from: unfurl & msmith
This commit is contained in:
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962f01757d
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4f6f879901
@ -36,7 +36,7 @@
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $Id: identcpu.c,v 1.62 1999/05/10 10:51:25 bde Exp $
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* $Id: identcpu.c,v 1.63 1999/05/29 06:57:38 phk Exp $
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*/
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#include "opt_cpu.h"
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@ -458,7 +458,16 @@ printcpuinfo(void)
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}
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break;
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}
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} else if (strcmp(cpu_vendor,"IBM") == 0)
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} else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
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strcpy(cpu_model, "Rise ");
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switch (cpu_id & 0xff0) {
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case 0x500:
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strcat(cpu_model, "mP6");
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break;
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default:
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strcat(cpu_model, "Unknown");
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}
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} else if (strcmp(cpu_vendor, "IBM") == 0)
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strcpy(cpu_model, "Blue Lightning CPU");
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#endif
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@ -510,6 +519,7 @@ printcpuinfo(void)
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
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strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
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((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
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((cpu_id & 0xf00) > 0x500))) {
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printf(" Stepping=%u", cpu_id & 0xf);
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.135 1999/05/29 06:57:55 phk Exp $
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* $Id: clock.c,v 1.136 1999/05/31 18:35:59 dfr Exp $
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*/
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/*
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@ -585,6 +585,7 @@ readrtc(int port)
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static u_int
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calibrate_clocks(void)
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{
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u_int64_t old_tsc;
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u_int count, prev_count, tot_count;
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int sec, start_sec, timeout;
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@ -623,7 +624,7 @@ calibrate_clocks(void)
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tot_count = 0;
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if (tsc_present)
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wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
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old_tsc = rdtsc();
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/*
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* Wait for the mc146818A seconds counter to change. Read the i8254
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@ -658,7 +659,7 @@ calibrate_clocks(void)
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* similar to those for the i8254 clock.
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*/
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if (tsc_present)
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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if (bootverbose) {
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if (tsc_present)
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@ -762,9 +763,10 @@ startrtclock()
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* clock failed. Do a less accurate calibration relative
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* to the i8254 clock.
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*/
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wrmsr(0x10, 0LL); /* XXX */
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u_int64_t old_tsc = rdtsc();
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DELAY(1000000);
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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#ifdef CLK_USE_TSC_CALIBRATION
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if (bootverbose)
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printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.135 1999/05/29 06:57:55 phk Exp $
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* $Id: clock.c,v 1.136 1999/05/31 18:35:59 dfr Exp $
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*/
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/*
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@ -585,6 +585,7 @@ readrtc(int port)
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static u_int
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calibrate_clocks(void)
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{
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u_int64_t old_tsc;
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u_int count, prev_count, tot_count;
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int sec, start_sec, timeout;
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@ -623,7 +624,7 @@ calibrate_clocks(void)
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tot_count = 0;
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if (tsc_present)
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wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
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old_tsc = rdtsc();
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/*
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* Wait for the mc146818A seconds counter to change. Read the i8254
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@ -658,7 +659,7 @@ calibrate_clocks(void)
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* similar to those for the i8254 clock.
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*/
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if (tsc_present)
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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if (bootverbose) {
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if (tsc_present)
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@ -762,9 +763,10 @@ startrtclock()
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* clock failed. Do a less accurate calibration relative
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* to the i8254 clock.
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*/
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wrmsr(0x10, 0LL); /* XXX */
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u_int64_t old_tsc = rdtsc();
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DELAY(1000000);
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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#ifdef CLK_USE_TSC_CALIBRATION
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if (bootverbose)
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printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
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@ -36,7 +36,7 @@
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $Id: identcpu.c,v 1.62 1999/05/10 10:51:25 bde Exp $
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* $Id: identcpu.c,v 1.63 1999/05/29 06:57:38 phk Exp $
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*/
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#include "opt_cpu.h"
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@ -458,7 +458,16 @@ printcpuinfo(void)
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}
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break;
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}
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} else if (strcmp(cpu_vendor,"IBM") == 0)
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} else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
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strcpy(cpu_model, "Rise ");
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switch (cpu_id & 0xff0) {
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case 0x500:
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strcat(cpu_model, "mP6");
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break;
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default:
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strcat(cpu_model, "Unknown");
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}
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} else if (strcmp(cpu_vendor, "IBM") == 0)
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strcpy(cpu_model, "Blue Lightning CPU");
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#endif
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@ -510,6 +519,7 @@ printcpuinfo(void)
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
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strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
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((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
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((cpu_id & 0xf00) > 0x500))) {
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printf(" Stepping=%u", cpu_id & 0xf);
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.135 1999/05/29 06:57:55 phk Exp $
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* $Id: clock.c,v 1.136 1999/05/31 18:35:59 dfr Exp $
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*/
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/*
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@ -585,6 +585,7 @@ readrtc(int port)
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static u_int
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calibrate_clocks(void)
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{
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u_int64_t old_tsc;
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u_int count, prev_count, tot_count;
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int sec, start_sec, timeout;
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@ -623,7 +624,7 @@ calibrate_clocks(void)
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tot_count = 0;
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if (tsc_present)
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wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
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old_tsc = rdtsc();
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/*
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* Wait for the mc146818A seconds counter to change. Read the i8254
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@ -658,7 +659,7 @@ calibrate_clocks(void)
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* similar to those for the i8254 clock.
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*/
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if (tsc_present)
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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if (bootverbose) {
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if (tsc_present)
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@ -762,9 +763,10 @@ startrtclock()
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* clock failed. Do a less accurate calibration relative
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* to the i8254 clock.
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*/
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wrmsr(0x10, 0LL); /* XXX */
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u_int64_t old_tsc = rdtsc();
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DELAY(1000000);
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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#ifdef CLK_USE_TSC_CALIBRATION
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if (bootverbose)
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printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.135 1999/05/29 06:57:55 phk Exp $
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* $Id: clock.c,v 1.136 1999/05/31 18:35:59 dfr Exp $
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*/
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/*
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@ -585,6 +585,7 @@ readrtc(int port)
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static u_int
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calibrate_clocks(void)
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{
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u_int64_t old_tsc;
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u_int count, prev_count, tot_count;
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int sec, start_sec, timeout;
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@ -623,7 +624,7 @@ calibrate_clocks(void)
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tot_count = 0;
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if (tsc_present)
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wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
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old_tsc = rdtsc();
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/*
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* Wait for the mc146818A seconds counter to change. Read the i8254
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@ -658,7 +659,7 @@ calibrate_clocks(void)
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* similar to those for the i8254 clock.
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*/
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if (tsc_present)
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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if (bootverbose) {
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if (tsc_present)
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@ -762,9 +763,10 @@ startrtclock()
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* clock failed. Do a less accurate calibration relative
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* to the i8254 clock.
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*/
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wrmsr(0x10, 0LL); /* XXX */
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u_int64_t old_tsc = rdtsc();
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DELAY(1000000);
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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#ifdef CLK_USE_TSC_CALIBRATION
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if (bootverbose)
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printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.135 1999/05/29 06:57:55 phk Exp $
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* $Id: clock.c,v 1.136 1999/05/31 18:35:59 dfr Exp $
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*/
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/*
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@ -585,6 +585,7 @@ readrtc(int port)
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static u_int
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calibrate_clocks(void)
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{
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u_int64_t old_tsc;
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u_int count, prev_count, tot_count;
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int sec, start_sec, timeout;
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@ -623,7 +624,7 @@ calibrate_clocks(void)
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tot_count = 0;
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if (tsc_present)
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wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
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old_tsc = rdtsc();
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/*
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* Wait for the mc146818A seconds counter to change. Read the i8254
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@ -658,7 +659,7 @@ calibrate_clocks(void)
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* similar to those for the i8254 clock.
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*/
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if (tsc_present)
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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if (bootverbose) {
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if (tsc_present)
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@ -762,9 +763,10 @@ startrtclock()
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* clock failed. Do a less accurate calibration relative
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* to the i8254 clock.
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*/
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wrmsr(0x10, 0LL); /* XXX */
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u_int64_t old_tsc = rdtsc();
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DELAY(1000000);
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tsc_freq = rdtsc();
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tsc_freq = rdtsc() - old_tsc;
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#ifdef CLK_USE_TSC_CALIBRATION
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if (bootverbose)
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printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
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