Prefer upstream RISC-V additions in libunwind instead of ours, as these
arrived via roundabout way upstream, and got updated in the mean time.
This commit is contained in:
Dimitry Andric
parent
773bec0868
commit
4f73ee074c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang1000-import/; revision=357209
@ -21,7 +21,6 @@
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64 95
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 95
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
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@ -83,12 +82,6 @@
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# define _LIBUNWIND_CONTEXT_SIZE 16
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# define _LIBUNWIND_CURSOR_SIZE 24
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K
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# elif defined(__riscv)
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# define _LIBUNWIND_TARGET_RISCV 1
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# define _LIBUNWIND_CONTEXT_SIZE 64
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# define _LIBUNWIND_CURSOR_SIZE 76
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
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# define _LIBUNWIND_MAX_REGISTER 96
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# elif defined(__mips__)
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# if defined(_ABIO32) && _MIPS_SIM == _ABIO32
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# define _LIBUNWIND_TARGET_MIPS_O32 1
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@ -726,77 +726,6 @@ enum {
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UNW_OR1K_EPCR = 32,
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};
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// 64-bit RISC-V registers
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enum {
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UNW_RISCV_X0 = 0,
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UNW_RISCV_X1 = 1,
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UNW_RISCV_RA = 1,
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UNW_RISCV_X2 = 2,
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UNW_RISCV_SP = 2,
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UNW_RISCV_X3 = 3,
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UNW_RISCV_X4 = 4,
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UNW_RISCV_X5 = 5,
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UNW_RISCV_X6 = 6,
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UNW_RISCV_X7 = 7,
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UNW_RISCV_X8 = 8,
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UNW_RISCV_X9 = 9,
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UNW_RISCV_X10 = 10,
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UNW_RISCV_X11 = 11,
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UNW_RISCV_X12 = 12,
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UNW_RISCV_X13 = 13,
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UNW_RISCV_X14 = 14,
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UNW_RISCV_X15 = 15,
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UNW_RISCV_X16 = 16,
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UNW_RISCV_X17 = 17,
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UNW_RISCV_X18 = 18,
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UNW_RISCV_X19 = 19,
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UNW_RISCV_X20 = 20,
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UNW_RISCV_X21 = 21,
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UNW_RISCV_X22 = 22,
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UNW_RISCV_X23 = 23,
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UNW_RISCV_X24 = 24,
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UNW_RISCV_X25 = 25,
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UNW_RISCV_X26 = 26,
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UNW_RISCV_X27 = 27,
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UNW_RISCV_X28 = 28,
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UNW_RISCV_X29 = 29,
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UNW_RISCV_X30 = 30,
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UNW_RISCV_X31 = 31,
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// reserved block
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UNW_RISCV_D0 = 64,
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UNW_RISCV_D1 = 65,
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UNW_RISCV_D2 = 66,
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UNW_RISCV_D3 = 67,
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UNW_RISCV_D4 = 68,
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UNW_RISCV_D5 = 69,
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UNW_RISCV_D6 = 70,
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UNW_RISCV_D7 = 71,
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UNW_RISCV_D8 = 72,
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UNW_RISCV_D9 = 73,
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UNW_RISCV_D10 = 74,
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UNW_RISCV_D11 = 75,
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UNW_RISCV_D12 = 76,
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UNW_RISCV_D13 = 77,
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UNW_RISCV_D14 = 78,
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UNW_RISCV_D15 = 79,
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UNW_RISCV_D16 = 80,
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UNW_RISCV_D17 = 81,
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UNW_RISCV_D18 = 82,
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UNW_RISCV_D19 = 83,
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UNW_RISCV_D20 = 84,
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UNW_RISCV_D21 = 85,
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UNW_RISCV_D22 = 86,
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UNW_RISCV_D23 = 87,
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UNW_RISCV_D24 = 88,
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UNW_RISCV_D25 = 89,
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UNW_RISCV_D26 = 90,
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UNW_RISCV_D27 = 91,
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UNW_RISCV_D28 = 92,
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UNW_RISCV_D29 = 93,
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UNW_RISCV_D30 = 94,
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UNW_RISCV_D31 = 95,
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};
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// MIPS registers
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enum {
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UNW_MIPS_R0 = 0,
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@ -31,7 +31,6 @@ enum {
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REGISTERS_ARM64,
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REGISTERS_ARM,
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REGISTERS_OR1K,
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REGISTERS_RISCV,
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REGISTERS_MIPS_O32,
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REGISTERS_MIPS_NEWABI,
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REGISTERS_SPARC,
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@ -2723,267 +2722,6 @@ inline const char *Registers_or1k::getRegisterName(int regNum) {
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}
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#endif // _LIBUNWIND_TARGET_OR1K
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#if defined(_LIBUNWIND_TARGET_RISCV)
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/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V
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/// process.
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class _LIBUNWIND_HIDDEN Registers_riscv {
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public:
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Registers_riscv();
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Registers_riscv(const void *registers);
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bool validRegister(int num) const;
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uint64_t getRegister(int num) const;
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void setRegister(int num, uint64_t value);
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bool validFloatRegister(int num) const;
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double getFloatRegister(int num) const;
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void setFloatRegister(int num, double value);
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bool validVectorRegister(int num) const;
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v128 getVectorRegister(int num) const;
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void setVectorRegister(int num, v128 value);
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static const char *getRegisterName(int num);
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void jumpto();
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static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV; }
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static int getArch() { return REGISTERS_RISCV; }
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uint64_t getSP() const { return _registers.__x[2]; }
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void setSP(uint64_t value) { _registers.__x[2] = value; }
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uint64_t getIP() const { return _registers.__x[1]; }
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void setIP(uint64_t value) { _registers.__x[1] = value; }
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private:
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struct GPRs {
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uint64_t __x[32]; // x0-x31
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};
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GPRs _registers;
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double _vectorHalfRegisters[32];
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// Currently only the lower double in 128-bit vectore registers
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// is perserved during unwinding. We could define new register
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// numbers (> 96) which mean whole vector registers, then this
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// struct would need to change to contain whole vector registers.
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};
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inline Registers_riscv::Registers_riscv(const void *registers) {
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static_assert((check_fit<Registers_riscv, unw_context_t>::does_fit),
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"riscv registers do not fit into unw_context_t");
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memcpy(&_registers, registers, sizeof(_registers));
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static_assert(sizeof(GPRs) == 0x100,
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"expected VFP registers to be at offset 256");
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memcpy(_vectorHalfRegisters,
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static_cast<const uint8_t *>(registers) + sizeof(GPRs),
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sizeof(_vectorHalfRegisters));
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}
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inline Registers_riscv::Registers_riscv() {
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memset(&_registers, 0, sizeof(_registers));
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memset(&_vectorHalfRegisters, 0, sizeof(_vectorHalfRegisters));
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}
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inline bool Registers_riscv::validRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return true;
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if (regNum == UNW_REG_SP)
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return true;
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if (regNum < 0)
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return false;
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if (regNum > 95)
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return false;
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if ((regNum > 31) && (regNum < 64))
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return false;
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return true;
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}
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inline uint64_t Registers_riscv::getRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return _registers.__x[1];
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if (regNum == UNW_REG_SP)
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return _registers.__x[2];
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if ((regNum >= 0) && (regNum < 32))
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return _registers.__x[regNum];
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_LIBUNWIND_ABORT("unsupported riscv register");
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}
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inline void Registers_riscv::setRegister(int regNum, uint64_t value) {
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if (regNum == UNW_REG_IP)
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_registers.__x[1] = value;
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else if (regNum == UNW_REG_SP)
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_registers.__x[2] = value;
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else if ((regNum >= 0) && (regNum < 32))
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_registers.__x[regNum] = value;
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else
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_LIBUNWIND_ABORT("unsupported riscv register");
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}
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inline const char *Registers_riscv::getRegisterName(int regNum) {
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switch (regNum) {
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case UNW_REG_IP:
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return "ra";
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case UNW_REG_SP:
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return "sp";
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case UNW_RISCV_X0:
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return "x0";
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case UNW_RISCV_X1:
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return "ra";
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case UNW_RISCV_X2:
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return "sp";
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case UNW_RISCV_X3:
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return "x3";
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case UNW_RISCV_X4:
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return "x4";
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case UNW_RISCV_X5:
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return "x5";
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case UNW_RISCV_X6:
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return "x6";
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case UNW_RISCV_X7:
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return "x7";
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case UNW_RISCV_X8:
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return "x8";
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case UNW_RISCV_X9:
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return "x9";
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case UNW_RISCV_X10:
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return "x10";
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case UNW_RISCV_X11:
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return "x11";
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case UNW_RISCV_X12:
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return "x12";
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case UNW_RISCV_X13:
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return "x13";
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case UNW_RISCV_X14:
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return "x14";
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case UNW_RISCV_X15:
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return "x15";
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case UNW_RISCV_X16:
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return "x16";
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case UNW_RISCV_X17:
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return "x17";
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case UNW_RISCV_X18:
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return "x18";
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case UNW_RISCV_X19:
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return "x19";
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case UNW_RISCV_X20:
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return "x20";
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case UNW_RISCV_X21:
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return "x21";
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case UNW_RISCV_X22:
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return "x22";
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case UNW_RISCV_X23:
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return "x23";
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case UNW_RISCV_X24:
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return "x24";
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case UNW_RISCV_X25:
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return "x25";
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case UNW_RISCV_X26:
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return "x26";
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case UNW_RISCV_X27:
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return "x27";
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case UNW_RISCV_X28:
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return "x28";
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case UNW_RISCV_X29:
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return "x29";
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case UNW_RISCV_X30:
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return "x30";
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case UNW_RISCV_X31:
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return "x31";
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case UNW_RISCV_D0:
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return "d0";
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case UNW_RISCV_D1:
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return "d1";
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case UNW_RISCV_D2:
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return "d2";
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case UNW_RISCV_D3:
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return "d3";
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case UNW_RISCV_D4:
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return "d4";
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case UNW_RISCV_D5:
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return "d5";
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case UNW_RISCV_D6:
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return "d6";
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case UNW_RISCV_D7:
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return "d7";
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case UNW_RISCV_D8:
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return "d8";
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case UNW_RISCV_D9:
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return "d9";
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case UNW_RISCV_D10:
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return "d10";
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case UNW_RISCV_D11:
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return "d11";
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case UNW_RISCV_D12:
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return "d12";
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case UNW_RISCV_D13:
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return "d13";
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case UNW_RISCV_D14:
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return "d14";
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case UNW_RISCV_D15:
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return "d15";
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case UNW_RISCV_D16:
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return "d16";
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case UNW_RISCV_D17:
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return "d17";
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case UNW_RISCV_D18:
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return "d18";
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case UNW_RISCV_D19:
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return "d19";
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case UNW_RISCV_D20:
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return "d20";
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case UNW_RISCV_D21:
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return "d21";
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case UNW_RISCV_D22:
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return "d22";
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case UNW_RISCV_D23:
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return "d23";
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case UNW_RISCV_D24:
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return "d24";
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case UNW_RISCV_D25:
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return "d25";
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case UNW_RISCV_D26:
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return "d26";
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case UNW_RISCV_D27:
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return "d27";
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case UNW_RISCV_D28:
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return "d28";
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case UNW_RISCV_D29:
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return "d29";
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case UNW_RISCV_D30:
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return "d30";
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case UNW_RISCV_D31:
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return "d31";
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default:
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return "unknown register";
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}
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}
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inline bool Registers_riscv::validFloatRegister(int regNum) const {
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if (regNum < UNW_RISCV_D0)
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return false;
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if (regNum > UNW_RISCV_D31)
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return false;
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return true;
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}
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inline double Registers_riscv::getFloatRegister(int regNum) const {
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assert(validFloatRegister(regNum));
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return _vectorHalfRegisters[regNum - UNW_RISCV_D0];
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}
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inline void Registers_riscv::setFloatRegister(int regNum, double value) {
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assert(validFloatRegister(regNum));
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_vectorHalfRegisters[regNum - UNW_RISCV_D0] = value;
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}
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inline bool Registers_riscv::validVectorRegister(int) const {
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return false;
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}
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inline v128 Registers_riscv::getVectorRegister(int) const {
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_LIBUNWIND_ABORT("no riscv vector register support yet");
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}
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inline void Registers_riscv::setVectorRegister(int, v128) {
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_LIBUNWIND_ABORT("no riscv vector register support yet");
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}
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#endif // _LIBUNWIND_TARGET_RISCV
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#if defined(_LIBUNWIND_TARGET_MIPS_O32)
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/// Registers_mips_o32 holds the register state of a thread in a 32-bit MIPS
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/// process.
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@ -1123,12 +1123,6 @@ class UnwindCursor : public AbstractUnwindCursor{
|
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}
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#endif
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#if defined (_LIBUNWIND_TARGET_RISCV)
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compact_unwind_encoding_t dwarfEncoding(Registers_riscv &) const {
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return 0;
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}
|
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#endif
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#if defined (_LIBUNWIND_TARGET_MIPS_O32)
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compact_unwind_encoding_t dwarfEncoding(Registers_mips_o32 &) const {
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return 0;
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@ -808,87 +808,6 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
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l.jr r9
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l.nop
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#elif defined(__riscv)
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//
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// void libunwind::Registers_riscv::jumpto()
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//
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// On entry:
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// thread_state pointer is in a0
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//
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.p2align 2
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DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
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#ifdef __riscv_float_abi_double
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fld f0, (8 * 32 + 8 * 0)(a0)
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fld f1, (8 * 32 + 8 * 1)(a0)
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fld f2, (8 * 32 + 8 * 2)(a0)
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fld f3, (8 * 32 + 8 * 3)(a0)
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fld f4, (8 * 32 + 8 * 4)(a0)
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fld f5, (8 * 32 + 8 * 5)(a0)
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fld f6, (8 * 32 + 8 * 6)(a0)
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fld f7, (8 * 32 + 8 * 7)(a0)
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fld f8, (8 * 32 + 8 * 8)(a0)
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fld f9, (8 * 32 + 8 * 9)(a0)
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fld f10, (8 * 32 + 8 * 10)(a0)
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fld f11, (8 * 32 + 8 * 11)(a0)
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fld f12, (8 * 32 + 8 * 12)(a0)
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fld f13, (8 * 32 + 8 * 13)(a0)
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fld f14, (8 * 32 + 8 * 14)(a0)
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fld f15, (8 * 32 + 8 * 15)(a0)
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fld f16, (8 * 32 + 8 * 16)(a0)
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fld f17, (8 * 32 + 8 * 17)(a0)
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fld f18, (8 * 32 + 8 * 18)(a0)
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fld f19, (8 * 32 + 8 * 19)(a0)
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fld f20, (8 * 32 + 8 * 20)(a0)
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fld f21, (8 * 32 + 8 * 21)(a0)
|
||||
fld f22, (8 * 32 + 8 * 22)(a0)
|
||||
fld f23, (8 * 32 + 8 * 23)(a0)
|
||||
fld f24, (8 * 32 + 8 * 24)(a0)
|
||||
fld f25, (8 * 32 + 8 * 25)(a0)
|
||||
fld f26, (8 * 32 + 8 * 26)(a0)
|
||||
fld f27, (8 * 32 + 8 * 27)(a0)
|
||||
fld f28, (8 * 32 + 8 * 28)(a0)
|
||||
fld f29, (8 * 32 + 8 * 29)(a0)
|
||||
fld f30, (8 * 32 + 8 * 30)(a0)
|
||||
fld f31, (8 * 32 + 8 * 31)(a0)
|
||||
#endif
|
||||
|
||||
// x0 is zero
|
||||
ld x1, (8 * 1)(a0)
|
||||
ld x2, (8 * 2)(a0)
|
||||
ld x3, (8 * 3)(a0)
|
||||
ld x4, (8 * 4)(a0)
|
||||
ld x5, (8 * 5)(a0)
|
||||
ld x6, (8 * 6)(a0)
|
||||
ld x7, (8 * 7)(a0)
|
||||
ld x8, (8 * 8)(a0)
|
||||
ld x9, (8 * 9)(a0)
|
||||
// skip a0 for now
|
||||
ld x11, (8 * 11)(a0)
|
||||
ld x12, (8 * 12)(a0)
|
||||
ld x13, (8 * 13)(a0)
|
||||
ld x14, (8 * 14)(a0)
|
||||
ld x15, (8 * 15)(a0)
|
||||
ld x16, (8 * 16)(a0)
|
||||
ld x17, (8 * 17)(a0)
|
||||
ld x18, (8 * 18)(a0)
|
||||
ld x19, (8 * 19)(a0)
|
||||
ld x20, (8 * 20)(a0)
|
||||
ld x21, (8 * 21)(a0)
|
||||
ld x22, (8 * 22)(a0)
|
||||
ld x23, (8 * 23)(a0)
|
||||
ld x24, (8 * 24)(a0)
|
||||
ld x25, (8 * 25)(a0)
|
||||
ld x26, (8 * 26)(a0)
|
||||
ld x27, (8 * 27)(a0)
|
||||
ld x28, (8 * 28)(a0)
|
||||
ld x29, (8 * 29)(a0)
|
||||
ld x30, (8 * 30)(a0)
|
||||
ld x31, (8 * 31)(a0)
|
||||
ld x10, (8 * 10)(a0) // restore a0
|
||||
|
||||
ret // jump to ra
|
||||
|
||||
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
|
||||
|
||||
//
|
||||
|
||||
@ -557,7 +557,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
|
||||
#elif defined(__ppc__)
|
||||
|
||||
//
|
||||
// extern int __unw_getcontext(unw_context_t* thread_state)
|
||||
// extern int unw_getcontext(unw_context_t* thread_state)
|
||||
//
|
||||
// On entry:
|
||||
// thread_state pointer is in r3
|
||||
@ -945,86 +945,6 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
|
||||
# zero epcr
|
||||
l.sw 132(r3), r0
|
||||
|
||||
#elif defined(__riscv)
|
||||
|
||||
#
|
||||
# extern int __unw_getcontext(unw_context_t* thread_state)
|
||||
#
|
||||
# On entry:
|
||||
# thread_state pointer is in a0
|
||||
#
|
||||
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
|
||||
// x0 is zero
|
||||
sd x1, (8 * 1)(a0)
|
||||
sd x2, (8 * 2)(a0)
|
||||
sd x3, (8 * 3)(a0)
|
||||
sd x4, (8 * 4)(a0)
|
||||
sd x5, (8 * 5)(a0)
|
||||
sd x6, (8 * 6)(a0)
|
||||
sd x7, (8 * 7)(a0)
|
||||
sd x8, (8 * 8)(a0)
|
||||
sd x9, (8 * 9)(a0)
|
||||
sd x10, (8 * 10)(a0)
|
||||
sd x11, (8 * 11)(a0)
|
||||
sd x12, (8 * 12)(a0)
|
||||
sd x13, (8 * 13)(a0)
|
||||
sd x14, (8 * 14)(a0)
|
||||
sd x15, (8 * 15)(a0)
|
||||
sd x16, (8 * 16)(a0)
|
||||
sd x17, (8 * 17)(a0)
|
||||
sd x18, (8 * 18)(a0)
|
||||
sd x19, (8 * 19)(a0)
|
||||
sd x20, (8 * 20)(a0)
|
||||
sd x21, (8 * 21)(a0)
|
||||
sd x22, (8 * 22)(a0)
|
||||
sd x23, (8 * 23)(a0)
|
||||
sd x24, (8 * 24)(a0)
|
||||
sd x25, (8 * 25)(a0)
|
||||
sd x26, (8 * 26)(a0)
|
||||
sd x27, (8 * 27)(a0)
|
||||
sd x28, (8 * 28)(a0)
|
||||
sd x29, (8 * 29)(a0)
|
||||
sd x30, (8 * 30)(a0)
|
||||
sd x31, (8 * 31)(a0)
|
||||
|
||||
#ifdef __riscv_float_abi_double
|
||||
fsd f0, (8 * 32 + 8 * 0)(a0)
|
||||
fsd f1, (8 * 32 + 8 * 1)(a0)
|
||||
fsd f2, (8 * 32 + 8 * 2)(a0)
|
||||
fsd f3, (8 * 32 + 8 * 3)(a0)
|
||||
fsd f4, (8 * 32 + 8 * 4)(a0)
|
||||
fsd f5, (8 * 32 + 8 * 5)(a0)
|
||||
fsd f6, (8 * 32 + 8 * 6)(a0)
|
||||
fsd f7, (8 * 32 + 8 * 7)(a0)
|
||||
fsd f8, (8 * 32 + 8 * 8)(a0)
|
||||
fsd f9, (8 * 32 + 8 * 9)(a0)
|
||||
fsd f10, (8 * 32 + 8 * 10)(a0)
|
||||
fsd f11, (8 * 32 + 8 * 11)(a0)
|
||||
fsd f12, (8 * 32 + 8 * 12)(a0)
|
||||
fsd f13, (8 * 32 + 8 * 13)(a0)
|
||||
fsd f14, (8 * 32 + 8 * 14)(a0)
|
||||
fsd f15, (8 * 32 + 8 * 15)(a0)
|
||||
fsd f16, (8 * 32 + 8 * 16)(a0)
|
||||
fsd f17, (8 * 32 + 8 * 17)(a0)
|
||||
fsd f18, (8 * 32 + 8 * 18)(a0)
|
||||
fsd f19, (8 * 32 + 8 * 19)(a0)
|
||||
fsd f20, (8 * 32 + 8 * 20)(a0)
|
||||
fsd f21, (8 * 32 + 8 * 21)(a0)
|
||||
fsd f22, (8 * 32 + 8 * 22)(a0)
|
||||
fsd f23, (8 * 32 + 8 * 23)(a0)
|
||||
fsd f24, (8 * 32 + 8 * 24)(a0)
|
||||
fsd f25, (8 * 32 + 8 * 25)(a0)
|
||||
fsd f26, (8 * 32 + 8 * 26)(a0)
|
||||
fsd f27, (8 * 32 + 8 * 27)(a0)
|
||||
fsd f28, (8 * 32 + 8 * 28)(a0)
|
||||
fsd f29, (8 * 32 + 8 * 29)(a0)
|
||||
fsd f30, (8 * 32 + 8 * 30)(a0)
|
||||
fsd f31, (8 * 32 + 8 * 31)(a0)
|
||||
#endif
|
||||
|
||||
li a0, 0 // return UNW_ESUCCESS
|
||||
ret // jump to ra
|
||||
|
||||
#elif defined(__sparc__)
|
||||
|
||||
#
|
||||
|
||||
@ -50,8 +50,6 @@ _LIBUNWIND_HIDDEN int __unw_init_local(unw_cursor_t *cursor,
|
||||
# define REGISTER_KIND Registers_arm
|
||||
#elif defined(__or1k__)
|
||||
# define REGISTER_KIND Registers_or1k
|
||||
#elif defined(__riscv)
|
||||
# define REGISTER_KIND Registers_riscv
|
||||
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
|
||||
# define REGISTER_KIND Registers_mips_o32
|
||||
#elif defined(__mips64)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user