cxgbe(4): Updated register dumps.
- Get the list of registers to read during a regdump from the shared code instead of the OS specific code. This follows a similar move internally. The shared code includes the list for T6. - Update cxgbetool to be able to decode T5 VF, T6, and T6 VF register dumps (and catch up with some updates to T4 and T5 register decode). Obtained from: Chelsio Communications Sponsored by: Chelsio Communications
This commit is contained in:
Navdeep Parhar
parent
8a81693ad5
commit
4f8a1fd8cd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=296471
@ -42,6 +42,11 @@ enum {
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MACADDR_LEN = 12, /* MAC Address length */
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};
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enum {
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T4_REGMAP_SIZE = (160 * 1024),
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T5_REGMAP_SIZE = (332 * 1024),
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};
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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enum {
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@ -510,6 +515,9 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *pari
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int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
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__be32 *data);
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unsigned int t4_get_regs_len(struct adapter *adapter);
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void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size);
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const char *t4_get_port_type_description(enum fw_port_type port_type);
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void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
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void t4_get_port_stats_offset(struct adapter *adap, int idx,
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File diff suppressed because it is too large
Load Diff
@ -425,9 +425,7 @@ static void quiesce_fl(struct adapter *, struct sge_fl *);
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static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
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driver_intr_t *, void *, char *);
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static int t4_free_irq(struct adapter *, struct irq *);
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static void reg_block_dump(struct adapter *, uint8_t *, unsigned int,
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unsigned int);
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static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
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static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
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static void vi_refresh_stats(struct adapter *, struct vi_info *);
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static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
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static void cxgbe_tick(void *);
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@ -4163,691 +4161,11 @@ t4_free_irq(struct adapter *sc, struct irq *irq)
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}
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static void
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reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start,
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unsigned int end)
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get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
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{
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uint32_t *p = (uint32_t *)(buf + start);
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for ( ; start <= end; start += sizeof(uint32_t))
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*p++ = t4_read_reg(sc, start);
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}
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static void
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t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
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{
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int i, n;
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const unsigned int *reg_ranges;
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static const unsigned int t4_reg_ranges[] = {
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0x1008, 0x1108,
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0x1180, 0x11b4,
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0x11fc, 0x123c,
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0x1300, 0x173c,
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0x1800, 0x18fc,
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0x3000, 0x30d8,
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0x30e0, 0x5924,
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0x5960, 0x59d4,
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0x5a00, 0x5af8,
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0x6000, 0x6098,
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0x6100, 0x6150,
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0x6200, 0x6208,
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0x6240, 0x6248,
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0x6280, 0x6338,
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0x6370, 0x638c,
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0x6400, 0x643c,
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0x6500, 0x6524,
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0x6a00, 0x6a38,
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0x6a60, 0x6a78,
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0x6b00, 0x6b84,
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0x6bf0, 0x6c84,
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0x6cf0, 0x6d84,
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0x6df0, 0x6e84,
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0x6ef0, 0x6f84,
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0x6ff0, 0x7084,
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0x70f0, 0x7184,
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0x71f0, 0x7284,
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0x72f0, 0x7384,
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0x73f0, 0x7450,
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0x7500, 0x7530,
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0x7600, 0x761c,
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0x7680, 0x76cc,
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0x7700, 0x7798,
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0x77c0, 0x77fc,
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0x7900, 0x79fc,
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0x7b00, 0x7c38,
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0x7d00, 0x7efc,
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0x8dc0, 0x8e1c,
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0x8e30, 0x8e78,
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0x8ea0, 0x8f6c,
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0x8fc0, 0x9074,
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0x90fc, 0x90fc,
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0x9400, 0x9458,
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0x9600, 0x96bc,
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0x9800, 0x9808,
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0x9820, 0x983c,
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0x9850, 0x9864,
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0x9c00, 0x9c6c,
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0x9c80, 0x9cec,
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0x9d00, 0x9d6c,
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0x9d80, 0x9dec,
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0x9e00, 0x9e6c,
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0x9e80, 0x9eec,
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0x9f00, 0x9f6c,
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0x9f80, 0x9fec,
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0xd004, 0xd03c,
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0xdfc0, 0xdfe0,
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0xe000, 0xea7c,
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0xf000, 0x11110,
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0x11118, 0x11190,
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0x19040, 0x1906c,
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0x19078, 0x19080,
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0x1908c, 0x19124,
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0x19150, 0x191b0,
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0x191d0, 0x191e8,
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0x19238, 0x1924c,
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0x193f8, 0x19474,
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0x19490, 0x194f8,
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0x19800, 0x19f30,
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0x1a000, 0x1a06c,
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0x1a0b0, 0x1a120,
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0x1a128, 0x1a138,
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0x1a190, 0x1a1c4,
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0x1a1fc, 0x1a1fc,
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0x1e040, 0x1e04c,
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0x1e284, 0x1e28c,
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0x1e2c0, 0x1e2c0,
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0x1e2e0, 0x1e2e0,
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0x1e300, 0x1e384,
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0x1e3c0, 0x1e3c8,
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0x1e440, 0x1e44c,
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0x1e684, 0x1e68c,
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0x1e6c0, 0x1e6c0,
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0x1e6e0, 0x1e6e0,
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0x1e700, 0x1e784,
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0x1e7c0, 0x1e7c8,
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0x1e840, 0x1e84c,
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0x1ea84, 0x1ea8c,
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0x1eac0, 0x1eac0,
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0x1eae0, 0x1eae0,
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0x1eb00, 0x1eb84,
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0x1ebc0, 0x1ebc8,
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0x1ec40, 0x1ec4c,
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0x1ee84, 0x1ee8c,
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0x1eec0, 0x1eec0,
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0x1eee0, 0x1eee0,
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0x1ef00, 0x1ef84,
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0x1efc0, 0x1efc8,
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0x1f040, 0x1f04c,
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0x1f284, 0x1f28c,
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0x1f2c0, 0x1f2c0,
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0x1f2e0, 0x1f2e0,
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0x1f300, 0x1f384,
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0x1f3c0, 0x1f3c8,
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0x1f440, 0x1f44c,
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0x1f684, 0x1f68c,
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0x1f6c0, 0x1f6c0,
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0x1f6e0, 0x1f6e0,
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0x1f700, 0x1f784,
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0x1f7c0, 0x1f7c8,
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0x1f840, 0x1f84c,
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0x1fa84, 0x1fa8c,
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0x1fac0, 0x1fac0,
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0x1fae0, 0x1fae0,
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0x1fb00, 0x1fb84,
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0x1fbc0, 0x1fbc8,
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0x1fc40, 0x1fc4c,
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0x1fe84, 0x1fe8c,
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0x1fec0, 0x1fec0,
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0x1fee0, 0x1fee0,
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0x1ff00, 0x1ff84,
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0x1ffc0, 0x1ffc8,
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0x20000, 0x2002c,
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0x20100, 0x2013c,
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0x20190, 0x201c8,
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0x20200, 0x20318,
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0x20400, 0x20528,
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0x20540, 0x20614,
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0x21000, 0x21040,
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0x2104c, 0x21060,
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0x210c0, 0x210ec,
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0x21200, 0x21268,
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0x21270, 0x21284,
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0x212fc, 0x21388,
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0x21400, 0x21404,
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0x21500, 0x21518,
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0x2152c, 0x2153c,
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0x21550, 0x21554,
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0x21600, 0x21600,
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0x21608, 0x21628,
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0x21630, 0x2163c,
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0x21700, 0x2171c,
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0x21780, 0x2178c,
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0x21800, 0x21c38,
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0x21c80, 0x21d7c,
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0x21e00, 0x21e04,
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0x22000, 0x2202c,
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0x22100, 0x2213c,
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0x22190, 0x221c8,
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0x22200, 0x22318,
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0x22400, 0x22528,
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0x22540, 0x22614,
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0x23000, 0x23040,
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0x2304c, 0x23060,
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0x230c0, 0x230ec,
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0x23200, 0x23268,
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0x23270, 0x23284,
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0x232fc, 0x23388,
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0x23400, 0x23404,
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0x23500, 0x23518,
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0x2352c, 0x2353c,
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0x23550, 0x23554,
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0x23600, 0x23600,
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0x23608, 0x23628,
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0x23630, 0x2363c,
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0x23700, 0x2371c,
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0x23780, 0x2378c,
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0x23800, 0x23c38,
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0x23c80, 0x23d7c,
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0x23e00, 0x23e04,
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0x24000, 0x2402c,
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0x24100, 0x2413c,
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0x24190, 0x241c8,
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0x24200, 0x24318,
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0x24400, 0x24528,
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0x24540, 0x24614,
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0x25000, 0x25040,
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0x2504c, 0x25060,
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0x250c0, 0x250ec,
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0x25200, 0x25268,
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0x25270, 0x25284,
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0x252fc, 0x25388,
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0x25400, 0x25404,
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0x25500, 0x25518,
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0x2552c, 0x2553c,
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0x25550, 0x25554,
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0x25600, 0x25600,
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0x25608, 0x25628,
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0x25630, 0x2563c,
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0x25700, 0x2571c,
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0x25780, 0x2578c,
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0x25800, 0x25c38,
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0x25c80, 0x25d7c,
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0x25e00, 0x25e04,
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0x26000, 0x2602c,
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0x26100, 0x2613c,
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0x26190, 0x261c8,
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0x26200, 0x26318,
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0x26400, 0x26528,
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0x26540, 0x26614,
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0x27000, 0x27040,
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0x2704c, 0x27060,
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0x270c0, 0x270ec,
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0x27200, 0x27268,
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0x27270, 0x27284,
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0x272fc, 0x27388,
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0x27400, 0x27404,
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0x27500, 0x27518,
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0x2752c, 0x2753c,
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0x27550, 0x27554,
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0x27600, 0x27600,
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0x27608, 0x27628,
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0x27630, 0x2763c,
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0x27700, 0x2771c,
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0x27780, 0x2778c,
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0x27800, 0x27c38,
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0x27c80, 0x27d7c,
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0x27e00, 0x27e04
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};
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static const unsigned int t5_reg_ranges[] = {
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0x1008, 0x1148,
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0x1180, 0x11b4,
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0x11fc, 0x123c,
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0x1280, 0x173c,
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0x1800, 0x18fc,
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0x3000, 0x3028,
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0x3060, 0x30d8,
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0x30e0, 0x30fc,
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0x3140, 0x357c,
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0x35a8, 0x35cc,
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0x35ec, 0x35ec,
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0x3600, 0x5624,
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0x56cc, 0x575c,
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0x580c, 0x5814,
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0x5890, 0x58bc,
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0x5940, 0x59dc,
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0x59fc, 0x5a18,
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0x5a60, 0x5a9c,
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0x5b94, 0x5bfc,
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0x6000, 0x6040,
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0x6058, 0x614c,
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0x7700, 0x7798,
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0x77c0, 0x78fc,
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0x7b00, 0x7c54,
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0x7d00, 0x7efc,
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0x8dc0, 0x8de0,
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0x8df8, 0x8e84,
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0x8ea0, 0x8f84,
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0x8fc0, 0x90f8,
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0x9400, 0x9470,
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0x9600, 0x96f4,
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0x9800, 0x9808,
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0x9820, 0x983c,
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0x9850, 0x9864,
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0x9c00, 0x9c6c,
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0x9c80, 0x9cec,
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0x9d00, 0x9d6c,
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0x9d80, 0x9dec,
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0x9e00, 0x9e6c,
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0x9e80, 0x9eec,
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0x9f00, 0x9f6c,
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0x9f80, 0xa020,
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0xd004, 0xd03c,
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0xdfc0, 0xdfe0,
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0xe000, 0x11088,
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0x1109c, 0x11110,
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0x11118, 0x1117c,
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0x11190, 0x11204,
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0x19040, 0x1906c,
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0x19078, 0x19080,
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0x1908c, 0x19124,
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0x19150, 0x191b0,
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0x191d0, 0x191e8,
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0x19238, 0x19290,
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0x193f8, 0x19474,
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0x19490, 0x194cc,
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0x194f0, 0x194f8,
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0x19c00, 0x19c60,
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0x19c94, 0x19e10,
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0x19e50, 0x19f34,
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0x19f40, 0x19f50,
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0x19f90, 0x19fe4,
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0x1a000, 0x1a06c,
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0x1a0b0, 0x1a120,
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0x1a128, 0x1a138,
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0x1a190, 0x1a1c4,
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0x1a1fc, 0x1a1fc,
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0x1e008, 0x1e00c,
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0x1e040, 0x1e04c,
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0x1e284, 0x1e290,
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0x1e2c0, 0x1e2c0,
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0x1e2e0, 0x1e2e0,
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0x1e300, 0x1e384,
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0x1e3c0, 0x1e3c8,
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0x1e408, 0x1e40c,
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0x1e440, 0x1e44c,
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0x1e684, 0x1e690,
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0x1e6c0, 0x1e6c0,
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0x1e6e0, 0x1e6e0,
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0x1e700, 0x1e784,
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0x1e7c0, 0x1e7c8,
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0x1e808, 0x1e80c,
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0x1e840, 0x1e84c,
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0x1ea84, 0x1ea90,
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0x1eac0, 0x1eac0,
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0x1eae0, 0x1eae0,
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0x1eb00, 0x1eb84,
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0x1ebc0, 0x1ebc8,
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0x1ec08, 0x1ec0c,
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0x1ec40, 0x1ec4c,
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0x1ee84, 0x1ee90,
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0x1eec0, 0x1eec0,
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0x1eee0, 0x1eee0,
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0x1ef00, 0x1ef84,
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0x1efc0, 0x1efc8,
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0x1f008, 0x1f00c,
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0x1f040, 0x1f04c,
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0x1f284, 0x1f290,
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0x1f2c0, 0x1f2c0,
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0x1f2e0, 0x1f2e0,
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0x1f300, 0x1f384,
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0x1f3c0, 0x1f3c8,
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0x1f408, 0x1f40c,
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0x1f440, 0x1f44c,
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0x1f684, 0x1f690,
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0x1f6c0, 0x1f6c0,
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0x1f6e0, 0x1f6e0,
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0x1f700, 0x1f784,
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0x1f7c0, 0x1f7c8,
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0x1f808, 0x1f80c,
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0x1f840, 0x1f84c,
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0x1fa84, 0x1fa90,
|
||||
0x1fac0, 0x1fac0,
|
||||
0x1fae0, 0x1fae0,
|
||||
0x1fb00, 0x1fb84,
|
||||
0x1fbc0, 0x1fbc8,
|
||||
0x1fc08, 0x1fc0c,
|
||||
0x1fc40, 0x1fc4c,
|
||||
0x1fe84, 0x1fe90,
|
||||
0x1fec0, 0x1fec0,
|
||||
0x1fee0, 0x1fee0,
|
||||
0x1ff00, 0x1ff84,
|
||||
0x1ffc0, 0x1ffc8,
|
||||
0x30000, 0x30030,
|
||||
0x30100, 0x30144,
|
||||
0x30190, 0x301d0,
|
||||
0x30200, 0x30318,
|
||||
0x30400, 0x3052c,
|
||||
0x30540, 0x3061c,
|
||||
0x30800, 0x30834,
|
||||
0x308c0, 0x30908,
|
||||
0x30910, 0x309ac,
|
||||
0x30a00, 0x30a2c,
|
||||
0x30a44, 0x30a50,
|
||||
0x30a74, 0x30c24,
|
||||
0x30d00, 0x30d00,
|
||||
0x30d08, 0x30d14,
|
||||
0x30d1c, 0x30d20,
|
||||
0x30d3c, 0x30d50,
|
||||
0x31200, 0x3120c,
|
||||
0x31220, 0x31220,
|
||||
0x31240, 0x31240,
|
||||
0x31600, 0x3160c,
|
||||
0x31a00, 0x31a1c,
|
||||
0x31e00, 0x31e20,
|
||||
0x31e38, 0x31e3c,
|
||||
0x31e80, 0x31e80,
|
||||
0x31e88, 0x31ea8,
|
||||
0x31eb0, 0x31eb4,
|
||||
0x31ec8, 0x31ed4,
|
||||
0x31fb8, 0x32004,
|
||||
0x32200, 0x32200,
|
||||
0x32208, 0x32240,
|
||||
0x32248, 0x32280,
|
||||
0x32288, 0x322c0,
|
||||
0x322c8, 0x322fc,
|
||||
0x32600, 0x32630,
|
||||
0x32a00, 0x32abc,
|
||||
0x32b00, 0x32b70,
|
||||
0x33000, 0x33048,
|
||||
0x33060, 0x3309c,
|
||||
0x330f0, 0x33148,
|
||||
0x33160, 0x3319c,
|
||||
0x331f0, 0x332e4,
|
||||
0x332f8, 0x333e4,
|
||||
0x333f8, 0x33448,
|
||||
0x33460, 0x3349c,
|
||||
0x334f0, 0x33548,
|
||||
0x33560, 0x3359c,
|
||||
0x335f0, 0x336e4,
|
||||
0x336f8, 0x337e4,
|
||||
0x337f8, 0x337fc,
|
||||
0x33814, 0x33814,
|
||||
0x3382c, 0x3382c,
|
||||
0x33880, 0x3388c,
|
||||
0x338e8, 0x338ec,
|
||||
0x33900, 0x33948,
|
||||
0x33960, 0x3399c,
|
||||
0x339f0, 0x33ae4,
|
||||
0x33af8, 0x33b10,
|
||||
0x33b28, 0x33b28,
|
||||
0x33b3c, 0x33b50,
|
||||
0x33bf0, 0x33c10,
|
||||
0x33c28, 0x33c28,
|
||||
0x33c3c, 0x33c50,
|
||||
0x33cf0, 0x33cfc,
|
||||
0x34000, 0x34030,
|
||||
0x34100, 0x34144,
|
||||
0x34190, 0x341d0,
|
||||
0x34200, 0x34318,
|
||||
0x34400, 0x3452c,
|
||||
0x34540, 0x3461c,
|
||||
0x34800, 0x34834,
|
||||
0x348c0, 0x34908,
|
||||
0x34910, 0x349ac,
|
||||
0x34a00, 0x34a2c,
|
||||
0x34a44, 0x34a50,
|
||||
0x34a74, 0x34c24,
|
||||
0x34d00, 0x34d00,
|
||||
0x34d08, 0x34d14,
|
||||
0x34d1c, 0x34d20,
|
||||
0x34d3c, 0x34d50,
|
||||
0x35200, 0x3520c,
|
||||
0x35220, 0x35220,
|
||||
0x35240, 0x35240,
|
||||
0x35600, 0x3560c,
|
||||
0x35a00, 0x35a1c,
|
||||
0x35e00, 0x35e20,
|
||||
0x35e38, 0x35e3c,
|
||||
0x35e80, 0x35e80,
|
||||
0x35e88, 0x35ea8,
|
||||
0x35eb0, 0x35eb4,
|
||||
0x35ec8, 0x35ed4,
|
||||
0x35fb8, 0x36004,
|
||||
0x36200, 0x36200,
|
||||
0x36208, 0x36240,
|
||||
0x36248, 0x36280,
|
||||
0x36288, 0x362c0,
|
||||
0x362c8, 0x362fc,
|
||||
0x36600, 0x36630,
|
||||
0x36a00, 0x36abc,
|
||||
0x36b00, 0x36b70,
|
||||
0x37000, 0x37048,
|
||||
0x37060, 0x3709c,
|
||||
0x370f0, 0x37148,
|
||||
0x37160, 0x3719c,
|
||||
0x371f0, 0x372e4,
|
||||
0x372f8, 0x373e4,
|
||||
0x373f8, 0x37448,
|
||||
0x37460, 0x3749c,
|
||||
0x374f0, 0x37548,
|
||||
0x37560, 0x3759c,
|
||||
0x375f0, 0x376e4,
|
||||
0x376f8, 0x377e4,
|
||||
0x377f8, 0x377fc,
|
||||
0x37814, 0x37814,
|
||||
0x3782c, 0x3782c,
|
||||
0x37880, 0x3788c,
|
||||
0x378e8, 0x378ec,
|
||||
0x37900, 0x37948,
|
||||
0x37960, 0x3799c,
|
||||
0x379f0, 0x37ae4,
|
||||
0x37af8, 0x37b10,
|
||||
0x37b28, 0x37b28,
|
||||
0x37b3c, 0x37b50,
|
||||
0x37bf0, 0x37c10,
|
||||
0x37c28, 0x37c28,
|
||||
0x37c3c, 0x37c50,
|
||||
0x37cf0, 0x37cfc,
|
||||
0x38000, 0x38030,
|
||||
0x38100, 0x38144,
|
||||
0x38190, 0x381d0,
|
||||
0x38200, 0x38318,
|
||||
0x38400, 0x3852c,
|
||||
0x38540, 0x3861c,
|
||||
0x38800, 0x38834,
|
||||
0x388c0, 0x38908,
|
||||
0x38910, 0x389ac,
|
||||
0x38a00, 0x38a2c,
|
||||
0x38a44, 0x38a50,
|
||||
0x38a74, 0x38c24,
|
||||
0x38d00, 0x38d00,
|
||||
0x38d08, 0x38d14,
|
||||
0x38d1c, 0x38d20,
|
||||
0x38d3c, 0x38d50,
|
||||
0x39200, 0x3920c,
|
||||
0x39220, 0x39220,
|
||||
0x39240, 0x39240,
|
||||
0x39600, 0x3960c,
|
||||
0x39a00, 0x39a1c,
|
||||
0x39e00, 0x39e20,
|
||||
0x39e38, 0x39e3c,
|
||||
0x39e80, 0x39e80,
|
||||
0x39e88, 0x39ea8,
|
||||
0x39eb0, 0x39eb4,
|
||||
0x39ec8, 0x39ed4,
|
||||
0x39fb8, 0x3a004,
|
||||
0x3a200, 0x3a200,
|
||||
0x3a208, 0x3a240,
|
||||
0x3a248, 0x3a280,
|
||||
0x3a288, 0x3a2c0,
|
||||
0x3a2c8, 0x3a2fc,
|
||||
0x3a600, 0x3a630,
|
||||
0x3aa00, 0x3aabc,
|
||||
0x3ab00, 0x3ab70,
|
||||
0x3b000, 0x3b048,
|
||||
0x3b060, 0x3b09c,
|
||||
0x3b0f0, 0x3b148,
|
||||
0x3b160, 0x3b19c,
|
||||
0x3b1f0, 0x3b2e4,
|
||||
0x3b2f8, 0x3b3e4,
|
||||
0x3b3f8, 0x3b448,
|
||||
0x3b460, 0x3b49c,
|
||||
0x3b4f0, 0x3b548,
|
||||
0x3b560, 0x3b59c,
|
||||
0x3b5f0, 0x3b6e4,
|
||||
0x3b6f8, 0x3b7e4,
|
||||
0x3b7f8, 0x3b7fc,
|
||||
0x3b814, 0x3b814,
|
||||
0x3b82c, 0x3b82c,
|
||||
0x3b880, 0x3b88c,
|
||||
0x3b8e8, 0x3b8ec,
|
||||
0x3b900, 0x3b948,
|
||||
0x3b960, 0x3b99c,
|
||||
0x3b9f0, 0x3bae4,
|
||||
0x3baf8, 0x3bb10,
|
||||
0x3bb28, 0x3bb28,
|
||||
0x3bb3c, 0x3bb50,
|
||||
0x3bbf0, 0x3bc10,
|
||||
0x3bc28, 0x3bc28,
|
||||
0x3bc3c, 0x3bc50,
|
||||
0x3bcf0, 0x3bcfc,
|
||||
0x3c000, 0x3c030,
|
||||
0x3c100, 0x3c144,
|
||||
0x3c190, 0x3c1d0,
|
||||
0x3c200, 0x3c318,
|
||||
0x3c400, 0x3c52c,
|
||||
0x3c540, 0x3c61c,
|
||||
0x3c800, 0x3c834,
|
||||
0x3c8c0, 0x3c908,
|
||||
0x3c910, 0x3c9ac,
|
||||
0x3ca00, 0x3ca2c,
|
||||
0x3ca44, 0x3ca50,
|
||||
0x3ca74, 0x3cc24,
|
||||
0x3cd00, 0x3cd00,
|
||||
0x3cd08, 0x3cd14,
|
||||
0x3cd1c, 0x3cd20,
|
||||
0x3cd3c, 0x3cd50,
|
||||
0x3d200, 0x3d20c,
|
||||
0x3d220, 0x3d220,
|
||||
0x3d240, 0x3d240,
|
||||
0x3d600, 0x3d60c,
|
||||
0x3da00, 0x3da1c,
|
||||
0x3de00, 0x3de20,
|
||||
0x3de38, 0x3de3c,
|
||||
0x3de80, 0x3de80,
|
||||
0x3de88, 0x3dea8,
|
||||
0x3deb0, 0x3deb4,
|
||||
0x3dec8, 0x3ded4,
|
||||
0x3dfb8, 0x3e004,
|
||||
0x3e200, 0x3e200,
|
||||
0x3e208, 0x3e240,
|
||||
0x3e248, 0x3e280,
|
||||
0x3e288, 0x3e2c0,
|
||||
0x3e2c8, 0x3e2fc,
|
||||
0x3e600, 0x3e630,
|
||||
0x3ea00, 0x3eabc,
|
||||
0x3eb00, 0x3eb70,
|
||||
0x3f000, 0x3f048,
|
||||
0x3f060, 0x3f09c,
|
||||
0x3f0f0, 0x3f148,
|
||||
0x3f160, 0x3f19c,
|
||||
0x3f1f0, 0x3f2e4,
|
||||
0x3f2f8, 0x3f3e4,
|
||||
0x3f3f8, 0x3f448,
|
||||
0x3f460, 0x3f49c,
|
||||
0x3f4f0, 0x3f548,
|
||||
0x3f560, 0x3f59c,
|
||||
0x3f5f0, 0x3f6e4,
|
||||
0x3f6f8, 0x3f7e4,
|
||||
0x3f7f8, 0x3f7fc,
|
||||
0x3f814, 0x3f814,
|
||||
0x3f82c, 0x3f82c,
|
||||
0x3f880, 0x3f88c,
|
||||
0x3f8e8, 0x3f8ec,
|
||||
0x3f900, 0x3f948,
|
||||
0x3f960, 0x3f99c,
|
||||
0x3f9f0, 0x3fae4,
|
||||
0x3faf8, 0x3fb10,
|
||||
0x3fb28, 0x3fb28,
|
||||
0x3fb3c, 0x3fb50,
|
||||
0x3fbf0, 0x3fc10,
|
||||
0x3fc28, 0x3fc28,
|
||||
0x3fc3c, 0x3fc50,
|
||||
0x3fcf0, 0x3fcfc,
|
||||
0x40000, 0x4000c,
|
||||
0x40040, 0x40068,
|
||||
0x4007c, 0x40144,
|
||||
0x40180, 0x4018c,
|
||||
0x40200, 0x40298,
|
||||
0x402ac, 0x4033c,
|
||||
0x403f8, 0x403fc,
|
||||
0x41304, 0x413c4,
|
||||
0x41400, 0x4141c,
|
||||
0x41480, 0x414d0,
|
||||
0x44000, 0x44078,
|
||||
0x440c0, 0x44278,
|
||||
0x442c0, 0x44478,
|
||||
0x444c0, 0x44678,
|
||||
0x446c0, 0x44878,
|
||||
0x448c0, 0x449fc,
|
||||
0x45000, 0x45068,
|
||||
0x45080, 0x45084,
|
||||
0x450a0, 0x450b0,
|
||||
0x45200, 0x45268,
|
||||
0x45280, 0x45284,
|
||||
0x452a0, 0x452b0,
|
||||
0x460c0, 0x460e4,
|
||||
0x47000, 0x4708c,
|
||||
0x47200, 0x47250,
|
||||
0x47400, 0x47420,
|
||||
0x47600, 0x47618,
|
||||
0x47800, 0x47814,
|
||||
0x48000, 0x4800c,
|
||||
0x48040, 0x48068,
|
||||
0x4807c, 0x48144,
|
||||
0x48180, 0x4818c,
|
||||
0x48200, 0x48298,
|
||||
0x482ac, 0x4833c,
|
||||
0x483f8, 0x483fc,
|
||||
0x49304, 0x493c4,
|
||||
0x49400, 0x4941c,
|
||||
0x49480, 0x494d0,
|
||||
0x4c000, 0x4c078,
|
||||
0x4c0c0, 0x4c278,
|
||||
0x4c2c0, 0x4c478,
|
||||
0x4c4c0, 0x4c678,
|
||||
0x4c6c0, 0x4c878,
|
||||
0x4c8c0, 0x4c9fc,
|
||||
0x4d000, 0x4d068,
|
||||
0x4d080, 0x4d084,
|
||||
0x4d0a0, 0x4d0b0,
|
||||
0x4d200, 0x4d268,
|
||||
0x4d280, 0x4d284,
|
||||
0x4d2a0, 0x4d2b0,
|
||||
0x4e0c0, 0x4e0e4,
|
||||
0x4f000, 0x4f08c,
|
||||
0x4f200, 0x4f250,
|
||||
0x4f400, 0x4f420,
|
||||
0x4f600, 0x4f618,
|
||||
0x4f800, 0x4f814,
|
||||
0x50000, 0x500cc,
|
||||
0x50400, 0x50400,
|
||||
0x50800, 0x508cc,
|
||||
0x50c00, 0x50c00,
|
||||
0x51000, 0x5101c,
|
||||
0x51300, 0x51308,
|
||||
};
|
||||
|
||||
if (is_t4(sc)) {
|
||||
reg_ranges = &t4_reg_ranges[0];
|
||||
n = nitems(t4_reg_ranges);
|
||||
} else {
|
||||
reg_ranges = &t5_reg_ranges[0];
|
||||
n = nitems(t5_reg_ranges);
|
||||
}
|
||||
|
||||
regs->version = chip_id(sc) | chip_rev(sc) << 10;
|
||||
for (i = 0; i < n; i += 2)
|
||||
reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]);
|
||||
t4_get_regs(sc, buf, regs->len);
|
||||
}
|
||||
|
||||
#define A_PL_INDIR_CMD 0x1f8
|
||||
@ -9009,7 +8327,7 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
|
||||
|
||||
regs->len = reglen;
|
||||
buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
|
||||
t4_get_regs(sc, regs, buf);
|
||||
get_regs(sc, regs, buf);
|
||||
rc = copyout(buf, regs->data, reglen);
|
||||
free(buf, M_CXGBE);
|
||||
break;
|
||||
|
||||
@ -79,8 +79,9 @@ struct field_desc {
|
||||
};
|
||||
|
||||
#include "reg_defs_t4.c"
|
||||
#include "reg_defs_t4vf.c"
|
||||
#include "reg_defs_t5.c"
|
||||
#include "reg_defs_t6.c"
|
||||
#include "reg_defs_t4vf.c"
|
||||
|
||||
static void
|
||||
usage(FILE *fp)
|
||||
@ -350,20 +351,6 @@ dump_regs_t4(int argc, const char *argv[], const uint32_t *regs)
|
||||
}
|
||||
#undef T4_MODREGS
|
||||
|
||||
static int
|
||||
dump_regs_t4vf(int argc, const char *argv[], const uint32_t *regs)
|
||||
{
|
||||
static struct mod_regs t4vf_mod[] = {
|
||||
{ "sge", t4vf_sge_regs },
|
||||
{ "mps", t4vf_mps_regs },
|
||||
{ "pl", t4vf_pl_regs },
|
||||
{ "mbdata", t4vf_mbdata_regs },
|
||||
{ "cim", t4vf_cim_regs },
|
||||
};
|
||||
|
||||
return dump_regs_table(argc, argv, regs, t4vf_mod, nitems(t4vf_mod));
|
||||
}
|
||||
|
||||
#define T5_MODREGS(name) { #name, t5_##name##_regs }
|
||||
static int
|
||||
dump_regs_t5(int argc, const char *argv[], const uint32_t *regs)
|
||||
@ -402,6 +389,85 @@ dump_regs_t5(int argc, const char *argv[], const uint32_t *regs)
|
||||
}
|
||||
#undef T5_MODREGS
|
||||
|
||||
#define T6_MODREGS(name) { #name, t6_##name##_regs }
|
||||
static int
|
||||
dump_regs_t6(int argc, const char *argv[], const uint32_t *regs)
|
||||
{
|
||||
static struct mod_regs t6_mod[] = {
|
||||
T6_MODREGS(sge),
|
||||
{ "pci", t6_pcie_regs },
|
||||
T6_MODREGS(dbg),
|
||||
{ "mc0", t6_mc_0_regs },
|
||||
T6_MODREGS(ma),
|
||||
{ "edc0", t6_edc_t60_regs },
|
||||
{ "edc1", t6_edc_t61_regs },
|
||||
T6_MODREGS(cim),
|
||||
T6_MODREGS(tp),
|
||||
{ "ulprx", t6_ulp_rx_regs },
|
||||
{ "ulptx", t6_ulp_tx_regs },
|
||||
{ "pmrx", t6_pm_rx_regs },
|
||||
{ "pmtx", t6_pm_tx_regs },
|
||||
T6_MODREGS(mps),
|
||||
{ "cplsw", t6_cpl_switch_regs },
|
||||
T6_MODREGS(smb),
|
||||
{ "i2c", t6_i2cm_regs },
|
||||
T6_MODREGS(mi),
|
||||
T6_MODREGS(uart),
|
||||
T6_MODREGS(pmu),
|
||||
T6_MODREGS(sf),
|
||||
T6_MODREGS(pl),
|
||||
T6_MODREGS(le),
|
||||
T6_MODREGS(ncsi),
|
||||
T6_MODREGS(mac),
|
||||
{ "hma", t6_hma_t6_regs }
|
||||
};
|
||||
|
||||
return dump_regs_table(argc, argv, regs, t6_mod, nitems(t6_mod));
|
||||
}
|
||||
#undef T6_MODREGS
|
||||
|
||||
static int
|
||||
dump_regs_t4vf(int argc, const char *argv[], const uint32_t *regs)
|
||||
{
|
||||
static struct mod_regs t4vf_mod[] = {
|
||||
{ "sge", t4vf_sge_regs },
|
||||
{ "mps", t4vf_mps_regs },
|
||||
{ "pl", t4vf_pl_regs },
|
||||
{ "mbdata", t4vf_mbdata_regs },
|
||||
{ "cim", t4vf_cim_regs },
|
||||
};
|
||||
|
||||
return dump_regs_table(argc, argv, regs, t4vf_mod, nitems(t4vf_mod));
|
||||
}
|
||||
|
||||
static int
|
||||
dump_regs_t5vf(int argc, const char *argv[], const uint32_t *regs)
|
||||
{
|
||||
static struct mod_regs t5vf_mod[] = {
|
||||
{ "sge", t5vf_sge_regs },
|
||||
{ "mps", t4vf_mps_regs },
|
||||
{ "pl", t5vf_pl_regs },
|
||||
{ "mbdata", t4vf_mbdata_regs },
|
||||
{ "cim", t4vf_cim_regs },
|
||||
};
|
||||
|
||||
return dump_regs_table(argc, argv, regs, t5vf_mod, nitems(t5vf_mod));
|
||||
}
|
||||
|
||||
static int
|
||||
dump_regs_t6vf(int argc, const char *argv[], const uint32_t *regs)
|
||||
{
|
||||
static struct mod_regs t6vf_mod[] = {
|
||||
{ "sge", t5vf_sge_regs },
|
||||
{ "mps", t4vf_mps_regs },
|
||||
{ "pl", t6vf_pl_regs },
|
||||
{ "mbdata", t4vf_mbdata_regs },
|
||||
{ "cim", t4vf_cim_regs },
|
||||
};
|
||||
|
||||
return dump_regs_table(argc, argv, regs, t6vf_mod, nitems(t6vf_mod));
|
||||
}
|
||||
|
||||
static int
|
||||
dump_regs(int argc, const char *argv[])
|
||||
{
|
||||
@ -429,9 +495,17 @@ dump_regs(int argc, const char *argv[])
|
||||
rc = dump_regs_t4vf(argc, argv, regs.data);
|
||||
else
|
||||
rc = dump_regs_t4(argc, argv, regs.data);
|
||||
} else if (vers == 5)
|
||||
rc = dump_regs_t5(argc, argv, regs.data);
|
||||
else {
|
||||
} else if (vers == 5) {
|
||||
if (revision == 0x3f)
|
||||
rc = dump_regs_t5vf(argc, argv, regs.data);
|
||||
else
|
||||
rc = dump_regs_t5(argc, argv, regs.data);
|
||||
} else if (vers == 6) {
|
||||
if (revision == 0x3f)
|
||||
rc = dump_regs_t6vf(argc, argv, regs.data);
|
||||
else
|
||||
rc = dump_regs_t6(argc, argv, regs.data);
|
||||
} else {
|
||||
warnx("%s (type %d, rev %d) is not a known card.",
|
||||
nexus, vers, revision);
|
||||
return (ENOTSUP);
|
||||
|
||||
@ -1,4 +1,6 @@
|
||||
/* This file is automatically generated --- changes will be lost */
|
||||
/* Generation Date : Tue Dec 8 09:33:01 IST 2015 */
|
||||
/* Directory name: t4_reg.txt, Changeset: */
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
struct reg_info t4_sge_regs[] = {
|
||||
@ -1742,7 +1744,7 @@ struct reg_info t4_sge_regs[] = {
|
||||
{ "SGE_LA_RDDATA_15", 0x18f4, 0 },
|
||||
{ "SGE_LA_WRPTR_15", 0x18f8, 0 },
|
||||
{ "SGE_LA_RESERVED_15", 0x18fc, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_pcie_regs[] = {
|
||||
@ -13810,7 +13812,7 @@ struct reg_info t4_pcie_regs[] = {
|
||||
{ "PCIE_PF_GEN_MSG", 0x1fc48, 0 },
|
||||
{ "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
|
||||
{ "Offset", 10, 14 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_dbg_regs[] = {
|
||||
@ -14159,7 +14161,7 @@ struct reg_info t4_dbg_regs[] = {
|
||||
{ "DRVN_B_HISTORY", 4, 4 },
|
||||
{ "DRVN_A_HISTORY", 0, 4 },
|
||||
{ "DBG_PVT_REG_SAMPLE_WAIT_CLKS", 0x6150, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_mc_regs[] = {
|
||||
@ -15134,7 +15136,7 @@ struct reg_info t4_mc_regs[] = {
|
||||
{ "MC_BIST_STATUS_RDATA", 0x76c4, 0 },
|
||||
{ "MC_BIST_STATUS_RDATA", 0x76c8, 0 },
|
||||
{ "MC_BIST_STATUS_RDATA", 0x76cc, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_ma_regs[] = {
|
||||
@ -15439,7 +15441,7 @@ struct reg_info t4_ma_regs[] = {
|
||||
{ "COHERANCY_THREAD_NUM", 1, 3 },
|
||||
{ "COHERANCY_ENABLE", 0, 1 },
|
||||
{ "MA_ERROR_ENABLE", 0x77fc, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_edc_0_regs[] = {
|
||||
@ -15496,7 +15498,7 @@ struct reg_info t4_edc_0_regs[] = {
|
||||
{ "EDC_ECC_STATUS", 0x797c, 0 },
|
||||
{ "ECC_CECNT", 16, 16 },
|
||||
{ "ECC_UECNT", 0, 16 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_edc_1_regs[] = {
|
||||
@ -15553,11 +15555,11 @@ struct reg_info t4_edc_1_regs[] = {
|
||||
{ "EDC_ECC_STATUS", 0x79fc, 0 },
|
||||
{ "ECC_CECNT", 16, 16 },
|
||||
{ "ECC_UECNT", 0, 16 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_hma_regs[] = {
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_cim_regs[] = {
|
||||
@ -16152,7 +16154,7 @@ struct reg_info t4_cim_regs[] = {
|
||||
{ "MBMsgRdyIntEn", 19, 1 },
|
||||
{ "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
|
||||
{ "MBMsgRdyInt", 19, 1 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_tp_regs[] = {
|
||||
@ -16879,7 +16881,7 @@ struct reg_info t4_tp_regs[] = {
|
||||
{ "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
|
||||
{ "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
|
||||
{ "TP_PROTOCOL_DATA4", 0x7efc, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_ulp_tx_regs[] = {
|
||||
@ -17125,7 +17127,7 @@ struct reg_info t4_ulp_tx_regs[] = {
|
||||
{ "ULP_TX_LA_RDDATA_10", 0x8f64, 0 },
|
||||
{ "ULP_TX_LA_WRPTR_10", 0x8f68, 0 },
|
||||
{ "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_pm_rx_regs[] = {
|
||||
@ -17193,7 +17195,7 @@ struct reg_info t4_pm_rx_regs[] = {
|
||||
{ "db_options_par_error", 2, 1 },
|
||||
{ "iespi_par_error", 1, 1 },
|
||||
{ "e_pcmd_par_error", 0, 1 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_pm_tx_regs[] = {
|
||||
@ -17284,7 +17286,7 @@ struct reg_info t4_pm_tx_regs[] = {
|
||||
{ "db_options_par_error", 2, 1 },
|
||||
{ "icspi_par_error", 1, 1 },
|
||||
{ "c_pcmd_par_error", 0, 1 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_mps_regs[] = {
|
||||
@ -17339,8 +17341,7 @@ struct reg_info t4_mps_regs[] = {
|
||||
{ "MPS_DEBUG_DATA_REG_L", 0x906c, 0 },
|
||||
{ "MPS_DEBUG_DATA_REG_H", 0x9070, 0 },
|
||||
{ "MPS_TOP_SPARE", 0x9074, 0 },
|
||||
{ "TopSpare", 12, 20 },
|
||||
{ "Chikn_14463", 8, 4 },
|
||||
{ "TopSpare", 8, 24 },
|
||||
{ "oVlanSelLpbk3", 7, 1 },
|
||||
{ "oVlanSelLpbk2", 6, 1 },
|
||||
{ "oVlanSelLpbk1", 5, 1 },
|
||||
@ -30521,7 +30522,7 @@ struct reg_info t4_mps_regs[] = {
|
||||
{ "MPS_CLS_TCAM_X_H", 0x10fdc, 0 },
|
||||
{ "MPS_CLS_TCAM_X_H", 0x10fec, 0 },
|
||||
{ "MPS_CLS_TCAM_X_H", 0x10ffc, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_cpl_switch_regs[] = {
|
||||
@ -30554,7 +30555,7 @@ struct reg_info t4_cpl_switch_regs[] = {
|
||||
{ "zero_switch_error", 0, 1 },
|
||||
{ "CPL_MAP_TBL_IDX", 0x19058, 0 },
|
||||
{ "CPL_MAP_TBL_DATA", 0x1905c, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_smb_regs[] = {
|
||||
@ -30689,7 +30690,7 @@ struct reg_info t4_smb_regs[] = {
|
||||
{ "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
|
||||
{ "MacroCntClkCfg", 8, 5 },
|
||||
{ "MicroCntClkCfg", 0, 8 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_i2cm_regs[] = {
|
||||
@ -30700,7 +30701,7 @@ struct reg_info t4_i2cm_regs[] = {
|
||||
{ "Ack", 30, 1 },
|
||||
{ "Cont", 1, 1 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_mi_regs[] = {
|
||||
@ -30720,7 +30721,7 @@ struct reg_info t4_mi_regs[] = {
|
||||
{ "St", 3, 2 },
|
||||
{ "Inc", 2, 1 },
|
||||
{ "Op", 0, 2 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_uart_regs[] = {
|
||||
@ -30729,7 +30730,7 @@ struct reg_info t4_uart_regs[] = {
|
||||
{ "Parity", 20, 2 },
|
||||
{ "DataBits", 16, 4 },
|
||||
{ "ClkDiv", 0, 12 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_pmu_regs[] = {
|
||||
@ -30749,7 +30750,7 @@ struct reg_info t4_pmu_regs[] = {
|
||||
{ "Port1SleepMode", 2, 1 },
|
||||
{ "Port0SleepMode", 1, 1 },
|
||||
{ "WakeUp", 0, 1 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_ulp_rx_regs[] = {
|
||||
@ -30776,24 +30777,24 @@ struct reg_info t4_ulp_rx_regs[] = {
|
||||
{ "ENABLE_APF_0", 20, 1 },
|
||||
{ "ENABLE_AF_1", 19, 1 },
|
||||
{ "ENABLE_AF_0", 18, 1 },
|
||||
{ "ENABLE_PCMDF_1", 17, 1 },
|
||||
{ "ENABLE_MPARC_1", 16, 1 },
|
||||
{ "ENABLE_MPARF_1", 15, 1 },
|
||||
{ "ENABLE_DDPCF_1", 14, 1 },
|
||||
{ "ENABLE_TPTCF_1", 13, 1 },
|
||||
{ "ENABLE_PCMDF_0", 12, 1 },
|
||||
{ "ENABLE_MPARC_0", 11, 1 },
|
||||
{ "ENABLE_MPARF_0", 10, 1 },
|
||||
{ "ENABLE_DDPCF_0", 9, 1 },
|
||||
{ "ENABLE_TPTCF_0", 8, 1 },
|
||||
{ "ENABLE_DDPDF_1", 7, 1 },
|
||||
{ "ENABLE_DDPMF_1", 6, 1 },
|
||||
{ "ENABLE_MEMRF_1", 5, 1 },
|
||||
{ "ENABLE_PRSDF_1", 4, 1 },
|
||||
{ "ENABLE_DDPDF_0", 3, 1 },
|
||||
{ "ENABLE_DDPMF_0", 2, 1 },
|
||||
{ "ENABLE_MEMRF_0", 1, 1 },
|
||||
{ "ENABLE_PRSDF_0", 0, 1 },
|
||||
{ "ENABLE_DDPDF_1", 17, 1 },
|
||||
{ "ENABLE_DDPMF_1", 16, 1 },
|
||||
{ "ENABLE_MEMRF_1", 15, 1 },
|
||||
{ "ENABLE_PRSDF_1", 14, 1 },
|
||||
{ "ENABLE_DDPDF_0", 13, 1 },
|
||||
{ "ENABLE_DDPMF_0", 12, 1 },
|
||||
{ "ENABLE_MEMRF_0", 11, 1 },
|
||||
{ "ENABLE_PRSDF_0", 10, 1 },
|
||||
{ "ENABLE_PCMDF_1", 9, 1 },
|
||||
{ "ENABLE_TPTCF_1", 8, 1 },
|
||||
{ "ENABLE_DDPCF_1", 7, 1 },
|
||||
{ "ENABLE_MPARF_1", 6, 1 },
|
||||
{ "ENABLE_MPARC_1", 5, 1 },
|
||||
{ "ENABLE_PCMDF_0", 4, 1 },
|
||||
{ "ENABLE_TPTCF_0", 3, 1 },
|
||||
{ "ENABLE_DDPCF_0", 2, 1 },
|
||||
{ "ENABLE_MPARF_0", 1, 1 },
|
||||
{ "ENABLE_MPARC_0", 0, 1 },
|
||||
{ "ULP_RX_INT_CAUSE", 0x19158, 0 },
|
||||
{ "CAUSE_CTX_1", 24, 1 },
|
||||
{ "CAUSE_CTX_0", 23, 1 },
|
||||
@ -30802,24 +30803,24 @@ struct reg_info t4_ulp_rx_regs[] = {
|
||||
{ "CAUSE_APF_0", 20, 1 },
|
||||
{ "CAUSE_AF_1", 19, 1 },
|
||||
{ "CAUSE_AF_0", 18, 1 },
|
||||
{ "CAUSE_PCMDF_1", 17, 1 },
|
||||
{ "CAUSE_MPARC_1", 16, 1 },
|
||||
{ "CAUSE_MPARF_1", 15, 1 },
|
||||
{ "CAUSE_DDPCF_1", 14, 1 },
|
||||
{ "CAUSE_TPTCF_1", 13, 1 },
|
||||
{ "CAUSE_PCMDF_0", 12, 1 },
|
||||
{ "CAUSE_MPARC_0", 11, 1 },
|
||||
{ "CAUSE_MPARF_0", 10, 1 },
|
||||
{ "CAUSE_DDPCF_0", 9, 1 },
|
||||
{ "CAUSE_TPTCF_0", 8, 1 },
|
||||
{ "CAUSE_DDPDF_1", 7, 1 },
|
||||
{ "CAUSE_DDPMF_1", 6, 1 },
|
||||
{ "CAUSE_MEMRF_1", 5, 1 },
|
||||
{ "CAUSE_PRSDF_1", 4, 1 },
|
||||
{ "CAUSE_DDPDF_0", 3, 1 },
|
||||
{ "CAUSE_DDPMF_0", 2, 1 },
|
||||
{ "CAUSE_MEMRF_0", 1, 1 },
|
||||
{ "CAUSE_PRSDF_0", 0, 1 },
|
||||
{ "CAUSE_DDPDF_1", 17, 1 },
|
||||
{ "CAUSE_DDPMF_1", 16, 1 },
|
||||
{ "CAUSE_MEMRF_1", 15, 1 },
|
||||
{ "CAUSE_PRSDF_1", 14, 1 },
|
||||
{ "CAUSE_DDPDF_0", 13, 1 },
|
||||
{ "CAUSE_DDPMF_0", 12, 1 },
|
||||
{ "CAUSE_MEMRF_0", 11, 1 },
|
||||
{ "CAUSE_PRSDF_0", 10, 1 },
|
||||
{ "CAUSE_PCMDF_1", 9, 1 },
|
||||
{ "CAUSE_TPTCF_1", 8, 1 },
|
||||
{ "CAUSE_DDPCF_1", 7, 1 },
|
||||
{ "CAUSE_MPARF_1", 6, 1 },
|
||||
{ "CAUSE_MPARC_1", 5, 1 },
|
||||
{ "CAUSE_PCMDF_0", 4, 1 },
|
||||
{ "CAUSE_TPTCF_0", 3, 1 },
|
||||
{ "CAUSE_DDPCF_0", 2, 1 },
|
||||
{ "CAUSE_MPARF_0", 1, 1 },
|
||||
{ "CAUSE_MPARC_0", 0, 1 },
|
||||
{ "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
|
||||
{ "IscsiLlimit", 6, 26 },
|
||||
{ "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
|
||||
@ -30850,29 +30851,29 @@ struct reg_info t4_ulp_rx_regs[] = {
|
||||
{ "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
|
||||
{ "ULP_RX_CTX_BASE", 0x19194, 0 },
|
||||
{ "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
|
||||
{ "ENABLE_FF", 22, 1 },
|
||||
{ "ENABLE_APF_1", 21, 1 },
|
||||
{ "ENABLE_APF_0", 20, 1 },
|
||||
{ "ENABLE_AF_1", 19, 1 },
|
||||
{ "ENABLE_AF_0", 18, 1 },
|
||||
{ "ENABLE_PCMDF_1", 17, 1 },
|
||||
{ "ENABLE_MPARC_1", 16, 1 },
|
||||
{ "ENABLE_MPARF_1", 15, 1 },
|
||||
{ "ENABLE_DDPCF_1", 14, 1 },
|
||||
{ "ENABLE_TPTCF_1", 13, 1 },
|
||||
{ "ENABLE_PCMDF_0", 12, 1 },
|
||||
{ "ENABLE_MPARC_0", 11, 1 },
|
||||
{ "ENABLE_MPARF_0", 10, 1 },
|
||||
{ "ENABLE_DDPCF_0", 9, 1 },
|
||||
{ "ENABLE_TPTCF_0", 8, 1 },
|
||||
{ "ENABLE_DDPDF_1", 7, 1 },
|
||||
{ "ENABLE_DDPMF_1", 6, 1 },
|
||||
{ "ENABLE_MEMRF_1", 5, 1 },
|
||||
{ "ENABLE_PRSDF_1", 4, 1 },
|
||||
{ "ENABLE_DDPDF_0", 3, 1 },
|
||||
{ "ENABLE_DDPMF_0", 2, 1 },
|
||||
{ "ENABLE_MEMRF_0", 1, 1 },
|
||||
{ "ENABLE_PRSDF_0", 0, 1 },
|
||||
{ "PERR_ENABLE_FF", 22, 1 },
|
||||
{ "PERR_ENABLE_APF_1", 21, 1 },
|
||||
{ "PERR_ENABLE_APF_0", 20, 1 },
|
||||
{ "PERR_ENABLE_AF_1", 19, 1 },
|
||||
{ "PERR_ENABLE_AF_0", 18, 1 },
|
||||
{ "PERR_ENABLE_DDPDF_1", 17, 1 },
|
||||
{ "PERR_ENABLE_DDPMF_1", 16, 1 },
|
||||
{ "PERR_ENABLE_MEMRF_1", 15, 1 },
|
||||
{ "PERR_ENABLE_PRSDF_1", 14, 1 },
|
||||
{ "PERR_ENABLE_DDPDF_0", 13, 1 },
|
||||
{ "PERR_ENABLE_DDPMF_0", 12, 1 },
|
||||
{ "PERR_ENABLE_MEMRF_0", 11, 1 },
|
||||
{ "PERR_ENABLE_PRSDF_0", 10, 1 },
|
||||
{ "PERR_ENABLE_PCMDF_1", 9, 1 },
|
||||
{ "PERR_ENABLE_TPTCF_1", 8, 1 },
|
||||
{ "PERR_ENABLE_DDPCF_1", 7, 1 },
|
||||
{ "PERR_ENABLE_MPARF_1", 6, 1 },
|
||||
{ "PERR_ENABLE_MPARC_1", 5, 1 },
|
||||
{ "PERR_ENABLE_PCMDF_0", 4, 1 },
|
||||
{ "PERR_ENABLE_TPTCF_0", 3, 1 },
|
||||
{ "PERR_ENABLE_DDPCF_0", 2, 1 },
|
||||
{ "PERR_ENABLE_MPARF_0", 1, 1 },
|
||||
{ "PERR_ENABLE_MPARC_0", 0, 1 },
|
||||
{ "ULP_RX_PERR_INJECT", 0x191a0, 0 },
|
||||
{ "MemSel", 1, 5 },
|
||||
{ "InjectDataErr", 0, 1 },
|
||||
@ -30923,7 +30924,7 @@ struct reg_info t4_ulp_rx_regs[] = {
|
||||
{ "ULP_RX_LA_RDDATA", 0x19244, 0 },
|
||||
{ "ULP_RX_LA_WRPTR", 0x19248, 0 },
|
||||
{ "ULP_RX_LA_RESERVED", 0x1924c, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_sf_regs[] = {
|
||||
@ -30934,7 +30935,7 @@ struct reg_info t4_sf_regs[] = {
|
||||
{ "Cont", 3, 1 },
|
||||
{ "ByteCnt", 1, 2 },
|
||||
{ "Op", 0, 1 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_pl_regs[] = {
|
||||
@ -32072,7 +32073,7 @@ struct reg_info t4_pl_regs[] = {
|
||||
{ "PL_VFID_MAP", 0x19bfc, 0 },
|
||||
{ "Valid", 7, 1 },
|
||||
{ "VFID", 0, 7 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_le_regs[] = {
|
||||
@ -32351,7 +32352,14 @@ struct reg_info t4_le_regs[] = {
|
||||
{ "LE_REQ_DEBUG_LA_WRPTR", 0x19f28, 0 },
|
||||
{ "LE_RSP_DEBUG_LA_DATA", 0x19f2c, 0 },
|
||||
{ "LE_RSP_DEBUG_LA_WRPTR", 0x19f30, 0 },
|
||||
{ NULL, 0, 0 }
|
||||
{ "LE_DEBUG_LA_SELECTOR", 0x19f34, 0 },
|
||||
{ "LE_DEBUG_LA_CAPTURED_DATA", 0x19f38, 0 },
|
||||
{ "LE_MA_DEBUG_LA_DATA", 0x19f3c, 0 },
|
||||
{ "LE_RSP_DEBUG_LA_HASH_WRPTR", 0x19f40, 0 },
|
||||
{ "LE_HASH_DEBUG_LA_DATA", 0x19f44, 0 },
|
||||
{ "LE_RSP_DEBUG_LA_TCAM_WRPTR", 0x19f48, 0 },
|
||||
{ "LE_TCAM_DEBUG_LA_DATA", 0x19f4c, 0 },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_ncsi_regs[] = {
|
||||
@ -32622,7 +32630,7 @@ struct reg_info t4_ncsi_regs[] = {
|
||||
{ "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
|
||||
{ "PartRef", 16, 16 },
|
||||
{ "DesRev", 0, 16 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
struct reg_info t4_xgmac_regs[] = {
|
||||
@ -40390,5 +40398,5 @@ struct reg_info t4_xgmac_regs[] = {
|
||||
{ "PRST", 4, 1 },
|
||||
{ "PCHKEN", 3, 1 },
|
||||
{ "PRBSSEL", 0, 3 },
|
||||
{ NULL, 0, 0 }
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
@ -19,6 +19,21 @@ struct reg_info t4vf_sge_regs[] = {
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t5vf_sge_regs[] = {
|
||||
{ "SGE_VF_KDOORBELL", 0x000, 0 },
|
||||
{ "QID", 15, 17 },
|
||||
{ "Priority", 14, 1 },
|
||||
{ "Type", 13, 1 },
|
||||
{ "PIDX", 0, 13 },
|
||||
{ "SGE_VF_GTS", 0x004, 0 },
|
||||
{ "IngressQID", 16, 16 },
|
||||
{ "TimerReg", 13, 3 },
|
||||
{ "SEIntArm", 12, 1 },
|
||||
{ "CIDXInc", 0, 12 },
|
||||
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t4vf_mps_regs[] = {
|
||||
{ "MPS_VF_CTL", 0x100, 0 },
|
||||
{ "TxEn", 1, 1 },
|
||||
@ -70,9 +85,41 @@ struct reg_info t4vf_mps_regs[] = {
|
||||
|
||||
struct reg_info t4vf_pl_regs[] = {
|
||||
{ "PL_VF_WHOAMI", 0x200, 0 },
|
||||
{ "PortxMap", 5, 3 },
|
||||
{ "SourceBus", 3, 2 },
|
||||
{ "SourcePF", 0, 3 },
|
||||
{ "PortxMap", 24, 3 },
|
||||
{ "SourceBus", 16, 2 },
|
||||
{ "SourcePF", 8, 3 },
|
||||
{ "IsVF", 7, 1 },
|
||||
{ "VFID", 0, 7 },
|
||||
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t5vf_pl_regs[] = {
|
||||
{ "PL_WHOAMI", 0x200, 0 },
|
||||
{ "PortxMap", 24, 3 },
|
||||
{ "SourceBus", 16, 2 },
|
||||
{ "SourcePF", 8, 3 },
|
||||
{ "IsVF", 7, 1 },
|
||||
{ "VFID", 0, 7 },
|
||||
{ "PL_VF_REV", 0x204, 0 },
|
||||
{ "ChipID", 4, 4 },
|
||||
{ "Rev", 0, 4 },
|
||||
{ "PL_VF_REVISION", 0x208, 0 },
|
||||
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
|
||||
struct reg_info t6vf_pl_regs[] = {
|
||||
{ "PL_WHOAMI", 0x200, 0 },
|
||||
{ "PortxMap", 24, 3 },
|
||||
{ "SourceBus", 16, 2 },
|
||||
{ "SourcePF", 9, 3 },
|
||||
{ "IsVF", 8, 1 },
|
||||
{ "VFID", 0, 8 },
|
||||
{ "PL_VF_REV", 0x204, 0 },
|
||||
{ "ChipID", 4, 4 },
|
||||
{ "Rev", 0, 4 },
|
||||
{ "PL_VF_REVISION", 0x208, 0 },
|
||||
|
||||
{ NULL, 0, 0 }
|
||||
};
|
||||
@ -85,7 +132,7 @@ struct reg_info t4vf_cim_regs[] = {
|
||||
{ "CIM_VF_EXT_MAILBOX_CTRL", 0x300, 0 },
|
||||
{ "MBGeneric", 4, 4 },
|
||||
{ "MBMsgValid", 3, 1 },
|
||||
{ "MBIntReq", 3, 1 },
|
||||
{ "MBIntReq", 2, 1 },
|
||||
{ "MBOwner", 0, 2 },
|
||||
{ "CIM_VF_EXT_MAILBOX_STATUS", 0x304, 0 },
|
||||
{ "MBVFReady", 0, 1 },
|
||||
|
||||
@ -1,4 +1,6 @@
|
||||
/* This file is automatically generated --- changes will be lost */
|
||||
/* Generation Date : Mon Dec 7 19:40:45 IST 2015 */
|
||||
/* Directory name: t5_reg.txt, Changeset: 6934:86d3c0167c2c */
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
struct reg_info t5_sge_regs[] = {
|
||||
@ -20516,10 +20518,10 @@ struct reg_info t5_dbg_regs[] = {
|
||||
{ "GPIO17_CHG_DET", 6, 1 },
|
||||
{ "GPIO18_CHG_DET", 5, 1 },
|
||||
{ "GPIO19_CHG_DET", 4, 1 },
|
||||
{ "GPIO16_IN", 3, 1 },
|
||||
{ "GPIO17_IN", 2, 1 },
|
||||
{ "GPIO18_IN", 1, 1 },
|
||||
{ "GPIO19_IN", 0, 1 },
|
||||
{ "GPIO19_IN", 3, 1 },
|
||||
{ "GPIO18_IN", 2, 1 },
|
||||
{ "GPIO17_IN", 1, 1 },
|
||||
{ "GPIO16_IN", 0, 1 },
|
||||
{ "DBG_INT_ENABLE", 0x6018, 0 },
|
||||
{ "GPIO19", 29, 1 },
|
||||
{ "GPIO18", 28, 1 },
|
||||
@ -24446,63 +24448,63 @@ struct reg_info t5_mps_regs[] = {
|
||||
{ "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 },
|
||||
{ "SOPCh1", 31, 1 },
|
||||
{ "EOPCh1", 30, 1 },
|
||||
{ "SizeCh1", 27, 3 },
|
||||
{ "ErrCh1", 26, 1 },
|
||||
{ "FullCh1", 25, 1 },
|
||||
{ "ValidCh1", 24, 1 },
|
||||
{ "DataCh1", 16, 8 },
|
||||
{ "SizeCh1", 26, 4 },
|
||||
{ "ErrCh1", 25, 1 },
|
||||
{ "FullCh1", 24, 1 },
|
||||
{ "ValidCh1", 23, 1 },
|
||||
{ "DataCh1", 16, 7 },
|
||||
{ "SOPCh0", 15, 1 },
|
||||
{ "EOPCh0", 14, 1 },
|
||||
{ "SizeCh0", 11, 3 },
|
||||
{ "ErrCh0", 10, 1 },
|
||||
{ "FullCh0", 9, 1 },
|
||||
{ "ValidCh0", 8, 1 },
|
||||
{ "DataCh0", 0, 8 },
|
||||
{ "SizeCh0", 10, 4 },
|
||||
{ "ErrCh0", 9, 1 },
|
||||
{ "FullCh0", 8, 1 },
|
||||
{ "ValidCh0", 7, 1 },
|
||||
{ "DataCh0", 0, 7 },
|
||||
{ "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 },
|
||||
{ "SOPCh3", 31, 1 },
|
||||
{ "EOPCh3", 30, 1 },
|
||||
{ "SizeCh3", 27, 3 },
|
||||
{ "ErrCh3", 26, 1 },
|
||||
{ "FullCh3", 25, 1 },
|
||||
{ "ValidCh3", 24, 1 },
|
||||
{ "DataCh3", 16, 8 },
|
||||
{ "SizeCh3", 26, 4 },
|
||||
{ "ErrCh3", 25, 1 },
|
||||
{ "FullCh3", 24, 1 },
|
||||
{ "ValidCh3", 23, 1 },
|
||||
{ "DataCh3", 16, 7 },
|
||||
{ "SOPCh2", 15, 1 },
|
||||
{ "EOPCh2", 14, 1 },
|
||||
{ "SizeCh2", 11, 3 },
|
||||
{ "ErrCh2", 10, 1 },
|
||||
{ "FullCh2", 9, 1 },
|
||||
{ "ValidCh2", 8, 1 },
|
||||
{ "DataCh2", 0, 8 },
|
||||
{ "SizeCh2", 10, 4 },
|
||||
{ "ErrCh2", 9, 1 },
|
||||
{ "FullCh2", 8, 1 },
|
||||
{ "ValidCh2", 7, 1 },
|
||||
{ "DataCh2", 0, 7 },
|
||||
{ "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 },
|
||||
{ "SOPPt1", 31, 1 },
|
||||
{ "EOPPt1", 30, 1 },
|
||||
{ "SizePt1", 27, 3 },
|
||||
{ "ErrPt1", 26, 1 },
|
||||
{ "FullPt1", 25, 1 },
|
||||
{ "ValidPt1", 24, 1 },
|
||||
{ "DataPt1", 16, 8 },
|
||||
{ "SizePt1", 26, 4 },
|
||||
{ "ErrPt1", 25, 1 },
|
||||
{ "FullPt1", 24, 1 },
|
||||
{ "ValidPt1", 23, 1 },
|
||||
{ "DataPt1", 16, 7 },
|
||||
{ "SOPPt0", 15, 1 },
|
||||
{ "EOPPt0", 14, 1 },
|
||||
{ "SizePt0", 11, 3 },
|
||||
{ "ErrPt0", 10, 1 },
|
||||
{ "FullPt0", 9, 1 },
|
||||
{ "ValidPt0", 8, 1 },
|
||||
{ "DataPt0", 0, 8 },
|
||||
{ "SizePt0", 10, 4 },
|
||||
{ "ErrPt0", 9, 1 },
|
||||
{ "FullPt0", 8, 1 },
|
||||
{ "ValidPt0", 7, 1 },
|
||||
{ "DataPt0", 0, 7 },
|
||||
{ "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 },
|
||||
{ "SOPPt3", 31, 1 },
|
||||
{ "EOPPt3", 30, 1 },
|
||||
{ "SizePt3", 27, 3 },
|
||||
{ "ErrPt3", 26, 1 },
|
||||
{ "FullPt3", 25, 1 },
|
||||
{ "ValidPt3", 24, 1 },
|
||||
{ "DataPt3", 16, 8 },
|
||||
{ "SizePt3", 26, 4 },
|
||||
{ "ErrPt3", 25, 1 },
|
||||
{ "FullPt3", 24, 1 },
|
||||
{ "ValidPt3", 23, 1 },
|
||||
{ "DataPt3", 16, 7 },
|
||||
{ "SOPPt2", 15, 1 },
|
||||
{ "EOPPt2", 14, 1 },
|
||||
{ "SizePt2", 11, 3 },
|
||||
{ "ErrPt2", 10, 1 },
|
||||
{ "FullPt2", 9, 1 },
|
||||
{ "ValidPt2", 8, 1 },
|
||||
{ "DataPt2", 0, 8 },
|
||||
{ "SizePt2", 10, 4 },
|
||||
{ "ErrPt2", 9, 1 },
|
||||
{ "FullPt2", 8, 1 },
|
||||
{ "ValidPt2", 7, 1 },
|
||||
{ "DataPt2", 0, 7 },
|
||||
{ "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
|
||||
{ "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 },
|
||||
{ "SubPrtH", 11, 5 },
|
||||
@ -58429,13 +58431,14 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "PER_ENA_RANK_PAIR", 12, 4 },
|
||||
{ "PER_ENA_ZCAL", 11, 1 },
|
||||
{ "PER_ENA_SYSCLK_ALIGN", 10, 1 },
|
||||
{ "ENA_PER_RDCLK_ALIGN", 9, 1 },
|
||||
{ "ENA_PER_DQS_ALIGN", 8, 1 },
|
||||
{ "ENA_PER_READ_CTR", 7, 1 },
|
||||
{ "ENA_PER_READ_CTR", 9, 1 },
|
||||
{ "ENA_PER_RDCLK_ALIGN", 8, 1 },
|
||||
{ "ENA_PER_DQS_ALIGN", 7, 1 },
|
||||
{ "PER_NEXT_RANK_PAIR", 5, 2 },
|
||||
{ "FAST_SIM_PER_CNTR", 4, 1 },
|
||||
{ "START_INIT_CAL", 3, 1 },
|
||||
{ "START_PER_CAL", 2, 1 },
|
||||
{ "ABORT_ON_ERR_EN", 1, 1 },
|
||||
{ "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4703c, 0 },
|
||||
{ "PER_ZCAL_ENA_RANK", 8, 8 },
|
||||
{ "PER_ZCAL_NEXT_RANK", 5, 3 },
|
||||
@ -59284,6 +59287,8 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44078, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x440d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x440d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x441b4, 0 },
|
||||
@ -59298,10 +59303,13 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x441fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44048, 0 },
|
||||
@ -59711,6 +59719,8 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44278, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x442d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x442d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x443b4, 0 },
|
||||
@ -59725,10 +59735,13 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x443fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44248, 0 },
|
||||
@ -60138,6 +60151,8 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44478, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x444d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x444d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x445b4, 0 },
|
||||
@ -60152,10 +60167,13 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x445fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44448, 0 },
|
||||
@ -60565,6 +60583,8 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44678, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x446d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x446d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x447b4, 0 },
|
||||
@ -60579,10 +60599,13 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x447fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44648, 0 },
|
||||
@ -60992,6 +61015,8 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44878, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x448d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x448d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x449b4, 0 },
|
||||
@ -61006,10 +61031,13 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x449fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44848, 0 },
|
||||
@ -61091,6 +61119,7 @@ struct reg_info t5_mc_0_regs[] = {
|
||||
{ "MC_DDRPHY_WC_CONFIG2", 0x47608, 0 },
|
||||
{ "NUM_VALID_SAMPLES", 12, 4 },
|
||||
{ "FW_RD_WR", 6, 6 },
|
||||
{ "EN_RESET_WR_DELAY_WL", 0, 1 },
|
||||
{ "MC_DDRPHY_WC_CONFIG3", 0x47614, 0 },
|
||||
{ "DDR4_MRS_CMD_DQ_EN", 15, 1 },
|
||||
{ "MRS_CMD_DQ_ON", 9, 6 },
|
||||
@ -61660,13 +61689,14 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "PER_ENA_RANK_PAIR", 12, 4 },
|
||||
{ "PER_ENA_ZCAL", 11, 1 },
|
||||
{ "PER_ENA_SYSCLK_ALIGN", 10, 1 },
|
||||
{ "ENA_PER_RDCLK_ALIGN", 9, 1 },
|
||||
{ "ENA_PER_DQS_ALIGN", 8, 1 },
|
||||
{ "ENA_PER_READ_CTR", 7, 1 },
|
||||
{ "ENA_PER_READ_CTR", 9, 1 },
|
||||
{ "ENA_PER_RDCLK_ALIGN", 8, 1 },
|
||||
{ "ENA_PER_DQS_ALIGN", 7, 1 },
|
||||
{ "PER_NEXT_RANK_PAIR", 5, 2 },
|
||||
{ "FAST_SIM_PER_CNTR", 4, 1 },
|
||||
{ "START_INIT_CAL", 3, 1 },
|
||||
{ "START_PER_CAL", 2, 1 },
|
||||
{ "ABORT_ON_ERR_EN", 1, 1 },
|
||||
{ "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4f03c, 0 },
|
||||
{ "PER_ZCAL_ENA_RANK", 8, 8 },
|
||||
{ "PER_ZCAL_NEXT_RANK", 5, 3 },
|
||||
@ -62515,6 +62545,8 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c078, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c0d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c0d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c1b4, 0 },
|
||||
@ -62529,10 +62561,13 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c1fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c048, 0 },
|
||||
@ -62942,6 +62977,8 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c278, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c2d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c2d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c3b4, 0 },
|
||||
@ -62956,10 +62993,13 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c3fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c248, 0 },
|
||||
@ -63369,6 +63409,8 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c478, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c4d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c4d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c5b4, 0 },
|
||||
@ -63383,10 +63425,13 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c5fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c448, 0 },
|
||||
@ -63796,6 +63841,8 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c678, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c6d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c6d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c7b4, 0 },
|
||||
@ -63810,10 +63857,13 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c7fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c648, 0 },
|
||||
@ -64223,6 +64273,8 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MEMINTD22_POS", 2, 2 },
|
||||
{ "MEMINTD23_POS", 0, 2 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c878, 0 },
|
||||
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
||||
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c8d4, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c8d8, 0 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c9b4, 0 },
|
||||
@ -64237,10 +64289,13 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c9fc, 0 },
|
||||
{ "MASTER_PD_CNTL", 15, 1 },
|
||||
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
||||
{ "EYEDAC_PD", 13, 1 },
|
||||
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
||||
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
||||
{ "SYSCLK_CLK_GATE", 6, 2 },
|
||||
{ "WR_FIFO_STAB", 5, 1 },
|
||||
{ "ADR_RX_PD", 4, 1 },
|
||||
{ "DP18_RX_PD", 2, 2 },
|
||||
{ "TX_TRISTATE_CNTL", 1, 1 },
|
||||
{ "DVCC_REG_PD", 0, 1 },
|
||||
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c848, 0 },
|
||||
@ -64322,6 +64377,7 @@ struct reg_info t5_mc_1_regs[] = {
|
||||
{ "MC_DDRPHY_WC_CONFIG2", 0x4f608, 0 },
|
||||
{ "NUM_VALID_SAMPLES", 12, 4 },
|
||||
{ "FW_RD_WR", 6, 6 },
|
||||
{ "EN_RESET_WR_DELAY_WL", 0, 1 },
|
||||
{ "MC_DDRPHY_WC_CONFIG3", 0x4f614, 0 },
|
||||
{ "DDR4_MRS_CMD_DQ_EN", 15, 1 },
|
||||
{ "MRS_CMD_DQ_ON", 9, 6 },
|
||||
@ -64906,6 +64962,9 @@ struct reg_info t5_edc_t50_regs[] = {
|
||||
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
||||
{ "PERR_INT_ENABLE", 0, 1 },
|
||||
{ "EDC_H_INT_CAUSE", 0x50078, 0 },
|
||||
{ "ECC_UE_INT0_CAUSE", 5, 1 },
|
||||
{ "ECC_CE_INT0_CAUSE", 4, 1 },
|
||||
{ "PERR_INT0_CAUSE", 3, 1 },
|
||||
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
||||
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
||||
{ "PERR_INT_CAUSE", 0, 1 },
|
||||
@ -64985,6 +65044,9 @@ struct reg_info t5_edc_t51_regs[] = {
|
||||
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
||||
{ "PERR_INT_ENABLE", 0, 1 },
|
||||
{ "EDC_H_INT_CAUSE", 0x50878, 0 },
|
||||
{ "ECC_UE_INT0_CAUSE", 5, 1 },
|
||||
{ "ECC_CE_INT0_CAUSE", 4, 1 },
|
||||
{ "PERR_INT0_CAUSE", 3, 1 },
|
||||
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
||||
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
||||
{ "PERR_INT_CAUSE", 0, 1 },
|
||||
|
||||
57337
tools/tools/cxgbetool/reg_defs_t6.c
Normal file
57337
tools/tools/cxgbetool/reg_defs_t6.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user