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Merge ^/head r327169 through r327340.

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This commit is contained in:
Dimitry Andric 2017-12-29 12:51:26 +00:00
commit 4fc74049d2
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/clang600-import/; revision=327341
285 changed files with 3908 additions and 3280 deletions
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5
.gitattributes vendored Normal file
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@ -0,0 +1,5 @@
*.c diff=cpp
*.h diff=cpp
*.cpp diff=cpp
*.hpp diff=cpp
*.py diff=python

18
.gitignore vendored Normal file
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@ -0,0 +1,18 @@
_.tinderbox.*
_.amd64.*
_.arm.*
_.arm64.*
_.i386.*
_.ia64.*
_.mips.*
_.pc98.*
_.powerpc.*
_.riscv.*
_.sparc64.*
_.sun4v.*
GPATH
GRTAGS
GTAGS
ID
cscope.out
?cscope.out

4
UPDATING
View File

@ -821,7 +821,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 12.x IS SLOW:
20150623:
An additional fix for the issue described in the 20150614 sendmail
entry below has been been committed in revision 284717.
entry below has been committed in revision 284717.
20150616:
FreeBSD's old make (fmake) has been removed from the system. It is
@ -829,7 +829,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 12.x IS SLOW:
20150615:
The fix for the issue described in the 20150614 sendmail entry
below has been been committed in revision 284436. The work
below has been committed in revision 284436. The work
around described in that entry is no longer needed unless the
default setting is overridden by a confDH_PARAMETERS configuration
setting of '5' or pointing to a 512 bit DH parameter file.

2
bin/pax/buf_subs.c
View File

@ -485,7 +485,7 @@ wr_rdbuf(char *out, int outcnt)
int cnt;
/*
* while there is data to copy copy into the write buffer. when the
* while there is data to copy into the write buffer. when the
* write buffer fills, flush it to the archive and continue
*/
while (outcnt > 0) {

7
bin/sh/eval.c
View File

@ -43,7 +43,6 @@ __FBSDID("$FreeBSD$");
#include <stdlib.h>
#include <unistd.h>
#include <sys/resource.h>
#include <sys/wait.h> /* For WIFSIGNALED(status) */
#include <errno.h>
/*
@ -840,7 +839,7 @@ evalcommand(union node *cmd, int flags, struct backcmd *backcmd)
struct parsefile *savetopfile;
volatile int e;
char *lastarg;
int realstatus;
int signaled;
int do_clearcmdentry;
const char *path = pathval();
int i;
@ -1163,9 +1162,9 @@ evalcommand(union node *cmd, int flags, struct backcmd *backcmd)
parent: /* parent process gets here (if we forked) */
if (mode == FORK_FG) { /* argument to fork */
INTOFF;
exitstatus = waitforjob(jp, &realstatus);
exitstatus = waitforjob(jp, &signaled);
INTON;
if (iflag && loopnest > 0 && WIFSIGNALED(realstatus)) {
if (iflag && loopnest > 0 && signaled) {
evalskip = SKIPBREAK;
skipcount = loopnest;
}

6
bin/sh/jobs.c
View File

@ -1016,7 +1016,7 @@ vforkexecshell(struct job *jp, char **argv, char **envp, const char *path, int i
*/
int
waitforjob(struct job *jp, int *origstatus)
waitforjob(struct job *jp, int *signaled)
{
#if JOBS
int propagate_int = jp->jobctl && jp->foreground;
@ -1039,8 +1039,8 @@ waitforjob(struct job *jp, int *origstatus)
setcurjob(jp);
#endif
status = jp->ps[jp->nprocs - 1].status;
if (origstatus != NULL)
*origstatus = status;
if (signaled != NULL)
*signaled = WIFSIGNALED(status);
/* convert to 8 bits */
if (WIFEXITED(status))
st = WEXITSTATUS(status);

2
bin/sh/tests/builtins/var-assign.0
View File

@ -47,7 +47,7 @@ do
${SH} -c "VAR=1; VAR=0 ${cmd}; exit \${VAR}" >/dev/null 2>&1
done
# For other built-ins and utilites they do not.
# For other built-ins and utilities they do not.
set -- ${UTILS}
for cmd in "$@"
do

1
contrib/elftoolchain/readelf/readelf.c
View File

@ -2753,6 +2753,7 @@ dump_dyn_val(struct readelf *re, GElf_Dyn *dyn, uint32_t stab)
case DT_SYMENT:
case DT_RELSZ:
case DT_RELENT:
case DT_PREINIT_ARRAYSZ:
case DT_INIT_ARRAYSZ:
case DT_FINI_ARRAYSZ:
case DT_GNU_CONFLICTSZ:

24
etc/devd/hyperv.conf
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@ -39,39 +39,39 @@ notify 11 {
#
# How network VF works with hn(4) on Hyper-V in non-transparent mode:
#
# - Each network VF has a cooresponding hn(4).
# - The network VF and the it's cooresponding hn(4) have the same hardware
# - Each network VF has a corresponding hn(4).
# - The network VF and the it's corresponding hn(4) have the same hardware
# address.
# - Once the network VF is up, e.g. ifconfig VF up:
# o All of the transmission should go through the network VF.
# o Most of the reception goes through the network VF.
# o Small amount of reception may go through the cooresponding hn(4).
# This reception will happen, even if the the cooresponding hn(4) is
# down. The cooresponding hn(4) will change the reception interface
# o Small amount of reception may go through the corresponding hn(4).
# This reception will happen, even if the corresponding hn(4) is
# down. The corresponding hn(4) will change the reception interface
# to the network VF, so that network layer and application layer will
# be tricked into thinking that these packets were received by the
# network VF.
# o The cooresponding hn(4) pretends the physical link is down.
# o The corresponding hn(4) pretends the physical link is down.
# - Once the network VF is down or detached:
# o All of the transmission should go through the cooresponding hn(4).
# o All of the reception goes through the cooresponding hn(4).
# o The cooresponding hn(4) fallbacks to the original physical link
# o All of the transmission should go through the corresponding hn(4).
# o All of the reception goes through the corresponding hn(4).
# o The corresponding hn(4) fallbacks to the original physical link
# detection logic.
#
# All these features are mainly used to help live migration, during which
# the network VF will be detached, while the network communication to the
# VM must not be cut off. In order to reach this level of live migration
# transparency, we use failover mode lagg(4) with the network VF and the
# cooresponding hn(4) attached to it.
# corresponding hn(4) attached to it.
#
# To ease user configuration for both network VF and non-network VF, the
# lagg(4) will be created by the following rules, and the configuration
# of the cooresponding hn(4) will be applied to the lagg(4) automatically.
# of the corresponding hn(4) will be applied to the lagg(4) automatically.
#
# NOTE:
# If live migration is not needed at all, the following rules could be
# commented out, and the network VF interface could be used exclusively.
# Most often the cooresponding hn(4) could be completely ignored.
# Most often the corresponding hn(4) could be completely ignored.
#
#
# Default workflow for the network VF bringup:

1
etc/mail/mailer.conf
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@ -3,7 +3,6 @@
# Execute the "real" sendmail program, named /usr/libexec/sendmail/sendmail
#
sendmail /usr/libexec/sendmail/sendmail
send-mail /usr/libexec/sendmail/sendmail
mailq /usr/libexec/sendmail/sendmail
newaliases /usr/libexec/sendmail/sendmail
hoststat /usr/libexec/sendmail/sendmail

1
etc/portsnap.conf
View File

@ -30,7 +30,6 @@ KEYPRINT=9b5feee6d69f170e3dd0a2c8e469ddbd64f13f978f2f3aede40c98633216c330
# REFUSE korean polish portuguese russian ukrainian vietnamese
# List of INDEX files to build and the DESCRIBE file to use for each
#INDEX INDEX-9 DESCRIBE.9
#INDEX INDEX-10 DESCRIBE.10
#INDEX INDEX-11 DESCRIBE.11
INDEX INDEX-12 DESCRIBE.12

2
etc/rc.initdiskless
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@ -67,7 +67,7 @@
# /conf/T/M/remount
# The contents of the file is a mount command. E.g. if
# /conf/1.2.3.4/foo/remount contains "mount -o ro /dev/ad0s3",
# then /dev/ad0s3 will be be mounted on /conf/1.2.3.4/foo/
# then /dev/ad0s3 will be mounted on /conf/1.2.3.4/foo/
#
# /conf/T/M/remount_optional
# If this file exists, then failure to execute the mount

2
etc/rc.subr
View File

@ -1542,7 +1542,7 @@ debug()
# is created.
#
# update `file' has changed and needs to be backed up.
# If `cur' exists, it is copied to to `back'
# If `cur' exists, it is copied to `back'
# and then `file' is copied to `cur'.
#
# remove `file' is no longer being tracked by the backups

2
lib/libc/include/reentrant.h
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@ -67,7 +67,7 @@
* Implementation Details:
*
* The mutex primitives used by the library (mutex_t, mutex_lock, etc.)
* are macros which expand to the cooresponding primitives provided by
* are macros which expand to the corresponding primitives provided by
* the thread engine or to nothing. The latter is used so that code is
* not unreasonably cluttered with #ifdefs when all thread safe support
* is removed.

2
lib/libc/locale/euc.c
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@ -1,5 +1,5 @@
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright 2013 Garrett D'Amore <garrett@damore.org>
* Copyright 2011 Nexenta Systems, Inc. All rights reserved.

2
lib/libc/mips/SYS.h
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@ -2,7 +2,7 @@
/* $FreeBSD$ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: (BSD-4-Clause AND BSD-3-Clause)
*
* Copyright (c) 1996 Jonathan Stone
* All rights reserved.

2
lib/libc/sparc64/fpu/fpu_reg.h
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@ -31,7 +31,7 @@
#define _LIBC_SPARC64_FPU_FPU_REG_H_
/*
* These are not really of type char[]. They are are arrays of functions defined
* These are not really of type char[]. They are arrays of functions defined
* in fpu_reg.S; each array member loads/stores a certain fpu register of the
* given size.
*/

13
lib/libc/stdio/fflush.3
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@ -32,7 +32,7 @@
.\" @(#)fflush.3 8.1 (Berkeley) 6/4/93
.\" $FreeBSD$
.\"
.Dd June 4, 1993
.Dd December 25, 2017
.Dt FFLUSH 3
.Os
.Sh NAME
@ -87,9 +87,7 @@ is set to indicate the error.
The
.Fa stream
argument
is not an open stream, or, in the case of
.Fn fflush ,
not a stream open for writing.
is not an open stream.
.El
.Pp
The function
@ -97,7 +95,12 @@ The function
may also fail and set
.Va errno
for any of the errors specified for the routine
.Xr write 2 .
.Xr write 2 ,
except that in case of
.Fa stream
being a read-only descriptor,
.Fn fflush
returns 0.
.Sh SEE ALSO
.Xr write 2 ,
.Xr fclose 3 ,

2
lib/libc/sys/kqueue.2
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@ -190,7 +190,7 @@ The
.Fa ext[2]
and
.Fa ext[3]
members are always passed throught the kernel as-is,
members are always passed through the kernel as-is,
making additional context available to application.
.El
.Pp

2
lib/libc/sys/sendfile.2
View File

@ -190,7 +190,7 @@ may read ahead when reading the file.
A macro
.Fn SF_FLAGS
is provided to combine readahead amount and flags.
Example shows specifing readahead of 16 pages and
An example showing specifying readahead of 16 pages and
.Dv SF_NOCACHE
flag:
.Pp

2
lib/libcam/camlib.h
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@ -1,5 +1,5 @@
/*-
* SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD
* SPDX-License-Identifier: (BSD-2-Clause-FreeBSD AND BSD-4-Clause)
*
* Copyright (c) 1997, 1998 Kenneth D. Merry.
* All rights reserved.

2
lib/libedit/map.c
View File

@ -370,7 +370,7 @@ private const el_action_t el_map_vi_insert[] = {
* NOTE: These mappings do NOT Correspond well
* to the KSH VI editing assignments.
* On the other and they are convenient and
* many people have have gotten used to them.
* many people have gotten used to them.
*/
/* 0 */ ED_UNASSIGNED, /* ^@ */
/* 1 */ ED_MOVE_TO_BEG, /* ^A */

2
lib/libedit/refresh.c
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@ -1148,7 +1148,7 @@ re_fastaddc(EditLine *el)
/* re_clear_display():
* clear the screen buffers so that new new prompt starts fresh.
* clear the screen buffers so that new prompt starts fresh.
*/
protected void
re_clear_display(EditLine *el)

2
lib/libefivar/uefi-dputil.c
View File

@ -134,7 +134,7 @@ GetDevicePathSize (
@param MaxSize The maximum size of the device path data structure.
@retval TRUE DevicePath is valid.
@retval FALSE The length of any node node in the DevicePath is less
@retval FALSE The length of any node in the DevicePath is less
than sizeof (EFI_DEVICE_PATH_PROTOCOL).
@retval FALSE If MaxSize is not zero, the size of the DevicePath
exceeds MaxSize.

2
lib/libopenbsd/imsg_init.3
View File

@ -347,7 +347,7 @@ On success
returns a pointer to the buffer; on failure it returns NULL.
.Pp
.Fn ibuf_dynamic
allocates a resizeable buffer of initial length
allocates a resizable buffer of initial length
.Fa len
and maximum size
.Fa max .

1
lib/libufs/type.c
View File

@ -83,6 +83,7 @@ ufs_disk_fillout(struct uufsd *disk, const char *name)
}
if (sbread(disk) == -1) {
ERROR(disk, "could not read superblock to fill out disk");
ufs_disk_close(disk);
return (-1);
}
return (0);

6
lib/libutil/humanize_number.3
View File

@ -200,3 +200,9 @@ The
.Dv HN_IEC_PREFIXES
flag was introduced in
.Fx 9.0 .
.Sh CAVEATS
For numbers greater than 999 using buffer length of 4 and less can cause
rounding errors.
When using
.Dv HN_IEC_PREFIXES
the same error occurs for buffer length of 5 or less.

3
lib/libutil/humanize_number.c
View File

@ -145,7 +145,8 @@ humanize_number(char *buf, size_t len, int64_t quotient,
*/
for (i = 0;
(quotient >= max || (quotient == max - 1 &&
remainder >= divisordeccut)) && i < maxscale; i++) {
(remainder >= divisordeccut || remainder >=
divisor / 2))) && i < maxscale; i++) {
remainder = quotient % divisor;
quotient /= divisor;
}

3
lib/libutil/pty.c
View File

@ -101,12 +101,13 @@ forkpty(int *amaster, char *name, struct termios *termp, struct winsize *winp)
return (-1);
switch (pid = fork()) {
case -1:
(void)close(slave);
return (-1);
case 0:
/*
* child
*/
(void) close(master);
(void)close(master);
login_tty(slave);
return (0);
}

566
lib/libutil/tests/humanize_number_test.c
View File

@ -49,333 +49,337 @@ static struct {
int64_t num;
int flags;
int scale;
size_t buflen;
} test_args[] = {
/* tests 0-13 test 1000 suffixes */
{ 2, "0 ", (int64_t)0L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 k", (int64_t)500L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 M", (int64_t)500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 G", (int64_t)500*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 T", (int64_t)500*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 P", (int64_t)500*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 E", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 2, "1 ", (int64_t)1L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "2 k", (int64_t)1500L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "2 M", (int64_t)1500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "2 G", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "2 T", (int64_t)1500*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "2 P", (int64_t)1500*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "2 E", (int64_t)1500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 2, "0 ", (int64_t)0L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 k", (int64_t)500L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 M", (int64_t)500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 G", (int64_t)500*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 T", (int64_t)500*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 P", (int64_t)500*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 E", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 2, "1 ", (int64_t)1L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "2 k", (int64_t)1500L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "2 M", (int64_t)1500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "2 G", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "2 T", (int64_t)1500*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "2 P", (int64_t)1500*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "2 E", (int64_t)1500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
/* tests 14-27 test 1024 suffixes */
{ 2, "0 ", (int64_t)0L, 0, HN_AUTOSCALE },
{ 3, "1 K", (int64_t)512L, 0, HN_AUTOSCALE },
{ 3, "1 M", (int64_t)512*1024L, 0, HN_AUTOSCALE },
{ 3, "1 G", (int64_t)512*1024*1024L, 0, HN_AUTOSCALE },
{ 3, "1 T", (int64_t)512*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 3, "1 P", (int64_t)512*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 3, "1 E", (int64_t)512*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 2, "1 ", (int64_t)1L, 0, HN_AUTOSCALE },
{ 3, "2 K", (int64_t)1536L, 0, HN_AUTOSCALE },
{ 3, "2 M", (int64_t)1536*1024L, 0, HN_AUTOSCALE },
{ 3, "2 G", (int64_t)1536*1024*1024L, 0, HN_AUTOSCALE },
{ 3, "2 T", (int64_t)1536*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 3, "2 P", (int64_t)1536*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 3, "2 E", (int64_t)1536*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 2, "0 ", (int64_t)0L, 0, HN_AUTOSCALE, 4 },
{ 3, "1 K", (int64_t)512L, 0, HN_AUTOSCALE, 4 },
{ 3, "1 M", (int64_t)512*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "1 G", (int64_t)512*1024*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "1 T", (int64_t)512*1024*1024*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "1 P", (int64_t)512*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "1 E", (int64_t)512*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 4 },
{ 2, "1 ", (int64_t)1L, 0, HN_AUTOSCALE, 4 },
{ 3, "2 K", (int64_t)1536L, 0, HN_AUTOSCALE, 4 },
{ 3, "2 M", (int64_t)1536*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "2 G", (int64_t)1536*1024*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "2 T", (int64_t)1536*1024*1024*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "2 P", (int64_t)1536*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "2 E", (int64_t)1536*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 4 },
/* tests 28-37 test rounding */
{ 3, "0 M", (int64_t)500*1000L-1, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 M", (int64_t)500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "1 M", (int64_t)1000*1000L + 500*1000L-1, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "2 M", (int64_t)1000*1000L + 500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "0 K", (int64_t)512L-1, 0, HN_AUTOSCALE },
{ 3, "1 K", (int64_t)512L, 0, HN_AUTOSCALE },
{ 3, "0 M", (int64_t)512*1024L-1, 0, HN_AUTOSCALE },
{ 3, "1 M", (int64_t)512*1024L, 0, HN_AUTOSCALE },
{ 3, "1 M", (int64_t)1024*1024L + 512*1024L-1, 0, HN_AUTOSCALE },
{ 3, "2 M", (int64_t)1024*1024L + 512*1024L, 0, HN_AUTOSCALE },
{ 3, "0 M", (int64_t)500*1000L-1, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 M", (int64_t)500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "1 M", (int64_t)1000*1000L + 500*1000L-1, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "2 M", (int64_t)1000*1000L + 500*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 4 },
{ 3, "0 K", (int64_t)512L-1, 0, HN_AUTOSCALE, 4 },
{ 3, "1 K", (int64_t)512L, 0, HN_AUTOSCALE, 4 },
{ 3, "0 M", (int64_t)512*1024L-1, 0, HN_AUTOSCALE, 4 },
{ 3, "1 M", (int64_t)512*1024L, 0, HN_AUTOSCALE, 4 },
{ 3, "1 M", (int64_t)1024*1024L + 512*1024L-1, 0, HN_AUTOSCALE, 4 },
{ 3, "2 M", (int64_t)1024*1024L + 512*1024L, 0, HN_AUTOSCALE, 4 },
/* tests 38-61 test specific scale factors with 1000 divisor */
{ 3, "0 k", (int64_t)0L, HN_DIVISOR_1000, 1 },
{ 3, "1 k", (int64_t)500L, HN_DIVISOR_1000, 1 },
{ 3, "0 M", (int64_t)500L, HN_DIVISOR_1000, 2 },
{ 3, "1 M", (int64_t)500*1000L, HN_DIVISOR_1000, 2 },
{ 3, "0 G", (int64_t)500*1000L, HN_DIVISOR_1000, 3 },
{ 3, "1 G", (int64_t)500*1000*1000L, HN_DIVISOR_1000, 3 },
{ 3, "0 T", (int64_t)500*1000*1000L, HN_DIVISOR_1000, 4 },
{ 3, "1 T", (int64_t)500*1000*1000*1000L, HN_DIVISOR_1000, 4 },
{ 3, "0 P", (int64_t)500*1000*1000*1000L, HN_DIVISOR_1000, 5 },
{ 3, "1 P", (int64_t)500*1000*1000*1000*1000L, HN_DIVISOR_1000, 5 },
{ 3, "0 E", (int64_t)500*1000*1000*1000*1000L, HN_DIVISOR_1000, 6 },
{ 3, "1 E", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6 },
{ 3, "0 k", (int64_t)1L, HN_DIVISOR_1000, 1 },
{ 3, "2 k", (int64_t)1500L, HN_DIVISOR_1000, 1 },
{ 3, "0 M", (int64_t)1500L, HN_DIVISOR_1000, 2 },
{ 3, "2 M", (int64_t)1500*1000L, HN_DIVISOR_1000, 2 },
{ 3, "0 G", (int64_t)1500*1000L, HN_DIVISOR_1000, 3 },
{ 3, "2 G", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, 3 },
{ 3, "0 T", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, 4 },
{ 3, "2 T", (int64_t)1500*1000*1000*1000L, HN_DIVISOR_1000, 4 },
{ 3, "0 P", (int64_t)1500*1000*1000*1000L, HN_DIVISOR_1000, 5 },
{ 3, "2 P", (int64_t)1500*1000*1000*1000*1000L, HN_DIVISOR_1000, 5 },
{ 3, "0 E", (int64_t)1500*1000*1000*1000*1000L, HN_DIVISOR_1000, 6 },
{ 3, "2 E", (int64_t)1500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6 },
{ 3, "0 k", (int64_t)0L, HN_DIVISOR_1000, 1, 4 },
{ 3, "1 k", (int64_t)500L, HN_DIVISOR_1000, 1, 4 },
{ 3, "0 M", (int64_t)500L, HN_DIVISOR_1000, 2, 4 },
{ 3, "1 M", (int64_t)500*1000L, HN_DIVISOR_1000, 2, 4 },
{ 3, "0 G", (int64_t)500*1000L, HN_DIVISOR_1000, 3, 4 },
{ 3, "1 G", (int64_t)500*1000*1000L, HN_DIVISOR_1000, 3, 4 },
{ 3, "0 T", (int64_t)500*1000*1000L, HN_DIVISOR_1000, 4, 4 },
{ 3, "1 T", (int64_t)500*1000*1000*1000L, HN_DIVISOR_1000, 4, 4 },
{ 3, "0 P", (int64_t)500*1000*1000*1000L, HN_DIVISOR_1000, 5, 4 },
{ 3, "1 P", (int64_t)500*1000*1000*1000*1000L, HN_DIVISOR_1000, 5, 4 },
{ 3, "0 E", (int64_t)500*1000*1000*1000*1000L, HN_DIVISOR_1000, 6, 4 },
{ 3, "1 E", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6, 4 },
{ 3, "0 k", (int64_t)1L, HN_DIVISOR_1000, 1, 4 },
{ 3, "2 k", (int64_t)1500L, HN_DIVISOR_1000, 1, 4 },
{ 3, "0 M", (int64_t)1500L, HN_DIVISOR_1000, 2, 4 },
{ 3, "2 M", (int64_t)1500*1000L, HN_DIVISOR_1000, 2, 4 },
{ 3, "0 G", (int64_t)1500*1000L, HN_DIVISOR_1000, 3, 4 },
{ 3, "2 G", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, 3, 4 },
{ 3, "0 T", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, 4, 4 },
{ 3, "2 T", (int64_t)1500*1000*1000*1000L, HN_DIVISOR_1000, 4, 4 },
{ 3, "0 P", (int64_t)1500*1000*1000*1000L, HN_DIVISOR_1000, 5, 4 },
{ 3, "2 P", (int64_t)1500*1000*1000*1000*1000L, HN_DIVISOR_1000, 5, 4 },
{ 3, "0 E", (int64_t)1500*1000*1000*1000*1000L, HN_DIVISOR_1000, 6, 4 },
{ 3, "2 E", (int64_t)1500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6, 4 },
/* tests 62-85 test specific scale factors with 1024 divisor */
{ 3, "0 K", (int64_t)0L, 0, 1 },
{ 3, "1 K", (int64_t)512L, 0, 1 },
{ 3, "0 M", (int64_t)512L, 0, 2 },
{ 3, "1 M", (int64_t)512*1024L, 0, 2 },
{ 3, "0 G", (int64_t)512*1024L, 0, 3 },
{ 3, "1 G", (int64_t)512*1024*1024L, 0, 3 },
{ 3, "0 T", (int64_t)512*1024*1024L, 0, 4 },
{ 3, "1 T", (int64_t)512*1024*1024*1024L, 0, 4 },
{ 3, "0 P", (int64_t)512*1024*1024*1024L, 0, 5 },
{ 3, "1 P", (int64_t)512*1024*1024*1024*1024L, 0, 5 },
{ 3, "0 E", (int64_t)512*1024*1024*1024*1024L, 0, 6 },
{ 3, "1 E", (int64_t)512*1024*1024*1024*1024*1024L, 0, 6 },
{ 3, "0 K", (int64_t)1L, 0, 1 },
{ 3, "2 K", (int64_t)1536L, 0, 1 },
{ 3, "0 M", (int64_t)1536L, 0, 2 },
{ 3, "2 M", (int64_t)1536*1024L, 0, 2 },
{ 3, "0 G", (int64_t)1536*1024L, 0, 3 },
{ 3, "2 G", (int64_t)1536*1024*1024L, 0, 3 },
{ 3, "0 T", (int64_t)1536*1024*1024L, 0, 4 },
{ 3, "2 T", (int64_t)1536*1024*1024*1024L, 0, 4 },
{ 3, "0 P", (int64_t)1536*1024*1024*1024L, 0, 5 },
{ 3, "2 P", (int64_t)1536*1024*1024*1024*1024L, 0, 5 },
{ 3, "0 E", (int64_t)1536*1024*1024*1024*1024L, 0, 6 },
{ 3, "2 E", (int64_t)1536*1024*1024*1024*1024*1024L, 0, 6 },
{ 3, "0 K", (int64_t)0L, 0, 1, 4 },
{ 3, "1 K", (int64_t)512L, 0, 1, 4 },
{ 3, "0 M", (int64_t)512L, 0, 2, 4 },
{ 3, "1 M", (int64_t)512*1024L, 0, 2, 4 },
{ 3, "0 G", (int64_t)512*1024L, 0, 3, 4 },
{ 3, "1 G", (int64_t)512*1024*1024L, 0, 3, 4 },
{ 3, "0 T", (int64_t)512*1024*1024L, 0, 4, 4 },
{ 3, "1 T", (int64_t)512*1024*1024*1024L, 0, 4, 4 },
{ 3, "0 P", (int64_t)512*1024*1024*1024L, 0, 5, 4 },
{ 3, "1 P", (int64_t)512*1024*1024*1024*1024L, 0, 5, 4 },
{ 3, "0 E", (int64_t)512*1024*1024*1024*1024L, 0, 6, 4 },
{ 3, "1 E", (int64_t)512*1024*1024*1024*1024*1024L, 0, 6, 4 },
{ 3, "0 K", (int64_t)1L, 0, 1, 4 },
{ 3, "2 K", (int64_t)1536L, 0, 1, 4 },
{ 3, "0 M", (int64_t)1536L, 0, 2, 4 },
{ 3, "2 M", (int64_t)1536*1024L, 0, 2, 4 },
{ 3, "0 G", (int64_t)1536*1024L, 0, 3, 4 },
{ 3, "2 G", (int64_t)1536*1024*1024L, 0, 3, 4 },
{ 3, "0 T", (int64_t)1536*1024*1024L, 0, 4, 4 },
{ 3, "2 T", (int64_t)1536*1024*1024*1024L, 0, 4, 4 },
{ 3, "0 P", (int64_t)1536*1024*1024*1024L, 0, 5, 4 },
{ 3, "2 P", (int64_t)1536*1024*1024*1024*1024L, 0, 5, 4 },
{ 3, "0 E", (int64_t)1536*1024*1024*1024*1024L, 0, 6, 4 },
{ 3, "2 E", (int64_t)1536*1024*1024*1024*1024*1024L, 0, 6, 4 },
/* tests 86-99 test invalid specific scale values of < 0 or >= 7 with
and without HN_DIVISOR_1000 set */
/* all should return errors with new code; with old, the latter 3
are instead processed as if having AUTOSCALE and/or GETSCALE set */
{ -1, "", (int64_t)1L, 0, 7 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, 7 },
{ -1, "", (int64_t)1L, 0, 1000 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, 1000 },
{ -1, "", (int64_t)0L, 0, 1000*1000 },
{ -1, "", (int64_t)0L, HN_DIVISOR_1000, 1000*1000 },
{ -1, "", (int64_t)0L, 0, INT_MAX },
{ -1, "", (int64_t)0L, HN_DIVISOR_1000, INT_MAX },
{ -1, "", (int64_t)1L, 0, 7, 4 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, 7, 4 },
{ -1, "", (int64_t)1L, 0, 1000, 4 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, 1000, 4 },
{ -1, "", (int64_t)0L, 0, 1000*1000, 4 },
{ -1, "", (int64_t)0L, HN_DIVISOR_1000, 1000*1000, 4 },
{ -1, "", (int64_t)0L, 0, INT_MAX, 4 },
{ -1, "", (int64_t)0L, HN_DIVISOR_1000, INT_MAX, 4 },
/* Negative scale values are not handled well
by the existing library routine - should report as error */
/* all should return errors with new code, fail assertion with old */
{ -1, "", (int64_t)1L, 0, -1 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, -1 },
{ -1, "", (int64_t)1L, 0, -1000 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, -1000 },
{ -1, "", (int64_t)1L, 0, -1, 4 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, -1, 4 },
{ -1, "", (int64_t)1L, 0, -1000, 4 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, -1000, 4 },
/* __INT_MIN doesn't print properly, skipped. */
{ -1, "", (int64_t)1L, 0, -__INT_MAX },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, -__INT_MAX },
{ -1, "", (int64_t)1L, 0, -__INT_MAX, 4 },
{ -1, "", (int64_t)1L, HN_DIVISOR_1000, -__INT_MAX, 4 },
/* tests for scale == 0, without autoscale */
/* tests 100-114 test scale 0 with 1000 divisor - print first N digits */
{ 2, "0 ", (int64_t)0L, HN_DIVISOR_1000, 0 },
{ 2, "1 ", (int64_t)1L, HN_DIVISOR_1000, 0 },
{ 3, "10 ", (int64_t)10L, HN_DIVISOR_1000, 0 },
{ 3, "0 M", (int64_t)150L, HN_DIVISOR_1000, HN_NOSPACE },
{ 3, "0 M", (int64_t)500L, HN_DIVISOR_1000, HN_NOSPACE },
{ 3, "0 M", (int64_t)999L, HN_DIVISOR_1000, HN_NOSPACE },
{ 4, "150", (int64_t)150L, HN_DIVISOR_1000, 0 },
{ 4, "500", (int64_t)500L, HN_DIVISOR_1000, 0 },
{ 4, "999", (int64_t)999L, HN_DIVISOR_1000, 0 },
{ 5, "100", (int64_t)1000L, HN_DIVISOR_1000, 0 },
{ 5, "150", (int64_t)1500L, HN_DIVISOR_1000, 0 },
{ 7, "500", (int64_t)500*1000L, HN_DIVISOR_1000, 0 },
{ 8, "150", (int64_t)1500*1000L, HN_DIVISOR_1000, 0 },
{ 10, "500", (int64_t)500*1000*1000L, HN_DIVISOR_1000, 0 },
{ 11, "150", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, 0 },
{ 2, "0 ", (int64_t)0L, HN_DIVISOR_1000, 0, 4 },
{ 2, "1 ", (int64_t)1L, HN_DIVISOR_1000, 0, 4 },
{ 3, "10 ", (int64_t)10L, HN_DIVISOR_1000, 0, 4 },
{ 3, "0 M", (int64_t)150L, HN_DIVISOR_1000, HN_NOSPACE, 4 },
{ 3, "0 M", (int64_t)500L, HN_DIVISOR_1000, HN_NOSPACE, 4 },
{ 3, "0 M", (int64_t)999L, HN_DIVISOR_1000, HN_NOSPACE, 4 },
{ 4, "150", (int64_t)150L, HN_DIVISOR_1000, 0, 4 },
{ 4, "500", (int64_t)500L, HN_DIVISOR_1000, 0, 4 },
{ 4, "999", (int64_t)999L, HN_DIVISOR_1000, 0, 4 },
{ 5, "100", (int64_t)1000L, HN_DIVISOR_1000, 0, 4 },
{ 5, "150", (int64_t)1500L, HN_DIVISOR_1000, 0, 4 },
{ 7, "500", (int64_t)500*1000L, HN_DIVISOR_1000, 0, 4 },
{ 8, "150", (int64_t)1500*1000L, HN_DIVISOR_1000, 0, 4 },
{ 10, "500", (int64_t)500*1000*1000L, HN_DIVISOR_1000, 0, 4 },
{ 11, "150", (int64_t)1500*1000*1000L, HN_DIVISOR_1000, 0, 4 },
/* tests 115-126 test scale 0 with 1024 divisor - print first N digits */
{ 2, "0 ", (int64_t)0L, 0, 0 },
{ 2, "1 ", (int64_t)1L, 0, 0 },
{ 3, "10 ", (int64_t)10L, 0, 0 },
{ 4, "150", (int64_t)150L, 0, 0 },
{ 4, "500", (int64_t)500L, 0, 0 },
{ 4, "999", (int64_t)999L, 0, 0 },
{ 5, "100", (int64_t)1000L, 0, 0 },
{ 5, "150", (int64_t)1500L, 0, 0 },
{ 7, "500", (int64_t)500*1000L, 0, 0 },
{ 8, "150", (int64_t)1500*1000L, 0, 0 },
{ 10, "500", (int64_t)500*1000*1000L, 0, 0 },
{ 11, "150", (int64_t)1500*1000*1000L, 0, 0 },
{ 2, "0 ", (int64_t)0L, 0, 0, 4 },
{ 2, "1 ", (int64_t)1L, 0, 0, 4 },
{ 3, "10 ", (int64_t)10L, 0, 0, 4 },
{ 4, "150", (int64_t)150L, 0, 0, 4 },
{ 4, "500", (int64_t)500L, 0, 0, 4 },
{ 4, "999", (int64_t)999L, 0, 0, 4 },
{ 5, "100", (int64_t)1000L, 0, 0, 4 },
{ 5, "150", (int64_t)1500L, 0, 0, 4 },
{ 7, "500", (int64_t)500*1000L, 0, 0, 4 },
{ 8, "150", (int64_t)1500*1000L, 0, 0, 4 },
{ 10, "500", (int64_t)500*1000*1000L, 0, 0, 4 },
{ 11, "150", (int64_t)1500*1000*1000L, 0, 0, 4 },
/* Test case for rounding of edge numbers around 999.5+, see PR224498.
* Require buflen >= 5 */
{ 4, "1.0M", (int64_t)1023500, HN_DECIMAL|HN_B|HN_NOSPACE, HN_AUTOSCALE, 5 },
/* Test boundary cases for very large positive/negative number formatting */
/* Explicit scale, divisor 1024 */
/* XXX = requires length 5 (buflen 6) for some cases*/
/* KLUDGE - test loop below will bump length 5 up to 5 */
{ 3, "8 E", INT64_MAX, 0, 6 },
{ 4, "-8 E", -INT64_MAX, 0, 6 },
{ 3, "0 E", (int64_t)92*1024*1024*1024*1024*1024L, 0, 6 },
{ 3, "0 E", -(int64_t)92*1024*1024*1024*1024*1024L, 0, 6 },
{ 3, "0 E", (int64_t)82*1024*1024*1024*1024*1024L, 0, 6 },
{ 3, "0 E", -(int64_t)82*1024*1024*1024*1024*1024L, 0, 6 },
{ 3, "0 E", (int64_t)81*1024*1024*1024*1024*1024L, 0, 6 },
{ 3, "0 E", -(int64_t)81*1024*1024*1024*1024*1024L, 0, 6 },
{ 4, "92 P", (int64_t)92*1024*1024*1024*1024*1024L, 0, 5 },
{ 5, "-92 P", -(int64_t)92*1024*1024*1024*1024*1024L, 0, 5 },
{ 4, "82 P", (int64_t)82*1024*1024*1024*1024*1024L, 0, 5 },
{ 5, "-82 P", -(int64_t)82*1024*1024*1024*1024*1024L, 0, 5 },
{ 4, "81 P", (int64_t)81*1024*1024*1024*1024*1024L, 0, 5 },
{ 5, "-81 P", -(int64_t)81*1024*1024*1024*1024*1024L, 0, 5 },
/* Requires buflen >= 6 */
{ 3, "8 E", INT64_MAX, 0, 6, 6 },
{ 4, "-8 E", -INT64_MAX, 0, 6, 6 },
{ 3, "0 E", (int64_t)92*1024*1024*1024*1024*1024L, 0, 6, 6 },
{ 3, "0 E", -(int64_t)92*1024*1024*1024*1024*1024L, 0, 6, 6 },
{ 3, "0 E", (int64_t)82*1024*1024*1024*1024*1024L, 0, 6, 6 },
{ 3, "0 E", -(int64_t)82*1024*1024*1024*1024*1024L, 0, 6, 6 },
{ 3, "0 E", (int64_t)81*1024*1024*1024*1024*1024L, 0, 6, 6 },
{ 3, "0 E", -(int64_t)81*1024*1024*1024*1024*1024L, 0, 6, 6 },
{ 4, "92 P", (int64_t)92*1024*1024*1024*1024*1024L, 0, 5, 6 },
{ 5, "-92 P", -(int64_t)92*1024*1024*1024*1024*1024L, 0, 5, 6 },
{ 4, "82 P", (int64_t)82*1024*1024*1024*1024*1024L, 0, 5, 6 },
{ 5, "-82 P", -(int64_t)82*1024*1024*1024*1024*1024L, 0, 5, 6 },
{ 4, "81 P", (int64_t)81*1024*1024*1024*1024*1024L, 0, 5, 6 },
{ 5, "-81 P", -(int64_t)81*1024*1024*1024*1024*1024L, 0, 5, 6 },
/* Explicit scale, divisor 1000 */
{ 3, "9 E", INT64_MAX, HN_DIVISOR_1000, 6 },
{ 4, "-9 E", -INT64_MAX, HN_DIVISOR_1000, 6 },
{ 3, "0 E", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6 },
{ 3, "0 E", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6 },
{ 3, "0 E", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6 },
{ 3, "0 E", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6 },
{ 4, "92 P", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5 },
{ 5, "-92 P", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5 },
{ 4, "91 P", (int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5 },
{ 5, "-91 P", -(int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5 },
{ 3, "9 E", INT64_MAX, HN_DIVISOR_1000, 6, 6 },
{ 4, "-9 E", -INT64_MAX, HN_DIVISOR_1000, 6, 6 },
{ 3, "0 E", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6, 6 },
{ 3, "0 E", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6, 6 },
{ 3, "0 E", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6, 6 },
{ 3, "0 E", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 6, 6 },
{ 4, "92 P", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5, 6 },
{ 5, "-92 P", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5, 6 },
{ 4, "91 P", (int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5, 6 },
{ 5, "-91 P", -(int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 5, 6 },
/* Autoscale, divisor 1024 */
{ 3, "8 E", INT64_MAX, 0, HN_AUTOSCALE },
{ 4, "-8 E", -INT64_MAX, 0, HN_AUTOSCALE },
{ 4, "92 P", (int64_t)92*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 5, "-92 P", -(int64_t)92*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 4, "82 P", (int64_t)82*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 5, "-82 P", -(int64_t)82*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 4, "81 P", (int64_t)81*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 5, "-81 P", -(int64_t)81*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE },
{ 3, "8 E", INT64_MAX, 0, HN_AUTOSCALE, 6 },
{ 4, "-8 E", -INT64_MAX, 0, HN_AUTOSCALE, 6 },
{ 4, "92 P", (int64_t)92*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 6 },
{ 5, "-92 P", -(int64_t)92*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 6 },
{ 4, "82 P", (int64_t)82*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 6 },
{ 5, "-82 P", -(int64_t)82*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 6 },
{ 4, "81 P", (int64_t)81*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 6 },
{ 5, "-81 P", -(int64_t)81*1024*1024*1024*1024*1024L, 0, HN_AUTOSCALE, 6 },
/* Autoscale, divisor 1000 */
{ 3, "9 E", INT64_MAX, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 4, "-9 E", -INT64_MAX, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 4, "92 P", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "-92 P", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 4, "91 P", (int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "-91 P", -(int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 3, "9 E", INT64_MAX, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 4, "-9 E", -INT64_MAX, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 4, "92 P", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "-92 P", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 4, "91 P", (int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "-91 P", -(int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
/* 0 scale, divisor 1024 */
{ 12, "skdj", INT64_MAX, 0, 0 },
{ 21, "-9223", -INT64_MAX, 0, 0 },
{ 19, "10358", (int64_t)92*1024*1024*1024*1024*1024L, 0, 0 },
{ 20, "-1035", -(int64_t)92*1024*1024*1024*1024*1024L, 0, 0 },
{ 18, "92323", (int64_t)82*1024*1024*1024*1024*1024L, 0, 0 },
{ 19, "-9232", -(int64_t)82*1024*1024*1024*1024*1024L, 0, 0 },
{ 18, "91197", (int64_t)81*1024*1024*1024*1024*1024L, 0, 0 },
{ 19, "-9119", -(int64_t)81*1024*1024*1024*1024*1024L, 0, 0 },
{ 12, "skdj", INT64_MAX, 0, 0, 6 },
{ 21, "-9223", -INT64_MAX, 0, 0, 6 },
{ 19, "10358", (int64_t)92*1024*1024*1024*1024*1024L, 0, 0, 6 },
{ 20, "-1035", -(int64_t)92*1024*1024*1024*1024*1024L, 0, 0, 6 },
{ 18, "92323", (int64_t)82*1024*1024*1024*1024*1024L, 0, 0, 6 },
{ 19, "-9232", -(int64_t)82*1024*1024*1024*1024*1024L, 0, 0, 6 },
{ 18, "91197", (int64_t)81*1024*1024*1024*1024*1024L, 0, 0, 6 },
{ 19, "-9119", -(int64_t)81*1024*1024*1024*1024*1024L, 0, 0, 6 },
/* 0 scale, divisor 1000 */
/* XXX - why does this fail? */
{ -1, "", INT64_MAX, HN_DIVISOR_1000, 0 },
{ 21, "-9223", -INT64_MAX, HN_DIVISOR_1000, 0 },
{ 19, "10358", (int64_t)92*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0 },
{ 20, "-1035", -(int64_t)92*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0 },
{ 18, "92323", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0 },
{ 19, "-9232", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0 },
{ -1, "", INT64_MAX, HN_DIVISOR_1000, 0, 6 },
{ 21, "-9223", -INT64_MAX, HN_DIVISOR_1000, 0, 6 },
{ 19, "10358", (int64_t)92*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0, 6 },
{ 20, "-1035", -(int64_t)92*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0, 6 },
{ 18, "92323", (int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0, 6 },
{ 19, "-9232", -(int64_t)82*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0, 6 },
/* Expected to pass */
{ 18, "91197", (int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0 },
{ 19, "-9119", -(int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0 },
{ 18, "91197", (int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0, 6 },
{ 19, "-9119", -(int64_t)81*1024*1024*1024*1024*1024L, HN_DIVISOR_1000, 0, 6 },
/* Need to implement tests for GETSCALE */
/* { ?, "", (int64_t)0L, HN_DIVISOR_1000, HN_GETSCALE },
/* { ?, "", (int64_t)0L, HN_DIVISOR_1000, HN_GETSCALE, 6 },
...
*/
/* Tests for HN_DECIMAL */
/* Positive, Autoscale */
{ 5, "500 k", (int64_t)500*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "994 k", (int64_t)994*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "995 k", (int64_t)995*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "999 k", (int64_t)999*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "1.0 M", (int64_t)1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "1.5 M", (int64_t)1500*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "1.9 M", (int64_t)1949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "2.0 M", (int64_t)1950*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "9.9 M", (int64_t)9949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 4, "10 M", (int64_t)9950*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "500 M", (int64_t)500*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "994 M", (int64_t)994*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "995 M", (int64_t)995*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "999 M", (int64_t)999*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "500 k", (int64_t)500*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "994 k", (int64_t)994*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "995 k", (int64_t)995*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "999 k", (int64_t)999*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "1.0 M", (int64_t)1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "1.5 M", (int64_t)1500*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "1.9 M", (int64_t)1949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "2.0 M", (int64_t)1950*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "9.9 M", (int64_t)9949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 4, "10 M", (int64_t)9950*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "500 M", (int64_t)500*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "994 M", (int64_t)994*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "995 M", (int64_t)995*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "999 M", (int64_t)999*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "500 K", (int64_t)500*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "994 K", (int64_t)994*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "995 K", (int64_t)995*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "999 K", (int64_t)999*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "1.0 M", (int64_t)1000*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "1.0 M", (int64_t)1018*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "1.0 M", (int64_t)1019*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "1.5 M", (int64_t)1536*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "1.9 M", (int64_t)1996*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "2.0 M", (int64_t)1997*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "2.0 M", (int64_t)2047*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "2.0 M", (int64_t)2048*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "2.0 M", (int64_t)2099*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "2.1 M", (int64_t)2100*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "9.9 M", (int64_t)10188*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "500 K", (int64_t)500*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "994 K", (int64_t)994*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "995 K", (int64_t)995*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "999 K", (int64_t)999*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "1.0 M", (int64_t)1000*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "1.0 M", (int64_t)1018*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "1.0 M", (int64_t)1019*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "1.5 M", (int64_t)1536*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "1.9 M", (int64_t)1996*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "2.0 M", (int64_t)1997*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "2.0 M", (int64_t)2047*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "2.0 M", (int64_t)2048*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "2.0 M", (int64_t)2099*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "2.1 M", (int64_t)2100*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "9.9 M", (int64_t)10188*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
/* XXX - shouldn't the following two be "10. M"? */
{ 4, "10 M", (int64_t)10189*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 4, "10 M", (int64_t)10240*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "500 M", (int64_t)500*1024*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "994 M", (int64_t)994*1024*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "995 M", (int64_t)995*1024*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "999 M", (int64_t)999*1024*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "1.0 G", (int64_t)1000*1024*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "1.0 G", (int64_t)1023*1024*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 4, "10 M", (int64_t)10189*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 4, "10 M", (int64_t)10240*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "500 M", (int64_t)500*1024*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "994 M", (int64_t)994*1024*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "995 M", (int64_t)995*1024*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "999 M", (int64_t)999*1024*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "1.0 G", (int64_t)1000*1024*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "1.0 G", (int64_t)1023*1024*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
/* Negative, Autoscale - should pass */
{ 6, "-1.5 ", -(int64_t)1500*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 6, "-1.9 ", -(int64_t)1949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 6, "-9.9 ", -(int64_t)9949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 6, "-1.5 ", -(int64_t)1500*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 6, "-1.9 ", -(int64_t)1949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 6, "-9.9 ", -(int64_t)9949*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 6, "-1.5 ", -(int64_t)1536*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 6, "-1.9 ", -(int64_t)1949*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 6, "-9.7 ", -(int64_t)9949*1024L, HN_DECIMAL, HN_AUTOSCALE },
{ 6, "-1.5 ", -(int64_t)1536*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 6, "-1.9 ", -(int64_t)1949*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 6, "-9.7 ", -(int64_t)9949*1024L, HN_DECIMAL, HN_AUTOSCALE, 6 },
/* Positive/negative, at maximum scale */
{ 5, "500 P", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "1.9 E", (int64_t)1949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "8.9 E", (int64_t)8949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "9.2 E", INT64_MAX, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 5, "500 P", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "1.9 E", (int64_t)1949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "8.9 E", (int64_t)8949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "9.2 E", INT64_MAX, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
/* Negatives work with latest rev only: */
{ 6, "-9.2 ", -INT64_MAX, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 6, "-8.9 ", -(int64_t)8949*1000*1000*1000*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE },
{ 6, "-9.2 ", -INT64_MAX, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 6, "-8.9 ", -(int64_t)8949*1000*1000*1000*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, HN_AUTOSCALE, 6 },
{ 5, "8.0 E", INT64_MAX, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "7.9 E", INT64_MAX-(int64_t)100*1024*1024*1024*1024*1024LL, HN_DECIMAL, HN_AUTOSCALE },
{ 6, "-8.0 ", -INT64_MAX, HN_DECIMAL, HN_AUTOSCALE },
{ 6, "-7.9 ", -INT64_MAX+(int64_t)100*1024*1024*1024*1024*1024LL, HN_DECIMAL, HN_AUTOSCALE },
{ 5, "8.0 E", INT64_MAX, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 5, "7.9 E", INT64_MAX-(int64_t)100*1024*1024*1024*1024*1024LL, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 6, "-8.0 ", -INT64_MAX, HN_DECIMAL, HN_AUTOSCALE, 6 },
{ 6, "-7.9 ", -INT64_MAX+(int64_t)100*1024*1024*1024*1024*1024LL, HN_DECIMAL, HN_AUTOSCALE, 6 },
/* Positive, Fixed scales */
{ 5, "500 k", (int64_t)500*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1 },
{ 5, "0.5 M", (int64_t)500*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "949 k", (int64_t)949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1 },
{ 5, "0.9 M", (int64_t)949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "950 k", (int64_t)950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1 },
{ 5, "1.0 M", (int64_t)950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "999 k", (int64_t)999*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1 },
{ 5, "1.0 M", (int64_t)999*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "1.5 M", (int64_t)1500*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "1.9 M", (int64_t)1949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "2.0 M", (int64_t)1950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "9.9 M", (int64_t)9949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 4, "10 M", (int64_t)9950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "500 M", (int64_t)500*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "0.5 G", (int64_t)500*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 3 },
{ 5, "999 M", (int64_t)999*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2 },
{ 5, "1.0 G", (int64_t)999*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 3 },
{ 5, "500 k", (int64_t)500*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1, 6 },
{ 5, "0.5 M", (int64_t)500*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "949 k", (int64_t)949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1, 6 },
{ 5, "0.9 M", (int64_t)949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "950 k", (int64_t)950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1, 6 },
{ 5, "1.0 M", (int64_t)950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "999 k", (int64_t)999*1000L, HN_DECIMAL|HN_DIVISOR_1000, 1, 6 },
{ 5, "1.0 M", (int64_t)999*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "1.5 M", (int64_t)1500*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "1.9 M", (int64_t)1949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "2.0 M", (int64_t)1950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "9.9 M", (int64_t)9949*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 4, "10 M", (int64_t)9950*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "500 M", (int64_t)500*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "0.5 G", (int64_t)500*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 3, 6 },
{ 5, "999 M", (int64_t)999*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 2, 6 },
{ 5, "1.0 G", (int64_t)999*1000*1000L, HN_DECIMAL|HN_DIVISOR_1000, 3, 6 },
/* Positive/negative, at maximum scale */
{ 5, "500 P", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 5 },
{ 5, "1.0 E", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6 },
{ 5, "1.9 E", (int64_t)1949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6 },
{ 5, "8.9 E", (int64_t)8949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6 },
{ 5, "9.2 E", INT64_MAX, HN_DECIMAL|HN_DIVISOR_1000, 6 },
{ 5, "500 P", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 5, 6 },
{ 5, "1.0 E", (int64_t)500*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6, 6 },
{ 5, "1.9 E", (int64_t)1949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6, 6 },
{ 5, "8.9 E", (int64_t)8949*1000*1000*1000*1000*1000L, HN_DIVISOR_1000, 6, 6 },
{ 5, "9.2 E", INT64_MAX, HN_DECIMAL|HN_DIVISOR_1000, 6, 6 },
/* HN_DECIMAL + binary + fixed scale cases not completed */
{ 5, "512 K", (int64_t)512*1024L, HN_DECIMAL, 1 },
{ 5, "0.5 M", (int64_t)512*1024L, HN_DECIMAL, 2 },
{ 5, "512 K", (int64_t)512*1024L, HN_DECIMAL, 1, 6 },
{ 5, "0.5 M", (int64_t)512*1024L, HN_DECIMAL, 2, 6 },
/* Negative, Fixed scales */
/* Not yet added, but should work with latest rev */
@ -439,9 +443,9 @@ static struct {
} flags[] = {
{ HN_AUTOSCALE, "HN_AUTOSCALE" },
{ HN_GETSCALE, "HN_GETSCALE" },
{ HN_DIVISOR_1000, "HN_DIVISOR_1000"},
{ HN_B, "HN_B"},
{ HN_DECIMAL, "HN_DECIMAL"},
{ HN_DIVISOR_1000, "HN_DIVISOR_1000" },
{ HN_B, "HN_B" },
{ HN_DECIMAL, "HN_DECIMAL" },
};
static const char *separator = "|";
@ -496,13 +500,14 @@ main(int argc, char * const argv[])
{
char *buf;
char *flag_str, *scale_str;
size_t buflen, errcnt, i, skipped, tested;
size_t blen, buflen, errcnt, i, skipped, tested;
int r;
int includeNegScale;
int includeExabyteTests;
int verbose;
buflen = 4;
buf = NULL;
buflen = 0;
includeNegScale = 0;
includeExabyteTests = 0;
verbose = 0;
@ -510,7 +515,6 @@ main(int argc, char * const argv[])
read_options(argc, argv, &buflen, &includeNegScale,
&includeExabyteTests, &verbose);
buf = malloc(buflen);
errcnt = 0;
tested = 0;
skipped = 0;
@ -520,16 +524,8 @@ main(int argc, char * const argv[])
printf("1..%zu\n", nitems(test_args));
for (i = 0; i < nitems(test_args); i++) {
/* KLUDGE */
if (test_args[i].num == INT64_MAX && buflen == 4) {
/* Start final tests which require buffer of 6 */
free(buf);
buflen = 6;
buf = malloc(buflen);
if (verbose)
printf("Buffer length increased to %zu\n",
buflen);
}
blen = (buflen > 0) ? buflen : test_args[i].buflen;
buf = realloc(buf, blen);
if (test_args[i].scale < 0 && ! includeNegScale) {
skipped++;
@ -542,7 +538,7 @@ main(int argc, char * const argv[])
continue;
}
r = humanize_number(buf, buflen, test_args[i].num, "",
r = humanize_number(buf, blen, test_args[i].num, "",
test_args[i].scale, test_args[i].flags);
flag_str = str_flags(test_args[i].flags, "[no flags]");
scale_str = str_scale(test_args[i].scale);
@ -553,7 +549,7 @@ main(int argc, char * const argv[])
"buflen: %zu, got: %d + \"%s\", "
"expected %d + \"%s\"; num = %jd, "
"scale = %s, flags= %s.\n",
i, buflen, r, buf, test_args[i].retval,
i, blen, r, buf, test_args[i].retval,
test_args[i].res,
(intmax_t)test_args[i].num,
scale_str, flag_str);
@ -565,10 +561,10 @@ main(int argc, char * const argv[])
if (verbose)
printf("result mismatch on index %zu, got: "
"\"%s\", expected \"%s\"; num = %jd, "
"scale = %s, flags= %s.\n",
"buflen: %zu, scale = %s, flags= %s.\n",
i, buf, test_args[i].res,
(intmax_t)test_args[i].num,
scale_str, flag_str);
blen, scale_str, flag_str);
else
printf("not ok %zu # buf \"%s\" != \"%s\"\n",
i + 1, buf, test_args[i].res);
@ -577,15 +573,15 @@ main(int argc, char * const argv[])
if (verbose)
printf("successful result on index %zu, "
"returned %d, got: \"%s\"; num = %jd, "
"scale = %s, flags= %s.\n",
i, r, buf,
(intmax_t)test_args[i].num,
scale_str, flag_str);
"buflen = %zd, scale = %s, flags= %s.\n",
i, r, buf, (intmax_t)test_args[i].num,
blen, scale_str, flag_str);
else
printf("ok %zu\n", i + 1);
}
tested++;
}
free(buf);
if (verbose)
printf("total errors: %zu/%zu tests, %zu skipped\n", errcnt,

2
lib/msun/src/catrig.c
View File

@ -611,7 +611,7 @@ catanh(double complex z)
if (ax < SQRT_3_EPSILON / 2 && ay < SQRT_3_EPSILON / 2) {
/*
* z = 0 was filtered out above. All other cases must raise
* inexact, but this is the only only that needs to do it
* inexact, but this is the only case that needs to do it
* explicitly.
*/
raise_inexact();

1
libexec/dma/dmagent/mailer.conf
View File

@ -1,5 +1,4 @@
# $FreeBSD$
sendmail /usr/libexec/dma
send-mail /usr/libexec/dma
mailq /usr/libexec/dma

11
libexec/rpc.sprayd/rpc.sprayd.8
View File

@ -1,3 +1,4 @@
.\" $NetBSD: rpc.sprayd.8,v 1.10 2009/10/21 01:07:46 snj Exp $
.\"
.\" Copyright (c) 1994 Christos Zoulas
.\" All rights reserved.
@ -10,11 +11,6 @@
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Christos Zoulas.
.\" 4. The name of the author may not be used to endorse or promote products
.\" derived from this software without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@ -29,11 +25,12 @@
.\"
.\" $FreeBSD$
.\"
.Dd June 22, 1994
.Dd December 27, 2017
.Dt RPC.SPRAYD 8
.Os
.Sh NAME
.Nm rpc.sprayd
.Nm rpc.sprayd ,
.Nm sprayd
.Nd spray server
.Sh SYNOPSIS
.Nm /usr/libexec/rpc.sprayd

31
libexec/rpc.sprayd/sprayd.c
View File

@ -1,5 +1,7 @@
/* $NetBSD: sprayd.c,v 1.15 2009/10/21 01:07:46 snj Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 1994 Christos Zoulas
* All rights reserved.
@ -12,11 +14,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christos Zoulas.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@ -64,7 +61,7 @@ static int from_inetd = 1;
void
cleanup(int sig __unused)
{
(void) rpcb_unset(SPRAYPROG, SPRAYVERS, NULL);
(void)rpcb_unset(SPRAYPROG, SPRAYVERS, NULL);
exit(0);
}
@ -93,17 +90,17 @@ main(int argc, char *argv[])
if (!from_inetd) {
daemon(0, 0);
(void) rpcb_unset(SPRAYPROG, SPRAYVERS, NULL);
(void)rpcb_unset(SPRAYPROG, SPRAYVERS, NULL);
(void) signal(SIGINT, cleanup);
(void) signal(SIGTERM, cleanup);
(void) signal(SIGHUP, cleanup);
(void)signal(SIGINT, cleanup);
(void)signal(SIGTERM, cleanup);
(void)signal(SIGHUP, cleanup);
} else {
(void) signal(SIGALRM, die);
(void)signal(SIGALRM, die);
alarm(TIMEOUT);
}
openlog("rpc.sprayd", LOG_CONS|LOG_PID, LOG_DAEMON);
openlog("rpc.sprayd", LOG_PID, LOG_DAEMON);
if (from_inetd) {
transp = svc_tli_create(0, NULL, NULL, 0, 0);
@ -120,7 +117,7 @@ main(int argc, char *argv[])
syslog(LOG_ERR,
"unable to register (SPRAYPROG, SPRAYVERS, %s)",
(!from_inetd)?"udp":"(inetd)");
return 1;
exit(1);
}
svc_run();
@ -138,7 +135,7 @@ spray_service(struct svc_req *rqstp, SVCXPRT *transp)
switch (rqstp->rq_proc) {
case SPRAYPROC_CLEAR:
scum.counter = 0;
(void) gettimeofday(&clear, 0);
(void)gettimeofday(&clear, 0);
/*FALLTHROUGH*/
case NULLPROC:
@ -150,7 +147,7 @@ spray_service(struct svc_req *rqstp, SVCXPRT *transp)
return;
case SPRAYPROC_GET:
(void) gettimeofday(&get, 0);
(void)gettimeofday(&get, 0);
timersub(&get, &clear, &get);
scum.clock.sec = get.tv_sec;
scum.clock.usec = get.tv_usec;
@ -163,6 +160,6 @@ spray_service(struct svc_req *rqstp, SVCXPRT *transp)
if (!svc_sendreply(transp, (xdrproc_t)xdr_spraycumul, &scum)) {
svcerr_systemerr(transp);
syslog(LOG_ERR, "bad svc_sendreply");
syslog(LOG_WARNING, "bad svc_sendreply");
}
}

16
sbin/ccdconfig/ccdconfig.8
View File

@ -1,8 +1,11 @@
.\" $NetBSD: ccdconfig.8,v 1.1.2.1 1995/11/11 02:43:33 thorpej Exp $
.\" $NetBSD: ccdconfig.8,v 1.4 1996/02/28 01:01:17 thorpej Exp $
.\"
.\" Copyright (c) 1995 Jason R. Thorpe.
.\" Copyright (c) 1996 The NetBSD Foundation, Inc.
.\" All rights reserved.
.\"
.\" This code is derived from software contributed to The NetBSD Foundation
.\" by Jason R. Thorpe.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
@ -11,8 +14,13 @@
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 4. The name of the author may not be used to endorse or promote products
.\" derived from this software without specific prior written permission.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by the NetBSD
.\" Foundation, Inc. and its contributors.
.\" 4. Neither the name of The NetBSD Foundation nor the names of its
.\" contributors may be used to endorse or promote products derived
.\" from this software without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

38
sbin/ccdconfig/ccdconfig.c
View File

@ -1,10 +1,15 @@
/* $NetBSD: ccdconfig.c,v 1.6 1996/05/16 07:11:18 thorpej Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2003 Poul-Henning Kamp
* Copyright (c) 1995 Jason R. Thorpe.
* Copyright (c) 1996 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -15,22 +20,23 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project
* by Jason R. Thorpe.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>

37
sbin/ccdconfig/pathnames.h
View File

@ -1,11 +1,14 @@
/* $NetBSD: pathnames.h,v 1.1 1995/08/17 16:37:20 thorpej Exp $ */
/* $NetBSD: pathnames.h,v 1.4 2008/04/28 20:23:07 martin Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 1995 Jason R. Thorpe.
* Copyright (c) 1996 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -14,24 +17,18 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project
* by Jason R. Thorpe.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/

2
sbin/devfs/rule.c
View File

@ -267,7 +267,7 @@ ruleset_main(int ac, char **av)
* differs from the other rulespec_in*() routines in that it also
* calls ioctl() for the rules, since it is impractical (and not very
* useful) to return a list (or array) of rules, just so the caller
* can call call ioctl() for each of them.
* can call ioctl() for each of them.
*/
static void
rulespec_infp(FILE *fp, unsigned long request, devfs_rsnum rsnum)

4
sbin/dump/dump.h
View File

@ -108,7 +108,7 @@ int mapfiles(ino_t maxino, long *tapesize);
int mapdirs(ino_t maxino, long *tapesize);
/* file dumping routines */
void bread(ufs2_daddr_t blkno, char *buf, int size);
void blkread(ufs2_daddr_t blkno, char *buf, int size);
ssize_t cread(int fd, void *buf, size_t nbytes, off_t offset);
void dumpino(union dinode *dp, ino_t ino);
void dumpmap(char *map, int type, ino_t ino);
@ -127,7 +127,7 @@ void dumpabort(int signo) __dead2;
void dump_getfstab(void);
char *rawname(char *cp);
union dinode *getino(ino_t inum, int *mode);
union dinode *getinode(ino_t inum, int *mode);
/* rdump routines */
#ifdef RDUMP

8
sbin/dump/main.c
View File

@ -439,8 +439,8 @@ main(int argc, char *argv[])
sync();
sblock = (struct fs *)sblock_buf;
for (i = 0; sblock_try[i] != -1; i++) {
sblock->fs_fsize = SBLOCKSIZE; /* needed in bread */
bread(sblock_try[i] >> dev_bshift, (char *) sblock, SBLOCKSIZE);
sblock->fs_fsize = SBLOCKSIZE; /* needed in blkread */
blkread(sblock_try[i]>>dev_bshift, (char *) sblock, SBLOCKSIZE);
if ((sblock->fs_magic == FS_UFS1_MAGIC ||
(sblock->fs_magic == FS_UFS2_MAGIC &&
sblock->fs_sblockloc == sblock_try[i])) &&
@ -556,7 +556,7 @@ main(int argc, char *argv[])
/*
* Skip directory inodes deleted and maybe reallocated
*/
dp = getino(ino, &mode);
dp = getinode(ino, &mode);
if (mode != IFDIR)
continue;
(void)dumpino(dp, ino);
@ -575,7 +575,7 @@ main(int argc, char *argv[])
/*
* Skip inodes deleted and reallocated as directories.
*/
dp = getino(ino, &mode);
dp = getinode(ino, &mode);
if (mode == IFDIR)
continue;
(void)dumpino(dp, ino);

2
sbin/dump/tape.c
View File

@ -786,7 +786,7 @@ doslave(int cmd, int slave_number)
for (trecno = 0; trecno < ntrec;
trecno += p->count, p += p->count) {
if (p->dblk) {
bread(p->dblk, slp->tblock[trecno],
blkread(p->dblk, slp->tblock[trecno],
p->count * TP_BSIZE);
} else {
if (p->count != 1 || atomic(read, cmd,

20
sbin/dump/traverse.c
View File

@ -162,7 +162,7 @@ mapfiles(ino_t maxino, long *tapesize)
quit("mapfiles: cannot allocate memory.\n");
for (cg = 0; cg < sblock->fs_ncg; cg++) {
ino = cg * sblock->fs_ipg;
bread(fsbtodb(sblock, cgtod(sblock, cg)), (char *)cgp,
blkread(fsbtodb(sblock, cgtod(sblock, cg)), (char *)cgp,
sblock->fs_cgsize);
if (sblock->fs_magic == FS_UFS2_MAGIC)
inosused = cgp->cg_initediblk;
@ -194,7 +194,7 @@ mapfiles(ino_t maxino, long *tapesize)
}
for (i = 0; i < inosused; i++, ino++) {
if (ino < UFS_ROOTINO ||
(dp = getino(ino, &mode)) == NULL ||
(dp = getinode(ino, &mode)) == NULL ||
(mode & IFMT) == 0)
continue;
if (ino >= maxino) {
@ -276,7 +276,7 @@ mapdirs(ino_t maxino, long *tapesize)
nodump = !nonodump && (TSTINO(ino, usedinomap) == 0);
if ((isdir & 1) == 0 || (TSTINO(ino, dumpinomap) && !nodump))
continue;
dp = getino(ino, &i);
dp = getinode(ino, &i);
/*
* inode buf may change in searchdir().
*/
@ -342,7 +342,7 @@ dirindir(
int ret = 0;
int i;
bread(fsbtodb(sblock, blkno), (char *)&idblk, (int)sblock->fs_bsize);
blkread(fsbtodb(sblock, blkno), (char *)&idblk, (int)sblock->fs_bsize);
if (ind_level <= 0) {
for (i = 0; *filesize > 0 && i < NINDIR(sblock); i++) {
if (sblock->fs_magic == FS_UFS1_MAGIC)
@ -395,7 +395,7 @@ searchdir(
if (dblk == NULL && (dblk = malloc(sblock->fs_bsize)) == NULL)
quit("searchdir: cannot allocate indirect memory.\n");
bread(fsbtodb(sblock, blkno), dblk, (int)size);
blkread(fsbtodb(sblock, blkno), dblk, (int)size);
if (filesize < size)
size = filesize;
for (loc = 0; loc < size; ) {
@ -420,7 +420,7 @@ searchdir(
continue;
}
if (nodump) {
ip = getino(dp->d_ino, &mode);
ip = getinode(dp->d_ino, &mode);
if (TSTINO(dp->d_ino, dumpinomap)) {
CLRINO(dp->d_ino, dumpinomap);
*tapesize -= blockest(ip);
@ -591,7 +591,7 @@ dmpindir(union dinode *dp, ino_t ino, ufs2_daddr_t blk, int ind_level,
int i, cnt, last;
if (blk != 0)
bread(fsbtodb(sblock, blk), (char *)&idblk,
blkread(fsbtodb(sblock, blk), (char *)&idblk,
(int)sblock->fs_bsize);
else
memset(&idblk, 0, sblock->fs_bsize);
@ -871,7 +871,7 @@ writeheader(ino_t ino)
}
union dinode *
getino(ino_t inum, int *modep)
getinode(ino_t inum, int *modep)
{
static ino_t minino, maxino;
static caddr_t inoblock;
@ -883,7 +883,7 @@ getino(ino_t inum, int *modep)
curino = inum;
if (inum >= minino && inum < maxino)
goto gotit;
bread(fsbtodb(sblock, ino_to_fsba(sblock, inum)), inoblock,
blkread(fsbtodb(sblock, ino_to_fsba(sblock, inum)), inoblock,
(int)sblock->fs_bsize);
minino = inum - (inum % INOPB(sblock));
maxino = minino + INOPB(sblock);
@ -908,7 +908,7 @@ int breaderrors = 0;
#define BREADEMAX 32
void
bread(ufs2_daddr_t blkno, char *buf, int size)
blkread(ufs2_daddr_t blkno, char *buf, int size)
{
int secsize, bytes, resid, xfer, base, cnt, i;
static char *tmpbuf;

4
sbin/fsdb/fsdb.c
View File

@ -565,6 +565,10 @@ CMDFUNCSTART(findblk)
end:
curinum = ocurrent;
curinode = ginode(curinum);
if (is_ufs2)
free(wantedblk64);
else
free(wantedblk32);
return 0;
}

2
sbin/ipfw/ipfw.8
View File

@ -3020,7 +3020,7 @@ supports in-kernel IPv6/IPv4 network address and protocol translation.
Stateful NAT64 translation allows IPv6-only clients to contact IPv4 servers
using unicast TCP, UDP or ICMP protocols.
One or more IPv4 addresses assigned to a stateful NAT64 translator are shared
among serveral IPv6-only clients.
among several IPv6-only clients.
When stateful NAT64 is used in conjunction with DNS64, no changes are usually
required in the IPv6 client or the IPv4 server.
The kernel module

3
sbin/newfs_msdos/mkfs_msdos.c
View File

@ -247,6 +247,7 @@ mkfs_msdos(const char *fname, const char *dtype, const struct msdos_options *op)
img = NULL;
rv = -1;
fd = fd1 = -1;
if (o.block_size && o.sectors_per_cluster) {
warnx("Cannot specify both block size and sectors per cluster");
@ -716,6 +717,8 @@ mkfs_msdos(const char *fname, const char *dtype, const struct msdos_options *op)
rv = 0;
done:
free(img);
close(fd);
close(fd1);
return rv;
}

2
sbin/pfctl/pfctl.c
View File

@ -1510,6 +1510,7 @@ pfctl_rules(int dev, char *filename, int opts, int optimize,
if (pfctl_trans(dev, t, DIOCXCOMMIT, osize))
ERR("DIOCXCOMMIT");
}
free(path);
return (0);
_error:
@ -1519,6 +1520,7 @@ pfctl_rules(int dev, char *filename, int opts, int optimize,
err(1, "DIOCXROLLBACK");
exit(1);
} else { /* sub ruleset */
free(path);
return (-1);
}

1
sbin/routed/main.c
View File

@ -667,6 +667,7 @@ get_rip_sock(naddr addr,
if (bind(s, (struct sockaddr *)&rsin, sizeof(rsin)) < 0) {
if (serious)
BADERR(errno != EADDRINUSE, "bind(rip_sock)");
close(s);
return -1;
}
fix_sock(s,"rip_sock");

9
share/man/man4/Makefile
View File

@ -70,6 +70,9 @@ MAN= aac.4 \
audit.4 \
auditpipe.4 \
aue.4 \
${_aw_gpio.4} \
${_aw_mmc.4} \
${_aw_rtc.4} \
axe.4 \
axge.4 \
bce.4 \
@ -756,6 +759,12 @@ MLINKS+=xl.4 if_xl.4
_armv8crypto.4= armv8crypto.4
.endif
.if ${MACHINE_CPUARCH} == "arm" || ${MACHINE_CPUARCH} == "aarch64"
_aw_gpio.4= aw_gpio.4
_aw_mmc.4= aw_mmc.4
_aw_rtc.4= aw_rtc.4
.endif
.if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
_acpi_asus.4= acpi_asus.4
_acpi_asus_wmi.4= acpi_asus_wmi.4

102
share/man/man4/aw_gpio.4 Normal file
View File

@ -0,0 +1,102 @@
.\"-
.\" Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd Dec 25, 2017
.Dt AW_GPIO 4
.Os
.Sh NAME
.Nm aw_gpio
.Nd driver for the GPIO and pin muxing functionalities on Allwinner SoC
.Sh SYNOPSIS
.Cd "device gpio"
.Cd "options SOC_ALLWINNER_A10"
.Cd "options SOC_ALLWINNER_A13"
.Cd "options SOC_ALLWINNER_A20"
.Cd "options SOC_ALLWINNER_A31"
.Cd "options SOC_ALLWINNER_A31S"
.Cd "options SOC_ALLWINNER_A33"
.Cd "options SOC_ALLWINNER_A83T"
.Cd "options SOC_ALLWINNER_H2PLUS"
.Cd "options SOC_ALLWINNER_H3"
.Cd "options SOC_ALLWINNER_A64"
.Cd "options SOC_ALLWINNER_H5"
.Sh DESCRIPTION
The
.Nm
device driver provides support for the Allwinner pin muxing and GPIO on
Allwinner SoCs.
.Sh HARDWARE
The current version of the
.Nm
driver supports the GPIO/pinmuxing controller with one of the following
compatible strings :
.Pp
.Bl -bullet -compact
.It
allwinner,sun4i-a10-pinctrl
.It
allwinner,sun5i-a13-pinctrl
.It
allwinner,sun7i-a20-pinctrl
.It
allwinner,sun6i-a31-pinctrl
.It
allwinner,sun6i-a31s-pinctrl
.It
allwinner,sun6i-a31-r-pinctrl
.It
allwinner,sun6i-a33-pinctrl
.It
allwinner,sun8i-a83t-pinctrl
.It
allwinner,sun8i-a83t-r-pinctrl
.It
allwinner,sun8i-h3-pinctrl
.It
allwinner,sun50i-h5-pinctrl
.It
allwinner,sun8i-h3-r-pinctrl
.It
allwinner,sun50i-a64-pinctrl
.It
allwinner,sun50i-a64-r-pinctrl
.El
.Sh SEE ALSO
.Xr fdt 4 ,
.Xr gpio 4
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 10.0 .
.Sh AUTHORS
The
.Nm
device driver was originally written by
.An Ganbold Tsagaankhuu Aq Mt ganbold@freebsd.org .
This manual page was written by
.An Emmanuel Vadot Aq Mt manu@freebsd.org .

76
share/man/man4/aw_mmc.4 Normal file
View File

@ -0,0 +1,76 @@
.\"-
.\" Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd Dec 25, 2017
.Dt AW_MMC 4
.Os
.Sh NAME
.Nm aw_mmc
.Nd driver for the SD/MMC controller in Allwinner SoC
.Sh SYNOPSIS
.Cd "device mmc"
.Sh DESCRIPTION
The
.Nm
device driver provides support for the Allwinner SD/MMC host controller.
.Sh HARDWARE
The current version of the
.Nm
driver supports the SD/MMC controller with one of the following compatible strings :
.Pp
.Bl -bullet -compact
.It
allwinner,sun4i-a10-mmc
.It
allwinner,sun5i-a13-mmc
.It
allwinner,sun7i-a20-mmc
.It
allwinner,sun50i-a64-mmc
.El
.Sh SYSCTL VARIABLES
The following read-only variables are available via
.Xr sysctl 8 :
.Bl -tag -width indent
.It Va dev.aw_mmc.req_timeout
Request timeout in seconds (default: 10) .
.El
.Sh SEE ALSO
.Xr fdt 4 ,
.Xr mmc 4
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 10.0 .
.Sh AUTHORS
The
.Nm
device driver was originally written by
.An Alexander Fedorov Aq Mt alexander.fedorov@rtlservice.com .
Later work and this manual page was done by
.An Emmanuel Vadot Aq Mt manu@freebsd.org .

63
share/man/man4/aw_rtc.4 Normal file
View File

@ -0,0 +1,63 @@
.\"-
.\" Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd Dec 25, 2017
.Dt AW_RTC 4
.Os
.Sh NAME
.Nm aw_rtc
.Nd driver for the RTC controller in Allwinner SoC
.Sh DESCRIPTION
The
.Nm
device driver provides support for the Allwinner RTC controller.
.Sh HARDWARE
The current version of the
.Nm
driver supports the RTC controller with one of the following compatible
strings :
.Pp
.Bl -bullet -compact
.It
allwinner,sun4i-a10-rtc
.It
allwinner,sun7i-a20-rtc
.It
allwinner,sun6i-a31-rtc
.El
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 11.0 .
.Sh AUTHORS
The
.Nm
device driver was written by
.An Vladimir Belian Aq Mt fate10@gmail.com .
This manual page was written by
.An Emmanuel Vadot Aq Mt manu@freebsd.org .

2
share/man/man4/ip.4
View File

@ -224,7 +224,7 @@ or the socket should be bound to a local address and the address supplied with
.Dv IP_SENDSRCADDR
should be
.Dv INADDR_ANY .
In the latter case bound address is overriden via generic source address
In the latter case bound address is overridden via generic source address
selection logic, which would choose IP address of interface closest to
destination.
.Pp

21
share/man/man4/lm75.4
View File

@ -24,7 +24,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd May 11, 2014
.Dd December 26, 2017
.Dt LM75 4
.Os
.Sh NAME
@ -122,7 +122,7 @@ clones may not work reliably.
.Pp
On a
.Xr device.hints 5
based system, like
based system, such as
.Li MIPS ,
these values are configurable for
.Nm :
@ -140,31 +140,28 @@ i2c address on the
.Pp
On a
.Xr FDT 4
based system, like
based system, such as
.Li ARM ,
the DTS part for a
.Nm
device usually looks like:
.Bd -literal
i2c {
/* Properties describing the controller appear here. */
...
lm750 {
lm750@49 {
compatible = "national,lm75";
i2c-address = <0x49>;
reg = <0x49>;
};
};
.Ed
.Pp
Where:
.Bl -tag -width ".Va i2c-address"
.Bl -tag -width ".Va compatible"
.It Va compatible
Should always be set to "national,lm75".
.It Va i2c-address
The
.Va i2c-address
property indicates which i2c address the
.It Va reg
Indicates which 7-bit i2c address the
.Nm
is wired at.
.Nm

43
share/man/man4/md.4
View File

@ -7,7 +7,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd December 7, 2017
.Dd December 26, 2017
.Dt MD 4
.Os
.Sh NAME
@ -93,6 +93,47 @@ disk found in the
.Xr mdconfig 8
man page.
Other tools will also create these images, such as NanoBSD.
.Sh ARM KERNEL OPTIONS
On armv6 and armv7 architectures, an MD_ROOT image larger than
approximately 55 MiB may require building a custom kernel using
several tuning options related to kernel memory usage.
.Bl -tag -width indent
.It Cd options LOCORE_MAP_MB=<num>
This configures how much memory is mapped for the kernel during
the early initialization stages.
The value must be at least as large as the kernel plus all preloaded
modules, including the root image.
There is no downside to setting this value too large, as long
as it does not exceed the amount of physical memory.
The default is 64 MiB.
.It Cd options NKPT2PG=<num>
This configures the number of kernel L2 page table pages to
preallocate during kernel initialization.
Each L2 page can map 4 MiB of kernel space.
The value must be large enough to map the kernel plus all preloaded
modules, including the root image.
The default value is 32, which is sufficient to map 128 MiB.
.It Cd options VM_KMEM_SIZE_SCALE=<num>
This configures the amount of kernel virtual address (KVA) space to
dedicate to the kmem_arena map.
The value is the ratio of physical to virtual pages.
The default value of 3 allocates a page of KVA for each 3 pages
of physical ram in the system.
The kernel and modules, including the root image, also consume KVA.
The combination of a large root image and the default scaling
may preallocate so much KVA to kmem_arena that there is not enough
remaining address space to allocate kernel stacks, IO buffers,
and other resources that are not part of kmem_arena.
Overallocating kmem_arena space is likely to manifest as failure to
launch userland processes with "cannot allocate kernel stack" messages.
Setting the value too high may result in kernel failure to allocate
memory because kmem_arena is too small, and the failure may require
significant runtime to manifest.
Empirically, a value of 5 works well for a 200 MiB root image on
a system with 2 GiB of physical ram.
.El
.Sh SEE ALSO
.Xr gpart 8 ,
.Xr loader 8 ,

2
share/man/man4/nand.4
View File

@ -41,7 +41,7 @@ The
.Fx
.Nm
framework consists of a set of interfaces that aim to provide an extensible,
object oriented environement for NAND controllers and NAND Flash memory chips
object oriented environment for NAND controllers and NAND Flash memory chips
from various hardware vendors, and to allow for uniform and flexible
management of the NAND devices.
It comprises of the following major components:

7
share/man/man5/mailer.conf.5
View File

@ -31,7 +31,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd February 18, 2016
.Dd December 26, 2017
.Dt MAILER.CONF 5
.Os
.Sh NAME
@ -96,7 +96,6 @@ program:
# Execute the "real" sendmail program located in
# /usr/libexec/sendmail/sendmail
sendmail /usr/libexec/sendmail/sendmail
send-mail /usr/libexec/sendmail/sendmail
mailq /usr/libexec/sendmail/sendmail
newaliases /usr/libexec/sendmail/sendmail
.Ed
@ -109,7 +108,6 @@ to replace
.Bd -literal -offset indent
# Emulate sendmail using postfix
sendmail /usr/local/sbin/sendmail
send-mail /usr/local/sbin/sendmail
mailq /usr/local/sbin/sendmail
newaliases /usr/local/sbin/sendmail
.Ed
@ -122,7 +120,6 @@ to replace
.Bd -literal -offset indent
# Emulate sendmail using exim
sendmail /usr/local/sbin/exim
send-mail /usr/local/sbin/exim
mailq /usr/local/sbin/exim -bp
newaliases /usr/bin/true
rmail /usr/local/sbin/exim -i -oee
@ -136,7 +133,6 @@ to replace
.Bd -literal -offset indent
# Send outgoing mail to a smart relay using mini_sendmail
sendmail /usr/local/bin/mini_sendmail -srelayhost
send-mail /usr/local/bin/mini_sendmail -srelayhost
.Ed
.Pp
Using
@ -146,7 +142,6 @@ to replace
.Bd -literal -offset indent
# Execute dma instead of sendmail
sendmail /usr/libexec/dma
send-mail /usr/libexec/dma
mailq /usr/libexec/dma
newaliases /usr/libexec/dma
rmail /usr/libexec/dma

4
share/man/man5/rc.conf.5
View File

@ -989,7 +989,7 @@ is set to the list of
instances that should be started at system boot time.
If
.Va pflog_instances
is set, for each whitespace-seperated
is set, for each whitespace-separated
.Ar element
in the list,
.Ao Ar element Ac Ns Va _dev
@ -1031,7 +1031,7 @@ If multiple instances of
.Xr ftp-proxy 8
are desired at boot time,
.Va ftpproxy_instances
should contain a whitespace-seperated list of instance names.
should contain a whitespace-separated list of instance names.
For each
.Ar element
in the list, a variable named

2
share/man/man9/iflibdd.9
View File

@ -179,7 +179,7 @@
.Fc
.Sh FUNCTIONS
The above named functions are device dependent configuration functions.
These routines are registerd with iflib by the driver and are called from the
These routines are registered with iflib by the driver and are called from the
corresponding iflib function to configure device specific functions and
registers.
.Ss Device Dependent Functions

2
share/man/man9/iflibtxrx.9
View File

@ -190,7 +190,7 @@ event.
.Sh FUNCTIONS
All function calls are associated exclusively with either packet transmission
or receipt.
The void *sc passed as the first arguement to all of the following functions
The void *sc passed as the first argument to all of the following functions
represents the driver's softc.
.Ss Transmit Packet Functions
.Bl -ohang -offset indent

2
share/man/man9/uio.9
View File

@ -149,7 +149,7 @@ transfers when the request partially overlaps the buffer.
When
.Va uio_offset
is greater than or equal to the buffer size, the result is success
with no bytes transfered, effectively signaling EOF.
with no bytes transferred, effectively signaling EOF.
.Sh RETURN VALUES
On success
.Fn uiomove ,

30
share/misc/bsd-family-tree
View File

@ -290,6 +290,9 @@ FreeBSD 5.2 | | | |
| | | | | | | | |
| | | | | | NetBSD | |
| | | | | | 6.0.5 | |
| | | | | | | | |
| | | | | | NetBSD | |
| | | | | | 6.0.6 | |
| | | | | | | |
| | | | | |`-NetBSD 6.1 | |
| | FreeBSD | | | | |
@ -357,15 +360,23 @@ FreeBSD 5.2 | | | |
| FreeBSD | | | | DragonFly 5.0.0
| 11.1 FreeBSD | | | |
| | 10.4 | | OpenBSD 6.2 DragonFly 5.0.1
| | | | | |
| | | | | DragonFly 5.0.2
| | | | | |
| | | | | |
| v | | | |
| | | | |
FreeBSD 12 -current | NetBSD -current OpenBSD -current DragonFly -current
| | | | |
v v v v v
| | | v | | |
| | | | | DragonFly 5.0.2
| | | | | |
| | FreeBSD | | |
| | 10-stable | | |
| FreeBSD \ | | |
| 11-stable \ | | |
| / `| | | |
| HardenedBSD | | | |
| 11-stable HardenedBSD | | |
| 10-stable | | |
| | | |
| | | |
| | | |
FreeBSD 12 -current NetBSD -current OpenBSD -current DragonFly -current
| | | |
v v v v
Time
----------------
@ -695,6 +706,7 @@ DragonFly 3.8.1 2014-06-16 [DFB]
DragonFly 3.6.3 2014-06-17 [DFB]
FreeBSD 9.3 2014-07-05 [FBD]
DragonFly 3.8.2 2014-08-08 [DFB]
NetBSD 6.0.6 2014-09-22 [NDB]
NetBSD 6.1.5 2014-09-22 [NBD]
Mac OS X 10.10 2014-10-16 [APL]
OpenBSD 5.6 2014-11-01 [OBD]

72
share/misc/pci_vendors
View File

@ -3,8 +3,8 @@
#
# List of PCI ID's
#
# Version: 2017.12.06
# Date: 2017-12-06 03:15:02
# Version: 2017.12.20
# Date: 2017-12-20 03:15:01
#
# Maintained by Albert Pool, Martin Mares, and other volunteers from
# the PCI ID Project at http://pci-ids.ucw.cz/.
@ -586,6 +586,7 @@
0096 SAS3004 PCI-Express Fusion-MPT SAS-3
0097 SAS3008 PCI-Express Fusion-MPT SAS-3
1000 3090 SAS9311-8i
1000 30a0 SAS9300-8e
1000 30e0 SAS9300-8i
1000 3130 SAS 9300-16i
1028 1f45 HBA330 Adapter
@ -2508,6 +2509,7 @@
6842 Thames LE [Radeon HD 7000M Series]
6843 Thames [Radeon HD 7670M]
6861 Vega 10 XT [Radeon PRO WX 9100]
6862 Vega 10 XT [Radeon PRO SSG]
6863 Vega 10 XTX [Radeon Vega Frontier Edition]
687f Vega 10 XT [Radeon RX Vega 64]
6888 Cypress XT [FirePro V8800]
@ -4043,6 +4045,11 @@
1423 Family 15h (Models 30h-3fh) I/O Memory Management Unit
1424 Family 15h (Models 30h-3fh) Processor Root Port
1426 Family 15h (Models 30h-3fh) Processor Root Port
142e Liverpool Processor Function 0
142f Liverpool Processor Function 1
1430 Liverpool Processor Function 2
1431 Liverpool Processor Function 3
1432 Liverpool Processor Function 4
1436 Liverpool Processor Root Complex
1437 Liverpool I/O Memory Management Unit
1438 Liverpool Processor Root Port
@ -5652,6 +5659,22 @@
90a3 Aeolia Memory (DDR3/SPM)
90a4 Aeolia USB 3.0 xHCI Host Controller
90bc SxS Pro+ memory card
90c8 Belize ACPI
90c9 Belize Ethernet Controller
90ca Belize SATA AHCI Controller
90cb Belize SD/MMC Host Controller
90cc Belize PCI Express Glue and Miscellaneous Devices
90cd Belize DMA Controller
90ce Belize Memory (DDR3/SPM)
90cf Belize USB 3.0 xHCI Host Controller
90d7 Baikal ACPI
90d8 Baikal Ethernet Controller
90d9 Baikal SATA AHCI Controller
90da Baikal SD/MMC Host Controller
90db Baikal PCI Express Glue and Miscellaneous Devices
90dc Baikal DMA Controller
90dd Baikal Memory (DDR3/SPM)
90de Baikal USB 3.0 xHCI Host Controller
104e Oak Technology, Inc
0017 OTI-64017
0107 OTI-107 [Spitfire]
@ -10836,11 +10859,12 @@
13d8 GM204M [GeForce GTX 970M]
13d9 GM204M [GeForce GTX 965M]
13da GM204M [GeForce GTX 980 Mobile]
13e7 GM204 [GeForce GTX 980 Engineering Sample]
13e7 GM204GL [GeForce GTX 980 Engineering Sample]
13f0 GM204GL [Quadro M5000]
13f1 GM204GL [Quadro M4000]
13f2 GM204GL [Tesla M60]
13f3 GM204GL [Tesla M6]
10de 1184 GRID M6-8Q
13f8 GM204GLM [Quadro M5000M / M5000 SE]
13f9 GM204GLM [Quadro M4000M]
13fa GM204GLM [Quadro M3000M]
@ -10939,7 +10963,7 @@
1cb3 GP107GL [Quadro P400]
1d01 GP108 [GeForce GT 1030]
1d10 GP108M [GeForce MX150]
1d81 GV100
1d81 GV100 [TITAN V]
1db1 GV100 [Tesla V100 SXM2]
1db4 GV100 [Tesla V100 PCIe]
10df Emulex Corporation
@ -15644,6 +15668,7 @@
0252 XR17V252 Dual UART PCI controller
0254 XR17V254 Quad UART PCI controller
0258 XR17V258 Octal UART PCI controller
0352 XR17V3521 Dual PCIe UART
13a9 Siemens Medical Systems, Ultrasound Group
13aa Broadband Networks Inc
13ab Arcom Control Systems Ltd
@ -18255,6 +18280,8 @@
1556 PLDA
1100 PCI Express Core Reference Design
110f PCI Express Core Reference Design Virtual Function
1110 XpressRich Reference Design
1113 XpressSwitch
1557 MEDIASTAR Co Ltd
1558 CLEVO/KAPOK Computer
1559 SI LOGIC Ltd
@ -18410,6 +18437,7 @@
020b MT27710 Family [ConnectX-4 Lx Flash Recovery]
020d MT28800 Family [ConnectX-5 Flash Recovery]
020f MT28908A0 Family [ConnectX-6 Flash Recovery]
0210 MT28908A0 Family [ConnectX-6 Secure Flash Recovery]
0211 MT416842 Family [BlueField SoC Flash Recovery]
# reserved for RM#105916
024e MT53100 [Spectrum-2, Flash recovery mode]
@ -18474,6 +18502,7 @@
15b3 0050 ConnectX-4 100 GbE Dual Port QSFP28 Adapter
1014 MT27700 Family [ConnectX-4 Virtual Function]
1015 MT27710 Family [ConnectX-4 Lx]
15b3 0004 ConnectX-4 Lx Stand-up dual-port 10GbE MCX4121A-XCAT
15b3 0005 Mellanox Technologies ConnectX-4 Lx Stand-up single-port 40GbE MCX4131A-BCAT
15b3 0016 ConnectX-4 Lx 25 GbE Dual Port SFP28 Adapter
15b3 0020 MCX4411A-ACQN, ConnectX-4 Lx EN OCP, 1x25Gb
@ -18531,6 +18560,7 @@
7121 NPS-600 configuration and management interface
7122 NPS-600 network interface PF
7123 NPS-600 network interface VF
8200 Innova-2 FPGA
a2d0 MT416842 BlueField SoC Crypto enabled
a2d1 MT416842 BlueField SoC Crypto disabled
a2d2 MT416842 BlueField integrated ConnectX-5 network controller
@ -18567,6 +18597,7 @@
0015 ZBox
15b7 Sandisk Corp
2001 Skyhawk Series NVME SSD
5001 WD Black NVMe SSD
15b8 ADDI-DATA GmbH
1001 APCI1516 SP controller (16 digi outputs)
1003 APCI1032 SP controller (32 digi inputs w/ opto coupler)
@ -18715,6 +18746,11 @@
1006 Format synchronizer, model 10500
1007 Format synchronizer, model 21000
2002 Fast Universal Data Output
3100 IO31000 Frame Synchronizer and I/O
3200 IO32000 Frame Synchronizer and I/O
4002 High Rate Demodulator
5001 High Rate FEC
6001 High Rate Demodulator and FEC
1631 Packard Bell B.V.
1638 Standard Microsystems Corp [SMC]
1100 SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000
@ -20072,11 +20108,15 @@
1924 8019 SFN8542-R2 8000 Series 10/40G Adapter
1924 801a SFN8722-R1 8000 Series OCP 10G Adapter
1924 801b SFN8522-R3 8000 Series 10G Adapter
0b03 SFC9250 10/25/40/50/100G Ethernet Controller
1924 801d x2522-R1 2000 Series 10/25G Adapter
1924 801e x2542-R1 2000 Series 40/100G Adapter
1803 SFC9020 10G Ethernet Controller (Virtual Function)
1813 SFL9021 10GBASE-T Ethernet Controller (Virtual Function)
1903 SFC9120 10G Ethernet Controller (Virtual Function)
1923 SFC9140 10/40G Ethernet Controller (Virtual Function)
1a03 SFC9220 10/40G Ethernet Controller (Virtual Function)
1b03 SFC9250 10/25/40/50/100G Ethernet Controller (Virtual Function)
6703 SFC4000 rev A iSCSI/Onload [Solarstorm]
10b8 0102 SMC10GPCIe-10BT (A2) [TigerCard]
10b8 0103 SMC10GPCIe-10BT (A3) [TigerCard]
@ -20945,6 +20985,7 @@
1d7c Aerotech, Inc.
1d87 Fuzhou Rockchip Electronics Co., Ltd
1d8f Enyx
1d94 Chengdu Higon IC Design Co.Ltd
1d95 Graphcore Ltd
1da1 Teko Telecom S.r.l.
1da2 Sapphire Technology Limited
@ -23661,8 +23702,9 @@
15c7 Ethernet Connection X553 1GbE
15c8 Ethernet Connection X553/X557-AT 10GBASE-T
15ce Ethernet Connection X553 10 GbE SFP+
15d0 Ethernet SDI Adapter FM10420-100GbE-QDA2
15d0 Ethernet SDI Adapter
8086 0001 Ethernet SDI Adapter FM10420-100GbE-QDA2
8086 0002 Ethernet SDI Adapter FM10840-MTP2
15d1 Ethernet Controller 10G X550T
8086 0002 Ethernet Converged Network Adapter X550-T1
8086 001b Ethernet Server Adapter X550-T1 for OCP
@ -23687,6 +23729,14 @@
15e3 Ethernet Connection (5) I219-LM
15e4 Ethernet Connection X553 1GbE
15e5 Ethernet Connection X553 1GbE
15e7 JHL7540 Thunderbolt 3 Bridge [Titan Ridge 2C 2018]
15e8 JHL7540 Thunderbolt 3 NHI [Titan Ridge 2C 2018]
15e9 JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 2C 2018]
15ea JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018]
15eb JHL7540 Thunderbolt 3 NHI [Titan Ridge 4C 2018]
15ec JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018]
15ef JHL7540 Thunderbolt 3 Bridge [Titan Ridge DD 2018]
15f0 JHL7540 Thunderbolt 3 USB Controller [Titan Ridge DD 2018]
1600 Broadwell-U Host Bridge -OPI
1601 Broadwell-U PCI Express x16 Controller
1602 Broadwell-U Integrated Graphics
@ -24113,6 +24163,7 @@
144d c652 NP300E5C series laptop
1849 1e2d Motherboard
1e31 7 Series/C210 Series Chipset Family USB xHCI Host Controller
103c 179b Elitebook 8470p
103c 17ab ProBook 6570b
1043 108d VivoBook X202EV
1043 1477 N56VZ
@ -25486,6 +25537,12 @@
103c 31fe ProLiant DL140 G3
15d9 8680 X7DVL-E-O motherboard
15d9 9680 X7DBN Motherboard
2700 Optane SSD 900P Series
8086 3900 900P Series [Add-in Card]
8086 3901 900P Series [2.5" SFF]
2701 Optane DC P4800X Series SSD
8086 3904 DC P4800X Series [Add-in Card]
8086 3905 DC P4800X Series [2.5" SFF]
2770 82945G/GZ/P/PL Memory Controller Hub
1028 01ad OptiPlex GX620
103c 2a3b Pavilion A1512X
@ -29020,6 +29077,11 @@
103c 0701 Smart Array P204i-b SR Gen10
103c 1100 Smart Array P816i-a SR Gen10
103c 1101 Smart Array P416ie-m SR G10
152d 8a22 QS-8204-8i
152d 8a23 QS-8238-16i
152d 8a24 QS-8236-16i
152d 8a36 QS-8240-24i
152d 8a37 QS-8242-24i
9005 0800 SmartRAID 3154-8i
9005 0801 SmartRAID 3152-8i
9005 0802 SmartRAID 3151-4i

8
stand/fdt/fdt_loader_cmd.c
View File

@ -281,14 +281,12 @@ fdt_load_dtb_file(const char * filename)
static int
fdt_load_dtb_overlay(const char * filename)
{
struct preloaded_file *bfp, *oldbfp;
struct preloaded_file *bfp;
struct fdt_header header;
int err;
debugf("fdt_load_dtb_overlay(%s)\n", filename);
oldbfp = file_findfile(filename, "dtbo");
/* Attempt to load and validate a new dtb from a file. */
if ((bfp = file_loadraw(filename, "dtbo", 1)) == NULL) {
printf("failed to load file '%s'\n", filename);
@ -310,10 +308,6 @@ fdt_load_dtb_overlay(const char * filename)
return (1);
}
/* A new dtb was validated, discard any previous file. */
if (oldbfp)
file_discard(oldbfp);
return (0);
}

10
stand/fdt/fdt_overlay.c
View File

@ -324,10 +324,16 @@ fdt_overlay_do_fixups(void *main_fdtp, void *overlay_fdtp)
main_symbols_o = fdt_path_offset(main_fdtp, "/__symbols__");
overlay_fixups_o = fdt_path_offset(overlay_fdtp, "/__fixups__");
if (main_symbols_o < 0)
if (main_symbols_o < 0) {
if (main_symbols_o == -FDT_ERR_NOTFOUND)
return (0);
return (-1);
if (overlay_fixups_o < 0)
}
if (overlay_fixups_o < 0) {
if (overlay_fixups_o == -FDT_ERR_NOTFOUND)
return (0);
return (-1);
}
for (fixup_prop_o = fdt_first_property_offset(overlay_fdtp, overlay_fixups_o);
fixup_prop_o >= 0;

2
sys/amd64/amd64/support.S
View File

@ -596,7 +596,7 @@ END(subyte)
* copyinstr(from, to, maxlen, int *lencopied) - MP SAFE
* %rdi, %rsi, %rdx, %rcx
*
* copy a string from from to to, stop when a 0 character is reached.
* copy a string from 'from' to 'to', stop when a 0 character is reached.
* return ENAMETOOLONG if string is longer than maxlen, and
* EFAULT on protection violations. If lencopied is non-zero,
* return the actual length in *lencopied.

2
sys/arm/allwinner/a10/a10_intc.c
View File

@ -1,6 +1,6 @@
/*-
* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.org>
* Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

922
sys/arm/allwinner/a10_mmc.c
View File

@ -1,922 +0,0 @@
/*-
* Copyright (c) 2013 Alexander Fedorov
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <machine/bus.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/mmc/bridge.h>
#include <dev/mmc/mmcbrvar.h>
#include <arm/allwinner/a10_mmc.h>
#include <dev/extres/clk/clk.h>
#include <dev/extres/hwreset/hwreset.h>
#define A10_MMC_MEMRES 0
#define A10_MMC_IRQRES 1
#define A10_MMC_RESSZ 2
#define A10_MMC_DMA_SEGS ((MAXPHYS / PAGE_SIZE) + 1)
#define A10_MMC_DMA_MAX_SIZE 0x2000
#define A10_MMC_DMA_FTRGLEVEL 0x20070008
#define A10_MMC_RESET_RETRY 1000
#define CARD_ID_FREQUENCY 400000
static struct ofw_compat_data compat_data[] = {
{"allwinner,sun4i-a10-mmc", 1},
{"allwinner,sun5i-a13-mmc", 1},
{"allwinner,sun7i-a20-mmc", 1},
{"allwinner,sun50i-a64-mmc", 1},
{NULL, 0}
};
struct a10_mmc_softc {
device_t a10_dev;
clk_t a10_clk_ahb;
clk_t a10_clk_mmc;
hwreset_t a10_rst_ahb;
int a10_bus_busy;
int a10_resid;
int a10_timeout;
struct callout a10_timeoutc;
struct mmc_host a10_host;
struct mmc_request * a10_req;
struct mtx a10_mtx;
struct resource * a10_res[A10_MMC_RESSZ];
uint32_t a10_intr;
uint32_t a10_intr_wait;
void * a10_intrhand;
/* Fields required for DMA access. */
bus_addr_t a10_dma_desc_phys;
bus_dmamap_t a10_dma_map;
bus_dma_tag_t a10_dma_tag;
void * a10_dma_desc;
bus_dmamap_t a10_dma_buf_map;
bus_dma_tag_t a10_dma_buf_tag;
int a10_dma_map_err;
};
static struct resource_spec a10_mmc_res_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
{ -1, 0, 0 }
};
static int a10_mmc_probe(device_t);
static int a10_mmc_attach(device_t);
static int a10_mmc_detach(device_t);
static int a10_mmc_setup_dma(struct a10_mmc_softc *);
static int a10_mmc_reset(struct a10_mmc_softc *);
static void a10_mmc_intr(void *);
static int a10_mmc_update_clock(struct a10_mmc_softc *, uint32_t);
static int a10_mmc_update_ios(device_t, device_t);
static int a10_mmc_request(device_t, device_t, struct mmc_request *);
static int a10_mmc_get_ro(device_t, device_t);
static int a10_mmc_acquire_host(device_t, device_t);
static int a10_mmc_release_host(device_t, device_t);
#define A10_MMC_LOCK(_sc) mtx_lock(&(_sc)->a10_mtx)
#define A10_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->a10_mtx)
#define A10_MMC_READ_4(_sc, _reg) \
bus_read_4((_sc)->a10_res[A10_MMC_MEMRES], _reg)
#define A10_MMC_WRITE_4(_sc, _reg, _value) \
bus_write_4((_sc)->a10_res[A10_MMC_MEMRES], _reg, _value)
static int
a10_mmc_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
return (BUS_PROBE_DEFAULT);
}
static int
a10_mmc_attach(device_t dev)
{
device_t child;
struct a10_mmc_softc *sc;
struct sysctl_ctx_list *ctx;
struct sysctl_oid_list *tree;
uint32_t bus_width;
phandle_t node;
int error;
node = ofw_bus_get_node(dev);
sc = device_get_softc(dev);
sc->a10_dev = dev;
sc->a10_req = NULL;
if (bus_alloc_resources(dev, a10_mmc_res_spec, sc->a10_res) != 0) {
device_printf(dev, "cannot allocate device resources\n");
return (ENXIO);
}
if (bus_setup_intr(dev, sc->a10_res[A10_MMC_IRQRES],
INTR_TYPE_MISC | INTR_MPSAFE, NULL, a10_mmc_intr, sc,
&sc->a10_intrhand)) {
bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res);
device_printf(dev, "cannot setup interrupt handler\n");
return (ENXIO);
}
mtx_init(&sc->a10_mtx, device_get_nameunit(sc->a10_dev), "a10_mmc",
MTX_DEF);
callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0);
/* De-assert reset */
if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->a10_rst_ahb) == 0) {
error = hwreset_deassert(sc->a10_rst_ahb);
if (error != 0) {
device_printf(dev, "cannot de-assert reset\n");
goto fail;
}
}
/* Activate the module clock. */
error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->a10_clk_ahb);
if (error != 0) {
device_printf(dev, "cannot get ahb clock\n");
goto fail;
}
error = clk_enable(sc->a10_clk_ahb);
if (error != 0) {
device_printf(dev, "cannot enable ahb clock\n");
goto fail;
}
error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->a10_clk_mmc);
if (error != 0) {
device_printf(dev, "cannot get mmc clock\n");
goto fail;
}
error = clk_set_freq(sc->a10_clk_mmc, CARD_ID_FREQUENCY,
CLK_SET_ROUND_DOWN);
if (error != 0) {
device_printf(dev, "cannot init mmc clock\n");
goto fail;
}
error = clk_enable(sc->a10_clk_mmc);
if (error != 0) {
device_printf(dev, "cannot enable mmc clock\n");
goto fail;
}
sc->a10_timeout = 10;
ctx = device_get_sysctl_ctx(dev);
tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
&sc->a10_timeout, 0, "Request timeout in seconds");
/* Hardware reset */
A10_MMC_WRITE_4(sc, A10_MMC_HWRST, 1);
DELAY(100);
A10_MMC_WRITE_4(sc, A10_MMC_HWRST, 0);
DELAY(500);
/* Soft Reset controller. */
if (a10_mmc_reset(sc) != 0) {
device_printf(dev, "cannot reset the controller\n");
goto fail;
}
if (a10_mmc_setup_dma(sc) != 0) {
device_printf(sc->a10_dev, "Couldn't setup DMA!\n");
goto fail;
}
if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
bus_width = 4;
sc->a10_host.f_min = 400000;
sc->a10_host.f_max = 52000000;
sc->a10_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
sc->a10_host.mode = mode_sd;
sc->a10_host.caps = MMC_CAP_HSPEED;
if (bus_width >= 4)
sc->a10_host.caps |= MMC_CAP_4_BIT_DATA;
if (bus_width >= 8)
sc->a10_host.caps |= MMC_CAP_8_BIT_DATA;
child = device_add_child(dev, "mmc", -1);
if (child == NULL) {
device_printf(dev, "attaching MMC bus failed!\n");
goto fail;
}
if (device_probe_and_attach(child) != 0) {
device_printf(dev, "attaching MMC child failed!\n");
device_delete_child(dev, child);
goto fail;
}
return (0);
fail:
callout_drain(&sc->a10_timeoutc);
mtx_destroy(&sc->a10_mtx);
bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], sc->a10_intrhand);
bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res);
return (ENXIO);
}
static int
a10_mmc_detach(device_t dev)
{
return (EBUSY);
}
static void
a10_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
{
struct a10_mmc_softc *sc;
sc = (struct a10_mmc_softc *)arg;
if (err) {
sc->a10_dma_map_err = err;
return;
}
sc->a10_dma_desc_phys = segs[0].ds_addr;
}
static int
a10_mmc_setup_dma(struct a10_mmc_softc *sc)
{
int dma_desc_size, error;
/* Allocate the DMA descriptor memory. */
dma_desc_size = sizeof(struct a10_mmc_dma_desc) * A10_MMC_DMA_SEGS;
error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
A10_MMC_DMA_ALIGN, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->a10_dma_tag);
if (error)
return (error);
error = bus_dmamem_alloc(sc->a10_dma_tag, &sc->a10_dma_desc,
BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->a10_dma_map);
if (error)
return (error);
error = bus_dmamap_load(sc->a10_dma_tag, sc->a10_dma_map,
sc->a10_dma_desc, dma_desc_size, a10_dma_desc_cb, sc, 0);
if (error)
return (error);
if (sc->a10_dma_map_err)
return (sc->a10_dma_map_err);
/* Create the DMA map for data transfers. */
error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
A10_MMC_DMA_ALIGN, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS, A10_MMC_DMA_SEGS,
A10_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
&sc->a10_dma_buf_tag);
if (error)
return (error);
error = bus_dmamap_create(sc->a10_dma_buf_tag, 0,
&sc->a10_dma_buf_map);
if (error)
return (error);
return (0);
}
static void
a10_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
{
int i;
struct a10_mmc_dma_desc *dma_desc;
struct a10_mmc_softc *sc;
sc = (struct a10_mmc_softc *)arg;
sc->a10_dma_map_err = err;
if (err)
return;
dma_desc = sc->a10_dma_desc;
for (i = 0; i < nsegs; i++) {
dma_desc[i].buf_size = segs[i].ds_len;
dma_desc[i].buf_addr = segs[i].ds_addr;
dma_desc[i].config = A10_MMC_DMA_CONFIG_CH |
A10_MMC_DMA_CONFIG_OWN;
if (i == 0)
dma_desc[i].config |= A10_MMC_DMA_CONFIG_FD;
if (i < (nsegs - 1)) {
dma_desc[i].config |= A10_MMC_DMA_CONFIG_DIC;
dma_desc[i].next = sc->a10_dma_desc_phys +
((i + 1) * sizeof(struct a10_mmc_dma_desc));
} else {
dma_desc[i].config |= A10_MMC_DMA_CONFIG_LD |
A10_MMC_DMA_CONFIG_ER;
dma_desc[i].next = 0;
}
}
}
static int
a10_mmc_prepare_dma(struct a10_mmc_softc *sc)
{
bus_dmasync_op_t sync_op;
int error;
struct mmc_command *cmd;
uint32_t val;
cmd = sc->a10_req->cmd;
if (cmd->data->len > A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS)
return (EFBIG);
error = bus_dmamap_load(sc->a10_dma_buf_tag, sc->a10_dma_buf_map,
cmd->data->data, cmd->data->len, a10_dma_cb, sc, 0);
if (error)
return (error);
if (sc->a10_dma_map_err)
return (sc->a10_dma_map_err);
if (cmd->data->flags & MMC_DATA_WRITE)
sync_op = BUS_DMASYNC_PREWRITE;
else
sync_op = BUS_DMASYNC_PREREAD;
bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, sync_op);
bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE);
/* Enable DMA */
val = A10_MMC_READ_4(sc, A10_MMC_GCTL);
val &= ~A10_MMC_CTRL_FIFO_AC_MOD;
val |= A10_MMC_CTRL_DMA_ENB;
A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val);
/* Reset DMA */
val |= A10_MMC_CTRL_DMA_RST;
A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val);
A10_MMC_WRITE_4(sc, A10_MMC_DMAC, A10_MMC_DMAC_IDMAC_SOFT_RST);
A10_MMC_WRITE_4(sc, A10_MMC_DMAC,
A10_MMC_DMAC_IDMAC_IDMA_ON | A10_MMC_DMAC_IDMAC_FIX_BURST);
/* Enable RX or TX DMA interrupt */
if (cmd->data->flags & MMC_DATA_WRITE)
val |= A10_MMC_IDST_TX_INT;
else
val |= A10_MMC_IDST_RX_INT;
A10_MMC_WRITE_4(sc, A10_MMC_IDIE, val);
/* Set DMA descritptor list address */
A10_MMC_WRITE_4(sc, A10_MMC_DLBA, sc->a10_dma_desc_phys);
/* FIFO trigger level */
A10_MMC_WRITE_4(sc, A10_MMC_FWLR, A10_MMC_DMA_FTRGLEVEL);
return (0);
}
static int
a10_mmc_reset(struct a10_mmc_softc *sc)
{
int timeout;
A10_MMC_WRITE_4(sc, A10_MMC_GCTL, A10_MMC_RESET);
timeout = 1000;
while (--timeout > 0) {
if ((A10_MMC_READ_4(sc, A10_MMC_GCTL) & A10_MMC_RESET) == 0)
break;
DELAY(100);
}
if (timeout == 0)
return (ETIMEDOUT);
/* Set the timeout. */
A10_MMC_WRITE_4(sc, A10_MMC_TMOR,
A10_MMC_TMOR_DTO_LMT_SHIFT(A10_MMC_TMOR_DTO_LMT_MASK) |
A10_MMC_TMOR_RTO_LMT_SHIFT(A10_MMC_TMOR_RTO_LMT_MASK));
/* Clear pending interrupts. */
A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff);
A10_MMC_WRITE_4(sc, A10_MMC_IDST, 0xffffffff);
/* Unmask interrupts. */
A10_MMC_WRITE_4(sc, A10_MMC_IMKR,
A10_MMC_INT_CMD_DONE | A10_MMC_INT_ERR_BIT |
A10_MMC_INT_DATA_OVER | A10_MMC_INT_AUTO_STOP_DONE);
/* Enable interrupts and AHB access. */
A10_MMC_WRITE_4(sc, A10_MMC_GCTL,
A10_MMC_READ_4(sc, A10_MMC_GCTL) | A10_MMC_CTRL_INT_ENB);
return (0);
}
static void
a10_mmc_req_done(struct a10_mmc_softc *sc)
{
struct mmc_command *cmd;
struct mmc_request *req;
uint32_t val, mask;
int retry;
cmd = sc->a10_req->cmd;
if (cmd->error != MMC_ERR_NONE) {
/* Reset the FIFO and DMA engines. */
mask = A10_MMC_CTRL_FIFO_RST | A10_MMC_CTRL_DMA_RST;
val = A10_MMC_READ_4(sc, A10_MMC_GCTL);
A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val | mask);
retry = A10_MMC_RESET_RETRY;
while (--retry > 0) {
val = A10_MMC_READ_4(sc, A10_MMC_GCTL);
if ((val & mask) == 0)
break;
DELAY(10);
}
if (retry == 0)
device_printf(sc->a10_dev,
"timeout resetting DMA/FIFO\n");
a10_mmc_update_clock(sc, 1);
}
req = sc->a10_req;
callout_stop(&sc->a10_timeoutc);
sc->a10_req = NULL;
sc->a10_intr = 0;
sc->a10_resid = 0;
sc->a10_dma_map_err = 0;
sc->a10_intr_wait = 0;
req->done(req);
}
static void
a10_mmc_req_ok(struct a10_mmc_softc *sc)
{
int timeout;
struct mmc_command *cmd;
uint32_t status;
timeout = 1000;
while (--timeout > 0) {
status = A10_MMC_READ_4(sc, A10_MMC_STAR);
if ((status & A10_MMC_STAR_CARD_BUSY) == 0)
break;
DELAY(1000);
}
cmd = sc->a10_req->cmd;
if (timeout == 0) {
cmd->error = MMC_ERR_FAILED;
a10_mmc_req_done(sc);
return;
}
if (cmd->flags & MMC_RSP_PRESENT) {
if (cmd->flags & MMC_RSP_136) {
cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP3);
cmd->resp[1] = A10_MMC_READ_4(sc, A10_MMC_RESP2);
cmd->resp[2] = A10_MMC_READ_4(sc, A10_MMC_RESP1);
cmd->resp[3] = A10_MMC_READ_4(sc, A10_MMC_RESP0);
} else
cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP0);
}
/* All data has been transferred ? */
if (cmd->data != NULL && (sc->a10_resid << 2) < cmd->data->len)
cmd->error = MMC_ERR_FAILED;
a10_mmc_req_done(sc);
}
static void
a10_mmc_timeout(void *arg)
{
struct a10_mmc_softc *sc;
sc = (struct a10_mmc_softc *)arg;
if (sc->a10_req != NULL) {
device_printf(sc->a10_dev, "controller timeout\n");
sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
a10_mmc_req_done(sc);
} else
device_printf(sc->a10_dev,
"Spurious timeout - no active request\n");
}
static void
a10_mmc_intr(void *arg)
{
bus_dmasync_op_t sync_op;
struct a10_mmc_softc *sc;
struct mmc_data *data;
uint32_t idst, imask, rint;
sc = (struct a10_mmc_softc *)arg;
A10_MMC_LOCK(sc);
rint = A10_MMC_READ_4(sc, A10_MMC_RISR);
idst = A10_MMC_READ_4(sc, A10_MMC_IDST);
imask = A10_MMC_READ_4(sc, A10_MMC_IMKR);
if (idst == 0 && imask == 0 && rint == 0) {
A10_MMC_UNLOCK(sc);
return;
}
#ifdef DEBUG
device_printf(sc->a10_dev, "idst: %#x, imask: %#x, rint: %#x\n",
idst, imask, rint);
#endif
if (sc->a10_req == NULL) {
device_printf(sc->a10_dev,
"Spurious interrupt - no active request, rint: 0x%08X\n",
rint);
goto end;
}
if (rint & A10_MMC_INT_ERR_BIT) {
device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint);
if (rint & A10_MMC_INT_RESP_TIMEOUT)
sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
else
sc->a10_req->cmd->error = MMC_ERR_FAILED;
a10_mmc_req_done(sc);
goto end;
}
if (idst & A10_MMC_IDST_ERROR) {
device_printf(sc->a10_dev, "error idst: 0x%08x\n", idst);
sc->a10_req->cmd->error = MMC_ERR_FAILED;
a10_mmc_req_done(sc);
goto end;
}
sc->a10_intr |= rint;
data = sc->a10_req->cmd->data;
if (data != NULL && (idst & A10_MMC_IDST_COMPLETE) != 0) {
if (data->flags & MMC_DATA_WRITE)
sync_op = BUS_DMASYNC_POSTWRITE;
else
sync_op = BUS_DMASYNC_POSTREAD;
bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map,
sync_op);
bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->a10_dma_buf_tag, sc->a10_dma_buf_map);
sc->a10_resid = data->len >> 2;
}
if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)
a10_mmc_req_ok(sc);
end:
A10_MMC_WRITE_4(sc, A10_MMC_IDST, idst);
A10_MMC_WRITE_4(sc, A10_MMC_RISR, rint);
A10_MMC_UNLOCK(sc);
}
static int
a10_mmc_request(device_t bus, device_t child, struct mmc_request *req)
{
int blksz;
struct a10_mmc_softc *sc;
struct mmc_command *cmd;
uint32_t cmdreg;
int err;
sc = device_get_softc(bus);
A10_MMC_LOCK(sc);
if (sc->a10_req) {
A10_MMC_UNLOCK(sc);
return (EBUSY);
}
sc->a10_req = req;
cmd = req->cmd;
cmdreg = A10_MMC_CMDR_LOAD;
if (cmd->opcode == MMC_GO_IDLE_STATE)
cmdreg |= A10_MMC_CMDR_SEND_INIT_SEQ;
if (cmd->flags & MMC_RSP_PRESENT)
cmdreg |= A10_MMC_CMDR_RESP_RCV;
if (cmd->flags & MMC_RSP_136)
cmdreg |= A10_MMC_CMDR_LONG_RESP;
if (cmd->flags & MMC_RSP_CRC)
cmdreg |= A10_MMC_CMDR_CHK_RESP_CRC;
sc->a10_intr = 0;
sc->a10_resid = 0;
sc->a10_intr_wait = A10_MMC_INT_CMD_DONE;
cmd->error = MMC_ERR_NONE;
if (cmd->data != NULL) {
sc->a10_intr_wait |= A10_MMC_INT_DATA_OVER;
cmdreg |= A10_MMC_CMDR_DATA_TRANS | A10_MMC_CMDR_WAIT_PRE_OVER;
if (cmd->data->flags & MMC_DATA_MULTI) {
cmdreg |= A10_MMC_CMDR_STOP_CMD_FLAG;
sc->a10_intr_wait |= A10_MMC_INT_AUTO_STOP_DONE;
}
if (cmd->data->flags & MMC_DATA_WRITE)
cmdreg |= A10_MMC_CMDR_DIR_WRITE;
blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
A10_MMC_WRITE_4(sc, A10_MMC_BKSR, blksz);
A10_MMC_WRITE_4(sc, A10_MMC_BYCR, cmd->data->len);
err = a10_mmc_prepare_dma(sc);
if (err != 0)
device_printf(sc->a10_dev, "prepare_dma failed: %d\n", err);
}
A10_MMC_WRITE_4(sc, A10_MMC_CAGR, cmd->arg);
A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg | cmd->opcode);
callout_reset(&sc->a10_timeoutc, sc->a10_timeout * hz,
a10_mmc_timeout, sc);
A10_MMC_UNLOCK(sc);
return (0);
}
static int
a10_mmc_read_ivar(device_t bus, device_t child, int which,
uintptr_t *result)
{
struct a10_mmc_softc *sc;
sc = device_get_softc(bus);
switch (which) {
default:
return (EINVAL);
case MMCBR_IVAR_BUS_MODE:
*(int *)result = sc->a10_host.ios.bus_mode;
break;
case MMCBR_IVAR_BUS_WIDTH:
*(int *)result = sc->a10_host.ios.bus_width;
break;
case MMCBR_IVAR_CHIP_SELECT:
*(int *)result = sc->a10_host.ios.chip_select;
break;
case MMCBR_IVAR_CLOCK:
*(int *)result = sc->a10_host.ios.clock;
break;
case MMCBR_IVAR_F_MIN:
*(int *)result = sc->a10_host.f_min;
break;
case MMCBR_IVAR_F_MAX:
*(int *)result = sc->a10_host.f_max;
break;
case MMCBR_IVAR_HOST_OCR:
*(int *)result = sc->a10_host.host_ocr;
break;
case MMCBR_IVAR_MODE:
*(int *)result = sc->a10_host.mode;
break;
case MMCBR_IVAR_OCR:
*(int *)result = sc->a10_host.ocr;
break;
case MMCBR_IVAR_POWER_MODE:
*(int *)result = sc->a10_host.ios.power_mode;
break;
case MMCBR_IVAR_VDD:
*(int *)result = sc->a10_host.ios.vdd;
break;
case MMCBR_IVAR_CAPS:
*(int *)result = sc->a10_host.caps;
break;
case MMCBR_IVAR_MAX_DATA:
*(int *)result = 65535;
break;
}
return (0);
}
static int
a10_mmc_write_ivar(device_t bus, device_t child, int which,
uintptr_t value)
{
struct a10_mmc_softc *sc;
sc = device_get_softc(bus);
switch (which) {
default:
return (EINVAL);
case MMCBR_IVAR_BUS_MODE:
sc->a10_host.ios.bus_mode = value;
break;
case MMCBR_IVAR_BUS_WIDTH:
sc->a10_host.ios.bus_width = value;
break;
case MMCBR_IVAR_CHIP_SELECT:
sc->a10_host.ios.chip_select = value;
break;
case MMCBR_IVAR_CLOCK:
sc->a10_host.ios.clock = value;
break;
case MMCBR_IVAR_MODE:
sc->a10_host.mode = value;
break;
case MMCBR_IVAR_OCR:
sc->a10_host.ocr = value;
break;
case MMCBR_IVAR_POWER_MODE:
sc->a10_host.ios.power_mode = value;
break;
case MMCBR_IVAR_VDD:
sc->a10_host.ios.vdd = value;
break;
/* These are read-only */
case MMCBR_IVAR_CAPS:
case MMCBR_IVAR_HOST_OCR:
case MMCBR_IVAR_F_MIN:
case MMCBR_IVAR_F_MAX:
case MMCBR_IVAR_MAX_DATA:
return (EINVAL);
}
return (0);
}
static int
a10_mmc_update_clock(struct a10_mmc_softc *sc, uint32_t clkon)
{
uint32_t cmdreg;
int retry;
uint32_t ckcr;
ckcr = A10_MMC_READ_4(sc, A10_MMC_CKCR);
ckcr &= ~(A10_MMC_CKCR_CCLK_ENB | A10_MMC_CKCR_CCLK_CTRL);
if (clkon)
ckcr |= A10_MMC_CKCR_CCLK_ENB;
A10_MMC_WRITE_4(sc, A10_MMC_CKCR, ckcr);
cmdreg = A10_MMC_CMDR_LOAD | A10_MMC_CMDR_PRG_CLK |
A10_MMC_CMDR_WAIT_PRE_OVER;
A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg);
retry = 0xfffff;
while (--retry > 0) {
if ((A10_MMC_READ_4(sc, A10_MMC_CMDR) & A10_MMC_CMDR_LOAD) == 0) {
A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff);
return (0);
}
DELAY(10);
}
A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff);
device_printf(sc->a10_dev, "timeout updating clock\n");
return (ETIMEDOUT);
}
static int
a10_mmc_update_ios(device_t bus, device_t child)
{
int error;
struct a10_mmc_softc *sc;
struct mmc_ios *ios;
uint32_t ckcr;
sc = device_get_softc(bus);
ios = &sc->a10_host.ios;
/* Set the bus width. */
switch (ios->bus_width) {
case bus_width_1:
A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR1);
break;
case bus_width_4:
A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR4);
break;
case bus_width_8:
A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR8);
break;
}
if (ios->clock) {
/* Disable clock */
error = a10_mmc_update_clock(sc, 0);
if (error != 0)
return (error);
/* Reset the divider. */
ckcr = A10_MMC_READ_4(sc, A10_MMC_CKCR);
ckcr &= ~A10_MMC_CKCR_CCLK_DIV;
A10_MMC_WRITE_4(sc, A10_MMC_CKCR, ckcr);
/* Set the MMC clock. */
error = clk_set_freq(sc->a10_clk_mmc, ios->clock,
CLK_SET_ROUND_DOWN);
if (error != 0) {
device_printf(sc->a10_dev,
"failed to set frequency to %u Hz: %d\n",
ios->clock, error);
return (error);
}
/* Enable clock. */
error = a10_mmc_update_clock(sc, 1);
if (error != 0)
return (error);
}
return (0);
}
static int
a10_mmc_get_ro(device_t bus, device_t child)
{
return (0);
}
static int
a10_mmc_acquire_host(device_t bus, device_t child)
{
struct a10_mmc_softc *sc;
int error;
sc = device_get_softc(bus);
A10_MMC_LOCK(sc);
while (sc->a10_bus_busy) {
error = msleep(sc, &sc->a10_mtx, PCATCH, "mmchw", 0);
if (error != 0) {
A10_MMC_UNLOCK(sc);
return (error);
}
}
sc->a10_bus_busy++;
A10_MMC_UNLOCK(sc);
return (0);
}
static int
a10_mmc_release_host(device_t bus, device_t child)
{
struct a10_mmc_softc *sc;
sc = device_get_softc(bus);
A10_MMC_LOCK(sc);
sc->a10_bus_busy--;
wakeup(sc);
A10_MMC_UNLOCK(sc);
return (0);
}
static device_method_t a10_mmc_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, a10_mmc_probe),
DEVMETHOD(device_attach, a10_mmc_attach),
DEVMETHOD(device_detach, a10_mmc_detach),
/* Bus interface */
DEVMETHOD(bus_read_ivar, a10_mmc_read_ivar),
DEVMETHOD(bus_write_ivar, a10_mmc_write_ivar),
/* MMC bridge interface */
DEVMETHOD(mmcbr_update_ios, a10_mmc_update_ios),
DEVMETHOD(mmcbr_request, a10_mmc_request),
DEVMETHOD(mmcbr_get_ro, a10_mmc_get_ro),
DEVMETHOD(mmcbr_acquire_host, a10_mmc_acquire_host),
DEVMETHOD(mmcbr_release_host, a10_mmc_release_host),
DEVMETHOD_END
};
static devclass_t a10_mmc_devclass;
static driver_t a10_mmc_driver = {
"a10_mmc",
a10_mmc_methods,
sizeof(struct a10_mmc_softc),
};
DRIVER_MODULE(a10_mmc, simplebus, a10_mmc_driver, a10_mmc_devclass, NULL,
NULL);
MMC_DECLARE_BRIDGE(a10_mmc);

204
sys/arm/allwinner/a10_mmc.h
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@ -1,204 +0,0 @@
/*-
* Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _A10_MMC_H_
#define _A10_MMC_H_
#define A10_MMC_GCTL 0x00 /* Control Register */
#define A10_MMC_CKCR 0x04 /* Clock Control Register */
#define A10_MMC_TMOR 0x08 /* Timeout Register */
#define A10_MMC_BWDR 0x0C /* Bus Width Register */
#define A10_MMC_BKSR 0x10 /* Block Size Register */
#define A10_MMC_BYCR 0x14 /* Byte Count Register */
#define A10_MMC_CMDR 0x18 /* Command Register */
#define A10_MMC_CAGR 0x1C /* Argument Register */
#define A10_MMC_RESP0 0x20 /* Response Register 0 */
#define A10_MMC_RESP1 0x24 /* Response Register 1 */
#define A10_MMC_RESP2 0x28 /* Response Register 2 */
#define A10_MMC_RESP3 0x2C /* Response Register 3 */
#define A10_MMC_IMKR 0x30 /* Interrupt Mask Register */
#define A10_MMC_MISR 0x34 /* Masked Interrupt Status Register */
#define A10_MMC_RISR 0x38 /* Raw Interrupt Status Register */
#define A10_MMC_STAR 0x3C /* Status Register */
#define A10_MMC_FWLR 0x40 /* FIFO Threshold Watermark Register */
#define A10_MMC_FUNS 0x44 /* Function Select Register */
#define A10_MMC_HWRST 0x78 /* Hardware reset (not documented) */
#define A10_MMC_DMAC 0x80 /* IDMAC Control Register */
#define A10_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */
#define A10_MMC_IDST 0x88 /* IDMAC Status Register */
#define A10_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */
#define A10_MMC_FIFO 0x100 /* FIFO Access Address (A10/A20) */
#define A31_MMC_FIFO 0x200 /* FIFO Access Address (A31) */
/* A10_MMC_GCTL */
#define A10_MMC_CTRL_SOFT_RST (1U << 0)
#define A10_MMC_CTRL_FIFO_RST (1U << 1)
#define A10_MMC_CTRL_DMA_RST (1U << 2)
#define A10_MMC_CTRL_INT_ENB (1U << 4)
#define A10_MMC_CTRL_DMA_ENB (1U << 5)
#define A10_MMC_CTRL_CD_DBC_ENB (1U << 8)
#define A10_MMC_CTRL_DDR_MOD_SEL (1U << 10)
#define A10_MMC_CTRL_FIFO_AC_MOD (1U << 31)
#define A10_MMC_RESET \
(A10_MMC_CTRL_SOFT_RST | A10_MMC_CTRL_FIFO_RST | A10_MMC_CTRL_DMA_RST)
/* A10_MMC_CKCR */
#define A10_MMC_CKCR_CCLK_ENB (1U << 16)
#define A10_MMC_CKCR_CCLK_CTRL (1U << 17)
#define A10_MMC_CKCR_CCLK_DIV 0xff
/* A10_MMC_TMOR */
#define A10_MMC_TMOR_RTO_LMT_SHIFT(x) x /* Response timeout limit */
#define A10_MMC_TMOR_RTO_LMT_MASK 0xff
#define A10_MMC_TMOR_DTO_LMT_SHIFT(x) (x << 8) /* Data timeout limit */
#define A10_MMC_TMOR_DTO_LMT_MASK 0xffffff
/* A10_MMC_BWDR */
#define A10_MMC_BWDR1 0
#define A10_MMC_BWDR4 1
#define A10_MMC_BWDR8 2
/* A10_MMC_CMDR */
#define A10_MMC_CMDR_RESP_RCV (1U << 6)
#define A10_MMC_CMDR_LONG_RESP (1U << 7)
#define A10_MMC_CMDR_CHK_RESP_CRC (1U << 8)
#define A10_MMC_CMDR_DATA_TRANS (1U << 9)
#define A10_MMC_CMDR_DIR_WRITE (1U << 10)
#define A10_MMC_CMDR_TRANS_MODE_STREAM (1U << 11)
#define A10_MMC_CMDR_STOP_CMD_FLAG (1U << 12)
#define A10_MMC_CMDR_WAIT_PRE_OVER (1U << 13)
#define A10_MMC_CMDR_STOP_ABT_CMD (1U << 14)
#define A10_MMC_CMDR_SEND_INIT_SEQ (1U << 15)
#define A10_MMC_CMDR_PRG_CLK (1U << 21)
#define A10_MMC_CMDR_RD_CEDATA_DEV (1U << 22)
#define A10_MMC_CMDR_CCS_EXP (1U << 23)
#define A10_MMC_CMDR_BOOT_MOD_SHIFT 24
#define A10_MMC_CMDR_BOOT_MOD_NORMAL 0
#define A10_MMC_CMDR_BOOT_MOD_MANDATORY 1
#define A10_MMC_CMDR_BOOT_MOD_ALT 2
#define A10_MMC_CMDR_EXP_BOOT_ACK (1U << 26)
#define A10_MMC_CMDR_BOOT_ABT (1U << 27)
#define A10_MMC_CMDR_VOL_SW (1U << 28)
#define A10_MMC_CMDR_LOAD (1U << 31)
/* A10_MMC_IMKR and A10_MMC_RISR */
#define A10_MMC_INT_RESP_ERR (1U << 1)
#define A10_MMC_INT_CMD_DONE (1U << 2)
#define A10_MMC_INT_DATA_OVER (1U << 3)
#define A10_MMC_INT_TX_DATA_REQ (1U << 4)
#define A10_MMC_INT_RX_DATA_REQ (1U << 5)
#define A10_MMC_INT_RESP_CRC_ERR (1U << 6)
#define A10_MMC_INT_DATA_CRC_ERR (1U << 7)
#define A10_MMC_INT_RESP_TIMEOUT (1U << 8)
#define A10_MMC_INT_BOOT_ACK_RECV (1U << 8)
#define A10_MMC_INT_DATA_TIMEOUT (1U << 9)
#define A10_MMC_INT_BOOT_START (1U << 9)
#define A10_MMC_INT_DATA_STARVE (1U << 10)
#define A10_MMC_INT_VOL_CHG_DONE (1U << 10)
#define A10_MMC_INT_FIFO_RUN_ERR (1U << 11)
#define A10_MMC_INT_CMD_BUSY (1U << 12)
#define A10_MMC_INT_DATA_START_ERR (1U << 13)
#define A10_MMC_INT_AUTO_STOP_DONE (1U << 14)
#define A10_MMC_INT_DATA_END_BIT_ERR (1U << 15)
#define A10_MMC_INT_SDIO (1U << 16)
#define A10_MMC_INT_CARD_INSERT (1U << 30)
#define A10_MMC_INT_CARD_REMOVE (1U << 31)
#define A10_MMC_INT_ERR_BIT \
(A10_MMC_INT_RESP_ERR | A10_MMC_INT_RESP_CRC_ERR | \
A10_MMC_INT_DATA_CRC_ERR | A10_MMC_INT_RESP_TIMEOUT | \
A10_MMC_INT_FIFO_RUN_ERR | A10_MMC_INT_CMD_BUSY | \
A10_MMC_INT_DATA_START_ERR | A10_MMC_INT_DATA_END_BIT_ERR)
/* A10_MMC_STAR */
#define A10_MMC_STAR_FIFO_RX_LEVEL (1U << 0)
#define A10_MMC_STAR_FIFO_TX_LEVEL (1U << 1)
#define A10_MMC_STAR_FIFO_EMPTY (1U << 2)
#define A10_MMC_STAR_FIFO_FULL (1U << 3)
#define A10_MMC_STAR_CARD_PRESENT (1U << 8)
#define A10_MMC_STAR_CARD_BUSY (1U << 9)
#define A10_MMC_STAR_FSM_BUSY (1U << 10)
#define A10_MMC_STAR_DMA_REQ (1U << 31)
/* A10_MMC_FUNS */
#define A10_MMC_CE_ATA_ON (0xceaaU << 16)
#define A10_MMC_SEND_IRQ_RESP (1U << 0)
#define A10_MMC_SDIO_RD_WAIT (1U << 1)
#define A10_MMC_ABT_RD_DATA (1U << 2)
#define A10_MMC_SEND_CC_SD (1U << 8)
#define A10_MMC_SEND_AUTOSTOP_CC_SD (1U << 9)
#define A10_MMC_CE_ATA_DEV_INT_ENB (1U << 10)
/* IDMA CONTROLLER BUS MOD BIT FIELD */
#define A10_MMC_DMAC_IDMAC_SOFT_RST (1U << 0)
#define A10_MMC_DMAC_IDMAC_FIX_BURST (1U << 1)
#define A10_MMC_DMAC_IDMAC_IDMA_ON (1U << 7)
#define A10_MMC_DMAC_IDMAC_REFETCH_DES (1U << 31)
/* A10_MMC_IDST */
#define A10_MMC_IDST_TX_INT (1U << 0)
#define A10_MMC_IDST_RX_INT (1U << 1)
#define A10_MMC_IDST_FATAL_BERR_INT (1U << 2)
#define A10_MMC_IDST_DES_UNAVL_INT (1U << 4)
#define A10_MMC_IDST_ERR_FLAG_SUM (1U << 5)
#define A10_MMC_IDST_NOR_INT_SUM (1U << 8)
#define A10_MMC_IDST_ABN_INT_SUM (1U << 9)
#define A10_MMC_IDST_HOST_ABT_INTX (1U << 10)
#define A10_MMC_IDST_HOST_ABT_INRX (1U << 10)
#define A10_MMC_IDST_IDLE (0U << 13)
#define A10_MMC_IDST_SUSPEND (1U << 13)
#define A10_MMC_IDST_DESC_RD (2U << 13)
#define A10_MMC_IDST_DESC_CHECK (3U << 13)
#define A10_MMC_IDST_RD_REQ_WAIT (4U << 13)
#define A10_MMC_IDST_WR_REQ_WAIT (5U << 13)
#define A10_MMC_IDST_RD (6U << 13)
#define A10_MMC_IDST_WR (7U << 13)
#define A10_MMC_IDST_DESC_CLOSE (8U << 13)
#define A10_MMC_IDST_ERROR \
(A10_MMC_IDST_FATAL_BERR_INT | A10_MMC_IDST_ERR_FLAG_SUM | \
A10_MMC_IDST_DES_UNAVL_INT | A10_MMC_IDST_ABN_INT_SUM)
#define A10_MMC_IDST_COMPLETE \
(A10_MMC_IDST_TX_INT | A10_MMC_IDST_RX_INT)
/* The DMA descriptor table. */
struct a10_mmc_dma_desc {
uint32_t config;
#define A10_MMC_DMA_CONFIG_DIC (1U << 1) /* Disable Interrupt Completion */
#define A10_MMC_DMA_CONFIG_LD (1U << 2) /* Last DES */
#define A10_MMC_DMA_CONFIG_FD (1U << 3) /* First DES */
#define A10_MMC_DMA_CONFIG_CH (1U << 4) /* CHAIN MOD */
#define A10_MMC_DMA_CONFIG_ER (1U << 5) /* End of Ring (undocumented register) */
#define A10_MMC_DMA_CONFIG_CES (1U << 30) /* Card Error Summary */
#define A10_MMC_DMA_CONFIG_OWN (1U << 31) /* DES Own Flag */
uint32_t buf_size;
uint32_t buf_addr;
uint32_t next;
};
#define A10_MMC_DMA_ALIGN 4
#endif /* _A10_MMC_H_ */

2
sys/arm/allwinner/allwinner_pinctrl.h
View File

@ -1,5 +1,5 @@
/*-
* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com>
* Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

142
sys/arm/allwinner/aw_console.c
View File

@ -1,142 +0,0 @@
/*-
* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* Simple UART console driver for Allwinner A10 */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/cons.h>
#include <sys/consio.h>
#include <sys/kernel.h>
#ifndef A10_UART_BASE
#define A10_UART_BASE 0xe1c28000 /* UART0 */
#endif
#define REG_SHIFT 2
#define UART_DLL 0 /* Out: Divisor Latch Low */
#define UART_DLM 1 /* Out: Divisor Latch High */
#define UART_FCR 2 /* Out: FIFO Control Register */
#define UART_LCR 3 /* Out: Line Control Register */
#define UART_MCR 4 /* Out: Modem Control Register */
#define UART_LSR 5 /* In: Line Status Register */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_DR 0x01 /* Receiver data ready */
#define UART_MSR 6 /* In: Modem Status Register */
#define UART_SCR 7 /* I/O: Scratch Register */
static uint32_t
uart_getreg(uint32_t *bas)
{
return *((volatile uint32_t *)(bas)) & 0xff;
}
static void
uart_setreg(uint32_t *bas, uint32_t val)
{
*((volatile uint32_t *)(bas)) = val;
}
static int
ub_getc(void)
{
while ((uart_getreg((uint32_t *)(A10_UART_BASE +
(UART_LSR << REG_SHIFT))) & UART_LSR_DR) == 0);
__asm __volatile("nop");
return (uart_getreg((uint32_t *)A10_UART_BASE) & 0xff);
}
static void
ub_putc(unsigned char c)
{
if (c == '\n')
ub_putc('\r');
while ((uart_getreg((uint32_t *)(A10_UART_BASE +
(UART_LSR << REG_SHIFT))) & UART_LSR_THRE) == 0)
__asm __volatile("nop");
uart_setreg((uint32_t *)A10_UART_BASE, c);
}
static cn_probe_t uart_cnprobe;
static cn_init_t uart_cninit;
static cn_term_t uart_cnterm;
static cn_getc_t uart_cngetc;
static cn_putc_t uart_cnputc;
static cn_grab_t uart_cngrab;
static cn_ungrab_t uart_cnungrab;
static void
uart_cngrab(struct consdev *cp)
{
}
static void
uart_cnungrab(struct consdev *cp)
{
}
static void
uart_cnprobe(struct consdev *cp)
{
sprintf(cp->cn_name, "uart");
cp->cn_pri = CN_NORMAL;
}
static void
uart_cninit(struct consdev *cp)
{
uart_setreg((uint32_t *)(A10_UART_BASE +
(UART_FCR << REG_SHIFT)), 0x06);
}
void
uart_cnputc(struct consdev *cp, int c)
{
ub_putc(c);
}
int
uart_cngetc(struct consdev * cp)
{
return ub_getc();
}
static void
uart_cnterm(struct consdev * cp)
{
}
CONSOLE_DRIVER(uart);

352
sys/arm/allwinner/a10_gpio.c → sys/arm/allwinner/aw_gpio.c
View File

@ -62,15 +62,15 @@ __FBSDID("$FreeBSD$");
#include "gpio_if.h"
#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
#define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
#define A10_GPIO_NONE 0
#define A10_GPIO_PULLUP 1
#define A10_GPIO_PULLDOWN 2
#define AW_GPIO_NONE 0
#define AW_GPIO_PULLUP 1
#define AW_GPIO_PULLDOWN 2
#define A10_GPIO_INPUT 0
#define A10_GPIO_OUTPUT 1
#define AW_GPIO_INPUT 0
#define AW_GPIO_OUTPUT 1
#define AW_GPIO_DRV_MASK 0x3
#define AW_GPIO_PUD_MASK 0x3
@ -78,7 +78,7 @@ __FBSDID("$FreeBSD$");
#define AW_PINCTRL 1
#define AW_R_PINCTRL 2
/* Defined in a10_padconf.c */
/* Defined in aw_padconf.c */
#ifdef SOC_ALLWINNER_A10
extern const struct allwinner_padconf a10_padconf;
#endif
@ -173,7 +173,7 @@ struct clk_list {
clk_t clk;
};
struct a10_gpio_softc {
struct aw_gpio_softc {
device_t sc_dev;
device_t sc_busdev;
struct mtx sc_mtx;
@ -186,46 +186,46 @@ struct a10_gpio_softc {
TAILQ_HEAD(, clk_list) clk_list;
};
#define A10_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
#define A10_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
#define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
#define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
#define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
#define A10_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
#define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
#define A10_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
#define A10_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
#define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
#define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
#define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
#define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
#define A10_GPIO_GP_INT_CFG0 0x200
#define A10_GPIO_GP_INT_CFG1 0x204
#define A10_GPIO_GP_INT_CFG2 0x208
#define A10_GPIO_GP_INT_CFG3 0x20c
#define AW_GPIO_GP_INT_CFG0 0x200
#define AW_GPIO_GP_INT_CFG1 0x204
#define AW_GPIO_GP_INT_CFG2 0x208
#define AW_GPIO_GP_INT_CFG3 0x20c
#define A10_GPIO_GP_INT_CTL 0x210
#define A10_GPIO_GP_INT_STA 0x214
#define A10_GPIO_GP_INT_DEB 0x218
#define AW_GPIO_GP_INT_CTL 0x210
#define AW_GPIO_GP_INT_STA 0x214
#define AW_GPIO_GP_INT_DEB 0x218
static char *a10_gpio_parse_function(phandle_t node);
static const char **a10_gpio_parse_pins(phandle_t node, int *pins_nb);
static uint32_t a10_gpio_parse_bias(phandle_t node);
static int a10_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
static char *aw_gpio_parse_function(phandle_t node);
static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb);
static uint32_t aw_gpio_parse_bias(phandle_t node);
static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
static int a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
static int a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
static int a10_gpio_pin_get_locked(struct a10_gpio_softc *sc, uint32_t pin, unsigned int *value);
static int a10_gpio_pin_set_locked(struct a10_gpio_softc *sc, uint32_t pin, unsigned int value);
static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value);
static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value);
#define A10_GPIO_WRITE(_sc, _off, _val) \
#define AW_GPIO_WRITE(_sc, _off, _val) \
bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
#define A10_GPIO_READ(_sc, _off) \
#define AW_GPIO_READ(_sc, _off) \
bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
static uint32_t
a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin)
{
uint32_t bank, func, offset;
/* Must be called with lock held. */
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
if (pin > sc->padconf->npins)
return (0);
@ -233,13 +233,13 @@ a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
pin = sc->padconf->pins[pin].pin;
offset = ((pin & 0x07) << 2);
func = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
return ((func >> offset) & 0x7);
}
static int
a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f)
{
uint32_t bank, data, offset;
@ -248,127 +248,127 @@ a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
return (EINVAL);
/* Must be called with lock held. */
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
offset = ((pin & 0x07) << 2);
data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3));
data &= ~(7 << offset);
data |= (f << offset);
A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, pin >> 3), data);
AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data);
return (0);
}
static uint32_t
a10_gpio_get_pud(struct a10_gpio_softc *sc, uint32_t pin)
aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin)
{
uint32_t bank, offset, val;
/* Must be called with lock held. */
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
offset = ((pin & 0x0f) << 1);
val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
return ((val >> offset) & AW_GPIO_PUD_MASK);
}
static void
a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state)
{
uint32_t bank, offset, val;
if (a10_gpio_get_pud(sc, pin) == state)
if (aw_gpio_get_pud(sc, pin) == state)
return;
/* Must be called with lock held. */
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
offset = ((pin & 0x0f) << 1);
val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4));
val &= ~(AW_GPIO_PUD_MASK << offset);
val |= (state << offset);
A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pin >> 4), val);
AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val);
}
static uint32_t
a10_gpio_get_drv(struct a10_gpio_softc *sc, uint32_t pin)
aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin)
{
uint32_t bank, offset, val;
/* Must be called with lock held. */
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
offset = ((pin & 0x0f) << 1);
val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4));
val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
return ((val >> offset) & AW_GPIO_DRV_MASK);
}
static void
a10_gpio_set_drv(struct a10_gpio_softc *sc, uint32_t pin, uint32_t drive)
aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive)
{
uint32_t bank, offset, val;
if (a10_gpio_get_drv(sc, pin) == drive)
if (aw_gpio_get_drv(sc, pin) == drive)
return;
/* Must be called with lock held. */
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
offset = ((pin & 0x0f) << 1);
val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4));
val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4));
val &= ~(AW_GPIO_DRV_MASK << offset);
val |= (drive << offset);
A10_GPIO_WRITE(sc, A10_GPIO_GP_DRV(bank, pin >> 4), val);
AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val);
}
static int
a10_gpio_pin_configure(struct a10_gpio_softc *sc, uint32_t pin, uint32_t flags)
aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags)
{
u_int val;
int err = 0;
/* Must be called with lock held. */
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
if (pin > sc->padconf->npins)
return (EINVAL);
/* Manage input/output. */
if (flags & GPIO_PIN_INPUT) {
err = a10_gpio_set_function(sc, pin, A10_GPIO_INPUT);
err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
} else if ((flags & GPIO_PIN_OUTPUT) &&
a10_gpio_get_function(sc, pin) != A10_GPIO_OUTPUT) {
aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) {
if (flags & GPIO_PIN_PRESET_LOW) {
a10_gpio_pin_set_locked(sc, pin, 0);
aw_gpio_pin_set_locked(sc, pin, 0);
} else if (flags & GPIO_PIN_PRESET_HIGH) {
a10_gpio_pin_set_locked(sc, pin, 1);
aw_gpio_pin_set_locked(sc, pin, 1);
} else {
/* Read the pin and preset output to current state. */
err = a10_gpio_set_function(sc, pin, A10_GPIO_INPUT);
err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
if (err == 0) {
a10_gpio_pin_get_locked(sc, pin, &val);
a10_gpio_pin_set_locked(sc, pin, val);
aw_gpio_pin_get_locked(sc, pin, &val);
aw_gpio_pin_set_locked(sc, pin, val);
}
}
if (err == 0)
err = a10_gpio_set_function(sc, pin, A10_GPIO_OUTPUT);
err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT);
}
if (err)
@ -376,19 +376,19 @@ a10_gpio_pin_configure(struct a10_gpio_softc *sc, uint32_t pin, uint32_t flags)
/* Manage Pull-up/pull-down. */
if (flags & GPIO_PIN_PULLUP)
a10_gpio_set_pud(sc, pin, A10_GPIO_PULLUP);
aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP);
else if (flags & GPIO_PIN_PULLDOWN)
a10_gpio_set_pud(sc, pin, A10_GPIO_PULLDOWN);
aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN);
else
a10_gpio_set_pud(sc, pin, A10_GPIO_NONE);
aw_gpio_set_pud(sc, pin, AW_GPIO_NONE);
return (0);
}
static device_t
a10_gpio_get_bus(device_t dev)
aw_gpio_get_bus(device_t dev)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
sc = device_get_softc(dev);
@ -396,9 +396,9 @@ a10_gpio_get_bus(device_t dev)
}
static int
a10_gpio_pin_max(device_t dev, int *maxpin)
aw_gpio_pin_max(device_t dev, int *maxpin)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
sc = device_get_softc(dev);
@ -407,23 +407,23 @@ a10_gpio_pin_max(device_t dev, int *maxpin)
}
static int
a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
sc = device_get_softc(dev);
if (pin >= sc->padconf->npins)
return (EINVAL);
*caps = A10_GPIO_DEFAULT_CAPS;
*caps = AW_GPIO_DEFAULT_CAPS;
return (0);
}
static int
a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
uint32_t func;
uint32_t pud;
@ -431,13 +431,13 @@ a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
if (pin >= sc->padconf->npins)
return (EINVAL);
A10_GPIO_LOCK(sc);
func = a10_gpio_get_function(sc, pin);
AW_GPIO_LOCK(sc);
func = aw_gpio_get_function(sc, pin);
switch (func) {
case A10_GPIO_INPUT:
case AW_GPIO_INPUT:
*flags = GPIO_PIN_INPUT;
break;
case A10_GPIO_OUTPUT:
case AW_GPIO_OUTPUT:
*flags = GPIO_PIN_OUTPUT;
break;
default:
@ -445,27 +445,27 @@ a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
break;
}
pud = a10_gpio_get_pud(sc, pin);
pud = aw_gpio_get_pud(sc, pin);
switch (pud) {
case A10_GPIO_PULLDOWN:
case AW_GPIO_PULLDOWN:
*flags |= GPIO_PIN_PULLDOWN;
break;
case A10_GPIO_PULLUP:
case AW_GPIO_PULLUP:
*flags |= GPIO_PIN_PULLUP;
break;
default:
break;
}
A10_GPIO_UNLOCK(sc);
AW_GPIO_UNLOCK(sc);
return (0);
}
static int
a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
sc = device_get_softc(dev);
if (pin >= sc->padconf->npins)
@ -479,29 +479,29 @@ a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
}
static int
a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
int err;
sc = device_get_softc(dev);
if (pin > sc->padconf->npins)
return (EINVAL);
A10_GPIO_LOCK(sc);
err = a10_gpio_pin_configure(sc, pin, flags);
A10_GPIO_UNLOCK(sc);
AW_GPIO_LOCK(sc);
err = aw_gpio_pin_configure(sc, pin, flags);
AW_GPIO_UNLOCK(sc);
return (err);
}
static int
a10_gpio_pin_set_locked(struct a10_gpio_softc *sc, uint32_t pin,
aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin,
unsigned int value)
{
uint32_t bank, data;
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
if (pin > sc->padconf->npins)
return (EINVAL);
@ -509,38 +509,38 @@ a10_gpio_pin_set_locked(struct a10_gpio_softc *sc, uint32_t pin,
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
if (value)
data |= (1 << pin);
else
data &= ~(1 << pin);
A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
return (0);
}
static int
a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
int ret;
sc = device_get_softc(dev);
A10_GPIO_LOCK(sc);
ret = a10_gpio_pin_set_locked(sc, pin, value);
A10_GPIO_UNLOCK(sc);
AW_GPIO_LOCK(sc);
ret = aw_gpio_pin_set_locked(sc, pin, value);
AW_GPIO_UNLOCK(sc);
return (ret);
}
static int
a10_gpio_pin_get_locked(struct a10_gpio_softc *sc,uint32_t pin,
aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin,
unsigned int *val)
{
uint32_t bank, reg_data;
A10_GPIO_LOCK_ASSERT(sc);
AW_GPIO_LOCK_ASSERT(sc);
if (pin > sc->padconf->npins)
return (EINVAL);
@ -548,14 +548,14 @@ a10_gpio_pin_get_locked(struct a10_gpio_softc *sc,uint32_t pin,
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
*val = (reg_data & (1 << pin)) ? 1 : 0;
return (0);
}
static char *
a10_gpio_parse_function(phandle_t node)
aw_gpio_parse_function(phandle_t node)
{
char *function;
@ -570,7 +570,7 @@ a10_gpio_parse_function(phandle_t node)
}
static const char **
a10_gpio_parse_pins(phandle_t node, int *pins_nb)
aw_gpio_parse_pins(phandle_t node, int *pins_nb)
{
const char **pinlist;
@ -587,7 +587,7 @@ a10_gpio_parse_pins(phandle_t node, int *pins_nb)
}
static uint32_t
a10_gpio_parse_bias(phandle_t node)
aw_gpio_parse_bias(phandle_t node)
{
uint32_t bias;
@ -596,17 +596,17 @@ a10_gpio_parse_bias(phandle_t node)
if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1)
return (bias);
if (OF_hasprop(node, "bias-disable"))
return (A10_GPIO_NONE);
return (AW_GPIO_NONE);
if (OF_hasprop(node, "bias-pull-up"))
return (A10_GPIO_PULLUP);
return (AW_GPIO_PULLUP);
if (OF_hasprop(node, "bias-pull-down"))
return (A10_GPIO_PULLDOWN);
return (AW_GPIO_PULLDOWN);
return (A10_GPIO_NONE);
return (AW_GPIO_NONE);
}
static int
a10_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
{
uint32_t drive_str;
@ -624,24 +624,24 @@ a10_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
}
static int
a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
int ret;
sc = device_get_softc(dev);
A10_GPIO_LOCK(sc);
ret = a10_gpio_pin_get_locked(sc, pin, val);
A10_GPIO_UNLOCK(sc);
AW_GPIO_LOCK(sc);
ret = aw_gpio_pin_get_locked(sc, pin, val);
AW_GPIO_UNLOCK(sc);
return (ret);
}
static int
a10_gpio_pin_toggle(device_t dev, uint32_t pin)
aw_gpio_pin_toggle(device_t dev, uint32_t pin)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
uint32_t bank, data;
sc = device_get_softc(dev);
@ -651,23 +651,23 @@ a10_gpio_pin_toggle(device_t dev, uint32_t pin)
bank = sc->padconf->pins[pin].port;
pin = sc->padconf->pins[pin].pin;
A10_GPIO_LOCK(sc);
data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
AW_GPIO_LOCK(sc);
data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
if (data & (1 << pin))
data &= ~(1 << pin);
else
data |= (1 << pin);
A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
A10_GPIO_UNLOCK(sc);
AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data);
AW_GPIO_UNLOCK(sc);
return (0);
}
static int
a10_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
uint32_t change_pins, uint32_t *orig_pins)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
uint32_t bank, data, pin;
sc = device_get_softc(dev);
@ -685,12 +685,12 @@ a10_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
if (pin != 0)
return (EINVAL);
A10_GPIO_LOCK(sc);
data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
AW_GPIO_LOCK(sc);
data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank));
if ((clear_pins | change_pins) != 0)
A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank),
AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank),
(data & ~clear_pins) ^ change_pins);
A10_GPIO_UNLOCK(sc);
AW_GPIO_UNLOCK(sc);
if (orig_pins != NULL)
*orig_pins = data;
@ -699,10 +699,10 @@ a10_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
}
static int
a10_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
uint32_t *pin_flags)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
uint32_t bank, pin;
int err;
@ -724,14 +724,14 @@ a10_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
*/
for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
err = a10_gpio_pin_configure(sc, pin, pin_flags[pin]);
err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]);
}
return (err);
}
static int
aw_find_pinnum_by_name(struct a10_gpio_softc *sc, const char *pinname)
aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname)
{
int i;
@ -743,7 +743,7 @@ aw_find_pinnum_by_name(struct a10_gpio_softc *sc, const char *pinname)
}
static int
aw_find_pin_func(struct a10_gpio_softc *sc, int pin, const char *func)
aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func)
{
int i;
@ -758,7 +758,7 @@ aw_find_pin_func(struct a10_gpio_softc *sc, int pin, const char *func)
static int
aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
phandle_t node;
const char **pinlist = NULL;
char *pin_function = NULL;
@ -772,20 +772,20 @@ aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
set_drive = false;
/* Getting all prop for configuring pins */
pinlist = a10_gpio_parse_pins(node, &pins_nb);
pinlist = aw_gpio_parse_pins(node, &pins_nb);
if (pinlist == NULL)
return (ENOENT);
pin_function = a10_gpio_parse_function(node);
pin_function = aw_gpio_parse_function(node);
if (pin_function == NULL) {
ret = ENOENT;
goto out;
}
if (a10_gpio_parse_drive_strength(node, &pin_drive) == 0)
if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0)
set_drive = true;
pin_pull = a10_gpio_parse_bias(node);
pin_pull = aw_gpio_parse_bias(node);
/* Configure each pin to the correct function, drive and pull */
for (i = 0; i < pins_nb; i++) {
@ -800,16 +800,16 @@ aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
goto out;
}
A10_GPIO_LOCK(sc);
AW_GPIO_LOCK(sc);
if (a10_gpio_get_function(sc, pin_num) != pin_func)
a10_gpio_set_function(sc, pin_num, pin_func);
if (aw_gpio_get_function(sc, pin_num) != pin_func)
aw_gpio_set_function(sc, pin_num, pin_func);
if (set_drive)
a10_gpio_set_drv(sc, pin_num, pin_drive);
if (pin_pull != A10_GPIO_NONE)
a10_gpio_set_pud(sc, pin_num, pin_pull);
aw_gpio_set_drv(sc, pin_num, pin_drive);
if (pin_pull != AW_GPIO_NONE)
aw_gpio_set_pud(sc, pin_num, pin_pull);
A10_GPIO_UNLOCK(sc);
AW_GPIO_UNLOCK(sc);
}
out:
@ -819,7 +819,7 @@ aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
}
static int
a10_gpio_probe(device_t dev)
aw_gpio_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
@ -833,11 +833,11 @@ a10_gpio_probe(device_t dev)
}
static int
a10_gpio_attach(device_t dev)
aw_gpio_attach(device_t dev)
{
int rid, error;
phandle_t gpio;
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
struct clk_list *clkp, *clkp_tmp;
clk_t clk;
hwreset_t rst = NULL;
@ -846,7 +846,7 @@ a10_gpio_attach(device_t dev)
sc = device_get_softc(dev);
sc->sc_dev = dev;
mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_SPIN);
mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN);
rid = 0;
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
@ -951,14 +951,14 @@ a10_gpio_attach(device_t dev)
}
static int
a10_gpio_detach(device_t dev)
aw_gpio_detach(device_t dev)
{
return (EBUSY);
}
static phandle_t
a10_gpio_get_node(device_t dev, device_t bus)
aw_gpio_get_node(device_t dev, device_t bus)
{
/* We only have one child, the GPIO bus, which needs our own node. */
@ -966,10 +966,10 @@ a10_gpio_get_node(device_t dev, device_t bus)
}
static int
a10_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
pcell_t *gpios, uint32_t *pin, uint32_t *flags)
{
struct a10_gpio_softc *sc;
struct aw_gpio_softc *sc;
int i;
sc = device_get_softc(bus);
@ -986,28 +986,28 @@ a10_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
return (0);
}
static device_method_t a10_gpio_methods[] = {
static device_method_t aw_gpio_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, a10_gpio_probe),
DEVMETHOD(device_attach, a10_gpio_attach),
DEVMETHOD(device_detach, a10_gpio_detach),
DEVMETHOD(device_probe, aw_gpio_probe),
DEVMETHOD(device_attach, aw_gpio_attach),
DEVMETHOD(device_detach, aw_gpio_detach),
/* GPIO protocol */
DEVMETHOD(gpio_get_bus, a10_gpio_get_bus),
DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
DEVMETHOD(gpio_pin_access_32, a10_gpio_pin_access_32),
DEVMETHOD(gpio_pin_config_32, a10_gpio_pin_config_32),
DEVMETHOD(gpio_map_gpios, a10_gpio_map_gpios),
DEVMETHOD(gpio_get_bus, aw_gpio_get_bus),
DEVMETHOD(gpio_pin_max, aw_gpio_pin_max),
DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname),
DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags),
DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps),
DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags),
DEVMETHOD(gpio_pin_get, aw_gpio_pin_get),
DEVMETHOD(gpio_pin_set, aw_gpio_pin_set),
DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle),
DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32),
DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32),
DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios),
/* ofw_bus interface */
DEVMETHOD(ofw_bus_get_node, a10_gpio_get_node),
DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node),
/* fdt_pinctrl interface */
DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
@ -1015,13 +1015,13 @@ static device_method_t a10_gpio_methods[] = {
DEVMETHOD_END
};
static devclass_t a10_gpio_devclass;
static devclass_t aw_gpio_devclass;
static driver_t a10_gpio_driver = {
static driver_t aw_gpio_driver = {
"gpio",
a10_gpio_methods,
sizeof(struct a10_gpio_softc),
aw_gpio_methods,
sizeof(struct aw_gpio_softc),
};
EARLY_DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0,
EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, aw_gpio_devclass, 0, 0,
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);

922
sys/arm/allwinner/aw_mmc.c Normal file
View File

@ -0,0 +1,922 @@
/*-
* Copyright (c) 2013 Alexander Fedorov
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <machine/bus.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/mmc/bridge.h>
#include <dev/mmc/mmcbrvar.h>
#include <arm/allwinner/aw_mmc.h>
#include <dev/extres/clk/clk.h>
#include <dev/extres/hwreset/hwreset.h>
#define AW_MMC_MEMRES 0
#define AW_MMC_IRQRES 1
#define AW_MMC_RESSZ 2
#define AW_MMC_DMA_SEGS ((MAXPHYS / PAGE_SIZE) + 1)
#define AW_MMC_DMA_MAX_SIZE 0x2000
#define AW_MMC_DMA_FTRGLEVEL 0x20070008
#define AW_MMC_RESET_RETRY 1000
#define CARD_ID_FREQUENCY 400000
static struct ofw_compat_data compat_data[] = {
{"allwinner,sun4i-a10-mmc", 1},
{"allwinner,sun5i-a13-mmc", 1},
{"allwinner,sun7i-a20-mmc", 1},
{"allwinner,sun50i-a64-mmc", 1},
{NULL, 0}
};
struct aw_mmc_softc {
device_t aw_dev;
clk_t aw_clk_ahb;
clk_t aw_clk_mmc;
hwreset_t aw_rst_ahb;
int aw_bus_busy;
int aw_resid;
int aw_timeout;
struct callout aw_timeoutc;
struct mmc_host aw_host;
struct mmc_request * aw_req;
struct mtx aw_mtx;
struct resource * aw_res[AW_MMC_RESSZ];
uint32_t aw_intr;
uint32_t aw_intr_wait;
void * aw_intrhand;
/* Fields required for DMA access. */
bus_addr_t aw_dma_desc_phys;
bus_dmamap_t aw_dma_map;
bus_dma_tag_t aw_dma_tag;
void * aw_dma_desc;
bus_dmamap_t aw_dma_buf_map;
bus_dma_tag_t aw_dma_buf_tag;
int aw_dma_map_err;
};
static struct resource_spec aw_mmc_res_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
{ -1, 0, 0 }
};
static int aw_mmc_probe(device_t);
static int aw_mmc_attach(device_t);
static int aw_mmc_detach(device_t);
static int aw_mmc_setup_dma(struct aw_mmc_softc *);
static int aw_mmc_reset(struct aw_mmc_softc *);
static void aw_mmc_intr(void *);
static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t);
static int aw_mmc_update_ios(device_t, device_t);
static int aw_mmc_request(device_t, device_t, struct mmc_request *);
static int aw_mmc_get_ro(device_t, device_t);
static int aw_mmc_acquire_host(device_t, device_t);
static int aw_mmc_release_host(device_t, device_t);
#define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx)
#define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx)
#define AW_MMC_READ_4(_sc, _reg) \
bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg)
#define AW_MMC_WRITE_4(_sc, _reg, _value) \
bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value)
static int
aw_mmc_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
return (BUS_PROBE_DEFAULT);
}
static int
aw_mmc_attach(device_t dev)
{
device_t child;
struct aw_mmc_softc *sc;
struct sysctl_ctx_list *ctx;
struct sysctl_oid_list *tree;
uint32_t bus_width;
phandle_t node;
int error;
node = ofw_bus_get_node(dev);
sc = device_get_softc(dev);
sc->aw_dev = dev;
sc->aw_req = NULL;
if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) {
device_printf(dev, "cannot allocate device resources\n");
return (ENXIO);
}
if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES],
INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc,
&sc->aw_intrhand)) {
bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
device_printf(dev, "cannot setup interrupt handler\n");
return (ENXIO);
}
mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc",
MTX_DEF);
callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0);
/* De-assert reset */
if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) {
error = hwreset_deassert(sc->aw_rst_ahb);
if (error != 0) {
device_printf(dev, "cannot de-assert reset\n");
goto fail;
}
}
/* Activate the module clock. */
error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb);
if (error != 0) {
device_printf(dev, "cannot get ahb clock\n");
goto fail;
}
error = clk_enable(sc->aw_clk_ahb);
if (error != 0) {
device_printf(dev, "cannot enable ahb clock\n");
goto fail;
}
error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc);
if (error != 0) {
device_printf(dev, "cannot get mmc clock\n");
goto fail;
}
error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY,
CLK_SET_ROUND_DOWN);
if (error != 0) {
device_printf(dev, "cannot init mmc clock\n");
goto fail;
}
error = clk_enable(sc->aw_clk_mmc);
if (error != 0) {
device_printf(dev, "cannot enable mmc clock\n");
goto fail;
}
sc->aw_timeout = 10;
ctx = device_get_sysctl_ctx(dev);
tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
&sc->aw_timeout, 0, "Request timeout in seconds");
/* Hardware reset */
AW_MMC_WRITE_4(sc, AW_MMC_HWRST, 1);
DELAY(100);
AW_MMC_WRITE_4(sc, AW_MMC_HWRST, 0);
DELAY(500);
/* Soft Reset controller. */
if (aw_mmc_reset(sc) != 0) {
device_printf(dev, "cannot reset the controller\n");
goto fail;
}
if (aw_mmc_setup_dma(sc) != 0) {
device_printf(sc->aw_dev, "Couldn't setup DMA!\n");
goto fail;
}
if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
bus_width = 4;
sc->aw_host.f_min = 400000;
sc->aw_host.f_max = 52000000;
sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
sc->aw_host.mode = mode_sd;
sc->aw_host.caps = MMC_CAP_HSPEED;
if (bus_width >= 4)
sc->aw_host.caps |= MMC_CAP_4_BIT_DATA;
if (bus_width >= 8)
sc->aw_host.caps |= MMC_CAP_8_BIT_DATA;
child = device_add_child(dev, "mmc", -1);
if (child == NULL) {
device_printf(dev, "attaching MMC bus failed!\n");
goto fail;
}
if (device_probe_and_attach(child) != 0) {
device_printf(dev, "attaching MMC child failed!\n");
device_delete_child(dev, child);
goto fail;
}
return (0);
fail:
callout_drain(&sc->aw_timeoutc);
mtx_destroy(&sc->aw_mtx);
bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
return (ENXIO);
}
static int
aw_mmc_detach(device_t dev)
{
return (EBUSY);
}
static void
aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
{
struct aw_mmc_softc *sc;
sc = (struct aw_mmc_softc *)arg;
if (err) {
sc->aw_dma_map_err = err;
return;
}
sc->aw_dma_desc_phys = segs[0].ds_addr;
}
static int
aw_mmc_setup_dma(struct aw_mmc_softc *sc)
{
int dma_desc_size, error;
/* Allocate the DMA descriptor memory. */
dma_desc_size = sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS;
error = bus_dma_tag_create(bus_get_dma_tag(sc->aw_dev),
AW_MMC_DMA_ALIGN, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->aw_dma_tag);
if (error)
return (error);
error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc,
BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->aw_dma_map);
if (error)
return (error);
error = bus_dmamap_load(sc->aw_dma_tag, sc->aw_dma_map,
sc->aw_dma_desc, dma_desc_size, aw_dma_desc_cb, sc, 0);
if (error)
return (error);
if (sc->aw_dma_map_err)
return (sc->aw_dma_map_err);
/* Create the DMA map for data transfers. */
error = bus_dma_tag_create(bus_get_dma_tag(sc->aw_dev),
AW_MMC_DMA_ALIGN, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
AW_MMC_DMA_MAX_SIZE * AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS,
AW_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
&sc->aw_dma_buf_tag);
if (error)
return (error);
error = bus_dmamap_create(sc->aw_dma_buf_tag, 0,
&sc->aw_dma_buf_map);
if (error)
return (error);
return (0);
}
static void
aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
{
int i;
struct aw_mmc_dma_desc *dma_desc;
struct aw_mmc_softc *sc;
sc = (struct aw_mmc_softc *)arg;
sc->aw_dma_map_err = err;
if (err)
return;
dma_desc = sc->aw_dma_desc;
for (i = 0; i < nsegs; i++) {
dma_desc[i].buf_size = segs[i].ds_len;
dma_desc[i].buf_addr = segs[i].ds_addr;
dma_desc[i].config = AW_MMC_DMA_CONFIG_CH |
AW_MMC_DMA_CONFIG_OWN;
if (i == 0)
dma_desc[i].config |= AW_MMC_DMA_CONFIG_FD;
if (i < (nsegs - 1)) {
dma_desc[i].config |= AW_MMC_DMA_CONFIG_DIC;
dma_desc[i].next = sc->aw_dma_desc_phys +
((i + 1) * sizeof(struct aw_mmc_dma_desc));
} else {
dma_desc[i].config |= AW_MMC_DMA_CONFIG_LD |
AW_MMC_DMA_CONFIG_ER;
dma_desc[i].next = 0;
}
}
}
static int
aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
{
bus_dmasync_op_t sync_op;
int error;
struct mmc_command *cmd;
uint32_t val;
cmd = sc->aw_req->cmd;
if (cmd->data->len > AW_MMC_DMA_MAX_SIZE * AW_MMC_DMA_SEGS)
return (EFBIG);
error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0);
if (error)
return (error);
if (sc->aw_dma_map_err)
return (sc->aw_dma_map_err);
if (cmd->data->flags & MMC_DATA_WRITE)
sync_op = BUS_DMASYNC_PREWRITE;
else
sync_op = BUS_DMASYNC_PREREAD;
bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op);
bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE);
/* Enable DMA */
val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
val &= ~AW_MMC_CTRL_FIFO_AC_MOD;
val |= AW_MMC_CTRL_DMA_ENB;
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
/* Reset DMA */
val |= AW_MMC_CTRL_DMA_RST;
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST);
AW_MMC_WRITE_4(sc, AW_MMC_DMAC,
AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST);
/* Enable RX or TX DMA interrupt */
if (cmd->data->flags & MMC_DATA_WRITE)
val |= AW_MMC_IDST_TX_INT;
else
val |= AW_MMC_IDST_RX_INT;
AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val);
/* Set DMA descritptor list address */
AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys);
/* FIFO trigger level */
AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL);
return (0);
}
static int
aw_mmc_reset(struct aw_mmc_softc *sc)
{
int timeout;
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, AW_MMC_RESET);
timeout = 1000;
while (--timeout > 0) {
if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_RESET) == 0)
break;
DELAY(100);
}
if (timeout == 0)
return (ETIMEDOUT);
/* Set the timeout. */
AW_MMC_WRITE_4(sc, AW_MMC_TMOR,
AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) |
AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK));
/* Clear pending interrupts. */
AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
/* Unmask interrupts. */
AW_MMC_WRITE_4(sc, AW_MMC_IMKR,
AW_MMC_INT_CMD_DONE | AW_MMC_INT_ERR_BIT |
AW_MMC_INT_DATA_OVER | AW_MMC_INT_AUTO_STOP_DONE);
/* Enable interrupts and AHB access. */
AW_MMC_WRITE_4(sc, AW_MMC_GCTL,
AW_MMC_READ_4(sc, AW_MMC_GCTL) | AW_MMC_CTRL_INT_ENB);
return (0);
}
static void
aw_mmc_req_done(struct aw_mmc_softc *sc)
{
struct mmc_command *cmd;
struct mmc_request *req;
uint32_t val, mask;
int retry;
cmd = sc->aw_req->cmd;
if (cmd->error != MMC_ERR_NONE) {
/* Reset the FIFO and DMA engines. */
mask = AW_MMC_CTRL_FIFO_RST | AW_MMC_CTRL_DMA_RST;
val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask);
retry = AW_MMC_RESET_RETRY;
while (--retry > 0) {
val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
if ((val & mask) == 0)
break;
DELAY(10);
}
if (retry == 0)
device_printf(sc->aw_dev,
"timeout resetting DMA/FIFO\n");
aw_mmc_update_clock(sc, 1);
}
req = sc->aw_req;
callout_stop(&sc->aw_timeoutc);
sc->aw_req = NULL;
sc->aw_intr = 0;
sc->aw_resid = 0;
sc->aw_dma_map_err = 0;
sc->aw_intr_wait = 0;
req->done(req);
}
static void
aw_mmc_req_ok(struct aw_mmc_softc *sc)
{
int timeout;
struct mmc_command *cmd;
uint32_t status;
timeout = 1000;
while (--timeout > 0) {
status = AW_MMC_READ_4(sc, AW_MMC_STAR);
if ((status & AW_MMC_STAR_CARD_BUSY) == 0)
break;
DELAY(1000);
}
cmd = sc->aw_req->cmd;
if (timeout == 0) {
cmd->error = MMC_ERR_FAILED;
aw_mmc_req_done(sc);
return;
}
if (cmd->flags & MMC_RSP_PRESENT) {
if (cmd->flags & MMC_RSP_136) {
cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3);
cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2);
cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1);
cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
} else
cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
}
/* All data has been transferred ? */
if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len)
cmd->error = MMC_ERR_FAILED;
aw_mmc_req_done(sc);
}
static void
aw_mmc_timeout(void *arg)
{
struct aw_mmc_softc *sc;
sc = (struct aw_mmc_softc *)arg;
if (sc->aw_req != NULL) {
device_printf(sc->aw_dev, "controller timeout\n");
sc->aw_req->cmd->error = MMC_ERR_TIMEOUT;
aw_mmc_req_done(sc);
} else
device_printf(sc->aw_dev,
"Spurious timeout - no active request\n");
}
static void
aw_mmc_intr(void *arg)
{
bus_dmasync_op_t sync_op;
struct aw_mmc_softc *sc;
struct mmc_data *data;
uint32_t idst, imask, rint;
sc = (struct aw_mmc_softc *)arg;
AW_MMC_LOCK(sc);
rint = AW_MMC_READ_4(sc, AW_MMC_RISR);
idst = AW_MMC_READ_4(sc, AW_MMC_IDST);
imask = AW_MMC_READ_4(sc, AW_MMC_IMKR);
if (idst == 0 && imask == 0 && rint == 0) {
AW_MMC_UNLOCK(sc);
return;
}
#ifdef DEBUG
device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n",
idst, imask, rint);
#endif
if (sc->aw_req == NULL) {
device_printf(sc->aw_dev,
"Spurious interrupt - no active request, rint: 0x%08X\n",
rint);
goto end;
}
if (rint & AW_MMC_INT_ERR_BIT) {
device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
if (rint & AW_MMC_INT_RESP_TIMEOUT)
sc->aw_req->cmd->error = MMC_ERR_TIMEOUT;
else
sc->aw_req->cmd->error = MMC_ERR_FAILED;
aw_mmc_req_done(sc);
goto end;
}
if (idst & AW_MMC_IDST_ERROR) {
device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst);
sc->aw_req->cmd->error = MMC_ERR_FAILED;
aw_mmc_req_done(sc);
goto end;
}
sc->aw_intr |= rint;
data = sc->aw_req->cmd->data;
if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) {
if (data->flags & MMC_DATA_WRITE)
sync_op = BUS_DMASYNC_POSTWRITE;
else
sync_op = BUS_DMASYNC_POSTREAD;
bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
sync_op);
bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
sc->aw_resid = data->len >> 2;
}
if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait)
aw_mmc_req_ok(sc);
end:
AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst);
AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint);
AW_MMC_UNLOCK(sc);
}
static int
aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
{
int blksz;
struct aw_mmc_softc *sc;
struct mmc_command *cmd;
uint32_t cmdreg;
int err;
sc = device_get_softc(bus);
AW_MMC_LOCK(sc);
if (sc->aw_req) {
AW_MMC_UNLOCK(sc);
return (EBUSY);
}
sc->aw_req = req;
cmd = req->cmd;
cmdreg = AW_MMC_CMDR_LOAD;
if (cmd->opcode == MMC_GO_IDLE_STATE)
cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ;
if (cmd->flags & MMC_RSP_PRESENT)
cmdreg |= AW_MMC_CMDR_RESP_RCV;
if (cmd->flags & MMC_RSP_136)
cmdreg |= AW_MMC_CMDR_LONG_RESP;
if (cmd->flags & MMC_RSP_CRC)
cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC;
sc->aw_intr = 0;
sc->aw_resid = 0;
sc->aw_intr_wait = AW_MMC_INT_CMD_DONE;
cmd->error = MMC_ERR_NONE;
if (cmd->data != NULL) {
sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER;
if (cmd->data->flags & MMC_DATA_MULTI) {
cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG;
sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE;
}
if (cmd->data->flags & MMC_DATA_WRITE)
cmdreg |= AW_MMC_CMDR_DIR_WRITE;
blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz);
AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
err = aw_mmc_prepare_dma(sc);
if (err != 0)
device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err);
}
AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz,
aw_mmc_timeout, sc);
AW_MMC_UNLOCK(sc);
return (0);
}
static int
aw_mmc_read_ivar(device_t bus, device_t child, int which,
uintptr_t *result)
{
struct aw_mmc_softc *sc;
sc = device_get_softc(bus);
switch (which) {
default:
return (EINVAL);
case MMCBR_IVAR_BUS_MODE:
*(int *)result = sc->aw_host.ios.bus_mode;
break;
case MMCBR_IVAR_BUS_WIDTH:
*(int *)result = sc->aw_host.ios.bus_width;
break;
case MMCBR_IVAR_CHIP_SELECT:
*(int *)result = sc->aw_host.ios.chip_select;
break;
case MMCBR_IVAR_CLOCK:
*(int *)result = sc->aw_host.ios.clock;
break;
case MMCBR_IVAR_F_MIN:
*(int *)result = sc->aw_host.f_min;
break;
case MMCBR_IVAR_F_MAX:
*(int *)result = sc->aw_host.f_max;
break;
case MMCBR_IVAR_HOST_OCR:
*(int *)result = sc->aw_host.host_ocr;
break;
case MMCBR_IVAR_MODE:
*(int *)result = sc->aw_host.mode;
break;
case MMCBR_IVAR_OCR:
*(int *)result = sc->aw_host.ocr;
break;
case MMCBR_IVAR_POWER_MODE:
*(int *)result = sc->aw_host.ios.power_mode;
break;
case MMCBR_IVAR_VDD:
*(int *)result = sc->aw_host.ios.vdd;
break;
case MMCBR_IVAR_CAPS:
*(int *)result = sc->aw_host.caps;
break;
case MMCBR_IVAR_MAX_DATA:
*(int *)result = 65535;
break;
}
return (0);
}
static int
aw_mmc_write_ivar(device_t bus, device_t child, int which,
uintptr_t value)
{
struct aw_mmc_softc *sc;
sc = device_get_softc(bus);
switch (which) {
default:
return (EINVAL);
case MMCBR_IVAR_BUS_MODE:
sc->aw_host.ios.bus_mode = value;
break;
case MMCBR_IVAR_BUS_WIDTH:
sc->aw_host.ios.bus_width = value;
break;
case MMCBR_IVAR_CHIP_SELECT:
sc->aw_host.ios.chip_select = value;
break;
case MMCBR_IVAR_CLOCK:
sc->aw_host.ios.clock = value;
break;
case MMCBR_IVAR_MODE:
sc->aw_host.mode = value;
break;
case MMCBR_IVAR_OCR:
sc->aw_host.ocr = value;
break;
case MMCBR_IVAR_POWER_MODE:
sc->aw_host.ios.power_mode = value;
break;
case MMCBR_IVAR_VDD:
sc->aw_host.ios.vdd = value;
break;
/* These are read-only */
case MMCBR_IVAR_CAPS:
case MMCBR_IVAR_HOST_OCR:
case MMCBR_IVAR_F_MIN:
case MMCBR_IVAR_F_MAX:
case MMCBR_IVAR_MAX_DATA:
return (EINVAL);
}
return (0);
}
static int
aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon)
{
uint32_t cmdreg;
int retry;
uint32_t ckcr;
ckcr = AW_MMC_READ_4(sc, AW_MMC_CKCR);
ckcr &= ~(AW_MMC_CKCR_CCLK_ENB | AW_MMC_CKCR_CCLK_CTRL);
if (clkon)
ckcr |= AW_MMC_CKCR_CCLK_ENB;
AW_MMC_WRITE_4(sc, AW_MMC_CKCR, ckcr);
cmdreg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
AW_MMC_CMDR_WAIT_PRE_OVER;
AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg);
retry = 0xfffff;
while (--retry > 0) {
if ((AW_MMC_READ_4(sc, AW_MMC_CMDR) & AW_MMC_CMDR_LOAD) == 0) {
AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
return (0);
}
DELAY(10);
}
AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
device_printf(sc->aw_dev, "timeout updating clock\n");
return (ETIMEDOUT);
}
static int
aw_mmc_update_ios(device_t bus, device_t child)
{
int error;
struct aw_mmc_softc *sc;
struct mmc_ios *ios;
uint32_t ckcr;
sc = device_get_softc(bus);
ios = &sc->aw_host.ios;
/* Set the bus width. */
switch (ios->bus_width) {
case bus_width_1:
AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1);
break;
case bus_width_4:
AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4);
break;
case bus_width_8:
AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8);
break;
}
if (ios->clock) {
/* Disable clock */
error = aw_mmc_update_clock(sc, 0);
if (error != 0)
return (error);
/* Reset the divider. */
ckcr = AW_MMC_READ_4(sc, AW_MMC_CKCR);
ckcr &= ~AW_MMC_CKCR_CCLK_DIV;
AW_MMC_WRITE_4(sc, AW_MMC_CKCR, ckcr);
/* Set the MMC clock. */
error = clk_set_freq(sc->aw_clk_mmc, ios->clock,
CLK_SET_ROUND_DOWN);
if (error != 0) {
device_printf(sc->aw_dev,
"failed to set frequency to %u Hz: %d\n",
ios->clock, error);
return (error);
}
/* Enable clock. */
error = aw_mmc_update_clock(sc, 1);
if (error != 0)
return (error);
}
return (0);
}
static int
aw_mmc_get_ro(device_t bus, device_t child)
{
return (0);
}
static int
aw_mmc_acquire_host(device_t bus, device_t child)
{
struct aw_mmc_softc *sc;
int error;
sc = device_get_softc(bus);
AW_MMC_LOCK(sc);
while (sc->aw_bus_busy) {
error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0);
if (error != 0) {
AW_MMC_UNLOCK(sc);
return (error);
}
}
sc->aw_bus_busy++;
AW_MMC_UNLOCK(sc);
return (0);
}
static int
aw_mmc_release_host(device_t bus, device_t child)
{
struct aw_mmc_softc *sc;
sc = device_get_softc(bus);
AW_MMC_LOCK(sc);
sc->aw_bus_busy--;
wakeup(sc);
AW_MMC_UNLOCK(sc);
return (0);
}
static device_method_t aw_mmc_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, aw_mmc_probe),
DEVMETHOD(device_attach, aw_mmc_attach),
DEVMETHOD(device_detach, aw_mmc_detach),
/* Bus interface */
DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar),
DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar),
/* MMC bridge interface */
DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios),
DEVMETHOD(mmcbr_request, aw_mmc_request),
DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro),
DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host),
DEVMETHOD(mmcbr_release_host, aw_mmc_release_host),
DEVMETHOD_END
};
static devclass_t aw_mmc_devclass;
static driver_t aw_mmc_driver = {
"aw_mmc",
aw_mmc_methods,
sizeof(struct aw_mmc_softc),
};
DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL,
NULL);
MMC_DECLARE_BRIDGE(aw_mmc);

204
sys/arm/allwinner/aw_mmc.h Normal file
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@ -0,0 +1,204 @@
/*-
* Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _AW_MMC_H_
#define _AW_MMC_H_
#define AW_MMC_GCTL 0x00 /* Control Register */
#define AW_MMC_CKCR 0x04 /* Clock Control Register */
#define AW_MMC_TMOR 0x08 /* Timeout Register */
#define AW_MMC_BWDR 0x0C /* Bus Width Register */
#define AW_MMC_BKSR 0x10 /* Block Size Register */
#define AW_MMC_BYCR 0x14 /* Byte Count Register */
#define AW_MMC_CMDR 0x18 /* Command Register */
#define AW_MMC_CAGR 0x1C /* Argument Register */
#define AW_MMC_RESP0 0x20 /* Response Register 0 */
#define AW_MMC_RESP1 0x24 /* Response Register 1 */
#define AW_MMC_RESP2 0x28 /* Response Register 2 */
#define AW_MMC_RESP3 0x2C /* Response Register 3 */
#define AW_MMC_IMKR 0x30 /* Interrupt Mask Register */
#define AW_MMC_MISR 0x34 /* Masked Interrupt Status Register */
#define AW_MMC_RISR 0x38 /* Raw Interrupt Status Register */
#define AW_MMC_STAR 0x3C /* Status Register */
#define AW_MMC_FWLR 0x40 /* FIFO Threshold Watermark Register */
#define AW_MMC_FUNS 0x44 /* Function Select Register */
#define AW_MMC_HWRST 0x78 /* Hardware reset (not documented) */
#define AW_MMC_DMAC 0x80 /* IDMAC Control Register */
#define AW_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */
#define AW_MMC_IDST 0x88 /* IDMAC Status Register */
#define AW_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */
#define AW_MMC_FIFO 0x100 /* FIFO Access Address (A10/A20) */
#define A31_MMC_FIFO 0x200 /* FIFO Access Address (A31) */
/* AW_MMC_GCTL */
#define AW_MMC_CTRL_SOFT_RST (1U << 0)
#define AW_MMC_CTRL_FIFO_RST (1U << 1)
#define AW_MMC_CTRL_DMA_RST (1U << 2)
#define AW_MMC_CTRL_INT_ENB (1U << 4)
#define AW_MMC_CTRL_DMA_ENB (1U << 5)
#define AW_MMC_CTRL_CD_DBC_ENB (1U << 8)
#define AW_MMC_CTRL_DDR_MOD_SEL (1U << 10)
#define AW_MMC_CTRL_FIFO_AC_MOD (1U << 31)
#define AW_MMC_RESET \
(AW_MMC_CTRL_SOFT_RST | AW_MMC_CTRL_FIFO_RST | AW_MMC_CTRL_DMA_RST)
/* AW_MMC_CKCR */
#define AW_MMC_CKCR_CCLK_ENB (1U << 16)
#define AW_MMC_CKCR_CCLK_CTRL (1U << 17)
#define AW_MMC_CKCR_CCLK_DIV 0xff
/* AW_MMC_TMOR */
#define AW_MMC_TMOR_RTO_LMT_SHIFT(x) x /* Response timeout limit */
#define AW_MMC_TMOR_RTO_LMT_MASK 0xff
#define AW_MMC_TMOR_DTO_LMT_SHIFT(x) (x << 8) /* Data timeout limit */
#define AW_MMC_TMOR_DTO_LMT_MASK 0xffffff
/* AW_MMC_BWDR */
#define AW_MMC_BWDR1 0
#define AW_MMC_BWDR4 1
#define AW_MMC_BWDR8 2
/* AW_MMC_CMDR */
#define AW_MMC_CMDR_RESP_RCV (1U << 6)
#define AW_MMC_CMDR_LONG_RESP (1U << 7)
#define AW_MMC_CMDR_CHK_RESP_CRC (1U << 8)
#define AW_MMC_CMDR_DATA_TRANS (1U << 9)
#define AW_MMC_CMDR_DIR_WRITE (1U << 10)
#define AW_MMC_CMDR_TRANS_MODE_STREAM (1U << 11)
#define AW_MMC_CMDR_STOP_CMD_FLAG (1U << 12)
#define AW_MMC_CMDR_WAIT_PRE_OVER (1U << 13)
#define AW_MMC_CMDR_STOP_ABT_CMD (1U << 14)
#define AW_MMC_CMDR_SEND_INIT_SEQ (1U << 15)
#define AW_MMC_CMDR_PRG_CLK (1U << 21)
#define AW_MMC_CMDR_RD_CEDATA_DEV (1U << 22)
#define AW_MMC_CMDR_CCS_EXP (1U << 23)
#define AW_MMC_CMDR_BOOT_MOD_SHIFT 24
#define AW_MMC_CMDR_BOOT_MOD_NORMAL 0
#define AW_MMC_CMDR_BOOT_MOD_MANDATORY 1
#define AW_MMC_CMDR_BOOT_MOD_ALT 2
#define AW_MMC_CMDR_EXP_BOOT_ACK (1U << 26)
#define AW_MMC_CMDR_BOOT_ABT (1U << 27)
#define AW_MMC_CMDR_VOL_SW (1U << 28)
#define AW_MMC_CMDR_LOAD (1U << 31)
/* AW_MMC_IMKR and AW_MMC_RISR */
#define AW_MMC_INT_RESP_ERR (1U << 1)
#define AW_MMC_INT_CMD_DONE (1U << 2)
#define AW_MMC_INT_DATA_OVER (1U << 3)
#define AW_MMC_INT_TX_DATA_REQ (1U << 4)
#define AW_MMC_INT_RX_DATA_REQ (1U << 5)
#define AW_MMC_INT_RESP_CRC_ERR (1U << 6)
#define AW_MMC_INT_DATA_CRC_ERR (1U << 7)
#define AW_MMC_INT_RESP_TIMEOUT (1U << 8)
#define AW_MMC_INT_BOOT_ACK_RECV (1U << 8)
#define AW_MMC_INT_DATA_TIMEOUT (1U << 9)
#define AW_MMC_INT_BOOT_START (1U << 9)
#define AW_MMC_INT_DATA_STARVE (1U << 10)
#define AW_MMC_INT_VOL_CHG_DONE (1U << 10)
#define AW_MMC_INT_FIFO_RUN_ERR (1U << 11)
#define AW_MMC_INT_CMD_BUSY (1U << 12)
#define AW_MMC_INT_DATA_START_ERR (1U << 13)
#define AW_MMC_INT_AUTO_STOP_DONE (1U << 14)
#define AW_MMC_INT_DATA_END_BIT_ERR (1U << 15)
#define AW_MMC_INT_SDIO (1U << 16)
#define AW_MMC_INT_CARD_INSERT (1U << 30)
#define AW_MMC_INT_CARD_REMOVE (1U << 31)
#define AW_MMC_INT_ERR_BIT \
(AW_MMC_INT_RESP_ERR | AW_MMC_INT_RESP_CRC_ERR | \
AW_MMC_INT_DATA_CRC_ERR | AW_MMC_INT_RESP_TIMEOUT | \
AW_MMC_INT_FIFO_RUN_ERR | AW_MMC_INT_CMD_BUSY | \
AW_MMC_INT_DATA_START_ERR | AW_MMC_INT_DATA_END_BIT_ERR)
/* AW_MMC_STAR */
#define AW_MMC_STAR_FIFO_RX_LEVEL (1U << 0)
#define AW_MMC_STAR_FIFO_TX_LEVEL (1U << 1)
#define AW_MMC_STAR_FIFO_EMPTY (1U << 2)
#define AW_MMC_STAR_FIFO_FULL (1U << 3)
#define AW_MMC_STAR_CARD_PRESENT (1U << 8)
#define AW_MMC_STAR_CARD_BUSY (1U << 9)
#define AW_MMC_STAR_FSM_BUSY (1U << 10)
#define AW_MMC_STAR_DMA_REQ (1U << 31)
/* AW_MMC_FUNS */
#define AW_MMC_CE_ATA_ON (0xceaaU << 16)
#define AW_MMC_SEND_IRQ_RESP (1U << 0)
#define AW_MMC_SDIO_RD_WAIT (1U << 1)
#define AW_MMC_ABT_RD_DATA (1U << 2)
#define AW_MMC_SEND_CC_SD (1U << 8)
#define AW_MMC_SEND_AUTOSTOP_CC_SD (1U << 9)
#define AW_MMC_CE_ATA_DEV_INT_ENB (1U << 10)
/* IDMA CONTROLLER BUS MOD BIT FIELD */
#define AW_MMC_DMAC_IDMAC_SOFT_RST (1U << 0)
#define AW_MMC_DMAC_IDMAC_FIX_BURST (1U << 1)
#define AW_MMC_DMAC_IDMAC_IDMA_ON (1U << 7)
#define AW_MMC_DMAC_IDMAC_REFETCH_DES (1U << 31)
/* AW_MMC_IDST */
#define AW_MMC_IDST_TX_INT (1U << 0)
#define AW_MMC_IDST_RX_INT (1U << 1)
#define AW_MMC_IDST_FATAL_BERR_INT (1U << 2)
#define AW_MMC_IDST_DES_UNAVL_INT (1U << 4)
#define AW_MMC_IDST_ERR_FLAG_SUM (1U << 5)
#define AW_MMC_IDST_NOR_INT_SUM (1U << 8)
#define AW_MMC_IDST_ABN_INT_SUM (1U << 9)
#define AW_MMC_IDST_HOST_ABT_INTX (1U << 10)
#define AW_MMC_IDST_HOST_ABT_INRX (1U << 10)
#define AW_MMC_IDST_IDLE (0U << 13)
#define AW_MMC_IDST_SUSPEND (1U << 13)
#define AW_MMC_IDST_DESC_RD (2U << 13)
#define AW_MMC_IDST_DESC_CHECK (3U << 13)
#define AW_MMC_IDST_RD_REQ_WAIT (4U << 13)
#define AW_MMC_IDST_WR_REQ_WAIT (5U << 13)
#define AW_MMC_IDST_RD (6U << 13)
#define AW_MMC_IDST_WR (7U << 13)
#define AW_MMC_IDST_DESC_CLOSE (8U << 13)
#define AW_MMC_IDST_ERROR \
(AW_MMC_IDST_FATAL_BERR_INT | AW_MMC_IDST_ERR_FLAG_SUM | \
AW_MMC_IDST_DES_UNAVL_INT | AW_MMC_IDST_ABN_INT_SUM)
#define AW_MMC_IDST_COMPLETE \
(AW_MMC_IDST_TX_INT | AW_MMC_IDST_RX_INT)
/* The DMA descriptor table. */
struct aw_mmc_dma_desc {
uint32_t config;
#define AW_MMC_DMA_CONFIG_DIC (1U << 1) /* Disable Interrupt Completion */
#define AW_MMC_DMA_CONFIG_LD (1U << 2) /* Last DES */
#define AW_MMC_DMA_CONFIG_FD (1U << 3) /* First DES */
#define AW_MMC_DMA_CONFIG_CH (1U << 4) /* CHAIN MOD */
#define AW_MMC_DMA_CONFIG_ER (1U << 5) /* End of Ring (undocumented register) */
#define AW_MMC_DMA_CONFIG_CES (1U << 30) /* Card Error Summary */
#define AW_MMC_DMA_CONFIG_OWN (1U << 31) /* DES Own Flag */
uint32_t buf_size;
uint32_t buf_addr;
uint32_t next;
};
#define AW_MMC_DMA_ALIGN 4
#endif /* _AW_MMC_H_ */

2
sys/arm/allwinner/aw_mp.c
View File

@ -1,6 +1,6 @@
/*-
* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com>
* Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
sys/arm/allwinner/aw_mp.h
View File

@ -1,5 +1,5 @@
/*-
* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com>
* Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

5
sys/arm/allwinner/aw_wdog.c
View File

@ -1,6 +1,6 @@
/*-
* Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com>
* Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -115,9 +115,6 @@ static void aw_wdog_shutdown_fn(void *, int);
static int
aw_wdog_probe(device_t dev)
{
struct aw_wdog_softc *sc;
sc = device_get_softc(dev);
if (!ofw_bus_status_okay(dev))
return (ENXIO);

2
sys/arm/allwinner/axp81x.c
View File

@ -352,13 +352,11 @@ axp81x_shutdown(void *devp, int howto)
static void
axp81x_intr(void *arg)
{
struct axp81x_softc *sc;
device_t dev;
uint8_t val;
int error;
dev = arg;
sc = device_get_softc(dev);
error = axp81x_read(dev, AXP_IRQSTAT5, &val, 1);
if (error != 0)

4
sys/arm/allwinner/clk/aw_pll.c
View File

@ -865,7 +865,7 @@ h3_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
int flags)
{
struct aw_pll_factor *f;
uint32_t val, n, k, m, p;
uint32_t val, m, p;
int i;
f = NULL;
@ -884,8 +884,6 @@ h3_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
DEVICE_LOCK(sc);
PLL_READ(sc, &val);
n = (val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT;
k = (val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT;
m = (val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT;
p = (val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT;

14
sys/arm/allwinner/files.allwinner
View File

@ -6,18 +6,18 @@ arm/allwinner/a10_codec.c optional sound
arm/allwinner/a10_dmac.c standard
arm/allwinner/a31_dmac.c standard
arm/allwinner/a10_ehci.c optional ehci
arm/allwinner/aw_usbphy.c optional ehci
arm/allwinner/a10_gpio.c optional gpio
arm/allwinner/a10_mmc.c optional mmc
arm/allwinner/a10_sramc.c standard
arm/allwinner/aw_nmi.c optional intrng
arm/allwinner/aw_gpio.c optional gpio
arm/allwinner/aw_if_dwc.c optional dwc
arm/allwinner/aw_machdep.c standard
arm/allwinner/aw_mmc.c optional mmc
arm/allwinner/aw_mp.c optional smp
arm/allwinner/aw_nmi.c optional intrng
arm/allwinner/aw_rsb.c optional rsb | p2wi
arm/allwinner/aw_rtc.c standard
arm/allwinner/aw_ts.c standard
arm/allwinner/aw_usbphy.c optional ehci | ohci
arm/allwinner/aw_wdog.c standard
arm/allwinner/aw_machdep.c standard
arm/allwinner/aw_mp.c optional smp
arm/allwinner/axp209.c optional axp209
arm/allwinner/axp81x.c optional axp81x
arm/allwinner/if_awg.c optional awg
@ -30,12 +30,10 @@ arm/allwinner/aw_sid.c standard
arm/allwinner/aw_thermal.c standard
dev/iicbus/sy8106a.c optional sy8106a
arm/allwinner/aw_cir.c optional aw_cir evdev
#arm/allwinner/aw_console.c standard
arm/allwinner/a10_fb.c optional vt
arm/allwinner/a10_hdmi.c optional hdmi
arm/allwinner/a10_hdmiaudio.c optional hdmi sound
dev/hdmi/hdmi_if.m optional hdmi
arm/allwinner/aw_reset.c standard
arm/allwinner/aw_ccu.c standard

8
sys/arm/allwinner/if_awg.c
View File

@ -1177,7 +1177,7 @@ awg_setup_phy(device_t dev)
if (sc->res[_RES_SYSCON] != NULL) {
reg = bus_read_4(sc->res[_RES_SYSCON], 0);
reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
if (strcmp(phy_type, "rgmii") == 0)
if (strncmp(phy_type, "rgmii", 5) == 0)
reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
else if (strcmp(phy_type, "rmii") == 0)
reg |= EMAC_CLK_RMII_EN;
@ -1217,7 +1217,7 @@ awg_setup_phy(device_t dev)
device_printf(dev, "EMAC clock: 0x%08x\n", reg);
bus_write_4(sc->res[_RES_SYSCON], 0, reg);
} else {
if (strcmp(phy_type, "rgmii") == 0)
if (strncmp(phy_type, "rgmii", 5) == 0)
tx_parent_name = "emac_int_tx";
else
tx_parent_name = "mii_phy_tx";
@ -1266,12 +1266,10 @@ awg_setup_extres(device_t dev)
hwreset_t rst_ahb, rst_ephy;
clk_t clk_ahb, clk_ephy;
regulator_t reg;
phandle_t node;
uint64_t freq;
int error, div;
sc = device_get_softc(dev);
node = ofw_bus_get_node(dev);
rst_ahb = rst_ephy = NULL;
clk_ahb = clk_ephy = NULL;
reg = NULL;
@ -1713,13 +1711,11 @@ awg_attach(device_t dev)
{
uint8_t eaddr[ETHER_ADDR_LEN];
struct awg_softc *sc;
phandle_t node;
int error;
sc = device_get_softc(dev);
sc->dev = dev;
sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
node = ofw_bus_get_node(dev);
if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) {
device_printf(dev, "cannot allocate resources for device\n");

9
sys/arm/arm/genassym.c
View File

@ -161,3 +161,12 @@ ASSYM(DCACHE_LINE_SIZE, offsetof(struct cpuinfo, dcache_line_size));
ASSYM(DCACHE_LINE_MASK, offsetof(struct cpuinfo, dcache_line_mask));
ASSYM(ICACHE_LINE_SIZE, offsetof(struct cpuinfo, icache_line_size));
ASSYM(ICACHE_LINE_MASK, offsetof(struct cpuinfo, icache_line_mask));
/*
* Emit the LOCORE_MAP_MB option as a #define only if the option was set.
*/
#include "opt_locore.h"
#ifdef LOCORE_MAP_MB
ASSYM(LOCORE_MAP_MB, LOCORE_MAP_MB);
#endif

2
sys/arm/arm/gic.c
View File

@ -1384,11 +1384,9 @@ int
arm_gicv2m_attach(device_t dev)
{
struct arm_gicv2m_softc *sc;
struct arm_gic_softc *psc;
uint32_t typer;
int rid;
psc = device_get_softc(device_get_parent(dev));
sc = device_get_softc(dev);
rid = 0;

12
sys/arm/arm/locore-v6.S
View File

@ -38,6 +38,11 @@
__FBSDID("$FreeBSD$");
/* We map 64MB of kernel unless overridden in assym.s by the kernel option. */
#ifndef LOCORE_MAP_MB
#define LOCORE_MAP_MB 64
#endif
#if __ARM_ARCH >= 7
#if defined(__ARM_ARCH_7VE__) || defined(__clang__)
/*
@ -176,12 +181,13 @@ ASENTRY_NP(_start)
bl build_pagetables
/*
* Next we do 64MiB starting at the physical load address, mapped to
* the VA the kernel is linked for.
* Next we map the kernel starting at the physical load address, mapped
* to the VA the kernel is linked for. The default size we map is 64MiB
* but it can be overridden with a kernel option.
*/
mov r1, r5
ldr r2, =(KERNVIRTADDR)
mov r3, #64
ldr r3, =(LOCORE_MAP_MB)
bl build_pagetables
/* Create a device mapping for early_printf if specified. */

10
sys/arm/broadcom/bcm2835/bcm2835_cpufreq.c
View File

@ -1386,9 +1386,6 @@ bcm2835_cpufreq_attach(device_t dev)
static int
bcm2835_cpufreq_detach(device_t dev)
{
struct bcm2835_cpufreq_softc *sc;
sc = device_get_softc(dev);
sema_destroy(&vc_sema);
@ -1400,7 +1397,10 @@ bcm2835_cpufreq_set(device_t dev, const struct cf_setting *cf)
{
struct bcm2835_cpufreq_softc *sc;
uint32_t rate_hz, rem;
int cur_freq, resp_freq, arm_freq, min_freq, core_freq;
int resp_freq, arm_freq, min_freq, core_freq;
#ifdef DEBUG
int cur_freq;
#endif
if (cf == NULL || cf->freq < 0)
return (EINVAL);
@ -1425,8 +1425,10 @@ bcm2835_cpufreq_set(device_t dev, const struct cf_setting *cf)
/* set new value and verify it */
VC_LOCK(sc);
#ifdef DEBUG
cur_freq = bcm2835_cpufreq_get_clock_rate(sc,
BCM2835_MBOX_CLOCK_ID_ARM);
#endif
resp_freq = bcm2835_cpufreq_set_clock_rate(sc,
BCM2835_MBOX_CLOCK_ID_ARM, rate_hz);
DELAY(TRANSITION_LATENCY);

3
sys/arm/broadcom/bcm2835/bcm2835_gpio.c
View File

@ -1017,7 +1017,7 @@ bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf,
u_int *irqp, uint32_t *modep)
{
u_int irq;
uint32_t mode, bank;
uint32_t mode;
/*
* The first cell is the interrupt number.
@ -1036,7 +1036,6 @@ bcm_gpio_pic_map_fdt(struct bcm_gpio_softc *sc, struct intr_map_data_fdt *daf,
return (EINVAL);
/* Only reasonable modes are supported. */
bank = BCM_GPIO_BANK(irq);
if (daf->cells[1] == 1)
mode = GPIO_INTR_EDGE_RISING;
else if (daf->cells[1] == 2)

4
sys/arm/broadcom/bcm2835/bcm2835_mbox.c
View File

@ -103,14 +103,18 @@ static struct ofw_compat_data compat_data[] = {
static int
bcm_mbox_read_msg(struct bcm_mbox_softc *sc, int *ochan)
{
#ifdef DEBUG
uint32_t data;
#endif
uint32_t msg;
int chan;
msg = mbox_read_4(sc, REG_READ);
dprintf("bcm_mbox_intr: raw data %08x\n", msg);
chan = MBOX_CHAN(msg);
#ifdef DEBUG
data = MBOX_DATA(msg);
#endif
if (sc->msg[chan]) {
printf("bcm_mbox_intr: channel %d oveflow\n", chan);
return (1);

1
sys/arm/freescale/imx/files.imx6
View File

@ -27,7 +27,6 @@ arm/freescale/imx/imx6_audmux.c optional sound
arm/freescale/imx/imx6_ssi.c optional sound
arm/freescale/imx/imx6_ahci.c optional ahci
dev/hdmi/hdmi_if.m optional hdmi
dev/hdmi/dwc_hdmi.c optional hdmi
arm/freescale/imx/imx6_hdmi.c optional hdmi

58
sys/arm/include/stdarg.h
View File

@ -1,9 +1,7 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2002 David E. O'Brien. All rights reserved.
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
* Copyright (c) 2017 Poul-Henning Kamp. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -13,14 +11,11 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
@ -29,55 +24,16 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)stdarg.h 8.1 (Berkeley) 6/10/93
* $FreeBSD$
*/
#ifndef _MACHINE_STDARG_H_
#define _MACHINE_STDARG_H_
#include <sys/cdefs.h>
#include <sys/_types.h>
#include <sys/_stdarg.h>
#ifndef _VA_LIST_DECLARED
#define _VA_LIST_DECLARED
typedef __va_list va_list;
#ifndef va_start
#error this file needs to be ported to your compiler
#endif
#ifdef __GNUCLIKE_BUILTIN_STDARG
#define va_start(ap, last) \
__builtin_va_start((ap), (last))
#define va_arg(ap, type) \
__builtin_va_arg((ap), type)
#if __ISO_C_VISIBLE >= 1999
#define va_copy(dest, src) \
__builtin_va_copy((dest), (src))
#endif
#define va_end(ap) \
__builtin_va_end(ap)
#else /* !__GNUCLIKE_BUILTIN_STDARG */
#define __va_size(type) \
(((sizeof(type) + sizeof(int) - 1) / sizeof(int)) * sizeof(int))
#ifdef __GNUCLIKE_BUILTIN_NEXT_ARG
#define va_start(ap, last) \
((ap) = (va_list)__builtin_next_arg(last))
#else /* !__GNUCLIKE_BUILTIN_NEXT_ARG */
#define va_start(ap, last) \
((ap) = (va_list)&(last) + __va_size(last))
#endif /* __GNUCLIKE_BUILTIN_NEXT_ARG */
#define va_arg(ap, type) \
(*(type *)((ap) += __va_size(type), (ap) - __va_size(type)))
#define va_end(ap)
#endif /* __GNUCLIKE_BUILTIN_STDARG */
#endif /* !_MACHINE_STDARG_H_ */

10
sys/arm/xscale/ixp425/ixdp425_pci.c
View File

@ -1,6 +1,6 @@
/* $NetBSD: ixdp425_pci.c,v 1.5 2005/12/11 12:17:09 christos Exp $ */
/* $NetBSD: ixdp425_pci.c,v 1.6 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -14,12 +14,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

10
sys/arm/xscale/ixp425/ixdp425reg.h
View File

@ -1,6 +1,6 @@
/* $NetBSD: ixdp425reg.h,v 1.6 2005/12/11 12:17:09 christos Exp $ */
/* $NetBSD: ixdp425reg.h,v 1.7 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -14,12 +14,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

10
sys/arm/xscale/ixp425/ixp425.c
View File

@ -1,7 +1,7 @@
/* $NetBSD: ixp425.c,v 1.10 2005/12/11 12:16:51 christos Exp $ */
/* $NetBSD: ixp425.c,v 1.13 2009/10/21 14:15:50 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -15,12 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

2
sys/arm/xscale/ixp425/ixp425_npe.c
View File

@ -1,5 +1,5 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-License-Identifier: (BSD-2-Clause-FreeBSD AND BSD-3-Clause)
*
* Copyright (c) 2006-2008 Sam Leffler, Errno Consulting
* All rights reserved.

2
sys/arm/xscale/ixp425/ixp425_npereg.h
View File

@ -1,5 +1,5 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-License-Identifier: (BSD-2-Clause-FreeBSD AND BSD-3-Clause)
*
* Copyright (c) 2006 Sam Leffler, Errno Consulting
* All rights reserved.

10
sys/arm/xscale/ixp425/ixp425_pci.c
View File

@ -1,7 +1,7 @@
/* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */
/* $NetBSD: ixp425_pci.c,v 1.6 2009/10/21 14:15:50 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -15,12 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

10
sys/arm/xscale/ixp425/ixp425_pci_space.c
View File

@ -1,7 +1,7 @@
/* $NetBSD: ixp425_pci_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $ */
/* $NetBSD: ixp425_pci_space.c,v 1.7 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -15,12 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

10
sys/arm/xscale/ixp425/ixp425_space.c
View File

@ -1,7 +1,7 @@
/* $NetBSD: ixp425_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $ */
/* $NetBSD: ixp425_space.c,v 1.7 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -15,12 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

10
sys/arm/xscale/ixp425/ixp425_timer.c
View File

@ -1,7 +1,7 @@
/* $NetBSD: ixp425_timer.c,v 1.11 2006/04/10 03:36:03 simonb Exp $ */
/* $NetBSD: ixp425_timer.c,v 1.15 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -15,12 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

10
sys/arm/xscale/ixp425/ixp425reg.h
View File

@ -1,6 +1,6 @@
/* $NetBSD: ixp425reg.h,v 1.19 2005/12/11 12:16:51 christos Exp $ */
/* $NetBSD: ixp425reg.h,v 1.21 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -14,12 +14,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

10
sys/arm/xscale/ixp425/ixp425var.h
View File

@ -1,7 +1,7 @@
/* $NetBSD: ixp425var.h,v 1.10 2006/04/10 03:36:03 simonb Exp $ */
/* $NetBSD: ixp425var.h,v 1.12 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -15,12 +15,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

2
sys/arm64/arm64/gic_v3.c
View File

@ -408,9 +408,7 @@ arm_gic_v3_intr(void *arg)
struct intr_pic *pic;
uint64_t active_irq;
struct trapframe *tf;
bool first;
first = true;
pic = sc->gic_pic;
while (1) {

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