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Enhanced floppy controllers have Data Rate Select Register (DSR) at 0x3f4.

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Use it to reset controller and to select data rate.  According to Intel
80277AA datasheet, software reset behaves the same as DOR reset except
that it is self clearing.  National Semiconductor PC8477B datasheet says
the same.  As a side effect, we no longer use Configuration Control
Register (CCR) at 0x3f7 for these controllers, which is often missing
in modern hardware.
This commit is contained in:
Jung-uk Kim 2006-07-06 21:12:18 +00:00
parent 65ee602e0c
commit 50d99d1a52
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=160137
2 changed files with 30 additions and 8 deletions
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32
sys/dev/fdc/fdc.c
View File

@ -191,6 +191,7 @@ static struct fd_type *fd_native_types[] = {
#define FDO_MOEN3 0x80 /* motor enable drive 3 */
#define FDSTS 4 /* NEC 765 Main Status Register (R) */
#define FDDSR 4 /* Data Rate Select Register (W) */
#define FDDATA 5 /* NEC 765 Data Register (R/W) */
#define FDCTL 7 /* Control Register (W) */
@ -343,6 +344,13 @@ fdsts_rd(struct fdc_data *fdc)
return fdregrd(fdc, FDSTS);
}
static void
fddsr_wr(struct fdc_data *fdc, u_int8_t v)
{
fdregwr(fdc, FDDSR, v);
}
static void
fddata_wr(struct fdc_data *fdc, u_int8_t v)
{
@ -494,13 +502,18 @@ fdc_reset(struct fdc_data *fdc)
{
int i, r[10];
/* Try a reset, keep motor on */
fdout_wr(fdc, fdc->fdout & ~(FDO_FRST|FDO_FDMAEN));
DELAY(100);
/* enable FDC, but defer interrupts a moment */
fdout_wr(fdc, fdc->fdout & ~FDO_FDMAEN);
DELAY(100);
fdout_wr(fdc, fdc->fdout);
if (fdc->fdct == FDC_ENHANCED) {
/* Try a software reset, default precomp, and 500 kb/s */
fddsr_wr(fdc, I8207X_DSR_SR);
} else {
/* Try a hardware reset, keep motor on */
fdout_wr(fdc, fdc->fdout & ~(FDO_FRST|FDO_FDMAEN));
DELAY(100);
/* enable FDC, but defer interrupts a moment */
fdout_wr(fdc, fdc->fdout & ~FDO_FDMAEN);
DELAY(100);
fdout_wr(fdc, fdc->fdout);
}
/* XXX after a reset, silently believe the FDC will accept commands */
if (fdc_cmd(fdc, 3, NE7CMD_SPECIFY, spec1, spec2, 0))
@ -804,7 +817,10 @@ fdc_worker(struct fdc_data *fdc)
/* Select drive, setup params */
fd_select(fd);
fdctl_wr(fdc, fd->ft->trans);
if (fdc->fdct == FDC_ENHANCED)
fddsr_wr(fdc, fd->ft->trans);
else
fdctl_wr(fdc, fd->ft->trans);
if (bp->bio_cmd & BIO_PROBE) {

6
sys/dev/ic/nec765.h
View File

@ -90,6 +90,12 @@
#define NE7_ST3_HD 0x04 /* upper head select */
#define NE7_ST3_US 0x03 /* unit select */
/* Data Rate Select Register DSR (enhanced controller) */
#define I8207X_DSR_SR 0x80 /* software reset */
#define I8207X_DSR_LP 0x40 /* low power */
#define I8207X_DSR_PS 0x1c /* precompensation select */
#define I8207X_DSR_RS 0x03 /* data rate select */
/* Commands */
/*
* the top three bits -- where appropriate -- are set as follows: