Reimport dts files from vendor repo now that it has been properly
trimmed.
This commit is contained in:
commit
50e7b30ffc
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=271143
175
sys/gnu/dts/arm/animeo_ip.dts
Normal file
175
sys/gnu/dts/arm/animeo_ip.dts
Normal file
@ -0,0 +1,175 @@
|
||||
/*
|
||||
* animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
|
||||
*
|
||||
* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2 only.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "at91sam9260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Somfy Animeo IP";
|
||||
compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
serial1 = &usart2;
|
||||
serial2 = &usart0;
|
||||
serial3 = &dbgu;
|
||||
serial4 = &usart3;
|
||||
serial5 = &uart0;
|
||||
serial6 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &usart2;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
usart0: serial@fffb0000 {
|
||||
pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000 {
|
||||
pinctrl-0 = <&pinctrl_usart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffc4000 {
|
||||
pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>;
|
||||
phy-mode = "mii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fffa8000 {
|
||||
pinctrl-0 = <&pinctrl_mmc0_clk
|
||||
&pinctrl_mmc0_slot1_cmd_dat0
|
||||
&pinctrl_mmc0_slot1_dat1_3>;
|
||||
status = "okay";
|
||||
|
||||
slot@1 {
|
||||
reg = <1>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
barebox@0 {
|
||||
label = "barebox";
|
||||
reg = <0x0 0x58000>;
|
||||
};
|
||||
|
||||
u_boot_env@58000 {
|
||||
label = "u_boot_env";
|
||||
reg = <0x58000 0x8000>;
|
||||
};
|
||||
|
||||
ubi@60000 {
|
||||
label = "ubi";
|
||||
reg = <0x60000 0x1FA0000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_green {
|
||||
label = "power_green";
|
||||
gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
power_red {
|
||||
label = "power_red";
|
||||
gpios = <&pioA 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
tx_green {
|
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label = "tx_green";
|
||||
gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
tx_red {
|
||||
label = "tx_red";
|
||||
gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
keyswitch_in {
|
||||
label = "keyswitch_in";
|
||||
gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <28>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
error_in {
|
||||
label = "error_in";
|
||||
gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <29>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
btn {
|
||||
label = "btn";
|
||||
gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <31>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
187
sys/gnu/dts/arm/at91-ariag25.dts
Normal file
187
sys/gnu/dts/arm/at91-ariag25.dts
Normal file
@ -0,0 +1,187 @@
|
||||
/*
|
||||
* at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based)
|
||||
*
|
||||
* Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>,
|
||||
* Robert Nelson <robertcnelson@gmail.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g25.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Acme Systems Aria G25";
|
||||
compatible = "acme,ariag25", "atmel,at91sam9x5ek",
|
||||
"atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
serial4 = &usart3;
|
||||
serial5 = &uart0;
|
||||
serial6 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
/* 128 MB, change this for 256 MB revision */
|
||||
reg = <0x20000000 0x8000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
mmc0: mmc@f0008000 {
|
||||
/* N.B. Aria has no SD card detect (CD), assumed present */
|
||||
|
||||
pinctrl-0 = <
|
||||
&pinctrl_mmc0_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f8014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
pinctrl-0 = <&pinctrl_usart0
|
||||
&pinctrl_usart0_rts
|
||||
&pinctrl_usart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@f8020000 {
|
||||
pinctrl-0 = <&pinctrl_usart1
|
||||
/* &pinctrl_usart1_rts */
|
||||
/* &pinctrl_usart1_cts */
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart2: serial@f8024000 {
|
||||
/* cannot activate RTS2+CTS2, clash with
|
||||
* ethernet on PB0 and PB1 */
|
||||
pinctrl-0 = <&pinctrl_usart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart3: serial@f8028000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8028000 0x200>;
|
||||
interrupts = <8 4 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart3
|
||||
/* &pinctrl_usart3_rts */
|
||||
/* &pinctrl_usart3_cts */
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
/*
|
||||
* following can be overwritten by bootloader:
|
||||
* for example u-boot 'ftd set' command
|
||||
*/
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* UART0/1 pins are marked as GPIO on
|
||||
* Aria documentation.
|
||||
* Change to "okay" if you need additional serial ports
|
||||
*/
|
||||
uart0: serial@f8040000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@f8044000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc0: adc@f804c000 {
|
||||
status = "okay";
|
||||
atmel,adc-channels-used = <0xf>;
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
w1_0 {
|
||||
pinctrl_w1_0: w1_0-0 {
|
||||
atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc@fffffeb0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00600000 {
|
||||
status = "okay";
|
||||
num-ports = <3>;
|
||||
};
|
||||
|
||||
usb1: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
/* little green LED in middle of Aria G25 module */
|
||||
aria_led {
|
||||
label = "aria_led";
|
||||
gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
onewire@0 {
|
||||
compatible = "w1-gpio";
|
||||
gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_w1_0>;
|
||||
};
|
||||
};
|
129
sys/gnu/dts/arm/at91-cosino.dtsi
Normal file
129
sys/gnu/dts/arm/at91-cosino.dtsi
Normal file
@ -0,0 +1,129 @@
|
||||
/*
|
||||
* at91-cosino.dtsi - Device Tree file for Cosino core module
|
||||
*
|
||||
* Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
|
||||
* HCE Engineering
|
||||
*
|
||||
* Derived from at91sam9x5ek.dtsi by:
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include "at91sam9g35.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HCE Cosino core module";
|
||||
compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x8000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
mmc0: mmc@f0008000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0
|
||||
&pinctrl_mmc0_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
adc0: adc@f804c000 {
|
||||
atmel,adc-ts-wires = <4>;
|
||||
atmel,adc-ts-pressure-threshold = <10000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
mmc0 {
|
||||
pinctrl_board_mmc0: mmc0-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
atmel,has-pmecc; /* Enable PMECC */
|
||||
atmel,pmecc-cap = <4>;
|
||||
atmel,pmecc-sector-size = <512>;
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
uboot@40000 {
|
||||
label = "u-boot";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
ubootenv@c0000 {
|
||||
label = "U-Boot Env";
|
||||
reg = <0xc0000 0x140000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
78
sys/gnu/dts/arm/at91-cosino_mega2560.dts
Normal file
78
sys/gnu/dts/arm/at91-cosino_mega2560.dts
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* at91-cosino_mega2560.dts - Device Tree file for Cosino board with
|
||||
* Mega 2560 extension
|
||||
*
|
||||
* Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
|
||||
* HCE Engineering
|
||||
*
|
||||
* Derived from at91sam9g35ek.dts by:
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "at91-cosino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HCE Cosino Mega 2560";
|
||||
compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
adc0: adc@f804c000 {
|
||||
atmel,adc-ts-wires = <4>;
|
||||
atmel,adc-ts-pressure-threshold = <10000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc@fffffeb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@f8020000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart2: serial@f8024000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: gadget@f803c000 {
|
||||
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc1: mmc@f000c000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_mmc1_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc1_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00600000 {
|
||||
status = "okay";
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */
|
||||
&pioD 19 GPIO_ACTIVE_LOW
|
||||
&pioD 20 GPIO_ACTIVE_LOW
|
||||
>;
|
||||
};
|
||||
|
||||
usb1: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
165
sys/gnu/dts/arm/at91-foxg20.dts
Normal file
165
sys/gnu/dts/arm/at91-foxg20.dts
Normal file
@ -0,0 +1,165 @@
|
||||
/*
|
||||
* at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board
|
||||
*
|
||||
* Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC)
|
||||
*
|
||||
* Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g20.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Acme Systems FoxG20";
|
||||
compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fffa8000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_mmc0_clk
|
||||
&pinctrl_mmc0_slot1_cmd_dat0
|
||||
&pinctrl_mmc0_slot1_dat1_3>;
|
||||
status = "okay";
|
||||
|
||||
slot@1 {
|
||||
reg = <1>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_usart0
|
||||
&pinctrl_usart0_rts
|
||||
&pinctrl_usart0_cts
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffc4000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart3: serial@fffd0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart0: serial@fffd4000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@fffd8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
board {
|
||||
pinctrl_pck0_as_mck: pck0_as_mck {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_slot1 {
|
||||
pinctrl_board_mmc0_slot1: mmc0_slot1-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* CD pin */
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
pinctrl_i2c0: i2c0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* TWD (SDA), open drain */
|
||||
AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* TWCK (SCL), open drain */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
i2c-gpio,delay-us = <5>; /* ~85 kHz */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
/* red LED marked "PC7" near mini USB (device) receptacle */
|
||||
user_led {
|
||||
label = "user_led";
|
||||
gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
btn {
|
||||
label = "Button";
|
||||
gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x103>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
193
sys/gnu/dts/arm/at91-qil_a9260.dts
Normal file
193
sys/gnu/dts/arm/at91-qil_a9260.dts
Normal file
@ -0,0 +1,193 @@
|
||||
/*
|
||||
* at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board
|
||||
*
|
||||
* Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9260.dtsi"
|
||||
/ {
|
||||
model = "Calao QIL A9260";
|
||||
compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fffa8000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_mmc0_clk
|
||||
&pinctrl_mmc0_slot0_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_usart0
|
||||
&pinctrl_usart0_rts
|
||||
&pinctrl_usart0_cts
|
||||
&pinctrl_usart0_dtr_dsr
|
||||
&pinctrl_usart0_dcd
|
||||
&pinctrl_usart0_ri>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_usart1
|
||||
&pinctrl_usart1_rts
|
||||
&pinctrl_usart1_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_usart2
|
||||
&pinctrl_usart2_rts
|
||||
&pinctrl_usart2_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffc4000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@fffc8000 {
|
||||
status = "okay";
|
||||
cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
m41t94@0 {
|
||||
compatible = "st,m41t94";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
shdwc@fffffd10 {
|
||||
atmel,wakeup-counter = <10>;
|
||||
atmel,wakeup-rtt-timer;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
barebox@20000 {
|
||||
label = "barebox";
|
||||
reg = <0x20000 0x40000>;
|
||||
};
|
||||
|
||||
bareboxenv@60000 {
|
||||
label = "bareboxenv";
|
||||
reg = <0x60000 0x20000>;
|
||||
};
|
||||
|
||||
bareboxenv2@80000 {
|
||||
label = "bareboxenv2";
|
||||
reg = <0x80000 0x20000>;
|
||||
};
|
||||
|
||||
oftree@a0000 {
|
||||
label = "oftree";
|
||||
reg = <0xa0000 0x20000>;
|
||||
};
|
||||
|
||||
kernel@c0000 {
|
||||
label = "kernel";
|
||||
reg = <0xc0000 0x400000>;
|
||||
};
|
||||
|
||||
rootfs@4c0000 {
|
||||
label = "rootfs";
|
||||
reg = <0x4c0000 0x7800000>;
|
||||
};
|
||||
|
||||
data@7cc0000 {
|
||||
label = "data";
|
||||
reg = <0x7cc0000 0x8340000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user_led {
|
||||
label = "user_led";
|
||||
gpios = <&pioB 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
user_pb {
|
||||
label = "user_pb";
|
||||
gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <28>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
301
sys/gnu/dts/arm/at91-sama5d3_xplained.dts
Normal file
301
sys/gnu/dts/arm/at91-sama5d3_xplained.dts
Normal file
@ -0,0 +1,301 @@
|
||||
/*
|
||||
* at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
|
||||
*
|
||||
* Copyright (C) 2014 Atmel,
|
||||
* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "sama5d36.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SAMA5D3 Xplained";
|
||||
compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x10000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
mmc0: mmc@f0000000 {
|
||||
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@f0004000 {
|
||||
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
can0: can@f000c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f0014000 {
|
||||
pinctrl-0 = <&pinctrl_i2c0_pu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
|
||||
pmic: act8865@5b {
|
||||
compatible = "active-semi,act8865";
|
||||
reg = <0x5b>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
vcc_1v8_reg: DCDC_REG1 {
|
||||
regulator-name = "VCC_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_1v2_reg: DCDC_REG2 {
|
||||
regulator-name = "VCC_1V2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3_reg: DCDC_REG3 {
|
||||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddfuse_reg: LDO_REG1 {
|
||||
regulator-name = "FUSE_2V5";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
};
|
||||
|
||||
vddana_reg: LDO_REG2 {
|
||||
regulator-name = "VDDANA";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
macb0: ethernet@f0028000 {
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm0: pwm@f002c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@f001c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@f0020000 {
|
||||
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart0: serial@f0024000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc1: mmc@f8000000 {
|
||||
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1: spi@f8008000 {
|
||||
cs-gpios = <&pioC 25 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
adc0: adc@f8018000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_adc0_adtrg
|
||||
&pinctrl_adc0_ad0
|
||||
&pinctrl_adc0_ad1
|
||||
&pinctrl_adc0_ad2
|
||||
&pinctrl_adc0_ad3
|
||||
&pinctrl_adc0_ad4
|
||||
&pinctrl_adc0_ad5
|
||||
&pinctrl_adc0_ad6
|
||||
&pinctrl_adc0_ad7
|
||||
&pinctrl_adc0_ad8
|
||||
&pinctrl_adc0_ad9
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c2: i2c@f801c000 {
|
||||
dmas = <0>, <0>; /* Do not use DMA for i2c2 */
|
||||
pinctrl-0 = <&pinctrl_i2c2_pu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb1: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff200 {
|
||||
board {
|
||||
pinctrl_i2c0_pu: i2c0_pu {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_pu: i2c2_pu {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
pinctrl_mmc0_cd: mmc0_cd {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
|
||||
pinctrl_mmc1_cd: mmc1_cd {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
|
||||
pinctrl_usba_vbus: usba_vbus {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
main: mainck {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@60000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
atmel,has-pmecc;
|
||||
atmel,pmecc-cap = <4>;
|
||||
atmel,pmecc-sector-size = <512>;
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
bootloader@40000 {
|
||||
label = "bootloader";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
bootloaderenv@c0000 {
|
||||
label = "bootloader env";
|
||||
reg = <0xc0000 0xc0000>;
|
||||
};
|
||||
|
||||
dtb@180000 {
|
||||
label = "device tree";
|
||||
reg = <0x180000 0x80000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: gadget@00500000 {
|
||||
atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usba_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: ohci@00600000 {
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0
|
||||
&pioE 3 GPIO_ACTIVE_LOW
|
||||
&pioE 4 GPIO_ACTIVE_LOW
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
bp3 {
|
||||
label = "PB_USER";
|
||||
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x104>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d2 {
|
||||
label = "d2";
|
||||
gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
d3 {
|
||||
label = "d3";
|
||||
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
947
sys/gnu/dts/arm/at91rm9200.dtsi
Normal file
947
sys/gnu/dts/arm/at91rm9200.dtsi
Normal file
@ -0,0 +1,947 @@
|
||||
/*
|
||||
* at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
|
||||
*
|
||||
* Copyright (C) 2011 Atmel,
|
||||
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
|
||||
* 2012 Joachim Eastwood <manabian@gmail.com>
|
||||
*
|
||||
* Based on at91sam9260.dtsi
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91RM9200 family SoC";
|
||||
compatible = "atmel,at91rm9200";
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
serial4 = &usart3;
|
||||
gpio0 = &pioA;
|
||||
gpio1 = &pioB;
|
||||
gpio2 = &pioC;
|
||||
gpio3 = &pioD;
|
||||
tcb0 = &tcb0;
|
||||
tcb1 = &tcb1;
|
||||
i2c0 = &i2c0;
|
||||
ssc0 = &ssc0;
|
||||
ssc1 = &ssc1;
|
||||
ssc2 = &ssc2;
|
||||
};
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm920t";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x04000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
slow_xtal: slow_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
main_xtal: main_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
aic: interrupt-controller@fffff000 {
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
reg = <0xfffff000 0x200>;
|
||||
atmel,external-irqs = <25 26 27 28 29 30 31>;
|
||||
};
|
||||
|
||||
ramc0: ramc@ffffff00 {
|
||||
compatible = "atmel,at91rm9200-sdramc";
|
||||
reg = <0xffffff00 0x100>;
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
compatible = "atmel,at91rm9200-pmc";
|
||||
reg = <0xfffffc00 0x100>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
main_osc: main_osc {
|
||||
compatible = "atmel,at91rm9200-clk-main-osc";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
|
||||
clocks = <&main_xtal>;
|
||||
};
|
||||
|
||||
main: mainck {
|
||||
compatible = "atmel,at91rm9200-clk-main";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&main_osc>;
|
||||
};
|
||||
|
||||
plla: pllack {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
|
||||
clocks = <&main>;
|
||||
reg = <0>;
|
||||
atmel,clk-input-range = <1000000 32000000>;
|
||||
#atmel,pll-clk-output-range-cells = <3>;
|
||||
atmel,pll-clk-output-ranges = <80000000 160000000 0>,
|
||||
<150000000 180000000 2>;
|
||||
};
|
||||
|
||||
pllb: pllbck {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
|
||||
clocks = <&main>;
|
||||
reg = <1>;
|
||||
atmel,clk-input-range = <1000000 32000000>;
|
||||
#atmel,pll-clk-output-range-cells = <3>;
|
||||
atmel,pll-clk-output-ranges = <80000000 160000000 0>,
|
||||
<150000000 180000000 2>;
|
||||
};
|
||||
|
||||
mck: masterck {
|
||||
compatible = "atmel,at91rm9200-clk-master";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
||||
atmel,clk-output-range = <0 80000000>;
|
||||
atmel,clk-divisors = <1 2 3 4>;
|
||||
};
|
||||
|
||||
usb: usbck {
|
||||
compatible = "atmel,at91rm9200-clk-usb";
|
||||
#clock-cells = <0>;
|
||||
atmel,clk-divisors = <1 2>;
|
||||
clocks = <&pllb>;
|
||||
};
|
||||
|
||||
prog: progck {
|
||||
compatible = "atmel,at91rm9200-clk-programmable";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
||||
|
||||
prog0: prog0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0>;
|
||||
interrupts = <AT91_PMC_PCKRDY(0)>;
|
||||
};
|
||||
|
||||
prog1: prog1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <1>;
|
||||
interrupts = <AT91_PMC_PCKRDY(1)>;
|
||||
};
|
||||
|
||||
prog2: prog2 {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
interrupts = <AT91_PMC_PCKRDY(2)>;
|
||||
};
|
||||
|
||||
prog3: prog3 {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
interrupts = <AT91_PMC_PCKRDY(3)>;
|
||||
};
|
||||
};
|
||||
|
||||
systemck {
|
||||
compatible = "atmel,at91rm9200-clk-system";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
udpck: udpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
uhpck: uhpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
pck0: pck0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
clocks = <&prog0>;
|
||||
};
|
||||
|
||||
pck1: pck1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
clocks = <&prog1>;
|
||||
};
|
||||
|
||||
pck2: pck2 {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
clocks = <&prog2>;
|
||||
};
|
||||
|
||||
pck3: pck3 {
|
||||
#clock-cells = <0>;
|
||||
reg = <11>;
|
||||
clocks = <&prog3>;
|
||||
};
|
||||
};
|
||||
|
||||
periphck {
|
||||
compatible = "atmel,at91rm9200-clk-peripheral";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mck>;
|
||||
|
||||
pioA_clk: pioA_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
pioB_clk: pioB_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
pioC_clk: pioC_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
pioD_clk: pioD_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
usart0_clk: usart0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
usart1_clk: usart1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
usart2_clk: usart2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
usart3_clk: usart3_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
mci0_clk: mci0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
};
|
||||
|
||||
udc_clk: udc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <11>;
|
||||
};
|
||||
|
||||
twi0_clk: twi0_clk {
|
||||
reg = <12>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
spi0_clk: spi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <13>;
|
||||
};
|
||||
|
||||
ssc0_clk: ssc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <14>;
|
||||
};
|
||||
|
||||
ssc1_clk: ssc1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <15>;
|
||||
};
|
||||
|
||||
ssc2_clk: ssc2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
tc0_clk: tc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
tc1_clk: tc1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
tc2_clk: tc2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <19>;
|
||||
};
|
||||
|
||||
tc3_clk: tc3_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <20>;
|
||||
};
|
||||
|
||||
tc4_clk: tc4_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <21>;
|
||||
};
|
||||
|
||||
tc5_clk: tc5_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <22>;
|
||||
};
|
||||
|
||||
ohci_clk: ohci_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <23>;
|
||||
};
|
||||
|
||||
macb0_clk: macb0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
st: timer@fffffd00 {
|
||||
compatible = "atmel,at91rm9200-st";
|
||||
reg = <0xfffffd00 0x100>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
};
|
||||
|
||||
tcb0: timer@fffa0000 {
|
||||
compatible = "atmel,at91rm9200-tcb";
|
||||
reg = <0xfffa0000 0x100>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
|
||||
18 IRQ_TYPE_LEVEL_HIGH 0
|
||||
19 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
|
||||
clock-names = "t0_clk", "t1_clk", "t2_clk";
|
||||
};
|
||||
|
||||
tcb1: timer@fffa4000 {
|
||||
compatible = "atmel,at91rm9200-tcb";
|
||||
reg = <0xfffa4000 0x100>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
|
||||
21 IRQ_TYPE_LEVEL_HIGH 0
|
||||
22 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
|
||||
clock-names = "t0_clk", "t1_clk", "t2_clk";
|
||||
};
|
||||
|
||||
i2c0: i2c@fffb8000 {
|
||||
compatible = "atmel,at91rm9200-i2c";
|
||||
reg = <0xfffb8000 0x4000>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_twi>;
|
||||
clocks = <&twi0_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@fffb4000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xfffb4000 0x4000>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&mci0_clk>;
|
||||
clock-names = "mci_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssc0: ssc@fffd0000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfffd0000 0x4000>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
||||
clocks = <&ssc0_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
ssc1: ssc@fffd4000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfffd4000 0x4000>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
|
||||
clocks = <&ssc1_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
ssc2: ssc@fffd8000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfffd8000 0x4000>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
|
||||
clocks = <&ssc2_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffbc000 {
|
||||
compatible = "cdns,at91rm9200-emac", "cdns,emac";
|
||||
reg = <0xfffbc000 0x4000>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_macb_rmii>;
|
||||
clocks = <&macb0_clk>;
|
||||
clock-names = "ether_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xffffffff 0xffffffff /* pioA */
|
||||
0xffffffff 0x083fffff /* pioB */
|
||||
0xffff3fff 0x00000000 /* pioC */
|
||||
0x03ff87ff 0x0fffff80 /* pioD */
|
||||
>;
|
||||
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
|
||||
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
|
||||
AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart0_cts: uart0_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart0_rts: uart0_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */
|
||||
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_rts: uart1_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_cts: uart1_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
|
||||
AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_dcd: uart1_dcd-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_ri: uart1_ri-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2: uart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */
|
||||
AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_uart2_rts: uart2_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
|
||||
};
|
||||
|
||||
pinctrl_uart2_cts: uart2_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3: uart3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
|
||||
AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */
|
||||
};
|
||||
|
||||
pinctrl_uart3_rts: uart3_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
|
||||
};
|
||||
|
||||
pinctrl_uart3_cts: uart3_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */
|
||||
AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
macb {
|
||||
pinctrl_macb_rmii: macb_rmii-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */
|
||||
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */
|
||||
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
|
||||
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
|
||||
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
|
||||
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
|
||||
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
|
||||
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
|
||||
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
|
||||
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
|
||||
};
|
||||
|
||||
pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */
|
||||
AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */
|
||||
AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */
|
||||
AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */
|
||||
AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */
|
||||
AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */
|
||||
AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */
|
||||
AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
mmc0 {
|
||||
pinctrl_mmc0_clk: mmc0_clk-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
|
||||
AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
|
||||
AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
|
||||
AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
|
||||
AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */
|
||||
AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
|
||||
AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
ssc0 {
|
||||
pinctrl_ssc0_tx: ssc0_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
|
||||
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
|
||||
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */
|
||||
};
|
||||
|
||||
pinctrl_ssc0_rx: ssc0_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
|
||||
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
|
||||
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
ssc1 {
|
||||
pinctrl_ssc1_tx: ssc1_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
|
||||
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
|
||||
AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
|
||||
};
|
||||
|
||||
pinctrl_ssc1_rx: ssc1_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
|
||||
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
|
||||
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
ssc2 {
|
||||
pinctrl_ssc2_tx: ssc2_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
|
||||
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
|
||||
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
|
||||
};
|
||||
|
||||
pinctrl_ssc2_rx: ssc2_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
|
||||
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
|
||||
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
twi {
|
||||
pinctrl_twi: twi-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */
|
||||
AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */
|
||||
};
|
||||
|
||||
pinctrl_twi_gpio: twi_gpio-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
|
||||
AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */
|
||||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb1 {
|
||||
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
pinctrl_spi0: spi0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
|
||||
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
|
||||
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioA_clk>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioB_clk>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioC_clk>;
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioD_clk>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91rm9200-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
clocks = <&mck>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@fffc0000 {
|
||||
compatible = "atmel,at91rm9200-usart";
|
||||
reg = <0xfffc0000 0x200>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&usart0_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@fffc4000 {
|
||||
compatible = "atmel,at91rm9200-usart";
|
||||
reg = <0xfffc4000 0x200>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&usart1_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@fffc8000 {
|
||||
compatible = "atmel,at91rm9200-usart";
|
||||
reg = <0xfffc8000 0x200>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&usart2_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@fffcc000 {
|
||||
compatible = "atmel,at91rm9200-usart";
|
||||
reg = <0xfffcc000 0x200>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&usart3_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: gadget@fffb0000 {
|
||||
compatible = "atmel,at91rm9200-udc";
|
||||
reg = <0xfffb0000 0x4000>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&udc_clk>, <&udpck>;
|
||||
clock-names = "pclk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@fffe0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xfffe0000 0x200>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&spi0_clk>;
|
||||
clock-names = "spi_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
compatible = "atmel,at91rm9200-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40000000 0x10000000>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
nand-ecc-mode = "soft";
|
||||
gpios = <&pioC 2 GPIO_ACTIVE_HIGH
|
||||
0
|
||||
&pioB 1 GPIO_ACTIVE_HIGH
|
||||
>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb0: ohci@00300000 {
|
||||
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
||||
reg = <0x00300000 0x100000>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
|
||||
&pioA 26 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,sda-open-drain;
|
||||
i2c-gpio,scl-open-drain;
|
||||
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_twi_gpio>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
17
sys/gnu/dts/arm/at91rm9200_pqfp.dtsi
Normal file
17
sys/gnu/dts/arm/at91rm9200_pqfp.dtsi
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC
|
||||
*
|
||||
* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include "at91rm9200.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200";
|
||||
};
|
||||
|
||||
&pioD {
|
||||
status = "disabled";
|
||||
};
|
137
sys/gnu/dts/arm/at91rm9200ek.dts
Normal file
137
sys/gnu/dts/arm/at91rm9200ek.dts
Normal file
@ -0,0 +1,137 @@
|
||||
/*
|
||||
* at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit
|
||||
*
|
||||
* Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
|
||||
*
|
||||
* Licensed under GPLv2 only
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91rm9200.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91RM9200 evaluation kit";
|
||||
compatible = "atmel,at91rm9200ek", "atmel,at91rm9200";
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
usb1: gadget@fffb0000 {
|
||||
atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
|
||||
atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffbc000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy {
|
||||
interrupt-parent = <&pioC>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@fffc4000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_uart1
|
||||
&pinctrl_uart1_rts
|
||||
&pinctrl_uart1_cts
|
||||
&pinctrl_uart1_dtr_dsr
|
||||
&pinctrl_uart1_dcd
|
||||
&pinctrl_uart1_ri>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@fffe0000 {
|
||||
status = "okay";
|
||||
cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <15000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00300000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
nor_flash@10000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x10000000 0x800000>;
|
||||
linux,mtd-name = "physmap-flash.0";
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
barebox@0 {
|
||||
label = "barebox";
|
||||
reg = <0x00000 0x40000>;
|
||||
};
|
||||
|
||||
bareboxenv@40000 {
|
||||
label = "bareboxenv";
|
||||
reg = <0x40000 0x10000>;
|
||||
};
|
||||
|
||||
kernel@50000 {
|
||||
label = "kernel";
|
||||
reg = <0x50000 0x300000>;
|
||||
};
|
||||
|
||||
root@350000 {
|
||||
label = "root";
|
||||
reg = <0x350000 0x4B0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds2 {
|
||||
label = "green";
|
||||
gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
ds4 {
|
||||
label = "yellow";
|
||||
gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds6 {
|
||||
label = "red";
|
||||
gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
1013
sys/gnu/dts/arm/at91sam9260.dtsi
Normal file
1013
sys/gnu/dts/arm/at91sam9260.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
853
sys/gnu/dts/arm/at91sam9261.dtsi
Normal file
853
sys/gnu/dts/arm/at91sam9261.dtsi
Normal file
@ -0,0 +1,853 @@
|
||||
/*
|
||||
* at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
|
||||
*
|
||||
* Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
|
||||
*
|
||||
* Licensed under GPLv2 only.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9261 family SoC";
|
||||
compatible = "atmel,at91sam9261";
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
gpio0 = &pioA;
|
||||
gpio1 = &pioB;
|
||||
gpio2 = &pioC;
|
||||
tcb0 = &tcb0;
|
||||
i2c0 = &i2c0;
|
||||
ssc0 = &ssc0;
|
||||
ssc1 = &ssc1;
|
||||
ssc2 = &ssc2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x08000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
main_xtal: main_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
slow_xtal: slow_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
||||
reg = <0x00500000 0x100000>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fb0: fb@0x00600000 {
|
||||
compatible = "atmel,at91sam9261-lcdc";
|
||||
reg = <0x00600000 0x1000>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fb>;
|
||||
clocks = <&lcd_clk>, <&hclk1>;
|
||||
clock-names = "lcdc_clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
compatible = "atmel,at91rm9200-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40000000 0x10000000>;
|
||||
atmel,nand-addr-offset = <22>;
|
||||
atmel,nand-cmd-offset = <21>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
|
||||
gpios = <&pioC 15 GPIO_ACTIVE_HIGH>,
|
||||
<&pioC 14 GPIO_ACTIVE_HIGH>,
|
||||
<0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
tcb0: timer@fffa0000 {
|
||||
compatible = "atmel,at91rm9200-tcb";
|
||||
reg = <0xfffa0000 0x100>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<18 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<19 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
|
||||
clock-names = "t0_clk", "t1_clk", "t2_clk";
|
||||
};
|
||||
|
||||
usb1: gadget@fffa4000 {
|
||||
compatible = "atmel,at91rm9200-udc";
|
||||
reg = <0xfffa4000 0x4000>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&udc_clk>, <&udpck>;
|
||||
clock-names = "usb_clk", "udc_clk", "udpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@fffa8000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xfffa8000 0x600>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mci0_clk>;
|
||||
clock-names = "mci_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@fffac000 {
|
||||
compatible = "atmel,at91sam9261-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c_twi>;
|
||||
reg = <0xfffac000 0x100>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&twi0_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffb0000 0x200>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart0>;
|
||||
clocks = <&usart0_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffb4000 0x200>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart1>;
|
||||
clocks = <&usart1_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000{
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffb8000 0x200>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart2>;
|
||||
clocks = <&usart2_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssc0: ssc@fffbc000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfffbc000 0x4000>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
||||
clocks = <&ssc0_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssc1: ssc@fffc0000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfffc0000 0x4000>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
|
||||
clocks = <&ssc1_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssc2: ssc@fffc4000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfffc4000 0x4000>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
|
||||
clocks = <&ssc2_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@fffc8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xfffc8000 0x200>;
|
||||
cs-gpios = <0>, <0>, <0>, <0>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&spi0_clk>;
|
||||
clock-names = "spi_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@fffcc000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xfffcc000 0x200>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&spi1_clk>;
|
||||
clock-names = "spi_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ramc: ramc@ffffea00 {
|
||||
compatible = "atmel,at91sam9260-sdramc";
|
||||
reg = <0xffffea00 0x200>;
|
||||
};
|
||||
|
||||
matrix: matrix@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-bus-matrix";
|
||||
reg = <0xffffee00 0x200>;
|
||||
};
|
||||
|
||||
aic: interrupt-controller@fffff000 {
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
reg = <0xfffff000 0x200>;
|
||||
atmel,external-irqs = <29 30 31>;
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
clocks = <&mck>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff400 0xfffff400 0x600>;
|
||||
|
||||
atmel,mux-mask =
|
||||
/* A B */
|
||||
<0xffffffff 0xfffffff7>, /* pioA */
|
||||
<0xffffffff 0xfffffff4>, /* pioB */
|
||||
<0xffffffff 0xffffff07>; /* pioC */
|
||||
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
};
|
||||
|
||||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_usart0_rts: usart0_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_usart0_cts: usart0_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_usart1_rts: usart1_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_usart1_cts: usart1_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_usart2_rts: usart2_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_usart2_cts: usart2_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0 {
|
||||
pinctrl_mmc0_clk: mmc0_clk-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
};
|
||||
|
||||
ssc0 {
|
||||
pinctrl_ssc0_tx: ssc0_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_ssc0_rx: ssc0_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
ssc1 {
|
||||
pinctrl_ssc1_tx: ssc1_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_ssc1_rx: ssc1_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
ssc2 {
|
||||
pinctrl_ssc2_tx: ssc2_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_ssc2_rx: ssc2_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
pinctrl_spi0: spi0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1 {
|
||||
pinctrl_spi1: spi1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
pinctrl_i2c_bitbang: i2c-0-bitbang {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
|
||||
};
|
||||
pinctrl_i2c_twi: i2c-0-twi {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
fb {
|
||||
pinctrl_fb: fb-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioA_clk>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioB_clk>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioC_clk>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
compatible = "atmel,at91rm9200-pmc";
|
||||
reg = <0xfffffc00 0x100>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
main_osc: main_osc {
|
||||
compatible = "atmel,at91rm9200-clk-main-osc";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
|
||||
clocks = <&main_xtal>;
|
||||
};
|
||||
|
||||
main: mainck {
|
||||
compatible = "atmel,at91rm9200-clk-main";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&main_osc>;
|
||||
};
|
||||
|
||||
plla: pllack {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
|
||||
clocks = <&main>;
|
||||
reg = <0>;
|
||||
atmel,clk-input-range = <1000000 32000000>;
|
||||
#atmel,pll-clk-output-range-cells = <4>;
|
||||
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
|
||||
<190000000 240000000 2 1>;
|
||||
};
|
||||
|
||||
pllb: pllbck {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
|
||||
clocks = <&main>;
|
||||
reg = <1>;
|
||||
atmel,clk-input-range = <1000000 5000000>;
|
||||
#atmel,pll-clk-output-range-cells = <4>;
|
||||
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
|
||||
};
|
||||
|
||||
mck: masterck {
|
||||
compatible = "atmel,at91rm9200-clk-master";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
||||
atmel,clk-output-range = <0 94000000>;
|
||||
atmel,clk-divisors = <1 2 4 0>;
|
||||
};
|
||||
|
||||
usb: usbck {
|
||||
compatible = "atmel,at91rm9200-clk-usb";
|
||||
#clock-cells = <0>;
|
||||
atmel,clk-divisors = <1 2 4 0>;
|
||||
clocks = <&pllb>;
|
||||
};
|
||||
|
||||
prog: progck {
|
||||
compatible = "atmel,at91rm9200-clk-programmable";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
||||
|
||||
prog0: prog0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0>;
|
||||
interrupts = <AT91_PMC_PCKRDY(0)>;
|
||||
};
|
||||
|
||||
prog1: prog1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <1>;
|
||||
interrupts = <AT91_PMC_PCKRDY(1)>;
|
||||
};
|
||||
|
||||
prog2: prog2 {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
interrupts = <AT91_PMC_PCKRDY(2)>;
|
||||
};
|
||||
|
||||
prog3: prog3 {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
interrupts = <AT91_PMC_PCKRDY(3)>;
|
||||
};
|
||||
};
|
||||
|
||||
systemck {
|
||||
compatible = "atmel,at91rm9200-clk-system";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
uhpck: uhpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
udpck: udpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
pck0: pck0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
clocks = <&prog0>;
|
||||
};
|
||||
|
||||
pck1: pck1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
clocks = <&prog1>;
|
||||
};
|
||||
|
||||
pck2: pck2 {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
clocks = <&prog2>;
|
||||
};
|
||||
|
||||
pck3: pck3 {
|
||||
#clock-cells = <0>;
|
||||
reg = <11>;
|
||||
clocks = <&prog3>;
|
||||
};
|
||||
|
||||
hclk0: hclk0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <16>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
hclk1: hclk1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <17>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
};
|
||||
|
||||
periphck {
|
||||
compatible = "atmel,at91rm9200-clk-peripheral";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mck>;
|
||||
|
||||
pioA_clk: pioA_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
pioB_clk: pioB_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
pioC_clk: pioC_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
usart0_clk: usart0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
usart1_clk: usart1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
usart2_clk: usart2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
mci0_clk: mci0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
udc_clk: udc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
};
|
||||
|
||||
twi0_clk: twi0_clk {
|
||||
reg = <11>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
spi0_clk: spi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <12>;
|
||||
};
|
||||
|
||||
spi1_clk: spi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <13>;
|
||||
};
|
||||
|
||||
ssc0_clk: ssc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <14>;
|
||||
};
|
||||
|
||||
ssc1_clk: ssc1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <15>;
|
||||
};
|
||||
|
||||
ssc2_clk: ssc2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
tc0_clk: tc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
tc1_clk: tc1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
tc2_clk: tc2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <19>;
|
||||
};
|
||||
|
||||
ohci_clk: ohci_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <20>;
|
||||
};
|
||||
|
||||
lcd_clk: lcd_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <21>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rstc@fffffd00 {
|
||||
compatible = "atmel,at91sam9260-rstc";
|
||||
reg = <0xfffffd00 0x10>;
|
||||
};
|
||||
|
||||
shdwc@fffffd10 {
|
||||
compatible = "atmel,at91sam9260-shdwc";
|
||||
reg = <0xfffffd10 0x10>;
|
||||
};
|
||||
|
||||
pit: timer@fffffd30 {
|
||||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xfffffd30 0xf>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
compatible = "atmel,at91sam9260-wdt";
|
||||
reg = <0xfffffd40 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
compatible = "i2c-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c_bitbang>;
|
||||
gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
|
||||
<&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
|
||||
i2c-gpio,sda-open-drain;
|
||||
i2c-gpio,scl-open-drain;
|
||||
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
219
sys/gnu/dts/arm/at91sam9261ek.dts
Normal file
219
sys/gnu/dts/arm/at91sam9261ek.dts
Normal file
@ -0,0 +1,219 @@
|
||||
/*
|
||||
* at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
|
||||
*
|
||||
* Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
|
||||
*
|
||||
* Licensed under GPLv2 only.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9261.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel at91sam9261ek";
|
||||
compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
usb0: ohci@00500000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fb0: fb@0x00600000 {
|
||||
display = <&display0>;
|
||||
atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
display0: display {
|
||||
bits-per-pixel = <16>;
|
||||
atmel,lcdcon-backlight;
|
||||
atmel,dmacon = <0x1>;
|
||||
atmel,lcdcon2 = <0x80008002>;
|
||||
atmel,guard-time = <1>;
|
||||
atmel,lcd-wiring-mode = "BRG";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <4965000>;
|
||||
hactive = <240>;
|
||||
vactive = <320>;
|
||||
hback-porch = <1>;
|
||||
hfront-porch = <33>;
|
||||
vback-porch = <1>;
|
||||
vfront-porch = <0>;
|
||||
hsync-len = <5>;
|
||||
vsync-len = <1>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
bootloader@40000 {
|
||||
label = "bootloader";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
bootloaderenv@c0000 {
|
||||
label = "bootloader env";
|
||||
reg = <0xc0000 0xc0000>;
|
||||
};
|
||||
|
||||
dtb@180000 {
|
||||
label = "device tree";
|
||||
reg = <0x180000 0x80000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
|
||||
apb {
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@fffc8000 {
|
||||
cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;
|
||||
status = "okay";
|
||||
|
||||
mtd_dataflash@0 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <15000000>;
|
||||
};
|
||||
|
||||
tsc2046@0 {
|
||||
reg = <2>;
|
||||
compatible = "ti,ads7843";
|
||||
interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;
|
||||
spi-max-frequency = <3000000>;
|
||||
pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ti,x-min = /bits/ 16 <150>;
|
||||
ti,x-max = /bits/ 16 <3830>;
|
||||
ti,y-min = /bits/ 16 <190>;
|
||||
ti,y-max = /bits/ 16 <3830>;
|
||||
ti,vref-delay-usecs = /bits/ 16 <450>;
|
||||
ti,x-plate-ohms = /bits/ 16 <450>;
|
||||
ti,y-plate-ohms = /bits/ 16 <250>;
|
||||
ti,pressure-max = /bits/ 16 <15000>;
|
||||
ti,debounce-rep = /bits/ 16 <0>;
|
||||
ti,debounce-tol = /bits/ 16 <65535>;
|
||||
ti,debounce-max = /bits/ 16 <1>;
|
||||
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds8 {
|
||||
label = "ds8";
|
||||
gpios = <&pioA 13 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
ds7 {
|
||||
label = "ds7";
|
||||
gpios = <&pioA 14 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "nand-disk";
|
||||
};
|
||||
|
||||
ds1 {
|
||||
label = "ds1";
|
||||
gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button_0 {
|
||||
label = "button_0";
|
||||
gpios = <&pioA 27 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <256>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
button_1 {
|
||||
label = "button_1";
|
||||
gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <257>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
button_2 {
|
||||
label = "button_2";
|
||||
gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <258>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
button_3 {
|
||||
label = "button_3";
|
||||
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <259>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
952
sys/gnu/dts/arm/at91sam9263.dtsi
Normal file
952
sys/gnu/dts/arm/at91sam9263.dtsi
Normal file
@ -0,0 +1,952 @@
|
||||
/*
|
||||
* at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2 only.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9263 family SoC";
|
||||
compatible = "atmel,at91sam9263";
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
gpio0 = &pioA;
|
||||
gpio1 = &pioB;
|
||||
gpio2 = &pioC;
|
||||
gpio3 = &pioD;
|
||||
gpio4 = &pioE;
|
||||
tcb0 = &tcb0;
|
||||
i2c0 = &i2c0;
|
||||
ssc0 = &ssc0;
|
||||
ssc1 = &ssc1;
|
||||
pwm0 = &pwm0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x08000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
main_xtal: main_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
slow_xtal: slow_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
aic: interrupt-controller@fffff000 {
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
reg = <0xfffff000 0x200>;
|
||||
atmel,external-irqs = <30 31>;
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
compatible = "atmel,at91rm9200-pmc";
|
||||
reg = <0xfffffc00 0x100>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
main_osc: main_osc {
|
||||
compatible = "atmel,at91rm9200-clk-main-osc";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
|
||||
clocks = <&main_xtal>;
|
||||
};
|
||||
|
||||
main: mainck {
|
||||
compatible = "atmel,at91rm9200-clk-main";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&main_osc>;
|
||||
};
|
||||
|
||||
plla: pllack {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
|
||||
clocks = <&main>;
|
||||
reg = <0>;
|
||||
atmel,clk-input-range = <1000000 32000000>;
|
||||
#atmel,pll-clk-output-range-cells = <4>;
|
||||
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
|
||||
<190000000 240000000 2 1>;
|
||||
};
|
||||
|
||||
pllb: pllbck {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
|
||||
clocks = <&main>;
|
||||
reg = <1>;
|
||||
atmel,clk-input-range = <1000000 5000000>;
|
||||
#atmel,pll-clk-output-range-cells = <4>;
|
||||
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
|
||||
};
|
||||
|
||||
mck: masterck {
|
||||
compatible = "atmel,at91rm9200-clk-master";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
||||
atmel,clk-output-range = <0 120000000>;
|
||||
atmel,clk-divisors = <1 2 4 0>;
|
||||
};
|
||||
|
||||
usb: usbck {
|
||||
compatible = "atmel,at91rm9200-clk-usb";
|
||||
#clock-cells = <0>;
|
||||
atmel,clk-divisors = <1 2 4 0>;
|
||||
clocks = <&pllb>;
|
||||
};
|
||||
|
||||
prog: progck {
|
||||
compatible = "atmel,at91rm9200-clk-programmable";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
||||
|
||||
prog0: prog0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0>;
|
||||
interrupts = <AT91_PMC_PCKRDY(0)>;
|
||||
};
|
||||
|
||||
prog1: prog1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <1>;
|
||||
interrupts = <AT91_PMC_PCKRDY(1)>;
|
||||
};
|
||||
|
||||
prog2: prog2 {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
interrupts = <AT91_PMC_PCKRDY(2)>;
|
||||
};
|
||||
|
||||
prog3: prog3 {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
interrupts = <AT91_PMC_PCKRDY(3)>;
|
||||
};
|
||||
};
|
||||
|
||||
systemck {
|
||||
compatible = "atmel,at91rm9200-clk-system";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
uhpck: uhpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
udpck: udpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
pck0: pck0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
clocks = <&prog0>;
|
||||
};
|
||||
|
||||
pck1: pck1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
clocks = <&prog1>;
|
||||
};
|
||||
|
||||
pck2: pck2 {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
clocks = <&prog2>;
|
||||
};
|
||||
|
||||
pck3: pck3 {
|
||||
#clock-cells = <0>;
|
||||
reg = <11>;
|
||||
clocks = <&prog3>;
|
||||
};
|
||||
};
|
||||
|
||||
periphck {
|
||||
compatible = "atmel,at91rm9200-clk-peripheral";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mck>;
|
||||
|
||||
pioA_clk: pioA_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
pioB_clk: pioB_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
pioCDE_clk: pioCDE_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
usart0_clk: usart0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
usart1_clk: usart1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
usart2_clk: usart2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
mci0_clk: mci0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
};
|
||||
|
||||
mci1_clk: mci1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <11>;
|
||||
};
|
||||
|
||||
can_clk: can_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <12>;
|
||||
};
|
||||
|
||||
twi0_clk: twi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <13>;
|
||||
};
|
||||
|
||||
spi0_clk: spi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <14>;
|
||||
};
|
||||
|
||||
spi1_clk: spi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <15>;
|
||||
};
|
||||
|
||||
ssc0_clk: ssc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
ssc1_clk: ssc1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
ac91_clk: ac97_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
tcb_clk: tcb_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <19>;
|
||||
};
|
||||
|
||||
pwm_clk: pwm_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <20>;
|
||||
};
|
||||
|
||||
macb0_clk: macb0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <21>;
|
||||
};
|
||||
|
||||
g2de_clk: g2de_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <23>;
|
||||
};
|
||||
|
||||
udc_clk: udc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <24>;
|
||||
};
|
||||
|
||||
isi_clk: isi_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <25>;
|
||||
};
|
||||
|
||||
lcd_clk: lcd_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <26>;
|
||||
};
|
||||
|
||||
dma_clk: dma_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <27>;
|
||||
};
|
||||
|
||||
ohci_clk: ohci_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <29>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ramc: ramc@ffffe200 {
|
||||
compatible = "atmel,at91sam9260-sdramc";
|
||||
reg = <0xffffe200 0x200
|
||||
0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
pit: timer@fffffd30 {
|
||||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xfffffd30 0xf>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
tcb0: timer@fff7c000 {
|
||||
compatible = "atmel,at91rm9200-tcb";
|
||||
reg = <0xfff7c000 0x100>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tcb_clk>;
|
||||
clock-names = "t0_clk";
|
||||
};
|
||||
|
||||
rstc@fffffd00 {
|
||||
compatible = "atmel,at91sam9260-rstc";
|
||||
reg = <0xfffffd00 0x10>;
|
||||
};
|
||||
|
||||
shdwc@fffffd10 {
|
||||
compatible = "atmel,at91sam9260-shdwc";
|
||||
reg = <0xfffffd10 0x10>;
|
||||
};
|
||||
|
||||
pinctrl@fffff200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff200 0xfffff200 0xa00>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xfffffffb 0xffffe07f /* pioA */
|
||||
0x0007ffff 0x39072fff /* pioB */
|
||||
0xffffffff 0x3ffffff8 /* pioC */
|
||||
0xfffffbff 0xffffffff /* pioD */
|
||||
0xffe00fff 0xfbfcff00 /* pioE */
|
||||
>;
|
||||
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
|
||||
AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */
|
||||
AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
|
||||
};
|
||||
|
||||
pinctrl_usart0_rts: usart0_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
|
||||
};
|
||||
|
||||
pinctrl_usart0_cts: usart0_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
|
||||
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */
|
||||
};
|
||||
|
||||
pinctrl_usart1_rts: usart1_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart1_cts: usart1_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
|
||||
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */
|
||||
};
|
||||
|
||||
pinctrl_usart2_rts: usart2_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart2_cts: usart2_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/
|
||||
AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
macb {
|
||||
pinctrl_macb_rmii: macb_rmii-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
|
||||
AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
|
||||
AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
|
||||
AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
|
||||
AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
|
||||
AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
|
||||
AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
|
||||
AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
|
||||
AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
|
||||
AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
|
||||
};
|
||||
|
||||
pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
|
||||
AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
|
||||
AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */
|
||||
AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */
|
||||
AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */
|
||||
AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
|
||||
AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
|
||||
AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
mmc0 {
|
||||
pinctrl_mmc0_clk: mmc0_clk-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
|
||||
AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
|
||||
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
|
||||
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
|
||||
AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
|
||||
AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
|
||||
AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
mmc1 {
|
||||
pinctrl_mmc1_clk: mmc1_clk-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
|
||||
};
|
||||
|
||||
pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
|
||||
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
|
||||
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
|
||||
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */
|
||||
AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */
|
||||
AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
|
||||
AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
ssc0 {
|
||||
pinctrl_ssc0_tx: ssc0_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
|
||||
AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */
|
||||
AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
|
||||
};
|
||||
|
||||
pinctrl_ssc0_rx: ssc0_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */
|
||||
AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */
|
||||
AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
ssc1 {
|
||||
pinctrl_ssc1_tx: ssc1_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
|
||||
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
|
||||
AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
|
||||
};
|
||||
|
||||
pinctrl_ssc1_rx: ssc1_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
|
||||
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
|
||||
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
pinctrl_spi0: spi0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
|
||||
AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */
|
||||
AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */
|
||||
};
|
||||
};
|
||||
|
||||
spi1 {
|
||||
pinctrl_spi1: spi1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */
|
||||
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */
|
||||
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
|
||||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
fb {
|
||||
pinctrl_fb: fb-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */
|
||||
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */
|
||||
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */
|
||||
AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */
|
||||
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */
|
||||
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */
|
||||
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */
|
||||
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */
|
||||
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */
|
||||
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */
|
||||
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */
|
||||
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */
|
||||
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */
|
||||
AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */
|
||||
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */
|
||||
AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */
|
||||
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */
|
||||
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */
|
||||
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */
|
||||
AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */
|
||||
AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */
|
||||
AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioA_clk>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioB_clk>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioCDE_clk>;
|
||||
};
|
||||
|
||||
pioD: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioCDE_clk>;
|
||||
};
|
||||
|
||||
pioE: gpio@fffffa00 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioCDE_clk>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
clocks = <&mck>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@fff8c000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfff8c000 0x200>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart0>;
|
||||
clocks = <&usart0_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@fff90000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfff90000 0x200>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart1>;
|
||||
clocks = <&usart1_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@fff94000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfff94000 0x200>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart2>;
|
||||
clocks = <&usart2_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssc0: ssc@fff98000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfff98000 0x4000>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
||||
clocks = <&ssc0_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssc1: ssc@fff9c000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
reg = <0xfff9c000 0x4000>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
|
||||
clocks = <&ssc1_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffbc000 {
|
||||
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||
reg = <0xfffbc000 0x100>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_macb_rmii>;
|
||||
clocks = <&macb0_clk>, <&macb0_clk>;
|
||||
clock-names = "hclk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: gadget@fff78000 {
|
||||
compatible = "atmel,at91rm9200-udc";
|
||||
reg = <0xfff78000 0x4000>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&udc_clk>, <&udpck>;
|
||||
clock-names = "pclk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@fff88000 {
|
||||
compatible = "atmel,at91sam9260-i2c";
|
||||
reg = <0xfff88000 0x100>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&twi0_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@fff80000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xfff80000 0x600>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mci0_clk>;
|
||||
clock-names = "mci_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@fff84000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xfff84000 0x600>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mci1_clk>;
|
||||
clock-names = "mci_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
compatible = "atmel,at91sam9260-wdt";
|
||||
reg = <0xfffffd40 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@fffa4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xfffa4000 0x200>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&spi0_clk>;
|
||||
clock-names = "spi_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@fffa8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xfffa8000 0x200>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&spi1_clk>;
|
||||
clock-names = "spi_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@fffb8000 {
|
||||
compatible = "atmel,at91sam9rl-pwm";
|
||||
reg = <0xfffb8000 0x300>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&pwm_clk>;
|
||||
clock-names = "pwm_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
fb0: fb@0x00700000 {
|
||||
compatible = "atmel,at91sam9263-lcdc";
|
||||
reg = <0x00700000 0x1000>;
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fb>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
compatible = "atmel,at91rm9200-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40000000 0x10000000
|
||||
0xffffe000 0x200
|
||||
>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
gpios = <&pioA 22 GPIO_ACTIVE_HIGH
|
||||
&pioD 15 GPIO_ACTIVE_HIGH
|
||||
0
|
||||
>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb0: ohci@00a00000 {
|
||||
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
||||
reg = <0x00a00000 0x100000>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
|
||||
&pioB 5 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,sda-open-drain;
|
||||
i2c-gpio,scl-open-drain;
|
||||
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
235
sys/gnu/dts/arm/at91sam9263ek.dts
Normal file
235
sys/gnu/dts/arm/at91sam9263ek.dts
Normal file
@ -0,0 +1,235 @@
|
||||
/*
|
||||
* at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2 only
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9263.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel at91sam9263ek";
|
||||
compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <16367660>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <16367660>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@ffffee00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@fff8c000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_usart0
|
||||
&pinctrl_usart0_rts
|
||||
&pinctrl_usart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffbc000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: gadget@fff78000 {
|
||||
atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fff80000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0
|
||||
&pinctrl_mmc0_clk
|
||||
&pinctrl_mmc0_slot0_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>;
|
||||
wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@fffff200 {
|
||||
mmc0 {
|
||||
pinctrl_board_mmc0: mmc0-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PE18 gpio CD pin pull up and deglitch */
|
||||
AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@fffa4000 {
|
||||
status = "okay";
|
||||
cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fb0: fb@0x00700000 {
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display {
|
||||
bits-per-pixel = <16>;
|
||||
atmel,lcdcon-backlight;
|
||||
atmel,dmacon = <0x1>;
|
||||
atmel,lcdcon2 = <0x80008002>;
|
||||
atmel,guard-time = <1>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <4965000>;
|
||||
hactive = <240>;
|
||||
vactive = <320>;
|
||||
hback-porch = <1>;
|
||||
hfront-porch = <33>;
|
||||
vback-porch = <1>;
|
||||
vfront-porch = <0>;
|
||||
hsync-len = <5>;
|
||||
vsync-len = <1>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt = <1>;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
barebox@20000 {
|
||||
label = "barebox";
|
||||
reg = <0x20000 0x40000>;
|
||||
};
|
||||
|
||||
bareboxenv@60000 {
|
||||
label = "bareboxenv";
|
||||
reg = <0x60000 0x20000>;
|
||||
};
|
||||
|
||||
bareboxenv2@80000 {
|
||||
label = "bareboxenv2";
|
||||
reg = <0x80000 0x20000>;
|
||||
};
|
||||
|
||||
oftree@80000 {
|
||||
label = "oftree";
|
||||
reg = <0xa0000 0x20000>;
|
||||
};
|
||||
|
||||
kernel@a0000 {
|
||||
label = "kernel";
|
||||
reg = <0xc0000 0x400000>;
|
||||
};
|
||||
|
||||
rootfs@4a0000 {
|
||||
label = "rootfs";
|
||||
reg = <0x4c0000 0x7800000>;
|
||||
};
|
||||
|
||||
data@7ca0000 {
|
||||
label = "data";
|
||||
reg = <0x7cc0000 0x8340000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00a00000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH
|
||||
&pioA 21 GPIO_ACTIVE_HIGH
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d3 {
|
||||
label = "d3";
|
||||
gpios = <&pioB 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
d2 {
|
||||
label = "d2";
|
||||
gpios = <&pioC 29 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "nand-disk";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
left_click {
|
||||
label = "left_click";
|
||||
gpios = <&pioC 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <272>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
right_click {
|
||||
label = "right_click";
|
||||
gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <273>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
status = "okay";
|
||||
|
||||
24c512@50 {
|
||||
compatible = "24c512";
|
||||
reg = <0x50>;
|
||||
pagesize = <128>;
|
||||
};
|
||||
};
|
||||
};
|
28
sys/gnu/dts/arm/at91sam9g15.dtsi
Normal file
28
sys/gnu/dts/arm/at91sam9g15.dtsi
Normal file
@ -0,0 +1,28 @@
|
||||
/*
|
||||
* at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include "at91sam9x5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G15 SoC";
|
||||
compatible = "atmel,at91sam9g15", "atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe0399f 0x00000000 /* pioA */
|
||||
0x00040000 0x00047e3f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x00000000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
16
sys/gnu/dts/arm/at91sam9g15ek.dts
Normal file
16
sys/gnu/dts/arm/at91sam9g15ek.dts
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g15.dtsi"
|
||||
#include "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G15-EK";
|
||||
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
};
|
54
sys/gnu/dts/arm/at91sam9g20.dtsi
Normal file
54
sys/gnu/dts/arm/at91sam9g20.dtsi
Normal file
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include "at91sam9260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G20 family SoC";
|
||||
compatible = "atmel,at91sam9g20";
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x08000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
i2c0: i2c@fffac000 {
|
||||
compatible = "atmel,at91sam9g20-i2c";
|
||||
};
|
||||
|
||||
adc0: adc@fffe0000 {
|
||||
atmel,adc-startup-time = <40>;
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
plla: pllack {
|
||||
atmel,clk-input-range = <2000000 32000000>;
|
||||
atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
|
||||
<695000000 750000000 1 0>,
|
||||
<645000000 700000000 2 0>,
|
||||
<595000000 650000000 3 0>,
|
||||
<545000000 600000000 0 1>,
|
||||
<495000000 550000000 1 1>,
|
||||
<445000000 500000000 2 1>,
|
||||
<400000000 450000000 3 1>;
|
||||
};
|
||||
|
||||
pllb: pllbck {
|
||||
atmel,clk-input-range = <2000000 32000000>;
|
||||
atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
|
||||
};
|
||||
|
||||
mck: masterck {
|
||||
atmel,clk-output-range = <0 133000000>;
|
||||
atmel,clk-divisors = <1 2 4 6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
29
sys/gnu/dts/arm/at91sam9g20ek.dts
Normal file
29
sys/gnu/dts/arm/at91sam9g20ek.dts
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g20ek_common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel at91sam9g20ek";
|
||||
compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds1 {
|
||||
label = "ds1";
|
||||
gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds5 {
|
||||
label = "ds5";
|
||||
gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
55
sys/gnu/dts/arm/at91sam9g20ek_2mmc.dts
Normal file
55
sys/gnu/dts/arm/at91sam9g20ek_2mmc.dts
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g20ek_common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel at91sam9g20ek 2 mmc";
|
||||
compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
|
||||
|
||||
ahb {
|
||||
apb{
|
||||
mmc0: mmc@fffa8000 {
|
||||
/* clk already mux wuth slot0 */
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0_slot0
|
||||
&pinctrl_mmc0_slot0_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
mmc0_slot0 {
|
||||
pinctrl_board_mmc0_slot0: mmc0_slot0-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC2 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds1 {
|
||||
label = "ds1";
|
||||
gpios = <&pioB 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds5 {
|
||||
label = "ds5";
|
||||
gpios = <&pioB 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
219
sys/gnu/dts/arm/at91sam9g20ek_common.dtsi
Normal file
219
sys/gnu/dts/arm/at91sam9g20ek_common.dtsi
Normal file
@ -0,0 +1,219 @@
|
||||
/*
|
||||
* at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
#include "at91sam9g20.dtsi"
|
||||
|
||||
/ {
|
||||
|
||||
chosen {
|
||||
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
board {
|
||||
pinctrl_pck0_as_mck: pck0_as_mck {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
mmc0_slot1 {
|
||||
pinctrl_board_mmc0_slot1: mmc0_slot1-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC9 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_usart0
|
||||
&pinctrl_usart0_rts
|
||||
&pinctrl_usart0_cts
|
||||
&pinctrl_usart0_dtr_dsr
|
||||
&pinctrl_usart0_dcd
|
||||
&pinctrl_usart0_ri>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffc4000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fffa8000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0_slot1
|
||||
&pinctrl_mmc0_clk
|
||||
&pinctrl_mmc0_slot1_cmd_dat0
|
||||
&pinctrl_mmc0_slot1_dat1_3>;
|
||||
status = "okay";
|
||||
slot@1 {
|
||||
reg = <1>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
ssc0: ssc@fffbc000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pinctrl_ssc0_tx>;
|
||||
};
|
||||
|
||||
spi0: spi@fffc8000 {
|
||||
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
barebox@20000 {
|
||||
label = "barebox";
|
||||
reg = <0x20000 0x40000>;
|
||||
};
|
||||
|
||||
bareboxenv@60000 {
|
||||
label = "bareboxenv";
|
||||
reg = <0x60000 0x20000>;
|
||||
};
|
||||
|
||||
bareboxenv2@80000 {
|
||||
label = "bareboxenv2";
|
||||
reg = <0x80000 0x20000>;
|
||||
};
|
||||
|
||||
oftree@80000 {
|
||||
label = "oftree";
|
||||
reg = <0xa0000 0x20000>;
|
||||
};
|
||||
|
||||
kernel@a0000 {
|
||||
label = "kernel";
|
||||
reg = <0xc0000 0x400000>;
|
||||
};
|
||||
|
||||
rootfs@4a0000 {
|
||||
label = "rootfs";
|
||||
reg = <0x4c0000 0x7800000>;
|
||||
};
|
||||
|
||||
data@7ca0000 {
|
||||
label = "data";
|
||||
reg = <0x7cc0000 0x8340000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
status = "okay";
|
||||
|
||||
24c512@50 {
|
||||
compatible = "24c512";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
wm8731: wm8731@1b {
|
||||
compatible = "wm8731";
|
||||
reg = <0x1b>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
btn3 {
|
||||
label = "Button 3";
|
||||
gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x103>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
btn4 {
|
||||
label = "Button 4";
|
||||
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x104>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "atmel,at91sam9g20ek-wm8731-audio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pck0_as_mck>;
|
||||
|
||||
atmel,model = "wm8731 @ AT91SAMG20EK";
|
||||
|
||||
atmel,audio-routing =
|
||||
"Ext Spk", "LHPOUT",
|
||||
"Int Mic", "MICIN";
|
||||
|
||||
atmel,ssc-controller = <&ssc0>;
|
||||
atmel,audio-codec = <&wm8731>;
|
||||
};
|
||||
};
|
30
sys/gnu/dts/arm/at91sam9g25.dtsi
Normal file
30
sys/gnu/dts/arm/at91sam9g25.dtsi
Normal file
@ -0,0 +1,30 @@
|
||||
/*
|
||||
* at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include "at91sam9x5.dtsi"
|
||||
#include "at91sam9x5_usart3.dtsi"
|
||||
#include "at91sam9x5_macb0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G25 SoC";
|
||||
compatible = "atmel,at91sam9g25", "atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe0399f 0xc000001c /* pioA */
|
||||
0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
|
||||
0x80000000 0x07c0ffff 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
25
sys/gnu/dts/arm/at91sam9g25ek.dts
Normal file
25
sys/gnu/dts/arm/at91sam9g25ek.dts
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g25.dtsi"
|
||||
#include "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G25-EK";
|
||||
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
29
sys/gnu/dts/arm/at91sam9g35.dtsi
Normal file
29
sys/gnu/dts/arm/at91sam9g35.dtsi
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include "at91sam9x5.dtsi"
|
||||
#include "at91sam9x5_macb0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G35 SoC";
|
||||
compatible = "atmel,at91sam9g35", "atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe0399f 0xc000000c /* pioA */
|
||||
0x000406ff 0x00047e3f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x00000000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
25
sys/gnu/dts/arm/at91sam9g35ek.dts
Normal file
25
sys/gnu/dts/arm/at91sam9g35ek.dts
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g35.dtsi"
|
||||
#include "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G35-EK";
|
||||
compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
1227
sys/gnu/dts/arm/at91sam9g45.dtsi
Normal file
1227
sys/gnu/dts/arm/at91sam9g45.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
303
sys/gnu/dts/arm/at91sam9m10g45ek.dts
Normal file
303
sys/gnu/dts/arm/at91sam9m10g45ek.dts
Normal file
@ -0,0 +1,303 @@
|
||||
/*
|
||||
* at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
|
||||
*
|
||||
* Copyright (C) 2011 Atmel,
|
||||
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9g45.dtsi"
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9M10G45-EK";
|
||||
compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@ffffee00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fff90000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_usart1
|
||||
&pinctrl_usart1_rts
|
||||
&pinctrl_usart1_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffbc000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@fff84000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@fff88000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@fff80000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0
|
||||
&pinctrl_mmc0_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1: mmc@fffd0000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc1
|
||||
&pinctrl_mmc1_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc1_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
|
||||
wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@fffff200 {
|
||||
mmc0 {
|
||||
pinctrl_board_mmc0: mmc0-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
|
||||
mmc1 {
|
||||
pinctrl_board_mmc1: mmc1-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */
|
||||
AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pinctrl_pwm_leds: pwm-led {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
|
||||
AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@fffa4000{
|
||||
status = "okay";
|
||||
cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <13000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2: gadget@fff78000 {
|
||||
atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
adc0: adc@fffb0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&pinctrl_adc0_ad0
|
||||
&pinctrl_adc0_ad1
|
||||
&pinctrl_adc0_ad2
|
||||
&pinctrl_adc0_ad3
|
||||
&pinctrl_adc0_ad4
|
||||
&pinctrl_adc0_ad5
|
||||
&pinctrl_adc0_ad6
|
||||
&pinctrl_adc0_ad7>;
|
||||
atmel,adc-ts-wires = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm0: pwm@fffb8000 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm_leds>;
|
||||
};
|
||||
};
|
||||
|
||||
fb0: fb@0x00500000 {
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display {
|
||||
bits-per-pixel = <32>;
|
||||
atmel,lcdcon-backlight;
|
||||
atmel,dmacon = <0x1>;
|
||||
atmel,lcdcon2 = <0x80008002>;
|
||||
atmel,guard-time = <9>;
|
||||
atmel,lcd-wiring-mode = "RGB";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <9000000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <1>;
|
||||
hfront-porch = <1>;
|
||||
vback-porch = <40>;
|
||||
vfront-porch = <1>;
|
||||
hsync-len = <45>;
|
||||
vsync-len = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
boot@0 {
|
||||
label = "bootstrap/uboot/kernel";
|
||||
reg = <0x0 0x400000>;
|
||||
};
|
||||
|
||||
rootfs@400000 {
|
||||
label = "rootfs";
|
||||
reg = <0x400000 0x3C00000>;
|
||||
};
|
||||
|
||||
data@4000000 {
|
||||
label = "data";
|
||||
reg = <0x4000000 0xC000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00700000 {
|
||||
status = "okay";
|
||||
num-ports = <2>;
|
||||
atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
|
||||
&pioD 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
usb1: ehci@00800000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d8 {
|
||||
label = "d8";
|
||||
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
|
||||
d6 {
|
||||
label = "d6";
|
||||
pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>;
|
||||
max-brightness = <255>;
|
||||
linux,default-trigger = "nand-disk";
|
||||
};
|
||||
|
||||
d7 {
|
||||
label = "d7";
|
||||
pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
|
||||
max-brightness = <255>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
left_click {
|
||||
label = "left_click";
|
||||
gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <272>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
right_click {
|
||||
label = "right_click";
|
||||
gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <273>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
left {
|
||||
label = "Joystick Left";
|
||||
gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <105>;
|
||||
};
|
||||
|
||||
right {
|
||||
label = "Joystick Right";
|
||||
gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <106>;
|
||||
};
|
||||
|
||||
up {
|
||||
label = "Joystick Up";
|
||||
gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <103>;
|
||||
};
|
||||
|
||||
down {
|
||||
label = "Joystick Down";
|
||||
gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <108>;
|
||||
};
|
||||
|
||||
enter {
|
||||
label = "Joystick Press";
|
||||
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <28>;
|
||||
};
|
||||
};
|
||||
};
|
949
sys/gnu/dts/arm/at91sam9n12.dtsi
Normal file
949
sys/gnu/dts/arm/at91sam9n12.dtsi
Normal file
@ -0,0 +1,949 @@
|
||||
/*
|
||||
* at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Hong Xu <hong.xu@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9N12 SoC";
|
||||
compatible = "atmel,at91sam9n12";
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
serial4 = &usart3;
|
||||
gpio0 = &pioA;
|
||||
gpio1 = &pioB;
|
||||
gpio2 = &pioC;
|
||||
gpio3 = &pioD;
|
||||
tcb0 = &tcb0;
|
||||
tcb1 = &tcb1;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
ssc0 = &ssc0;
|
||||
pwm0 = &pwm0;
|
||||
};
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x10000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
slow_xtal: slow_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
main_xtal: main_xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
aic: interrupt-controller@fffff000 {
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
reg = <0xfffff000 0x200>;
|
||||
atmel,external-irqs = <31>;
|
||||
};
|
||||
|
||||
ramc0: ramc@ffffe800 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
compatible = "atmel,at91sam9n12-pmc";
|
||||
reg = <0xfffffc00 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
main_rc_osc: main_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
|
||||
clock-frequency = <12000000>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
main_osc: main_osc {
|
||||
compatible = "atmel,at91rm9200-clk-main-osc";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
|
||||
clocks = <&main_xtal>;
|
||||
};
|
||||
|
||||
main: mainck {
|
||||
compatible = "atmel,at91sam9x5-clk-main";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
|
||||
clocks = <&main_rc_osc>, <&main_osc>;
|
||||
};
|
||||
|
||||
plla: pllack {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
|
||||
clocks = <&main>;
|
||||
reg = <0>;
|
||||
atmel,clk-input-range = <2000000 32000000>;
|
||||
#atmel,pll-clk-output-range-cells = <4>;
|
||||
atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
|
||||
<695000000 750000000 1 0>,
|
||||
<645000000 700000000 2 0>,
|
||||
<595000000 650000000 3 0>,
|
||||
<545000000 600000000 0 1>,
|
||||
<495000000 555000000 1 1>,
|
||||
<445000000 500000000 2 1>,
|
||||
<400000000 450000000 3 1>;
|
||||
};
|
||||
|
||||
plladiv: plladivck {
|
||||
compatible = "atmel,at91sam9x5-clk-plldiv";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&plla>;
|
||||
};
|
||||
|
||||
pllb: pllbck {
|
||||
compatible = "atmel,at91rm9200-clk-pll";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
|
||||
clocks = <&main>;
|
||||
reg = <1>;
|
||||
atmel,clk-input-range = <2000000 32000000>;
|
||||
#atmel,pll-clk-output-range-cells = <3>;
|
||||
atmel,pll-clk-output-ranges = <30000000 100000000 0>;
|
||||
};
|
||||
|
||||
mck: masterck {
|
||||
compatible = "atmel,at91sam9x5-clk-master";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
|
||||
clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
|
||||
atmel,clk-output-range = <0 133333333>;
|
||||
atmel,clk-divisors = <1 2 4 3>;
|
||||
atmel,master-clk-have-div3-pres;
|
||||
};
|
||||
|
||||
usb: usbck {
|
||||
compatible = "atmel,at91sam9n12-clk-usb";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&pllb>;
|
||||
};
|
||||
|
||||
prog: progck {
|
||||
compatible = "atmel,at91sam9x5-clk-programmable";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
|
||||
|
||||
prog0: prog0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0>;
|
||||
interrupts = <AT91_PMC_PCKRDY(0)>;
|
||||
};
|
||||
|
||||
prog1: prog1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <1>;
|
||||
interrupts = <AT91_PMC_PCKRDY(1)>;
|
||||
};
|
||||
};
|
||||
|
||||
systemck {
|
||||
compatible = "atmel,at91rm9200-clk-system";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ddrck: ddrck {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
lcdck: lcdck {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
uhpck: uhpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
udpck: udpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
pck0: pck0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
clocks = <&prog0>;
|
||||
};
|
||||
|
||||
pck1: pck1 {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
clocks = <&prog1>;
|
||||
};
|
||||
};
|
||||
|
||||
periphck {
|
||||
compatible = "atmel,at91sam9x5-clk-peripheral";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mck>;
|
||||
|
||||
pioAB_clk: pioAB_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
pioCD_clk: pioCD_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
fuse_clk: fuse_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
usart0_clk: usart0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
usart1_clk: usart1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
usart2_clk: usart2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
usart3_clk: usart3_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
twi0_clk: twi0_clk {
|
||||
reg = <9>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
twi1_clk: twi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
};
|
||||
|
||||
mci0_clk: mci0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <12>;
|
||||
};
|
||||
|
||||
spi0_clk: spi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <13>;
|
||||
};
|
||||
|
||||
spi1_clk: spi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <14>;
|
||||
};
|
||||
|
||||
uart0_clk: uart0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <15>;
|
||||
};
|
||||
|
||||
uart1_clk: uart1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
tcb_clk: tcb_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
pwm_clk: pwm_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
adc_clk: adc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <19>;
|
||||
};
|
||||
|
||||
dma0_clk: dma0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <20>;
|
||||
};
|
||||
|
||||
uhphs_clk: uhphs_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <22>;
|
||||
};
|
||||
|
||||
udphs_clk: udphs_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <23>;
|
||||
};
|
||||
|
||||
lcdc_clk: lcdc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <25>;
|
||||
};
|
||||
|
||||
sha_clk: sha_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <27>;
|
||||
};
|
||||
|
||||
ssc0_clk: ssc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <28>;
|
||||
};
|
||||
|
||||
aes_clk: aes_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <29>;
|
||||
};
|
||||
|
||||
trng_clk: trng_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <30>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rstc@fffffe00 {
|
||||
compatible = "atmel,at91sam9g45-rstc";
|
||||
reg = <0xfffffe00 0x10>;
|
||||
};
|
||||
|
||||
pit: timer@fffffe30 {
|
||||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xfffffe30 0xf>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
shdwc@fffffe10 {
|
||||
compatible = "atmel,at91sam9x5-shdwc";
|
||||
reg = <0xfffffe10 0x10>;
|
||||
};
|
||||
|
||||
sckc@fffffe50 {
|
||||
compatible = "atmel,at91sam9x5-sckc";
|
||||
reg = <0xfffffe50 0x4>;
|
||||
|
||||
slow_osc: slow_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_xtal>;
|
||||
};
|
||||
|
||||
slow_rc_osc: slow_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
clk32k: slck {
|
||||
compatible = "atmel,at91sam9x5-clk-slow";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_rc_osc>, <&slow_osc>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0: mmc@f0008000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xf0008000 0x600>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
|
||||
dma-names = "rxtx";
|
||||
clocks = <&mci0_clk>;
|
||||
clock-names = "mci_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tcb0: timer@f8008000 {
|
||||
compatible = "atmel,at91sam9x5-tcb";
|
||||
reg = <0xf8008000 0x100>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tcb_clk>;
|
||||
clock-names = "t0_clk";
|
||||
};
|
||||
|
||||
tcb1: timer@f800c000 {
|
||||
compatible = "atmel,at91sam9x5-tcb";
|
||||
reg = <0xf800c000 0x100>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&tcb_clk>;
|
||||
clock-names = "t0_clk";
|
||||
};
|
||||
|
||||
dma: dma-controller@ffffec00 {
|
||||
compatible = "atmel,at91sam9g45-dma";
|
||||
reg = <0xffffec00 0x200>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#dma-cells = <2>;
|
||||
clocks = <&dma0_clk>;
|
||||
clock-names = "dma_clk";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe07983 0x00000000 /* pioA */
|
||||
0x00040000 0x00047e0f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x07c00000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
|
||||
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
|
||||
AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
|
||||
};
|
||||
|
||||
pinctrl_usart0_rts: usart0_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
|
||||
};
|
||||
|
||||
pinctrl_usart0_cts: usart0_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
|
||||
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
|
||||
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
|
||||
};
|
||||
|
||||
pinctrl_usart2_rts: usart2_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart2_cts: usart2_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
usart3 {
|
||||
pinctrl_usart3: usart3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
|
||||
AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart3_rts: usart3_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart3_cts: usart3_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
|
||||
AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
|
||||
AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
|
||||
AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
mmc0 {
|
||||
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
|
||||
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
|
||||
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
|
||||
AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
|
||||
AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
|
||||
};
|
||||
|
||||
pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
|
||||
AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
|
||||
AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
|
||||
AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
ssc0 {
|
||||
pinctrl_ssc0_tx: ssc0_tx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
|
||||
AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
|
||||
AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
|
||||
};
|
||||
|
||||
pinctrl_ssc0_rx: ssc0_rx-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
|
||||
AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
|
||||
AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
pinctrl_spi0: spi0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
|
||||
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
|
||||
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
|
||||
};
|
||||
};
|
||||
|
||||
spi1 {
|
||||
pinctrl_spi1: spi1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
|
||||
AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
|
||||
AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
pinctrl_i2c0: i2c0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1: i2c1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
|
||||
AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb0 {
|
||||
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
tcb1 {
|
||||
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
||||
atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
||||
atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
||||
atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
||||
atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
||||
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
||||
atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
||||
atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
||||
atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
|
||||
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
||||
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioAB_clk>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioAB_clk>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioCD_clk>;
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pioCD_clk>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
clocks = <&mck>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssc0: ssc@f0010000 {
|
||||
compatible = "atmel,at91sam9g45-ssc";
|
||||
reg = <0xf0010000 0x4000>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
|
||||
<&dma 0 AT91_DMA_CFG_PER_ID(22)>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
||||
clocks = <&ssc0_clk>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf801c000 0x4000>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart0>;
|
||||
clocks = <&usart0_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@f8020000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8020000 0x4000>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart1>;
|
||||
clocks = <&usart1_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@f8024000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8024000 0x4000>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart2>;
|
||||
clocks = <&usart2_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@f8028000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8028000 0x4000>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart3>;
|
||||
clocks = <&usart3_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8010000 0x100>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(14)>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&twi0_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@f8014000 {
|
||||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8014000 0x100>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(16)>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&twi1_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xf0000000 0x100>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(2)>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&spi0_clk>;
|
||||
clock-names = "spi_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@f0004000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xf0004000 0x100>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
|
||||
<&dma 1 AT91_DMA_CFG_PER_ID(4)>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1>;
|
||||
clocks = <&spi1_clk>;
|
||||
clock-names = "spi_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
compatible = "atmel,at91sam9260-wdt";
|
||||
reg = <0xfffffe40 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@f8034000 {
|
||||
compatible = "atmel,at91sam9rl-pwm";
|
||||
reg = <0xf8034000 0x300>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&pwm_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
compatible = "atmel,at91rm9200-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = < 0x40000000 0x10000000
|
||||
0xffffe000 0x00000600
|
||||
0xffffe600 0x00000200
|
||||
0x00108000 0x00018000
|
||||
>;
|
||||
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
atmel,nand-has-dma;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
gpios = <&pioD 5 GPIO_ACTIVE_HIGH
|
||||
&pioD 4 GPIO_ACTIVE_HIGH
|
||||
0
|
||||
>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
||||
reg = <0x00500000 0x00100000>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
|
||||
<&uhpck>;
|
||||
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
|
||||
&pioA 31 GPIO_ACTIVE_HIGH /* scl */
|
||||
>;
|
||||
i2c-gpio,sda-open-drain;
|
||||
i2c-gpio,scl-open-drain;
|
||||
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
193
sys/gnu/dts/arm/at91sam9n12ek.dts
Normal file
193
sys/gnu/dts/arm/at91sam9n12ek.dts
Normal file
@ -0,0 +1,193 @@
|
||||
/*
|
||||
* at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Hong Xu <hong.xu@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9n12.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9N12-EK";
|
||||
compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x8000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <16000000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <16000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssc0: ssc@f0010000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
status = "okay";
|
||||
|
||||
wm8904: codec@1a {
|
||||
compatible = "wm8904";
|
||||
reg = <0x1a>;
|
||||
clocks = <&pck0>;
|
||||
clock-names = "mclk";
|
||||
};
|
||||
|
||||
qt1070: keyboard@1b {
|
||||
compatible = "qt1070";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&pioA>;
|
||||
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qt1070_irq>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1: i2c@f8014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: mmc@f0008000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0
|
||||
&pinctrl_mmc0_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
mmc0 {
|
||||
pinctrl_board_mmc0: mmc0-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
|
||||
qt1070 {
|
||||
pinctrl_qt1070_irq: qt1070_irq {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@f0000000 {
|
||||
status = "okay";
|
||||
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
|
||||
m25p80@0 {
|
||||
compatible = "atmel,at25df321a";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
atmel,has-pmecc;
|
||||
atmel,pmecc-cap = <2>;
|
||||
atmel,pmecc-sector-size = <512>;
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d8 {
|
||||
label = "d8";
|
||||
gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
d9 {
|
||||
label = "d6";
|
||||
gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "nand-disk";
|
||||
};
|
||||
|
||||
d10 {
|
||||
label = "d7";
|
||||
gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
enter {
|
||||
label = "Enter";
|
||||
gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <28>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "atmel,asoc-wm8904";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
|
||||
|
||||
atmel,model = "wm8904 @ AT91SAM9N12";
|
||||
atmel,audio-routing =
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"IN2L", "Line In Jack",
|
||||
"IN2R", "Line In Jack",
|
||||
"Mic", "MICBIAS",
|
||||
"IN1L", "Mic";
|
||||
|
||||
atmel,ssc-controller = <&ssc0>;
|
||||
atmel,audio-codec = <&wm8904>;
|
||||
};
|
||||
};
|
1092
sys/gnu/dts/arm/at91sam9rl.dtsi
Normal file
1092
sys/gnu/dts/arm/at91sam9rl.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
247
sys/gnu/dts/arm/at91sam9rlek.dts
Normal file
247
sys/gnu/dts/arm/at91sam9rlek.dts
Normal file
@ -0,0 +1,247 @@
|
||||
/*
|
||||
* at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board
|
||||
*
|
||||
* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
|
||||
*
|
||||
* Licensed under GPLv2 only
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9rl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel at91sam9rlek";
|
||||
compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
fb0: fb@00500000 {
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display {
|
||||
bits-per-pixel = <16>;
|
||||
atmel,lcdcon-backlight;
|
||||
atmel,dmacon = <0x1>;
|
||||
atmel,lcdcon2 = <0x80008002>;
|
||||
atmel,guard-time = <1>;
|
||||
atmel,lcd-wiring-mode = "RGB";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <4965000>;
|
||||
hactive = <240>;
|
||||
vactive = <320>;
|
||||
hback-porch = <1>;
|
||||
hfront-porch = <33>;
|
||||
vback-porch = <1>;
|
||||
vfront-porch = <0>;
|
||||
hsync-len = <5>;
|
||||
vsync-len = <1>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt = <1>;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
bootloader@40000 {
|
||||
label = "bootloader";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
bootloaderenv@c0000 {
|
||||
label = "bootloader env";
|
||||
reg = <0xc0000 0xc0000>;
|
||||
};
|
||||
|
||||
dtb@180000 {
|
||||
label = "device tree";
|
||||
reg = <0x180000 0x80000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
|
||||
apb {
|
||||
mmc0: mmc@fffa4000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0
|
||||
&pinctrl_mmc0_clk
|
||||
&pinctrl_mmc0_slot0_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_usart0
|
||||
&pinctrl_usart0_rts
|
||||
&pinctrl_usart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
adc0: adc@fffd0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&pinctrl_adc0_ad0
|
||||
&pinctrl_adc0_ad1
|
||||
&pinctrl_adc0_ad2
|
||||
&pinctrl_adc0_ad3
|
||||
&pinctrl_adc0_ad4
|
||||
&pinctrl_adc0_ad5
|
||||
&pinctrl_adc0_adtrg>;
|
||||
atmel,adc-ts-wires = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb0: gadget@fffd4000 {
|
||||
atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@fffcc000 {
|
||||
status = "okay";
|
||||
cs-gpios = <&pioA 28 0>, <0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <15000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0: pwm@fffc8000 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm0_pwm1_2>,
|
||||
<&pinctrl_pwm0_pwm2_2>;
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
mmc0 {
|
||||
pinctrl_board_mmc0: mmc0-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
main: mainck {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
|
||||
ds1 {
|
||||
label = "ds1";
|
||||
pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
|
||||
ds2 {
|
||||
label = "ds2";
|
||||
pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
ds3 {
|
||||
label = "ds3";
|
||||
gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
right_click {
|
||||
label = "right_click";
|
||||
gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <273>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
left_click {
|
||||
label = "left_click";
|
||||
gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <272>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
31
sys/gnu/dts/arm/at91sam9x25.dtsi
Normal file
31
sys/gnu/dts/arm/at91sam9x25.dtsi
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include "at91sam9x5.dtsi"
|
||||
#include "at91sam9x5_usart3.dtsi"
|
||||
#include "at91sam9x5_macb0.dtsi"
|
||||
#include "at91sam9x5_macb1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X25 SoC";
|
||||
compatible = "atmel,at91sam9x25", "atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe03fff 0xc000001c /* pioA */
|
||||
0x0007ffff 0x00047e3f 0x00000000 /* pioB */
|
||||
0x80000000 0xfffd0000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
30
sys/gnu/dts/arm/at91sam9x25ek.dts
Normal file
30
sys/gnu/dts/arm/at91sam9x25ek.dts
Normal file
@ -0,0 +1,30 @@
|
||||
/*
|
||||
* at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9x25.dtsi"
|
||||
#include "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X25-EK";
|
||||
compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb1: ethernet@f8030000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
29
sys/gnu/dts/arm/at91sam9x35.dtsi
Normal file
29
sys/gnu/dts/arm/at91sam9x35.dtsi
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include "at91sam9x5.dtsi"
|
||||
#include "at91sam9x5_macb0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X35 SoC";
|
||||
compatible = "atmel,at91sam9x35", "atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe03fff 0xc000000c /* pioA */
|
||||
0x000406ff 0x00047e3f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x00000000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
25
sys/gnu/dts/arm/at91sam9x35ek.dts
Normal file
25
sys/gnu/dts/arm/at91sam9x35ek.dts
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9x35.dtsi"
|
||||
#include "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X35-EK";
|
||||
compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
1220
sys/gnu/dts/arm/at91sam9x5.dtsi
Normal file
1220
sys/gnu/dts/arm/at91sam9x5.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
31
sys/gnu/dts/arm/at91sam9x5_can.dtsi
Normal file
31
sys/gnu/dts/arm/at91sam9x5_can.dtsi
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
|
||||
* Ethernet interface.
|
||||
*
|
||||
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
apb {
|
||||
pmc: pmc@fffffc00 {
|
||||
periphck {
|
||||
can0_clk: can0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <29>;
|
||||
};
|
||||
|
||||
can1_clk: can1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <30>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
26
sys/gnu/dts/arm/at91sam9x5_isi.dtsi
Normal file
26
sys/gnu/dts/arm/at91sam9x5_isi.dtsi
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
|
||||
* Image Sensor Interface.
|
||||
*
|
||||
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
apb {
|
||||
pmc: pmc@fffffc00 {
|
||||
periphck {
|
||||
isi_clk: isi_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <25>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
26
sys/gnu/dts/arm/at91sam9x5_lcd.dtsi
Normal file
26
sys/gnu/dts/arm/at91sam9x5_lcd.dtsi
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
|
||||
* LCD controller.
|
||||
*
|
||||
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
apb {
|
||||
pmc: pmc@fffffc00 {
|
||||
periphck {
|
||||
lcdc_clk: lcdc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <25>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
67
sys/gnu/dts/arm/at91sam9x5_macb0.dtsi
Normal file
67
sys/gnu/dts/arm/at91sam9x5_macb0.dtsi
Normal file
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
|
||||
* Ethernet interface.
|
||||
*
|
||||
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
macb0 {
|
||||
pinctrl_macb0_rmii: macb0_rmii-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
|
||||
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
|
||||
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
|
||||
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
|
||||
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
|
||||
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
|
||||
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
|
||||
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
|
||||
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
|
||||
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
|
||||
};
|
||||
|
||||
pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
|
||||
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
|
||||
AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
|
||||
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
|
||||
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
|
||||
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
|
||||
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
|
||||
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
periphck {
|
||||
macb0_clk: macb0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
macb0: ethernet@f802c000 {
|
||||
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||
reg = <0xf802c000 0x100>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_macb0_rmii>;
|
||||
clocks = <&macb0_clk>, <&macb0_clk>;
|
||||
clock-names = "hclk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
55
sys/gnu/dts/arm/at91sam9x5_macb1.dtsi
Normal file
55
sys/gnu/dts/arm/at91sam9x5_macb1.dtsi
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
|
||||
* Ethernet interfaces.
|
||||
*
|
||||
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
macb1 {
|
||||
pinctrl_macb1_rmii: macb1_rmii-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
|
||||
AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
|
||||
AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
|
||||
AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
|
||||
AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
|
||||
AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
|
||||
AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
|
||||
AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
|
||||
AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
|
||||
AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
periphck {
|
||||
macb1_clk: macb1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <27>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
macb1: ethernet@f8030000 {
|
||||
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||
reg = <0xf8030000 0x100>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_macb1_rmii>;
|
||||
clocks = <&macb1_clk>, <&macb1_clk>;
|
||||
clock-names = "hclk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
66
sys/gnu/dts/arm/at91sam9x5_usart3.dtsi
Normal file
66
sys/gnu/dts/arm/at91sam9x5_usart3.dtsi
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
|
||||
* 4 USART.
|
||||
*
|
||||
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial4 = &usart3;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
usart3 {
|
||||
pinctrl_usart3: usart3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
|
||||
AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart3_rts: usart3_rts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart3_cts: usart3_cts-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
|
||||
};
|
||||
|
||||
pinctrl_usart3_sck: usart3_sck-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
periphck {
|
||||
usart3_clk: usart3_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usart3: serial@f8028000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8028000 0x200>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart3>;
|
||||
clocks = <&usart3_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
107
sys/gnu/dts/arm/at91sam9x5cm.dtsi
Normal file
107
sys/gnu/dts/arm/at91sam9x5cm.dtsi
Normal file
@ -0,0 +1,107 @@
|
||||
/*
|
||||
* at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x20000000 0x8000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
1wire_cm {
|
||||
pinctrl_1wire_cm: 1wire_cm-0 {
|
||||
atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
atmel,has-pmecc; /* Enable PMECC */
|
||||
atmel,pmecc-cap = <2>;
|
||||
atmel,pmecc-sector-size = <512>;
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
uboot@40000 {
|
||||
label = "u-boot";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
ubootenv@c0000 {
|
||||
label = "U-Boot Env";
|
||||
reg = <0xc0000 0x140000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x1f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pb18 {
|
||||
label = "pb18";
|
||||
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
pd21 {
|
||||
label = "pd21";
|
||||
gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
1wire_cm {
|
||||
compatible = "w1-gpio";
|
||||
gpios = <&pioB 18 GPIO_ACTIVE_HIGH>;
|
||||
linux,open-drain;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_1wire_cm>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
132
sys/gnu/dts/arm/at91sam9x5ek.dtsi
Normal file
132
sys/gnu/dts/arm/at91sam9x5ek.dtsi
Normal file
@ -0,0 +1,132 @@
|
||||
/*
|
||||
* at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
#include "at91sam9x5cm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X5-EK";
|
||||
compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
mmc0: mmc@f0008000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc0
|
||||
&pinctrl_mmc0_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc0_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1: mmc@f000c000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_board_mmc1
|
||||
&pinctrl_mmc1_slot0_clk_cmd_dat0
|
||||
&pinctrl_mmc1_slot0_dat1_3>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: gadget@f803c000 {
|
||||
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
status = "okay";
|
||||
|
||||
wm8731: wm8731@1a {
|
||||
compatible = "wm8731";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
mmc0 {
|
||||
pinctrl_board_mmc0: mmc0-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
|
||||
mmc1 {
|
||||
pinctrl_board_mmc1: mmc1-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@f0000000 {
|
||||
status = "okay";
|
||||
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
|
||||
m25p80@0 {
|
||||
compatible = "atmel,at25df321a";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@fffffe40 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssc0: ssc@f0010000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00600000 {
|
||||
status = "okay";
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */
|
||||
&pioD 19 GPIO_ACTIVE_LOW
|
||||
&pioD 20 GPIO_ACTIVE_LOW
|
||||
>;
|
||||
};
|
||||
|
||||
usb1: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "atmel,sam9x5-wm8731-audio";
|
||||
|
||||
atmel,model = "wm8731 @ AT91SAM9X5EK";
|
||||
|
||||
atmel,audio-routing =
|
||||
"Headphone Jack", "RHPOUT",
|
||||
"Headphone Jack", "LHPOUT",
|
||||
"LLINEIN", "Line In Jack",
|
||||
"RLINEIN", "Line In Jack";
|
||||
|
||||
atmel,ssc-controller = <&ssc0>;
|
||||
atmel,audio-codec = <&wm8731>;
|
||||
};
|
||||
};
|
94
sys/gnu/dts/arm/ethernut5.dts
Normal file
94
sys/gnu/dts/arm/ethernut5.dts
Normal file
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* ethernut5.dts - Device Tree file for Ethernut 5 board
|
||||
*
|
||||
* Copyright (C) 2012 egnite GmbH <info@egnite.de>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ethernut 5";
|
||||
compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x08000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <18432000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffc4000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
gpios = <0
|
||||
&pioC 14 GPIO_ACTIVE_HIGH
|
||||
0
|
||||
>;
|
||||
|
||||
root@0 {
|
||||
label = "root";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
data@20000 {
|
||||
label = "data";
|
||||
reg = <0x08000000 0x38000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
status = "okay";
|
||||
|
||||
pcf8563@50 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
};
|
59
sys/gnu/dts/arm/evk-pro3.dts
Normal file
59
sys/gnu/dts/arm/evk-pro3.dts
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3
|
||||
*
|
||||
* Copyright (C) 2012 Telit,
|
||||
* 2012 Fabio Porcedda <fabio.porcedda@gmail.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ge863-pro3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Telit EVK-PRO3 for Telit GE863-PRO3";
|
||||
compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9";
|
||||
|
||||
clocks {
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
macb0: ethernet@fffc4000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
56
sys/gnu/dts/arm/ge863-pro3.dtsi
Normal file
56
sys/gnu/dts/arm/ge863-pro3.dtsi
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
|
||||
*
|
||||
* Copyright (C) 2012 Telit,
|
||||
* 2012 Fabio Porcedda <fabio.porcedda@gmail.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include "at91sam9260.dtsi"
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <6000000>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
boot@0 {
|
||||
label = "boot";
|
||||
reg = <0x0 0x7c0000>;
|
||||
};
|
||||
|
||||
root@07c0000 {
|
||||
label = "root";
|
||||
reg = <0x7c0000 0x7840000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs";
|
||||
};
|
||||
};
|
89
sys/gnu/dts/arm/imx51-apf51.dts
Normal file
89
sys/gnu/dts/arm/imx51-apf51.dts
Normal file
@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright 2012 Armadeus Systems - <support@armadeus.com>
|
||||
* Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
|
||||
*
|
||||
* Based on mx51-babbage.dts
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx51.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Armadeus Systems APF51 module";
|
||||
compatible = "armadeus,imx51-apf51", "fsl,imx51";
|
||||
|
||||
memory {
|
||||
reg = <0x90000000 0x20000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
osc {
|
||||
clock-frequency = <33554432>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "mii";
|
||||
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
|
||||
phy-reset-duration = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-apf51 {
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
211
sys/gnu/dts/arm/imx51-apf51dev.dts
Normal file
211
sys/gnu/dts/arm/imx51-apf51dev.dts
Normal file
@ -0,0 +1,211 @@
|
||||
/*
|
||||
* Copyright 2013 Armadeus Systems - <support@armadeus.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/* APF51Dev is a docking board for the APF51 SOM */
|
||||
#include "imx51-apf51.dts"
|
||||
|
||||
/ {
|
||||
model = "Armadeus Systems APF51Dev docking/development board";
|
||||
compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
|
||||
|
||||
display@di1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "bgr666";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp1>;
|
||||
|
||||
display-timings {
|
||||
lw700 {
|
||||
native-mode;
|
||||
clock-frequency = <33000033>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <96>;
|
||||
hfront-porch = <96>;
|
||||
vback-porch = <20>;
|
||||
vfront-porch = <21>;
|
||||
hsync-len = <64>;
|
||||
vsync-len = <4>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_disp0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
user-key {
|
||||
label = "user";
|
||||
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <256>; /* BTN_0 */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio4 25 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
|
||||
<&gpio3 27 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1>;
|
||||
cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx51-apf51dev {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
|
||||
MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
|
||||
MX51_PAD_EIM_CS4__GPIO2_29 0x100
|
||||
MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
|
||||
MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
|
||||
MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
|
||||
MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu_di0_disp0 {
|
||||
remote-endpoint = <&display_in>;
|
||||
};
|
667
sys/gnu/dts/arm/imx51-babbage.dts
Normal file
667
sys/gnu/dts/arm/imx51-babbage.dts
Normal file
@ -0,0 +1,667 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx51.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX51 Babbage Board";
|
||||
compatible = "fsl,imx51-babbage", "fsl,imx51";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x90000000 0x20000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
ckih1 {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
clk_26M: codec_clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
display0: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp1>;
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: dvi {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_disp0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
display1: display@di1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb565";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp2>;
|
||||
status = "disabled";
|
||||
display-timings {
|
||||
native-mode = <&timing1>;
|
||||
timing1: claawvga {
|
||||
clock-frequency = <27000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <40>;
|
||||
hfront-porch = <60>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <10>;
|
||||
hsync-len = <20>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display1_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_disp1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
led-diagnostic {
|
||||
label = "diagnostic";
|
||||
gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_usbh1_vbus: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1reg>;
|
||||
reg = <0>;
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotgreg>;
|
||||
reg = <1>;
|
||||
regulator-name = "usbotg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx51-babbage-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx51-babbage-sgtl5000";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
|
||||
usbphy {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
usbh1phy: usbh1phy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reg = <0>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio4 25 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13892@0 {
|
||||
compatible = "fsl,mc13892";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
spi-max-frequency = <6000000>;
|
||||
spi-cs-high;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,mc13xxx-uses-rtc;
|
||||
|
||||
regulators {
|
||||
sw1_reg: sw1 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1375000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3_reg: sw3 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: vpll {
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig_reg: vdig {
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <1650000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsd_reg: vsd {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
};
|
||||
|
||||
vusb2_reg: vusb2 {
|
||||
regulator-min-microvolt = <2400000>;
|
||||
regulator-max-microvolt = <2775000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vvideo_reg: vvideo {
|
||||
regulator-min-microvolt = <2775000>;
|
||||
regulator-max-microvolt = <2775000>;
|
||||
};
|
||||
|
||||
vaudio_reg: vaudio {
|
||||
regulator-min-microvolt = <2300000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
vcam_reg: vcam {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
flash: at45db321d@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "Kernel";
|
||||
reg = <0x40000 0x3c0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1>;
|
||||
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>;
|
||||
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "mii";
|
||||
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_clkcodec>;
|
||||
reg = <0x0a>;
|
||||
clocks = <&clk_26M>;
|
||||
VDDA-supply = <&vdig_reg>;
|
||||
VDDIO-supply = <&vvideo_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
&ipu_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&ipu_di1_disp1 {
|
||||
remote-endpoint = <&display1_in>;
|
||||
};
|
||||
|
||||
&kpp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_kpp>;
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0, 0, KEY_UP)
|
||||
MATRIX_KEY(0, 1, KEY_DOWN)
|
||||
MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
|
||||
MATRIX_KEY(0, 3, KEY_HOME)
|
||||
MATRIX_KEY(1, 0, KEY_RIGHT)
|
||||
MATRIX_KEY(1, 1, KEY_LEFT)
|
||||
MATRIX_KEY(1, 2, KEY_ENTER)
|
||||
MATRIX_KEY(1, 3, KEY_VOLUMEUP)
|
||||
MATRIX_KEY(2, 0, KEY_F6)
|
||||
MATRIX_KEY(2, 1, KEY_F8)
|
||||
MATRIX_KEY(2, 2, KEY_F9)
|
||||
MATRIX_KEY(2, 3, KEY_F10)
|
||||
MATRIX_KEY(3, 0, KEY_F1)
|
||||
MATRIX_KEY(3, 1, KEY_F2)
|
||||
MATRIX_KEY(3, 2, KEY_F3)
|
||||
MATRIX_KEY(3, 3, KEY_POWER)
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
fsl,usbphy = <&usbh1phy>;
|
||||
phy_type = "ulpi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "otg";
|
||||
disable-over-current;
|
||||
phy_type = "utmi_wide";
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-babbage {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_clkcodec: clkcodecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
MX51_PAD_GPIO1_0__GPIO1_0 0x100
|
||||
MX51_PAD_GPIO1_1__GPIO1_1 0x100
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
|
||||
MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
|
||||
MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
|
||||
MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
|
||||
MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
|
||||
MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
|
||||
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
|
||||
MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
|
||||
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpiokeysgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_A27__GPIO2_21 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D22__GPIO2_6 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp2: ipudisp2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
|
||||
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
|
||||
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
|
||||
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
|
||||
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
|
||||
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
|
||||
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
|
||||
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
|
||||
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
|
||||
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
|
||||
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
|
||||
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
|
||||
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
|
||||
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
|
||||
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
|
||||
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
|
||||
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
|
||||
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
|
||||
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
|
||||
MX51_PAD_DI_GP4__DI2_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
|
||||
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
|
||||
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
|
||||
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
|
||||
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
|
||||
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
|
||||
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
|
||||
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
|
||||
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1reg: usbh1reggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D21__GPIO2_5 0x85
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotgreg: usbotgreggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_7__GPIO1_7 0x85
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
108
sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts
Normal file
108
sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts
Normal file
@ -0,0 +1,108 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx51-digi-connectcore-som.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Digi ConnectCore CC(W)-MX51 JSK";
|
||||
compatible = "digi,connectcore-ccxmx51-jsk",
|
||||
"digi,connectcore-ccxmx51-som", "fsl,imx51";
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &uart1;
|
||||
};
|
||||
};
|
||||
|
||||
&owire {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_owire>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-digi-connectcore-jsk {
|
||||
pinctrl_owire: owiregrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
377
sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi
Normal file
377
sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi
Normal file
@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx51.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Digi ConnectCore CC(W)-MX51";
|
||||
compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
|
||||
|
||||
memory {
|
||||
reg = <0x90000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13892@0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mc13892>;
|
||||
compatible = "fsl,mc13892";
|
||||
spi-max-frequency = <16000000>;
|
||||
spi-cs-high;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,mc13xxx-uses-rtc;
|
||||
|
||||
regulators {
|
||||
sw1_reg: sw1 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <1225000>;
|
||||
regulator-max-microvolt = <1225000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3_reg: sw3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst { };
|
||||
|
||||
viohi_reg: viohi {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: vpll {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig_reg: vdig {
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vsd_reg: vsd {
|
||||
regulator-min-microvolt = <3150000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vusb2_reg: vusb2 {
|
||||
regulator-min-microvolt = <2600000>;
|
||||
regulator-max-microvolt = <2600000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vvideo_reg: vvideo {
|
||||
regulator-min-microvolt = <2775000>;
|
||||
regulator-max-microvolt = <2775000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaudio_reg: vaudio {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcam_reg: vcam {
|
||||
regulator-min-microvolt = <2750000>;
|
||||
regulator-max-microvolt = <2750000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <3150000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vusb_reg: vusb {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
gpo1_reg: gpo1 { };
|
||||
|
||||
gpo2_reg: gpo2 { };
|
||||
|
||||
gpo3_reg: gpo3 { };
|
||||
|
||||
gpo4_reg: gpo4 { };
|
||||
|
||||
pwgt2spi_reg: pwgt2spi {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcoincell_reg: vcoincell {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>;
|
||||
cap-sdio-irq;
|
||||
enable-sdio-wakeup;
|
||||
keep-power-in-suspend;
|
||||
max-frequency = <50000000>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
vmmc-supply = <&gpo4_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "mii";
|
||||
phy-supply = <&gpo3_reg>;
|
||||
/* Pins shared with LCD2, keep status disabled */
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
mma7455l@1d {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mma7455l>;
|
||||
compatible = "fsl,mma7455l";
|
||||
reg = <0x1d>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nfc>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
phy_type = "utmi_wide";
|
||||
disable-over-current;
|
||||
/* Device role is not known, keep status disabled */
|
||||
};
|
||||
|
||||
&weim {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_weim>;
|
||||
status = "okay";
|
||||
|
||||
lan9221: lan9221@5,0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lan9221>;
|
||||
compatible = "smsc,lan9221", "smsc,lan9115";
|
||||
reg = <5 0x00000000 0x1000>;
|
||||
fsl,weim-cs-timing = <
|
||||
0x00420081 0x00000000
|
||||
0x32260000 0x00000000
|
||||
0x72080f00 0x00000000
|
||||
>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <2>;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&gpo2_reg>;
|
||||
vddvario-supply = <&gpo2_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-digi-connectcore-som {
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nfc: nfcgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
|
||||
MX51_PAD_NANDF_D1__NANDF_D1 0x80000000
|
||||
MX51_PAD_NANDF_D2__NANDF_D2 0x80000000
|
||||
MX51_PAD_NANDF_D3__NANDF_D3 0x80000000
|
||||
MX51_PAD_NANDF_D4__NANDF_D4 0x80000000
|
||||
MX51_PAD_NANDF_D5__NANDF_D5 0x80000000
|
||||
MX51_PAD_NANDF_D6__NANDF_D6 0x80000000
|
||||
MX51_PAD_NANDF_D7__NANDF_D7 0x80000000
|
||||
MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000
|
||||
MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000
|
||||
MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000
|
||||
MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000
|
||||
MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000
|
||||
MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000
|
||||
MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lan9221: lan9221grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mc13892: mc13892grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mma7455l: mma7455lgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim: weimgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_DA0__EIM_DA0 0x80000000
|
||||
MX51_PAD_EIM_DA1__EIM_DA1 0x80000000
|
||||
MX51_PAD_EIM_DA2__EIM_DA2 0x80000000
|
||||
MX51_PAD_EIM_DA3__EIM_DA3 0x80000000
|
||||
MX51_PAD_EIM_DA4__EIM_DA4 0x80000000
|
||||
MX51_PAD_EIM_DA5__EIM_DA5 0x80000000
|
||||
MX51_PAD_EIM_DA6__EIM_DA6 0x80000000
|
||||
MX51_PAD_EIM_DA7__EIM_DA7 0x80000000
|
||||
MX51_PAD_EIM_DA8__EIM_DA8 0x80000000
|
||||
MX51_PAD_EIM_DA9__EIM_DA9 0x80000000
|
||||
MX51_PAD_EIM_DA10__EIM_DA10 0x80000000
|
||||
MX51_PAD_EIM_DA11__EIM_DA11 0x80000000
|
||||
MX51_PAD_EIM_DA12__EIM_DA12 0x80000000
|
||||
MX51_PAD_EIM_DA13__EIM_DA13 0x80000000
|
||||
MX51_PAD_EIM_DA14__EIM_DA14 0x80000000
|
||||
MX51_PAD_EIM_DA15__EIM_DA15 0x80000000
|
||||
MX51_PAD_EIM_A16__EIM_A16 0x80000000
|
||||
MX51_PAD_EIM_A17__EIM_A17 0x80000000
|
||||
MX51_PAD_EIM_A18__EIM_A18 0x80000000
|
||||
MX51_PAD_EIM_A19__EIM_A19 0x80000000
|
||||
MX51_PAD_EIM_A20__EIM_A20 0x80000000
|
||||
MX51_PAD_EIM_A21__EIM_A21 0x80000000
|
||||
MX51_PAD_EIM_A22__EIM_A22 0x80000000
|
||||
MX51_PAD_EIM_A23__EIM_A23 0x80000000
|
||||
MX51_PAD_EIM_A24__EIM_A24 0x80000000
|
||||
MX51_PAD_EIM_A25__EIM_A25 0x80000000
|
||||
MX51_PAD_EIM_A26__EIM_A26 0x80000000
|
||||
MX51_PAD_EIM_A27__EIM_A27 0x80000000
|
||||
MX51_PAD_EIM_D16__EIM_D16 0x80000000
|
||||
MX51_PAD_EIM_D17__EIM_D17 0x80000000
|
||||
MX51_PAD_EIM_D18__EIM_D18 0x80000000
|
||||
MX51_PAD_EIM_D19__EIM_D19 0x80000000
|
||||
MX51_PAD_EIM_D20__EIM_D20 0x80000000
|
||||
MX51_PAD_EIM_D21__EIM_D21 0x80000000
|
||||
MX51_PAD_EIM_D22__EIM_D22 0x80000000
|
||||
MX51_PAD_EIM_D23__EIM_D23 0x80000000
|
||||
MX51_PAD_EIM_D24__EIM_D24 0x80000000
|
||||
MX51_PAD_EIM_D25__EIM_D25 0x80000000
|
||||
MX51_PAD_EIM_D26__EIM_D26 0x80000000
|
||||
MX51_PAD_EIM_D27__EIM_D27 0x80000000
|
||||
MX51_PAD_EIM_D28__EIM_D28 0x80000000
|
||||
MX51_PAD_EIM_D29__EIM_D29 0x80000000
|
||||
MX51_PAD_EIM_D30__EIM_D30 0x80000000
|
||||
MX51_PAD_EIM_D31__EIM_D31 0x80000000
|
||||
MX51_PAD_EIM_OE__EIM_OE 0x80000000
|
||||
MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000
|
||||
MX51_PAD_EIM_LBA__EIM_LBA 0x80000000
|
||||
MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
104
sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi
Normal file
104
sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi
Normal file
@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "imx51.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Eukrea CPUIMX51";
|
||||
compatible = "eukrea,cpuimx51", "fsl,imx51";
|
||||
|
||||
memory {
|
||||
reg = <0x90000000 0x10000000>; /* 256M */
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pcf8563@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
tsc2007: tsc2007@49 {
|
||||
compatible = "ti,tsc2007";
|
||||
gpios = <&gpio4 0 1>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <0x0 0x8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc2007_1>;
|
||||
reg = <0x49>;
|
||||
ti,x-plate-ohms = <180>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-eukrea {
|
||||
pinctrl_tsc2007_1: tsc2007grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
|
||||
MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
|
||||
MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
294
sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts
Normal file
294
sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts
Normal file
@ -0,0 +1,294 @@
|
||||
/*
|
||||
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx51-eukrea-cpuimx51.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Eukrea CPUIMX51";
|
||||
compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
|
||||
|
||||
clocks {
|
||||
clk24M: can_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpiokeys_1>;
|
||||
|
||||
button-1 {
|
||||
label = "BP1";
|
||||
gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <256>;
|
||||
gpio-key,wakeup;
|
||||
linux,input-type = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpioled>;
|
||||
|
||||
led1 {
|
||||
label = "led1";
|
||||
gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_can: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "CAN_RST";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <20000>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "eukrea,asoc-tlv320";
|
||||
eukrea,model = "imx51-eukrea-tlv320aic23";
|
||||
ssi-controller = <&ssi2>;
|
||||
fsl,mux-int-port = <2>;
|
||||
fsl,mux-ext-port = <3>;
|
||||
};
|
||||
|
||||
usbphy {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
usbh1phy: usbh1phy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reg = <0>;
|
||||
clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
|
||||
clock-names = "main_clk";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
|
||||
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
can0: can@0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can>;
|
||||
compatible = "microchip,mcp2515";
|
||||
reg = <0>;
|
||||
clocks = <&clk24M>;
|
||||
spi-max-frequency = <10000000>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
vdd-supply = <®_can>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
tlv320aic23: codec@1a {
|
||||
compatible = "ti,tlv320aic23";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx51-eukrea {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
pinctrl_can: cangrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */
|
||||
MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_rtscts: uart3rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__UART3_RTS 0x1c5
|
||||
MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_backlight_1: backlightgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1_cd: esdhc1_cd {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_0__GPIO1_0 0xd5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpiokeys_1: gpiokeysgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D9__GPIO3_31 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpioled: gpioledgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_D10__GPIO3_30 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
codec-handle = <&tlv320aic23>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
fsl,usbphy = <&usbh1phy>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "otg";
|
||||
phy_type = "utmi_wide";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1_vbus>;
|
||||
reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
580
sys/gnu/dts/arm/imx51.dtsi
Normal file
580
sys/gnu/dts/arm/imx51.dtsi
Normal file
@ -0,0 +1,580 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include "imx51-pinfunc.h"
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = &fec;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
mmc0 = &esdhc1;
|
||||
mmc1 = &esdhc2;
|
||||
mmc2 = &esdhc3;
|
||||
mmc3 = &esdhc4;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &cspi;
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@e0000000 {
|
||||
compatible = "fsl,imx51-tzic", "fsl,tzic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xe0000000 0x4000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0>;
|
||||
clock-latency = <62500>;
|
||||
clocks = <&clks IMX5_CLK_CPU_PODF>;
|
||||
clock-names = "cpu";
|
||||
operating-points = <
|
||||
166000 1000000
|
||||
600000 1050000
|
||||
800000 1100000
|
||||
>;
|
||||
voltage-tolerance = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
usbphy {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reg = <0>;
|
||||
clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu_di0>, <&ipu_di1>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
|
||||
iram: iram@1ffe0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x1ffe0000 0x20000>;
|
||||
};
|
||||
|
||||
ipu: ipu@40000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-ipu";
|
||||
reg = <0x40000000 0x20000000>;
|
||||
interrupts = <11 10>;
|
||||
clocks = <&clks IMX5_CLK_IPU_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI0_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI1_GATE>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
|
||||
ipu_di0: port@2 {
|
||||
reg = <2>;
|
||||
|
||||
ipu_di0_disp0: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
ipu_di1: port@3 {
|
||||
reg = <3>;
|
||||
|
||||
ipu_di1_disp1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aips@70000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x70000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
spba@70000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x70000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
esdhc1: esdhc@70004000 {
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc2: esdhc@70008000 {
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@7000c000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x7000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART3_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi1: ecspi@70010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x70010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi2: ssi@70014000 {
|
||||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x70014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
|
||||
dmas = <&sdma 24 1 0>,
|
||||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc3: esdhc@70020000 {
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70020000 0x4000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc4: esdhc@70024000 {
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70024000 0x4000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usbotg: usb@73f80000 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh1: usb@73f80200 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh2: usb@73f80400 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh3: usb@73f80600 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@73f80800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx51-usbmisc";
|
||||
reg = <0x73f80800 0x200>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
};
|
||||
|
||||
gpio1: gpio@73f84000 {
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x73f84000 0x4000>;
|
||||
interrupts = <50 51>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@73f88000 {
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x73f88000 0x4000>;
|
||||
interrupts = <52 53>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@73f8c000 {
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x73f8c000 0x4000>;
|
||||
interrupts = <54 55>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@73f90000 {
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x73f90000 0x4000>;
|
||||
interrupts = <56 57>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
kpp: kpp@73f94000 {
|
||||
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
|
||||
reg = <0x73f94000 0x4000>;
|
||||
interrupts = <60>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@73f98000 {
|
||||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
};
|
||||
|
||||
wdog2: wdog@73f9c000 {
|
||||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: timer@73fa0000 {
|
||||
compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x73fa0000 0x4000>;
|
||||
interrupts = <39>;
|
||||
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
|
||||
<&clks IMX5_CLK_GPT_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
};
|
||||
|
||||
pwm1: pwm@73fb4000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x73fb4000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <61>;
|
||||
};
|
||||
|
||||
pwm2: pwm@73fb8000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x73fb8000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <94>;
|
||||
};
|
||||
|
||||
uart1: serial@73fbc000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART1_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@73fc0000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART2_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
src: src@73fd0000 {
|
||||
compatible = "fsl,imx51-src";
|
||||
reg = <0x73fd0000 0x4000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@73fd4000{
|
||||
compatible = "fsl,imx51-ccm";
|
||||
reg = <0x73fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aips@80000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
iim: iim@83f98000 {
|
||||
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
|
||||
reg = <0x83f98000 0x4000>;
|
||||
interrupts = <69>;
|
||||
clocks = <&clks IMX5_CLK_IIM_GATE>;
|
||||
};
|
||||
|
||||
owire: owire@83fa4000 {
|
||||
compatible = "fsl,imx51-owire", "fsl,imx21-owire";
|
||||
reg = <0x83fa4000 0x4000>;
|
||||
interrupts = <88>;
|
||||
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: ecspi@83fac000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x83fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma: sdma@83fb0000 {
|
||||
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x83fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
||||
<&clks IMX5_CLK_SDMA_GATE>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
cspi: cspi@83fc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x83fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
||||
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@83fc4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x83fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
clocks = <&clks IMX5_CLK_I2C2_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@83fc8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x83fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks IMX5_CLK_I2C1_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi1: ssi@83fcc000 {
|
||||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x83fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
|
||||
dmas = <&sdma 28 0 0>,
|
||||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audmux: audmux@83fd0000 {
|
||||
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
|
||||
reg = <0x83fd0000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
clock-names = "audmux";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
weim: weim@83fda000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,imx51-weim";
|
||||
reg = <0x83fda000 0x1000>;
|
||||
clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
|
||||
ranges = <
|
||||
0 0 0xb0000000 0x08000000
|
||||
1 0 0xb8000000 0x08000000
|
||||
2 0 0xc0000000 0x08000000
|
||||
3 0 0xc8000000 0x04000000
|
||||
4 0 0xcc000000 0x02000000
|
||||
5 0 0xce000000 0x02000000
|
||||
>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nfc: nand@83fdb000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,imx51-nand";
|
||||
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks IMX5_CLK_NFC_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pata: pata@83fe0000 {
|
||||
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
|
||||
reg = <0x83fe0000 0x4000>;
|
||||
interrupts = <70>;
|
||||
clocks = <&clks IMX5_CLK_PATA_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi3: ssi@83fe8000 {
|
||||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x83fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
|
||||
dmas = <&sdma 46 0 0>,
|
||||
<&sdma 47 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec: ethernet@83fec000 {
|
||||
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
|
||||
reg = <0x83fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
183
sys/gnu/dts/arm/imx53-ard.dts
Normal file
183
sys/gnu/dts/arm/imx53-ard.dts
Normal file
@ -0,0 +1,183 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Automotive Reference Design Board";
|
||||
compatible = "fsl,imx53-ard", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>;
|
||||
};
|
||||
|
||||
eim-cs1@f4000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eim-bus", "simple-bus";
|
||||
reg = <0xf4000000 0x3ff0000>;
|
||||
ranges;
|
||||
|
||||
lan9220@f4000000 {
|
||||
compatible = "smsc,lan9220", "smsc,lan9115";
|
||||
reg = <0xf4000000 0x2000000>;
|
||||
phy-mode = "mii";
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <31 0x8>;
|
||||
reg-io-width = <4>;
|
||||
/*
|
||||
* VDD33A and VDDVARIO of LAN9220 are supplied by
|
||||
* SW4_3V3 of LTC3589. Before the regulator driver
|
||||
* for this PMIC is available, we use a fixed dummy
|
||||
* 3V3 regulator to get LAN9220 driver probing work.
|
||||
*/
|
||||
vdd33a-supply = <®_3p3v>;
|
||||
vddvario-supply = <®_3p3v>;
|
||||
smsc,irq-push-pull;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
home {
|
||||
label = "Home";
|
||||
gpios = <&gpio5 10 0>;
|
||||
linux,code = <102>; /* KEY_HOME */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
gpios = <&gpio5 11 0>;
|
||||
linux,code = <158>; /* KEY_BACK */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
program {
|
||||
label = "Program";
|
||||
gpios = <&gpio5 12 0>;
|
||||
linux,code = <362>; /* KEY_PROGRAM */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio5 13 0>;
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio4 0 0>;
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1>;
|
||||
cd-gpios = <&gpio1 1 0>;
|
||||
wp-gpios = <&gpio1 9 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-ard {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
|
||||
MX53_PAD_GPIO_9__GPIO1_9 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_GPIO_10__GPIO4_0 0x80000000
|
||||
MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000
|
||||
MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000
|
||||
MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000
|
||||
MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000
|
||||
MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000
|
||||
MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000
|
||||
MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000
|
||||
MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000
|
||||
MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000
|
||||
MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000
|
||||
MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000
|
||||
MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000
|
||||
MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000
|
||||
MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000
|
||||
MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000
|
||||
MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000
|
||||
MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000
|
||||
MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000
|
||||
MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000
|
||||
MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000
|
||||
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000
|
||||
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000
|
||||
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000
|
||||
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000
|
||||
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000
|
||||
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000
|
||||
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000
|
||||
MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
|
||||
MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
|
||||
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
126
sys/gnu/dts/arm/imx53-evk.dts
Normal file
126
sys/gnu/dts/arm/imx53-evk.dts
Normal file
@ -0,0 +1,126 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Evaluation Kit";
|
||||
compatible = "fsl,imx53-evk", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x80000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
green {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio7 7 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
wp-gpios = <&gpio3 14 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
|
||||
status = "okay";
|
||||
|
||||
flash: at45db321d@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "Kernel";
|
||||
reg = <0x40000 0x3c0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3_1>;
|
||||
cd-gpios = <&gpio3 11 0>;
|
||||
wp-gpios = <&gpio3 12 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
|
||||
MX53_PAD_EIM_D19__GPIO3_19 0x80000000
|
||||
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
|
||||
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
|
||||
MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13892@08 {
|
||||
compatible = "fsl,mc13892", "fsl,mc13xxx";
|
||||
reg = <0x08>;
|
||||
};
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
};
|
140
sys/gnu/dts/arm/imx53-m53.dtsi
Normal file
140
sys/gnu/dts/arm/imx53-m53.dtsi
Normal file
@ -0,0 +1,140 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DENX M53";
|
||||
compatible = "denx,imx53-m53", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x20000000>,
|
||||
<0xb0000000 0x20000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p2v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P2V";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_backlight: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "lcd-supply";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
stmpe610@41 {
|
||||
compatible = "st,stmpe610";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x41>;
|
||||
id = <0>;
|
||||
blocks = <0x5>;
|
||||
interrupts = <6 0x0>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
irq-trigger = <0x1>;
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "st,stmpe-ts";
|
||||
reg = <0>;
|
||||
st,sample-time = <4>;
|
||||
st,mod-12b = <1>;
|
||||
st,ref-sel = <0>;
|
||||
st,adc-freq = <1>;
|
||||
st,ave-ctrl = <3>;
|
||||
st,touch-det-delay = <3>;
|
||||
st,settling = <4>;
|
||||
st,fraction-z = <7>;
|
||||
st,i-drive = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t62";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-m53evk {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nand: nandgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
||||
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
||||
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
||||
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
||||
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
||||
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
||||
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
||||
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
356
sys/gnu/dts/arm/imx53-m53evk.dts
Normal file
356
sys/gnu/dts/arm/imx53-m53evk.dts
Normal file
@ -0,0 +1,356 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53-m53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DENX M53EVK";
|
||||
compatible = "denx,imx53-m53evk", "fsl,imx53";
|
||||
|
||||
display1: display@di1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "bgr666";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp1>;
|
||||
|
||||
display-timings {
|
||||
800x480p60 {
|
||||
native-mode;
|
||||
clock-frequency = <31500000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <40>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
vback-porch = <33>;
|
||||
vfront-porch = <9>;
|
||||
vsync-len = <3>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display1_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_disp1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 3000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
power-supply = <®_backlight>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pin_gpio>;
|
||||
|
||||
user1 {
|
||||
label = "user1";
|
||||
gpios = <&gpio2 8 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
user2 {
|
||||
label = "user2";
|
||||
gpios = <&gpio2 9 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_usbh1_vbus: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 2 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx53-m53evk-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx53-m53evk-sgtl5000";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"LINE_IN", "Line In Jack",
|
||||
"Headphone Jack", "HP_OUT",
|
||||
"Ext Spk", "LINE_OUT";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1>;
|
||||
cd-gpios = <&gpio1 1 0>;
|
||||
wp-gpios = <&gpio1 9 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
VDDA-supply = <®_3p2v>;
|
||||
VDDIO-supply = <®_3p2v>;
|
||||
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-m53evk {
|
||||
pinctrl_usb: usbgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_2__GPIO1_2 0x80000000
|
||||
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
led_pin_gpio: led_gpio@0 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
|
||||
MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
|
||||
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
|
||||
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
|
||||
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can2: can2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
|
||||
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp1: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
|
||||
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
|
||||
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
|
||||
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
|
||||
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
|
||||
MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
|
||||
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu_di1_disp1 {
|
||||
remote-endpoint = <&display1_in>;
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb>;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
phy_type = "utmi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
255
sys/gnu/dts/arm/imx53-mba53.dts
Normal file
255
sys/gnu/dts/arm/imx53-mba53.dts
Normal file
@ -0,0 +1,255 @@
|
||||
/*
|
||||
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53-tqma53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ MBa53 starter kit";
|
||||
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 50000>;
|
||||
brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
|
||||
default-brightness-level = <10>;
|
||||
enable-gpios = <&gpio7 7 0>;
|
||||
power-supply = <®_backlight>;
|
||||
};
|
||||
|
||||
disp1: display@disp1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp1_1>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
display1_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_disp1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_backlight: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "lcd-supply";
|
||||
gpio = <&gpio2 5 0>;
|
||||
startup-delay-us = <5000>;
|
||||
};
|
||||
|
||||
reg_3p2v: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "3P2V";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "tq,imx53-mba53-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx53-mba53-sgtl5000";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lvds1_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
lvds1 {
|
||||
pinctrl_lvds1_1: lvds1-grp1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
|
||||
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
|
||||
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
|
||||
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
|
||||
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lvds1_2: lvds1-grp2 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
|
||||
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
|
||||
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
|
||||
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
|
||||
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
disp1 {
|
||||
pinctrl_disp1_1: disp1-grp1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
|
||||
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
|
||||
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
tve {
|
||||
pinctrl_vga_sync_1: vgasync-grp1 {
|
||||
fsl,pins = <
|
||||
/* VGA_VSYNC, HSYNC with max drive strength */
|
||||
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu_di1_disp1 {
|
||||
remote-endpoint = <&display1_in>;
|
||||
};
|
||||
|
||||
&cspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&audmux {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
codec: sgtl5000@a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
|
||||
VDDA-supply = <®_3p2v>;
|
||||
VDDIO-supply = <®_3p2v>;
|
||||
};
|
||||
|
||||
expander: pca9554@20 {
|
||||
compatible = "pca9554";
|
||||
reg = <0x20>;
|
||||
interrupts = <109>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
sensor2: lm75@49 {
|
||||
compatible = "lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tve {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_vga_sync_1>;
|
||||
ddc-i2c-bus = <&i2c3>;
|
||||
fsl,tve-mode = "vga";
|
||||
fsl,hsync-pin = <4>;
|
||||
fsl,vsync-pin = <6>;
|
||||
status = "okay";
|
||||
};
|
366
sys/gnu/dts/arm/imx53-qsb-common.dtsi
Normal file
366
sys/gnu/dts/arm/imx53-qsb-common.dtsi
Normal file
@ -0,0 +1,366 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x20000000>,
|
||||
<0xb0000000 0x20000000>;
|
||||
};
|
||||
|
||||
display0: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb565";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp0>;
|
||||
status = "disabled";
|
||||
display-timings {
|
||||
claawvga {
|
||||
native-mode;
|
||||
clock-frequency = <27000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <40>;
|
||||
hfront-porch = <60>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <10>;
|
||||
hsync-len = <20>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_disp0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio1 8 0>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio2 14 0>;
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio2 15 0>;
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pin_gpio7_7>;
|
||||
|
||||
user {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio7 7 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p2v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P2V";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio7 8 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx53-qsb-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx53-qsb-sgtl5000";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipu_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3>;
|
||||
cd-gpios = <&gpio3 11 0>;
|
||||
wp-gpios = <&gpio3 12 0>;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-qsb {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
|
||||
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
|
||||
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
|
||||
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
led_pin_gpio7_7: led_gpio7_7@0 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc3: esdhc3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
|
||||
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
|
||||
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
|
||||
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp0: ipudisp0grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
|
||||
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
|
||||
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
|
||||
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
|
||||
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
|
||||
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
|
||||
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
|
||||
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
|
||||
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
|
||||
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
|
||||
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
|
||||
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
|
||||
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
|
||||
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
|
||||
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
|
||||
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
|
||||
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
|
||||
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
|
||||
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
|
||||
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
|
||||
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
|
||||
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
|
||||
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
|
||||
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
|
||||
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
|
||||
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
|
||||
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
|
||||
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_vga_sync: vgasync-grp {
|
||||
fsl,pins = <
|
||||
/* VGA_HSYNC, VSYNC with max drive strength */
|
||||
MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
|
||||
MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tve {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_vga_sync>;
|
||||
fsl,tve-mode = "vga";
|
||||
fsl,hsync-pin = <4>;
|
||||
fsl,vsync-pin = <6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
VDDA-supply = <®_3p2v>;
|
||||
VDDIO-supply = <®_3p2v>;
|
||||
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
compatible = "fsl,mma8450";
|
||||
reg = <0x1c>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_vbus>;
|
||||
phy_type = "utmi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
115
sys/gnu/dts/arm/imx53-qsb.dts
Normal file
115
sys/gnu/dts/arm/imx53-qsb.dts
Normal file
@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53-qsb-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Quick Start Board";
|
||||
compatible = "fsl,imx53-qsb", "fsl,imx53";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pmic: dialog@48 {
|
||||
compatible = "dlg,da9053-aa", "dlg,da9052";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
|
||||
|
||||
regulators {
|
||||
buck1_reg: buck1 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <2075000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck2_reg: buck2 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <2075000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck3_reg: buck3 {
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck4_reg: buck4 {
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
regulator-min-microvolt = <1725000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
regulator-min-microvolt = <1725000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: ldo6 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: ldo7 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: ldo8 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: ldo10 {
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <3650000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
158
sys/gnu/dts/arm/imx53-qsrb.dts
Normal file
158
sys/gnu/dts/arm/imx53-qsrb.dts
Normal file
@ -0,0 +1,158 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx53-qsb-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Quick Start-R Board";
|
||||
compatible = "fsl,imx53-qsrb", "fsl,imx53";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
i2c1 {
|
||||
/* open drain */
|
||||
pinctrl_i2c1_qsrb: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
|
||||
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_qsrb>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc34708@8 {
|
||||
compatible = "fsl,mc34708";
|
||||
reg = <0x08>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <23 0x8>;
|
||||
regulators {
|
||||
sw1_reg: sw1a {
|
||||
regulator-name = "SW1";
|
||||
regulator-min-microvolt = <650000>;
|
||||
regulator-max-microvolt = <1437500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw1b_reg: sw1b {
|
||||
regulator-name = "SW1B";
|
||||
regulator-min-microvolt = <650000>;
|
||||
regulator-max-microvolt = <1437500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-name = "SW2";
|
||||
regulator-min-microvolt = <650000>;
|
||||
regulator-max-microvolt = <1437500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3_reg: sw3 {
|
||||
regulator-name = "SW3";
|
||||
regulator-min-microvolt = <650000>;
|
||||
regulator-max-microvolt = <1425000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw4a_reg: sw4a {
|
||||
regulator-name = "SW4A";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4b_reg: sw4b {
|
||||
regulator-name = "SW4B";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw5_reg: sw5 {
|
||||
regulator-name = "SW5";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-name = "SWBST";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: vpll {
|
||||
regulator-name = "VPLL";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vrefddr_reg: vrefddr {
|
||||
regulator-name = "VREFDDR";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vusb_reg: vusb {
|
||||
regulator-name = "VUSB";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vusb2_reg: vusb2 {
|
||||
regulator-name = "VUSB2";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: vdac {
|
||||
regulator-name = "VDAC";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2775000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-name = "VGEN1";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-name = "VGEN2";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
279
sys/gnu/dts/arm/imx53-smd.dts
Normal file
279
sys/gnu/dts/arm/imx53-smd.dts
Normal file
@ -0,0 +1,279 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Smart Mobile Reference Design Board";
|
||||
compatible = "fsl,imx53-smd", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio2 14 0>;
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio2 15 0>;
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
wp-gpios = <&gpio4 11 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
|
||||
status = "okay";
|
||||
|
||||
zigbee: mc1323@0 {
|
||||
compatible = "fsl,mc1323";
|
||||
spi-max-frequency = <8000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
flash: m25p32@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32", "st,m25p";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "Kernel";
|
||||
reg = <0x40000 0x3c0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-smd {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
|
||||
MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
|
||||
MX53_PAD_EIM_D19__GPIO3_19 0x80000000
|
||||
MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
|
||||
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
|
||||
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
|
||||
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
|
||||
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
|
||||
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
|
||||
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
|
||||
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc3: esdhc3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
|
||||
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
|
||||
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
|
||||
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
|
||||
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
};
|
||||
|
||||
magnetometer: mag3110@0e {
|
||||
compatible = "fsl,mag3110";
|
||||
reg = <0x0e>;
|
||||
};
|
||||
|
||||
touchkey: mpr121@5a {
|
||||
compatible = "fsl,mpr121";
|
||||
reg = <0x5a>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
compatible = "fsl,mma8450";
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
camera: ov5642@3c {
|
||||
compatible = "ovti,ov5642";
|
||||
reg = <0x3c>;
|
||||
};
|
||||
|
||||
pmic: dialog@48 {
|
||||
compatible = "dialog,da9053", "dialog,da9052";
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
};
|
288
sys/gnu/dts/arm/imx53-tqma53.dtsi
Normal file
288
sys/gnu/dts/arm/imx53-tqma53.dtsi
Normal file
@ -0,0 +1,288 @@
|
||||
/*
|
||||
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ TQMa53";
|
||||
compatible = "tq,tqma53", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>,
|
||||
<&pinctrl_esdhc2_cdwp>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
wp-gpios = <&gpio1 2 0>;
|
||||
cd-gpios = <&gpio1 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <4>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
|
||||
<&gpio3 24 0>, <&gpio3 25 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&esdhc3 { /* EMMC */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
non-removable;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-tqma53 {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
|
||||
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
|
||||
MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
|
||||
MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
|
||||
MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
|
||||
MX53_PAD_GPIO_3__GPIO1_3 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
|
||||
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can2: can2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_cspi: cspigrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
|
||||
MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
|
||||
MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
|
||||
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
|
||||
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
|
||||
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
|
||||
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
|
||||
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
|
||||
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
|
||||
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2_cdwp: esdhc2cdwp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
|
||||
MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc3: esdhc3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
|
||||
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
|
||||
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cspi>;
|
||||
fsl,spi-num-chipselects = <3>;
|
||||
cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
|
||||
<&gpio1 21 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc34708@8 {
|
||||
compatible = "fsl,mc34708";
|
||||
reg = <0x8>;
|
||||
fsl,mc13xxx-uses-rtc;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <6 4>; /* PATA_DATA6, active high */
|
||||
};
|
||||
|
||||
sensor1: lm75@48 {
|
||||
compatible = "lm75";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
eeprom: 24c64@50 {
|
||||
compatible = "at,24c64";
|
||||
pagesize = <32>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rmii";
|
||||
status = "disabled";
|
||||
};
|
324
sys/gnu/dts/arm/imx53-tx53-x03x.dts
Normal file
324
sys/gnu/dts/arm/imx53-tx53-x03x.dts
Normal file
@ -0,0 +1,324 @@
|
||||
/*
|
||||
* Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53-tx53.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX53 module (LCD)";
|
||||
compatible = "karo,tx53", "fsl,imx53";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
soc {
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rgb24_vga1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_3v3>;
|
||||
brightness-levels = <
|
||||
0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100
|
||||
>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
reg_lcd_pwr: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
regulator-name = "LCD POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_lcd_reset: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
regulator-name = "LCD RESET";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
VDDA-supply = <®_2v5>;
|
||||
VDDIO-supply = <®_3v3>;
|
||||
clocks = <&mclk>;
|
||||
};
|
||||
|
||||
polytouch: edt-ft5x06@38 {
|
||||
compatible = "edt,edt-ft5x06";
|
||||
reg = <0x38>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <15 0>;
|
||||
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
touchscreen: tsc2007@48 {
|
||||
compatible = "ti,tsc2007";
|
||||
reg = <0x48>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc2007>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <26 0>;
|
||||
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
|
||||
ti,x-plate-ohms = <660>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx53-tx53-x03x {
|
||||
pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */
|
||||
MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */
|
||||
MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_9__KPP_COL_6 0x1f4
|
||||
MX53_PAD_GPIO_4__KPP_COL_7 0x1f4
|
||||
MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4
|
||||
MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4
|
||||
MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4
|
||||
MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4
|
||||
MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4
|
||||
MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rgb24_vga1: rgb24-vgagrp1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
|
||||
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
|
||||
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
|
||||
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
|
||||
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
|
||||
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
|
||||
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
|
||||
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
|
||||
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
|
||||
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
|
||||
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
|
||||
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
|
||||
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
|
||||
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
|
||||
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
|
||||
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
|
||||
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
|
||||
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
|
||||
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
|
||||
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
|
||||
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
|
||||
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
|
||||
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
|
||||
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
|
||||
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
|
||||
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
|
||||
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
|
||||
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tsc2007: tsc2007grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&kpp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_kpp>;
|
||||
/* sample keymap */
|
||||
/* row/col 0,1 are mapped to KPP row/col 6,7 */
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(6, 6, KEY_POWER)
|
||||
MATRIX_KEY(6, 7, KEY_KP0)
|
||||
MATRIX_KEY(6, 2, KEY_KP1)
|
||||
MATRIX_KEY(6, 3, KEY_KP2)
|
||||
MATRIX_KEY(7, 6, KEY_KP3)
|
||||
MATRIX_KEY(7, 7, KEY_KP4)
|
||||
MATRIX_KEY(7, 2, KEY_KP5)
|
||||
MATRIX_KEY(7, 3, KEY_KP6)
|
||||
MATRIX_KEY(2, 6, KEY_KP7)
|
||||
MATRIX_KEY(2, 7, KEY_KP8)
|
||||
MATRIX_KEY(2, 2, KEY_KP9)
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
243
sys/gnu/dts/arm/imx53-tx53-x13x.dts
Normal file
243
sys/gnu/dts/arm/imx53-tx53-x13x.dts
Normal file
@ -0,0 +1,243 @@
|
||||
/*
|
||||
* Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53-tx53.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX53 module (LVDS)";
|
||||
compatible = "karo,tx53", "fsl,imx53";
|
||||
|
||||
aliases {
|
||||
display = &lvds0;
|
||||
lvds0 = &lvds0;
|
||||
lvds1 = &lvds1;
|
||||
};
|
||||
|
||||
backlight0: backlight0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_3v3>;
|
||||
brightness-levels = <
|
||||
0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100
|
||||
>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
backlight1: backlight1 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 500000 0>;
|
||||
power-supply = <®_3v3>;
|
||||
brightness-levels = <
|
||||
0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100
|
||||
>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
reg_lcd_pwr0: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
regulator-name = "LVDS0 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_lcd_pwr1: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
regulator-name = "LVDS1 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
touchscreen2: eeti@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eeti2>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <23 0>;
|
||||
wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
VDDA-supply = <®_2v5>;
|
||||
VDDIO-supply = <®_3v3>;
|
||||
clocks = <&mclk>;
|
||||
};
|
||||
|
||||
touchscreen1: eeti@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eeti1>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx53-tx53-x13x {
|
||||
pinctrl_i2c2: i2c2-grp1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lvds0: lvds0grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
|
||||
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
|
||||
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
|
||||
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
|
||||
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lvds1: lvds1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
|
||||
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
|
||||
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
|
||||
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
|
||||
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>;
|
||||
};
|
||||
|
||||
pinctrl_eeti1: eeti1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_eeti2: eeti2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>;
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "jeida";
|
||||
fsl,data-width = <24>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing0>;
|
||||
lvds_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hsync-len = <60>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <7>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-channel@1 {
|
||||
fsl,data-mapping = "jeida";
|
||||
fsl,data-width = <24>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing1>;
|
||||
lvds_timing1: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hsync-len = <60>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <7>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
549
sys/gnu/dts/arm/imx53-tx53.dtsi
Normal file
549
sys/gnu/dts/arm/imx53-tx53.dtsi
Normal file
@ -0,0 +1,549 @@
|
||||
/*
|
||||
* Copyright 2012 <LW@KARO-electronics.de>
|
||||
* based on imx53-qsb.dts
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx53.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX53 module";
|
||||
compatible = "karo,tx53", "fsl,imx53";
|
||||
|
||||
aliases {
|
||||
can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
|
||||
can1 = &can1;
|
||||
ipu = &ipu;
|
||||
reg_can_xcvr = ®_can_xcvr;
|
||||
usbh1 = &usbh1;
|
||||
usbotg = &usbotg;
|
||||
};
|
||||
|
||||
clocks {
|
||||
ckih1 {
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
mclk: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_key>;
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_stk5led>;
|
||||
|
||||
user {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_2v5: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "2V5";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
};
|
||||
|
||||
reg_3v3: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_can_xcvr: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "CAN XCVR";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can_xcvr>;
|
||||
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1_vbus>;
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "usbotg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_vbus>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000";
|
||||
model = "tx53-audio-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
/* '1' based port numbers according to datasheet names */
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssi1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1>;
|
||||
xceiver-supply = <®_can_xcvr>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can2>;
|
||||
xceiver-supply = <®_can_xcvr>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
status = "okay";
|
||||
|
||||
cs-gpios = <
|
||||
&gpio2 30 GPIO_ACTIVE_HIGH
|
||||
&gpio3 19 GPIO_ACTIVE_HIGH
|
||||
>;
|
||||
|
||||
spidev0: spi@0 {
|
||||
compatible = "spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <54000000>;
|
||||
};
|
||||
|
||||
spidev1: spi@1 {
|
||||
compatible = "spidev";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
|
||||
fsl,wp-controller;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
|
||||
fsl,wp-controller;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
|
||||
phy-handle = <&phy0>;
|
||||
mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <4>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
rtc1: ds1339@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ds1339>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <20 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-tx53 {
|
||||
pinctrl_hog: hoggrp {
|
||||
/* pins not in use by any device on the Starterkit board series */
|
||||
fsl,pins = <
|
||||
/* CMOS Sensor Interface */
|
||||
MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4
|
||||
MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4
|
||||
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4
|
||||
MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4
|
||||
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4
|
||||
MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4
|
||||
MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4
|
||||
MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4
|
||||
MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4
|
||||
MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4
|
||||
MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4
|
||||
MX53_PAD_GPIO_0__GPIO1_0 0x1f4
|
||||
/* Module Specific Signal */
|
||||
/* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */
|
||||
/* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */
|
||||
MX53_PAD_EIM_D29__GPIO3_29 0x1f4
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x1f4
|
||||
/* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */
|
||||
/* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */
|
||||
MX53_PAD_EIM_A19__GPIO2_19 0x1f4
|
||||
MX53_PAD_EIM_A20__GPIO2_18 0x1f4
|
||||
MX53_PAD_EIM_A21__GPIO2_17 0x1f4
|
||||
MX53_PAD_EIM_A22__GPIO2_16 0x1f4
|
||||
MX53_PAD_EIM_A23__GPIO6_6 0x1f4
|
||||
MX53_PAD_EIM_A24__GPIO5_4 0x1f4
|
||||
MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4
|
||||
MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4
|
||||
MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4
|
||||
MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4
|
||||
/* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */
|
||||
/* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */
|
||||
MX53_PAD_GPIO_13__GPIO4_3 0x1f4
|
||||
MX53_PAD_EIM_CS0__GPIO2_23 0x1f4
|
||||
MX53_PAD_EIM_CS1__GPIO2_24 0x1f4
|
||||
MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4
|
||||
MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4
|
||||
MX53_PAD_EIM_EB0__GPIO2_28 0x1f4
|
||||
MX53_PAD_EIM_EB1__GPIO2_29 0x1f4
|
||||
MX53_PAD_EIM_OE__GPIO2_25 0x1f4
|
||||
MX53_PAD_EIM_LBA__GPIO2_27 0x1f4
|
||||
MX53_PAD_EIM_RW__GPIO2_26 0x1f4
|
||||
MX53_PAD_EIM_DA8__GPIO3_8 0x1f4
|
||||
MX53_PAD_EIM_DA9__GPIO3_9 0x1f4
|
||||
MX53_PAD_EIM_DA10__GPIO3_10 0x1f4
|
||||
MX53_PAD_EIM_DA11__GPIO3_11 0x1f4
|
||||
MX53_PAD_EIM_DA12__GPIO3_12 0x1f4
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x1f4
|
||||
MX53_PAD_EIM_DA14__GPIO3_14 0x1f4
|
||||
MX53_PAD_EIM_DA15__GPIO3_15 0x1f4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can2: can2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can_xcvr: can-xcvrgrp {
|
||||
fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */
|
||||
};
|
||||
|
||||
pinctrl_ds1339: ds1339grp {
|
||||
fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
|
||||
MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
|
||||
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
|
||||
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
|
||||
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
|
||||
MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
MX53_PAD_EIM_D24__GPIO3_24 0x1f0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
|
||||
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
|
||||
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
|
||||
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
|
||||
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
|
||||
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
|
||||
MX53_PAD_EIM_D25__GPIO3_25 0x1f0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_key: gpio-keygrp {
|
||||
fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
|
||||
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nand: nandgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
|
||||
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
|
||||
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
|
||||
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
|
||||
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
|
||||
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
|
||||
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
|
||||
MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ssi1: ssi1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ssi2: ssi2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
|
||||
MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
|
||||
MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
|
||||
MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
|
||||
MX53_PAD_EIM_D27__GPIO3_27 0x1f0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_stk5led: stk5ledgrp {
|
||||
fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
|
||||
MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
|
||||
MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
|
||||
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg_vbus: usbotg-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */
|
||||
MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&sdma {
|
||||
fsl,sdma-ram-script-name = "sdma-imx53.bin";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
codec-handle = <&sgtl5000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
phy_type = "utmi";
|
||||
disable-over-current;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
phy_type = "utmi";
|
||||
dr_mode = "peripheral";
|
||||
disable-over-current;
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
status = "okay";
|
||||
};
|
158
sys/gnu/dts/arm/imx53-voipac-bsb.dts
Normal file
158
sys/gnu/dts/arm/imx53-voipac-bsb.dts
Normal file
@ -0,0 +1,158 @@
|
||||
/*
|
||||
* Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53-voipac-dmm-668.dtsi"
|
||||
|
||||
/ {
|
||||
sound {
|
||||
compatible = "fsl,imx53-voipac-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx53-voipac-sgtl5000";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <5>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pin_gpio>;
|
||||
|
||||
led1 {
|
||||
label = "led-red";
|
||||
gpios = <&gpio3 29 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "led-orange";
|
||||
gpios = <&gpio2 31 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-voipac {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* SD2_CD */
|
||||
MX53_PAD_EIM_D25__GPIO3_25 0x80000000
|
||||
/* SD2_WP */
|
||||
MX53_PAD_EIM_A19__GPIO2_19 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
led_pin_gpio: led_gpio {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D29__GPIO3_29 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
/* Keyboard controller */
|
||||
pinctrl_kpp_1: kppgrp-1 {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_9__KPP_COL_6 0xe8
|
||||
MX53_PAD_GPIO_4__KPP_COL_7 0xe8
|
||||
MX53_PAD_KEY_COL2__KPP_COL_2 0xe8
|
||||
MX53_PAD_KEY_COL3__KPP_COL_3 0xe8
|
||||
MX53_PAD_KEY_COL4__KPP_COL_4 0xe8
|
||||
MX53_PAD_GPIO_2__KPP_ROW_6 0xe0
|
||||
MX53_PAD_GPIO_5__KPP_ROW_7 0xe0
|
||||
MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0
|
||||
MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0
|
||||
MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc2: esdhc2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
|
||||
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
|
||||
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
|
||||
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
|
||||
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
|
||||
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2>;
|
||||
cd-gpios = <&gpio3 25 0>;
|
||||
wp-gpios = <&gpio2 19 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
VDDA-supply = <®_3p3v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
clocks = <&clks 150>;
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_kpp_1>;
|
||||
linux,keymap = <
|
||||
0x0203003b /* KEY_F1 */
|
||||
0x0603003c /* KEY_F2 */
|
||||
0x0207003d /* KEY_F3 */
|
||||
0x0607003e /* KEY_F4 */
|
||||
>;
|
||||
keypad,num-rows = <8>;
|
||||
keypad,num-columns = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
277
sys/gnu/dts/arm/imx53-voipac-dmm-668.dtsi
Normal file
277
sys/gnu/dts/arm/imx53-voipac-dmm-668.dtsi
Normal file
@ -0,0 +1,277 @@
|
||||
/*
|
||||
* Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Voipac i.MX53 X53-DMM-668";
|
||||
compatible = "voipac,imx53-dmm-668", "fsl,imx53";
|
||||
|
||||
memory@70000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x70000000 0x20000000>;
|
||||
};
|
||||
|
||||
memory@b0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xb0000000 0x20000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 31 0>; /* PEN */
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-voipac {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* Make DA9053 regulator functional */
|
||||
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
|
||||
/* FEC Power enable */
|
||||
MX53_PAD_GPIO_11__GPIO4_1 0x80000000
|
||||
/* FEC RST */
|
||||
MX53_PAD_GPIO_12__GPIO4_2 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
|
||||
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
|
||||
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
|
||||
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nand: nandgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
||||
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
||||
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
||||
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
||||
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
||||
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
||||
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
||||
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <4>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio4 2 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: dialog@48 {
|
||||
compatible = "dlg,da9053-aa", "dlg,da9052";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
|
||||
|
||||
regulators {
|
||||
buck1_reg: buck1 {
|
||||
regulator-name = "BUCKCORE";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck2_reg: buck2 {
|
||||
regulator-name = "BUCKPRO";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck3_reg: buck3 {
|
||||
regulator-name = "BUCKMEM";
|
||||
regulator-min-microvolt = <1420000>;
|
||||
regulator-max-microvolt = <1580000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck4_reg: buck4 {
|
||||
regulator-name = "BUCKPERI";
|
||||
regulator-min-microvolt = <2370000>;
|
||||
regulator-max-microvolt = <2630000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
regulator-name = "ldo1_1v3";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
regulator-name = "ldo2_1v3";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
regulator-name = "ldo3_3v3";
|
||||
regulator-min-microvolt = <3250000>;
|
||||
regulator-max-microvolt = <3350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
regulator-name = "ldo4_2v775";
|
||||
regulator-min-microvolt = <2770000>;
|
||||
regulator-max-microvolt = <2780000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
regulator-name = "ldo5_3v3";
|
||||
regulator-min-microvolt = <3250000>;
|
||||
regulator-max-microvolt = <3350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: ldo6 {
|
||||
regulator-name = "ldo6_1v3";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7_reg: ldo7 {
|
||||
regulator-name = "ldo7_2v75";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: ldo8 {
|
||||
regulator-name = "ldo8_1v8";
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
regulator-name = "ldo9_1v5";
|
||||
regulator-min-microvolt = <1450000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo10_reg: ldo10 {
|
||||
regulator-name = "ldo10_1v3";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_vbus>;
|
||||
phy_type = "utmi";
|
||||
status = "okay";
|
||||
};
|
748
sys/gnu/dts/arm/imx53.dtsi
Normal file
748
sys/gnu/dts/arm/imx53.dtsi
Normal file
@ -0,0 +1,748 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include "imx53-pinfunc.h"
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = &fec;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
gpio5 = &gpio6;
|
||||
gpio6 = &gpio7;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
mmc0 = &esdhc1;
|
||||
mmc1 = &esdhc2;
|
||||
mmc2 = &esdhc3;
|
||||
mmc3 = &esdhc4;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &cspi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu_di0>, <&ipu_di1>;
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@0fffc000 {
|
||||
compatible = "fsl,imx53-tzic", "fsl,tzic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x0fffc000 0x4000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
|
||||
sata: sata@10000000 {
|
||||
compatible = "fsl,imx53-ahci";
|
||||
reg = <0x10000000 0x1000>;
|
||||
interrupts = <28>;
|
||||
clocks = <&clks IMX5_CLK_SATA_GATE>,
|
||||
<&clks IMX5_CLK_SATA_REF>,
|
||||
<&clks IMX5_CLK_AHB>;
|
||||
clock-names = "sata", "sata_ref", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipu: ipu@18000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ipu";
|
||||
reg = <0x18000000 0x08000000>;
|
||||
interrupts = <11 10>;
|
||||
clocks = <&clks IMX5_CLK_IPU_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI0_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI1_GATE>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
|
||||
ipu_di0: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
ipu_di0_disp0: endpoint@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu_di0_lvds0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_di1: port@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
ipu_di1_disp1: endpoint@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu_di1_lvds1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&lvds1_in>;
|
||||
};
|
||||
|
||||
ipu_di1_tve: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tve_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aips@50000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x50000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
spba@50000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x50000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
esdhc1: esdhc@50004000 {
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc2: esdhc@50008000 {
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@5000c000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x5000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART3_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi1: ecspi@50010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x50010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi2: ssi@50014000 {
|
||||
compatible = "fsl,imx53-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
reg = <0x50014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
|
||||
dmas = <&sdma 24 1 0>,
|
||||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc3: esdhc@50020000 {
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50020000 0x4000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc4: esdhc@50024000 {
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50024000 0x4000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
|
||||
<&clks IMX5_CLK_DUMMY>,
|
||||
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aipstz1: bridge@53f00000 {
|
||||
compatible = "fsl,imx53-aipstz";
|
||||
reg = <0x53f00000 0x60>;
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
|
||||
clock-names = "main_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
|
||||
clock-names = "main_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbotg: usb@53f80000 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh1: usb@53f80200 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh2: usb@53f80400 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh3: usb@53f80600 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@53f80800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx53-usbmisc";
|
||||
reg = <0x53f80800 0x200>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
};
|
||||
|
||||
gpio1: gpio@53f84000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53f84000 0x4000>;
|
||||
interrupts = <50 51>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@53f88000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53f88000 0x4000>;
|
||||
interrupts = <52 53>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@53f8c000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53f8c000 0x4000>;
|
||||
interrupts = <54 55>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@53f90000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53f90000 0x4000>;
|
||||
interrupts = <56 57>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
kpp: kpp@53f94000 {
|
||||
compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
|
||||
reg = <0x53f94000 0x4000>;
|
||||
interrupts = <60>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@53f98000 {
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
};
|
||||
|
||||
wdog2: wdog@53f9c000 {
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: timer@53fa0000 {
|
||||
compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53fa0000 0x4000>;
|
||||
interrupts = <39>;
|
||||
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
|
||||
<&clks IMX5_CLK_GPT_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-gpr", "syscon";
|
||||
reg = <0x53fa8000 0xc>;
|
||||
};
|
||||
|
||||
ldb: ldb@53fa8008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ldb";
|
||||
reg = <0x53fa8008 0x4>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI0_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI1_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI0_GATE>,
|
||||
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
status = "disabled";
|
||||
|
||||
lvds-channel@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_lvds0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
lvds1_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_lvds1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@53fb4000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <61>;
|
||||
};
|
||||
|
||||
pwm2: pwm@53fb8000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb8000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <94>;
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART1_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@53fc0000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART2_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can2: can@53fcc000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
src: src@53fd0000 {
|
||||
compatible = "fsl,imx53-src", "fsl,imx51-src";
|
||||
reg = <0x53fd0000 0x4000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@53fdc000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
interrupts = <103 104>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@53fe0000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fe0000 0x4000>;
|
||||
interrupts = <105 106>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@53fe4000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fe4000 0x4000>;
|
||||
interrupts = <107 108>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
i2c3: i2c@53fec000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x53fec000 0x4000>;
|
||||
interrupts = <64>;
|
||||
clocks = <&clks IMX5_CLK_I2C3_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@53ff0000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53ff0000 0x4000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART4_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x60000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
aipstz2: bridge@63f00000 {
|
||||
compatible = "fsl,imx53-aipstz";
|
||||
reg = <0x63f00000 0x60>;
|
||||
};
|
||||
|
||||
iim: iim@63f98000 {
|
||||
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
|
||||
reg = <0x63f98000 0x4000>;
|
||||
interrupts = <69>;
|
||||
clocks = <&clks IMX5_CLK_IIM_GATE>;
|
||||
};
|
||||
|
||||
uart5: serial@63f90000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x63f90000 0x4000>;
|
||||
interrupts = <86>;
|
||||
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART5_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
owire: owire@63fa4000 {
|
||||
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
|
||||
reg = <0x63fa4000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: ecspi@63fac000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x63fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma: sdma@63fb0000 {
|
||||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
||||
<&clks IMX5_CLK_SDMA_GATE>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
cspi: cspi@63fc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x63fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
||||
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@63fc4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
clocks = <&clks IMX5_CLK_I2C2_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@63fc8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks IMX5_CLK_I2C1_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi1: ssi@63fcc000 {
|
||||
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
reg = <0x63fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
|
||||
dmas = <&sdma 28 0 0>,
|
||||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audmux: audmux@63fd0000 {
|
||||
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
|
||||
reg = <0x63fd0000 0x4000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nfc: nand@63fdb000 {
|
||||
compatible = "fsl,imx53-nand";
|
||||
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks IMX5_CLK_NFC_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi3: ssi@63fe8000 {
|
||||
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
reg = <0x63fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
|
||||
dmas = <&sdma 46 0 0>,
|
||||
<&sdma 47 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec: ethernet@63fec000 {
|
||||
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
||||
reg = <0x63fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tve: tve@63ff0000 {
|
||||
compatible = "fsl,imx53-tve";
|
||||
reg = <0x63ff0000 0x1000>;
|
||||
interrupts = <92>;
|
||||
clocks = <&clks IMX5_CLK_TVE_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI1_SEL>;
|
||||
clock-names = "tve", "di_sel";
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
tve_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_tve>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vpu: vpu@63ff4000 {
|
||||
compatible = "fsl,imx53-vpu";
|
||||
reg = <0x63ff4000 0x1000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
|
||||
<&clks IMX5_CLK_VPU_GATE>;
|
||||
clock-names = "per", "ahb";
|
||||
resets = <&src 1>;
|
||||
iram = <&ocram>;
|
||||
};
|
||||
};
|
||||
|
||||
ocram: sram@f8000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xf8000000 0x20000>;
|
||||
clocks = <&clks IMX5_CLK_OCRAM>;
|
||||
};
|
||||
};
|
||||
};
|
85
sys/gnu/dts/arm/imx6dl-aristainetos_4.dts
Normal file
85
sys/gnu/dts/arm/imx6dl-aristainetos_4.dts
Normal file
@ -0,0 +1,85 @@
|
||||
/*
|
||||
* support fot the imx6 based aristainetos board
|
||||
*
|
||||
* Copyright (C) 2014 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-aristainetos.dtsi"
|
||||
|
||||
/ {
|
||||
model = "aristainetos i.MX6 Dual Lite Board 4";
|
||||
compatible = "fsl,imx6dl";
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_backlight>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
display0: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
480x800p60 {
|
||||
native-mode;
|
||||
clock-frequency = <30000000>;
|
||||
hactive = <480>;
|
||||
vactive = <800>;
|
||||
hfront-porch = <59>;
|
||||
hback-porch = <10>;
|
||||
hsync-len = <10>;
|
||||
vback-porch = <15>;
|
||||
vfront-porch = <15>;
|
||||
vsync-len = <15>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
74
sys/gnu/dts/arm/imx6dl-aristainetos_7.dts
Normal file
74
sys/gnu/dts/arm/imx6dl-aristainetos_7.dts
Normal file
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* support fot the imx6 based aristainetos board
|
||||
*
|
||||
* Copyright (C) 2014 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-aristainetos.dtsi"
|
||||
|
||||
/ {
|
||||
model = "aristainetos i.MX6 Dual Lite Board 7";
|
||||
compatible = "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
display0: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
800x480p60 {
|
||||
native-mode;
|
||||
clock-frequency = <33246000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <88>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <80>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <10>;
|
||||
vsync-len = <25>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 3000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_backlight>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
12
sys/gnu/dts/arm/imx6dl-cubox-i.dts
Normal file
12
sys/gnu/dts/arm/imx6dl-cubox-i.dts
Normal file
@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Russell King
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-cubox-i.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun Cubox-i Solo/DualLite";
|
||||
compatible = "solidrun,cubox-i/dl", "fsl,imx6dl";
|
||||
};
|
23
sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts
Normal file
23
sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts
Normal file
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __DTS_V1__
|
||||
#define __DTS_V1__
|
||||
/dts-v1/;
|
||||
#endif
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-dfi-fs700-m60.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DFI FS700-M60-6DL i.MX6dl Q7 Board";
|
||||
compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl";
|
||||
};
|
19
sys/gnu/dts/arm/imx6dl-gw51xx.dts
Normal file
19
sys/gnu/dts/arm/imx6dl-gw51xx.dts
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-gw51xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX";
|
||||
compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
19
sys/gnu/dts/arm/imx6dl-gw52xx.dts
Normal file
19
sys/gnu/dts/arm/imx6dl-gw52xx.dts
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-gw52xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
|
||||
compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
19
sys/gnu/dts/arm/imx6dl-gw53xx.dts
Normal file
19
sys/gnu/dts/arm/imx6dl-gw53xx.dts
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-gw53xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
|
||||
compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
19
sys/gnu/dts/arm/imx6dl-gw54xx.dts
Normal file
19
sys/gnu/dts/arm/imx6dl-gw54xx.dts
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-gw54xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
|
||||
compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
204
sys/gnu/dts/arm/imx6dl-hummingboard.dts
Normal file
204
sys/gnu/dts/arm/imx6dl-hummingboard.dts
Normal file
@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Copyright (C) 2013,2014 Russell King
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-microsom.dtsi"
|
||||
#include "imx6qdl-microsom-ar8035.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun HummingBoard DL/Solo";
|
||||
compatible = "solidrun,hummingboard", "fsl,imx6dl";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
ir_recv: ir-receiver {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpio1 2 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_3p3v: 3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: usb-h1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 0 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: usb-otg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 22 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
/* IMX6 doesn't implement this yet */
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-out;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
|
||||
|
||||
/*
|
||||
* Not fitted on Carrier-1 board... yet
|
||||
status = "okay";
|
||||
|
||||
rtc: pcf8523@68 {
|
||||
compatible = "nxp,pcf8523";
|
||||
reg = <0x68>;
|
||||
};
|
||||
*/
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
hummingboard {
|
||||
pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
|
||||
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_hdmi: hummingboard-hdmi {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_spdif: hummingboard-spdif {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
|
||||
/*
|
||||
* Similar to pinctrl_usbotg_2, but we want it
|
||||
* pulled down for a fixed host connection.
|
||||
*/
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
|
||||
fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&pinctrl_hummingboard_usdhc2_aux
|
||||
&pinctrl_hummingboard_usdhc2
|
||||
>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
cd-gpios = <&gpio1 4 0>;
|
||||
status = "okay";
|
||||
};
|
21
sys/gnu/dts/arm/imx6dl-nitrogen6x.dts
Normal file
21
sys/gnu/dts/arm/imx6dl-nitrogen6x.dts
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright 2013 Boundary Devices, Inc.
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-nitrogen6x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 DualLite Nitrogen6x Board";
|
||||
compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl";
|
||||
};
|
19
sys/gnu/dts/arm/imx6dl-phytec-pbab01.dts
Normal file
19
sys/gnu/dts/arm/imx6dl-phytec-pbab01.dts
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl-phytec-pfla02.dtsi"
|
||||
#include "imx6qdl-phytec-pbab01.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board";
|
||||
compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl";
|
||||
};
|
22
sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi
Normal file
22
sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-phytec-pfla02.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Phytec phyFLEX-i.MX6 DualLite/Solo";
|
||||
compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x20000000>;
|
||||
};
|
||||
};
|
30
sys/gnu/dts/arm/imx6dl-rex-basic.dts
Normal file
30
sys/gnu/dts/arm/imx6dl-rex-basic.dts
Normal file
@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright 2014 FEDEVEL, Inc.
|
||||
*
|
||||
* Author: Robert Nelson <robertcnelson@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-rex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rex Basic i.MX6 Dual Lite Board";
|
||||
compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,sst25vf016b";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
538
sys/gnu/dts/arm/imx6dl-riotboard.dts
Normal file
538
sys/gnu/dts/arm/imx6dl-riotboard.dts
Normal file
@ -0,0 +1,538 @@
|
||||
/*
|
||||
* Copyright 2014 Iain Paton <ipaton0@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "RIoTboard i.MX6S";
|
||||
compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_2p5v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_led>;
|
||||
|
||||
led0: user1 {
|
||||
label = "user1";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led1: user2 {
|
||||
label = "user2";
|
||||
gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-sgtl5000";
|
||||
model = "imx6-riotboard-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio3 31 0>;
|
||||
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
pmic: pf0100@08 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <16 8>;
|
||||
|
||||
regulators {
|
||||
reg_vddcore: sw1ab { /* VDDARM_IN */
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vddsoc: sw1c { /* VDDSOC_IN */
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_gen_3v3: sw2 { /* VDDHIGH_IN */
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_ddr_vtt: sw4 { /* MIPI conn */
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_5v_600mA: swbst { /* not used */
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr { /* VREF_DDR */
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vgen1_1v5: vgen1 { /* not used */
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
reg_vgen2_1v2_eth: vgen2 { /* pcie ? */
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vgen3_2v8: vgen3 { /* not used */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clocks = <&clks 116>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
cd-gpios = <&gpio1 4 0>;
|
||||
wp-gpios = <&gpio1 2 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
cd-gpios = <&gpio7 0 0>;
|
||||
wp-gpios = <&gpio7 1 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
imx6-riotboard {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */
|
||||
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */
|
||||
MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3: ecspi3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */
|
||||
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
|
||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led: ledgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
|
||||
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
|
||||
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
17
sys/gnu/dts/arm/imx6dl-sabreauto.dts
Normal file
17
sys/gnu/dts/arm/imx6dl-sabreauto.dts
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-sabreauto.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
|
||||
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
|
||||
};
|
20
sys/gnu/dts/arm/imx6dl-sabrelite.dts
Normal file
20
sys/gnu/dts/arm/imx6dl-sabrelite.dts
Normal file
@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-sabrelite.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 DualLite SABRE Lite Board";
|
||||
compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
|
||||
};
|
17
sys/gnu/dts/arm/imx6dl-sabresd.dts
Normal file
17
sys/gnu/dts/arm/imx6dl-sabresd.dts
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-sabresd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
|
||||
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
|
||||
};
|
103
sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts
Normal file
103
sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts
Normal file
@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6DL Module on CoMpact TFT";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&ET070001DM6>;
|
||||
|
||||
ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
xceiver-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
®_can_xcvr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
status = "disabled";
|
||||
};
|
177
sys/gnu/dts/arm/imx6dl-tx6u-801x.dts
Normal file
177
sys/gnu/dts/arm/imx6dl-tx6u-801x.dts
Normal file
@ -0,0 +1,177 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6U-801x Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
150
sys/gnu/dts/arm/imx6dl-tx6u-811x.dts
Normal file
150
sys/gnu/dts/arm/imx6dl-tx6u-811x.dts
Normal file
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6U-811x Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &lvds0;
|
||||
lvds0 = &lvds0;
|
||||
lvds1 = &lvds1;
|
||||
};
|
||||
|
||||
backlight0: backlight0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_lcd0_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
backlight1: backlight1 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 500000 0>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
polytouch2: eeti@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eeti>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6dl-tx6u-811x {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled"; /* pad conflict with backlight1 PWM */
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing0>;
|
||||
lvds_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "disabled";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing1>;
|
||||
lvds_timing1: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
22
sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts
Normal file
22
sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-wandboard-revb1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Dual Lite Board";
|
||||
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
};
|
22
sys/gnu/dts/arm/imx6dl-wandboard.dts
Normal file
22
sys/gnu/dts/arm/imx6dl-wandboard.dts
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-wandboard-revc1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Dual Lite Board";
|
||||
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
};
|
116
sys/gnu/dts/arm/imx6dl.dtsi
Normal file
116
sys/gnu/dts/arm/imx6dl.dtsi
Normal file
@ -0,0 +1,116 @@
|
||||
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "imx6dl-pinfunc.h"
|
||||
#include "imx6qdl.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
996000 1275000
|
||||
792000 1175000
|
||||
396000 1075000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
996000 1175000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX6QDL_CLK_ARM>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_STEP>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SW>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SYS>;
|
||||
clock-names = "arm", "pll2_pfd2_396m", "step",
|
||||
"pll1_sw", "pll1_sys";
|
||||
arm-supply = <®_arm>;
|
||||
pu-supply = <®_pu>;
|
||||
soc-supply = <®_soc>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
ocram: sram@00900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x20000>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
aips1: aips-bus@02000000 {
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6dl-iomuxc";
|
||||
};
|
||||
|
||||
pxp: pxp@020f0000 {
|
||||
reg = <0x020f0000 0x4000>;
|
||||
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
epdc: epdc@020f4000 {
|
||||
reg = <0x020f4000 0x4000>;
|
||||
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
lcdif: lcdif@020f8000 {
|
||||
reg = <0x020f8000 0x4000>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
aips2: aips-bus@02100000 {
|
||||
i2c4: i2c@021f8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021f8000 0x4000>;
|
||||
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6DL_CLK_I2C4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu1_di0>, <&ipu1_di1>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
compatible = "fsl,imx6dl-hdmi";
|
||||
};
|
||||
|
||||
&ldb {
|
||||
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
};
|
228
sys/gnu/dts/arm/imx6q-arm2.dts
Normal file
228
sys/gnu/dts/arm/imx6q-arm2.dts
Normal file
@ -0,0 +1,228 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad Armadillo2 Board";
|
||||
compatible = "fsl,imx6q-arm2", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
debug-led {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio3 25 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
||||
status = "disabled"; /* gpmi nand conflicts with SD */
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6q-arm2 {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpmi_nand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_cdwp: usdhc3cdwp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
cd-gpios = <&gpio6 11 0>;
|
||||
wp-gpios = <&gpio6 14 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3
|
||||
&pinctrl_usdhc3_cdwp>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
non-removable;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
fsl,dte-mode;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
107
sys/gnu/dts/arm/imx6q-cm-fx6.dts
Normal file
107
sys/gnu/dts/arm/imx6q-cm-fx6.dts
Normal file
@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright 2013 CompuLab Ltd.
|
||||
*
|
||||
* Author: Valentin Raevsky <valentin@compulab.co.il>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CompuLab CM-FX6";
|
||||
compatible = "compulab,cm-fx6", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat-led {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio2 31 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6q-cm-fx6 {
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpmi_nand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
20
sys/gnu/dts/arm/imx6q-cubox-i.dts
Normal file
20
sys/gnu/dts/arm/imx6q-cubox-i.dts
Normal file
@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Russell King
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-cubox-i.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun Cubox-i Dual/Quad";
|
||||
compatible = "solidrun,cubox-i/q", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
fsl,transmit-level-mV = <1104>;
|
||||
fsl,transmit-boost-mdB = <0>;
|
||||
fsl,transmit-atten-16ths = <9>;
|
||||
fsl,no-spread-spectrum;
|
||||
};
|
23
sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts
Normal file
23
sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts
Normal file
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __DTS_V1__
|
||||
#define __DTS_V1__
|
||||
/dts-v1/;
|
||||
#endif
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-dfi-fs700-m60.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DFI FS700-M60-6QD i.MX6qd Q7 Board";
|
||||
compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q";
|
||||
};
|
487
sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts
Normal file
487
sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts
Normal file
@ -0,0 +1,487 @@
|
||||
/*
|
||||
* Copyright 2013 Data Modul AG
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Data Modul eDM-QMX6 Board";
|
||||
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
aliases {
|
||||
gpio7 = &stmpe_gpio1;
|
||||
gpio8 = &stmpe_gpio2;
|
||||
stmpe-i2c0 = &stmpe1;
|
||||
stmpe-i2c1 = &stmpe2;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_switch: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_otg_switch";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio7 12 0>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_host1: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "usb_host1_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 31 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-blue {
|
||||
label = "blue";
|
||||
gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led-green {
|
||||
label = "green";
|
||||
gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-pink {
|
||||
label = "pink";
|
||||
gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-red {
|
||||
label = "red";
|
||||
gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi5>;
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio1 12 0>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "m25p80";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio1 25 0>;
|
||||
phy-supply = <&vgen2_1v2_eth>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2
|
||||
&pinctrl_stmpe1
|
||||
&pinctrl_stmpe2
|
||||
&pinctrl_pfuze>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@08 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <20 8>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3b_reg: sw3b {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen2_1v2_eth: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vdd_high_in: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stmpe1: stmpe1601@40 {
|
||||
compatible = "st,stmpe1601";
|
||||
reg = <0x40>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
vcc-supply = <&sw2_reg>;
|
||||
vio-supply = <&sw2_reg>;
|
||||
|
||||
stmpe_gpio1: stmpe_gpio {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "st,stmpe-gpio";
|
||||
};
|
||||
};
|
||||
|
||||
stmpe2: stmpe1601@44 {
|
||||
compatible = "st,stmpe1601";
|
||||
reg = <0x44>;
|
||||
interrupts = <2 0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
vcc-supply = <&sw2_reg>;
|
||||
vio-supply = <&sw2_reg>;
|
||||
|
||||
stmpe_gpio2: stmpe_gpio {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "st,stmpe-gpio";
|
||||
};
|
||||
};
|
||||
|
||||
temp1: ad7414@4c {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
temp2: ad7414@4d {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x4d>;
|
||||
};
|
||||
|
||||
rtc: m41t62@68 {
|
||||
compatible = "stm,m41t62";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6q-dmo-edmqmx6 {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
|
||||
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi5: ecspi5rp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
|
||||
MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
|
||||
MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
|
||||
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pfuze: pfuze100grp1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_stmpe1: stmpe1grp {
|
||||
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
|
||||
};
|
||||
|
||||
pinctrl_stmpe2: stmpe2grp {
|
||||
fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio4 8 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_host1>;
|
||||
disable-over-current;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
non-removable;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
176
sys/gnu/dts/arm/imx6q-gk802.dts
Normal file
176
sys/gnu/dts/arm/imx6q-gk802.dts
Normal file
@ -0,0 +1,176 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Philipp Zabel
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Zealz GK802";
|
||||
compatible = "zealz,imx6q-gk802", "fsl,imx6q";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart4;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
recovery-button {
|
||||
label = "recovery";
|
||||
gpios = <&gpio3 16 1>;
|
||||
linux,code = <0x198>; /* KEY_RESTART */
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Internal I2C */
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
/* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */
|
||||
eeprom: dm2016@51 {
|
||||
compatible = "sdmc,dm2016";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
/* External I2C via HDMI */
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6q-gk802 {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* Recovery button, active-low */
|
||||
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1
|
||||
/* RTL8192CU enable GPIO, active-low */
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* External USB-A port (USBOTG) */
|
||||
&usbotg {
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Internal USB port (USBH1), connected to RTL8192CU */
|
||||
&usbh1 {
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* External microSD */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio6 11 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Internal microSD */
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user