Fix punctuation and grammar, mostly by ending sentences with a period.
MFC after: 1 day
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=213402
@ -388,7 +388,7 @@ requests include both L1D demand RFO misses as well as L1D RFO prefetches.
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.It Li L2_RQSTS.RFOS
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.Pq Event 24H , Umask 0CH
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Counts all L2 store RFO requests. L2 RFO requests include both L1D demand
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RFO misses as well as L1D RFO prefetches..
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RFO misses as well as L1D RFO prefetches.
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.It Li L2_RQSTS.IFETCH_HIT
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.Pq Event 24H , Umask 10H
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Counts number of instruction fetches that hit the L2 cache. L2 instruction
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@ -474,13 +474,13 @@ This is a demand RFO request
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.It Li L2_WRITE.RFO.S_STATE
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.Pq Event 27H , Umask 02H
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Counts number of L2 store RFO requests where the cache line to be loaded is
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in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch,.
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This is a demand RFO request
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in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch.
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This is a demand RFO request.
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.It Li L2_WRITE.RFO.M_STATE
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.Pq Event 27H , Umask 08H
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Counts number of L2 store RFO requests where the cache line to be loaded is
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in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch.
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This is a demand RFO request
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This is a demand RFO request.
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.It Li L2_WRITE.RFO.HIT
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.Pq Event 27H , Umask 0EH
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Counts number of L2 store RFO requests where the cache line to be loaded is
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@ -491,7 +491,7 @@ This is a demand RFO request
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.Pq Event 27H , Umask 0FH
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Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO
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prefetch.
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This is a demand RFO request
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This is a demand RFO request.
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.It Li L2_WRITE.LOCK.I_STATE
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.Pq Event 27H , Umask 10H
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Counts number of L2 demand lock RFO requests where the cache line to be
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@ -539,13 +539,13 @@ Counts all L1 writebacks to the L2.
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Counts uncore Last Level Cache references. Because cache hierarchy, cache
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sizes and other implementation-specific characteristics; value comparison to
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estimate performance differences is not recommended.
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see Table A-1
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See Table A-1.
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.It Li L3_LAT_CACHE.MISS
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.Pq Event 2EH , Umask 01H
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Counts uncore Last Level Cache misses. Because cache hierarchy, cache sizes
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and other implementation-specific characteristics; value comparison to
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estimate performance differences is not recommended.
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see Table A-1
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See Table A-1.
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.It Li CPU_CLK_UNHALTED.THREAD_P
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.Pq Event 3CH , Umask 00H
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Counts the number of thread cycles while the thread is not in a halt state.
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@ -601,16 +601,16 @@ Counts Extended Page walk cycles.
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.It Li L1D.REPL
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.Pq Event 51H , Umask 01H
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Counts the number of lines brought into the L1 data cache.
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Counter 0, 1 only
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Counter 0, 1 only.
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.It Li L1D.M_REPL
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.Pq Event 51H , Umask 02H
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Counts the number of modified lines brought into the L1 data cache.
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Counter 0, 1 only
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Counter 0, 1 only.
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.It Li L1D.M_EVICT
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.Pq Event 51H , Umask 04H
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Counts the number of modified lines evicted from the L1 data cache due to
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replacement.
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Counter 0, 1 only
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Counter 0, 1 only.
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.It Li L1D.M_SNOOP_EVICT
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.Pq Event 51H , Umask 08H
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Counts the number of modified lines evicted from the L1 data cache due to
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@ -628,22 +628,22 @@ accepted into the fill buffer.
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.Pq Event 60H , Umask 01H
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Counts weighted cycles of offcore demand data read requests. Does not
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include L2 prefetch requests.
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counter 0
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Counter 0.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE
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.Pq Event 60H , Umask 02H
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Counts weighted cycles of offcore demand code read requests. Does not
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include L2 prefetch requests.
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counter 0
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Counter 0.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO
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.Pq Event 60H , Umask 04H
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Counts weighted cycles of offcore demand RFO requests. Does not include L2
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prefetch requests.
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counter 0
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Counter 0.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ
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.Pq Event 60H , Umask 08H
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Counts weighted cycles of offcore read requests of any kind. Include L2
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prefetch requests.
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counter 0
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Ccounter 0.
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.It Li CACHE_LOCK_CYCLES.L1D_L2
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.Pq Event 63H , Umask 01H
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Cycle count during which the L1D and L2 are locked. A lock is asserted when
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@ -915,7 +915,7 @@ ports. This is a core count only and can not be collected per thread.
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.It Li UOPS_EXECUTED.PORT015
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.Pq Event B1H , Umask 40H
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Counts number of Uops executed that where issued on port 0, 1, or 5.
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use cmask=1, invert=1 to count stall cycles
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Use cmask=1, invert=1 to count stall cycles.
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.It Li UOPS_EXECUTED.PORT234
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.Pq Event B1H , Umask 80H
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Counts number of Uops executed that where issued on port 2, 3, or 4.
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@ -928,18 +928,18 @@ Counts weighted cycles of snoopq requests for data. Counter 0 only
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Use cmask=1 to count cycles not empty.
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.It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE
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.Pq Event B3H , Umask 02H
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Counts weighted cycles of snoopq invalidate requests. Counter 0 only
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Counts weighted cycles of snoopq invalidate requests. Counter 0 only.
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Use cmask=1 to count cycles not empty.
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.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE
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.Pq Event B3H , Umask 04H
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Counts weighted cycles of snoopq requests for code. Counter 0 only
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Counts weighted cycles of snoopq requests for code. Counter 0 only.
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Use cmask=1 to count cycles not empty.
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.It Li SNOOPQ_REQUESTS.CODE
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.Pq Event B4H , Umask 01H
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Counts the number of snoop code requests
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Counts the number of snoop code requests.
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.It Li SNOOPQ_REQUESTS.DATA
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.Pq Event B4H , Umask 02H
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Counts the number of snoop data requests
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Counts the number of snoop data requests.
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.It Li SNOOPQ_REQUESTS.INVALIDATE
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.Pq Event B4H , Umask 04H
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Counts the number of snoop invalidate requests
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@ -947,7 +947,7 @@ Counts the number of snoop invalidate requests
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.Pq Event B7H , Umask 01H
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see Section 30.6.1.3, Off-core Response Performance Monitoring in the
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Processor Core.
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Requires programming MSR 01A6H
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Requires programming MSR 01A6H.
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.It Li SNOOP_RESPONSE.HIT
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.Pq Event B8H , Umask 01H
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Counts HIT snoop response sent by this thread in response to a snoop
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@ -963,8 +963,8 @@ request.
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.It Li OFF_CORE_RESPONSE_1
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.Pq Event BBH , Umask 01H
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see Section 30.6.1.3, Off-core Response Performance Monitoring in the
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Processor Core
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Use MSR 01A7H
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Processor Core.
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Use MSR 01A7H.
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.It Li INST_RETIRED.ANY_P
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.Pq Event C0H , Umask 01H
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See Table A-1
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@ -1007,21 +1007,21 @@ Counts the number of machine clears due to memory order conflicts.
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Counts the number of times that a program writes to a code section.
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Self-modifying code causes a sever penalty in all Intel 64 and IA-32
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processors. The modified cache line is written back to the L2 and L3caches.
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.It Li BR_INST_RETIRED.ALL_BRANCHES
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.It Li BR_INST_RETIRED.ANY_P
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.Pq Event C4H , Umask 00H
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See Table A-1
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See Table A-1.
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.It Li BR_INST_RETIRED.CONDITIONAL
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.Pq Event C4H , Umask 01H
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Counts the number of conditional branch instructions retired.
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.It Li BR_INST_RETIRED.NEAR_CALL
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.Pq Event C4H , Umask 02H
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Counts the number of direct & indirect near unconditional calls retired
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Counts the number of direct & indirect near unconditional calls retired.
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.It Li BR_INST_RETIRED.ALL_BRANCHES
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.Pq Event C4H , Umask 04H
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Counts the number of branch instructions retired
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.It Li BR_MISP_RETIRED.ALL_BRANCHES
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Counts the number of branch instructions retired.
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.It Li BR_MISP_RETIRED.ANY_P
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.Pq Event C5H , Umask 00H
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See Table A-1
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See Table A-1.
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.It Li BR_MISP_RETIRED.CONDITIONAL
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.Pq Event C5H , Umask 01H
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Counts mispredicted conditional retired calls.
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@ -267,10 +267,10 @@ Number of responses to code or data read snoops to a remote home that the L3
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has the referenced line cached in the M state.
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.It Li SNP_RESP_TO_REMOTE_HOME.HITM
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.Pq Event 07H , Umask 24H
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Number of HITM snoop responses to a remote home
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Number of HITM snoop responses to a remote home.
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.It Li L3_HITS.READ
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.Pq Event 08H , Umask 01H
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Number of code read, data read and RFO requests that hit in the L3
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Number of code read, data read and RFO requests that hit in the L3.
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.It Li L3_HITS.WRITE
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.Pq Event 08H , Umask 02H
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Number of writeback requests that hit in the L3. Writebacks from the cores
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@ -715,7 +715,7 @@ qualified by mask value written to MSR 396H. The following mask values are
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supported:
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0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS
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40001D00_00000000H:RSPIWB
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Match opcode/address by writing MSR 396H with mask supported mask value
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Match opcode/address by writing MSR 396H with mask supported mask value.
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.It Li ADDR_OPCODE_MATCH.REMOTE
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.Pq Event 35H , Umask 02H
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Counts number of requests from the remote socket, address/opcode of request
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@ -723,7 +723,7 @@ is qualified by mask value written to MSR 396H. The following mask values
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are supported:
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0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS
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40001D00_00000000H:RSPIWB
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Match opcode/address by writing MSR 396H with mask supported mask value
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Match opcode/address by writing MSR 396H with mask supported mask value.
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.It Li ADDR_OPCODE_MATCH.LOCAL
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.Pq Event 35H , Umask 04H
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Counts number of requests from the local socket, address/opcode of request
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@ -731,7 +731,7 @@ is qualified by mask value written to MSR 396H. The following mask values
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are supported:
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0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS
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40001D00_00000000H:RSPIWB
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Match opcode/address by writing MSR 396H with mask supported mask value
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Match opcode/address by writing MSR 396H with mask supported mask value.
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.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0
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.Pq Event 40H , Umask 01H
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Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled
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