Workaround a hang on some nForce2 systems that can happen if the CPU goes
into and out of the halt state very quickly. Submitted by: Andriy Gapon <avg at icyb dot net dot ua> MFC after: 1 week
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parent
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53b8229e97
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=158881
@ -51,6 +51,7 @@ __FBSDID("$FreeBSD$");
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static int fixup_pci_probe(device_t dev);
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static void fixwsc_natoma(device_t dev);
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static void fixc1_nforce2(device_t dev);
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static device_method_t fixup_pci_methods[] = {
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/* Device interface */
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@ -76,6 +77,9 @@ fixup_pci_probe(device_t dev)
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case 0x12378086: /* Intel 82440FX (Natoma) */
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fixwsc_natoma(dev);
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break;
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case 0x01e010de: /* nVidia nForce2 */
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fixc1_nforce2(dev);
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break;
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}
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return(ENXIO);
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}
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@ -100,3 +104,37 @@ fixwsc_natoma(device_t dev)
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}
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#endif
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}
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/*
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* Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work
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* around a hang that is triggered when the CPU generates a very fast
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* CONNECT/HALT cycle sequence. Specifically, the hang can result in
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* the lapic timer being stopped.
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*
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* This requires changing the value for config register at offset 0x6c
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* for the Host-PCI bridge at bus/dev/function 0/0/0:
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*
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* Chip Current Value New Value
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* ---- ---------- ----------
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* C17 0x1F0FFF01 0x1F01FF01
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* C18D 0x9F0FFF01 0x9F01FF01
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*
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* We do this by always clearing the bits in 0x000e0000.
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*
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* See also: http://lkml.org/lkml/2004/5/3/157
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*/
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static void
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fixc1_nforce2(device_t dev)
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{
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uint32_t val;
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if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 &&
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pci_get_function(dev) == 0) {
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val = pci_read_config(dev, 0x6c, 4);
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if (val & 0x000e0000) {
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printf("Correcting nForce2 C1 CPU disconnect hangs\n");
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val &= ~0x000e0000;
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pci_write_config(dev, 0x6c, val, 4);
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}
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}
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}
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