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Workaround a hang on some nForce2 systems that can happen if the CPU goes

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into and out of the halt state very quickly.

Submitted by:	Andriy Gapon <avg at icyb dot net dot ua>
MFC after:	1 week
This commit is contained in:
John Baldwin 2006-05-24 14:08:31 +00:00
parent e06dbd3229
commit 53b8229e97
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=158881
1 changed files with 38 additions and 0 deletions
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38
sys/dev/pci/fixup_pci.c
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@ -51,6 +51,7 @@ __FBSDID("$FreeBSD$");
static int fixup_pci_probe(device_t dev);
static void fixwsc_natoma(device_t dev);
static void fixc1_nforce2(device_t dev);
static device_method_t fixup_pci_methods[] = {
/* Device interface */
@ -76,6 +77,9 @@ fixup_pci_probe(device_t dev)
case 0x12378086: /* Intel 82440FX (Natoma) */
fixwsc_natoma(dev);
break;
case 0x01e010de: /* nVidia nForce2 */
fixc1_nforce2(dev);
break;
}
return(ENXIO);
}
@ -100,3 +104,37 @@ fixwsc_natoma(device_t dev)
}
#endif
}
/*
* Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work
* around a hang that is triggered when the CPU generates a very fast
* CONNECT/HALT cycle sequence. Specifically, the hang can result in
* the lapic timer being stopped.
*
* This requires changing the value for config register at offset 0x6c
* for the Host-PCI bridge at bus/dev/function 0/0/0:
*
* Chip Current Value New Value
* ---- ---------- ----------
* C17 0x1F0FFF01 0x1F01FF01
* C18D 0x9F0FFF01 0x9F01FF01
*
* We do this by always clearing the bits in 0x000e0000.
*
* See also: http://lkml.org/lkml/2004/5/3/157
*/
static void
fixc1_nforce2(device_t dev)
{
uint32_t val;
if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 &&
pci_get_function(dev) == 0) {
val = pci_read_config(dev, 0x6c, 4);
if (val & 0x000e0000) {
printf("Correcting nForce2 C1 CPU disconnect hangs\n");
val &= ~0x000e0000;
pci_write_config(dev, 0x6c, val, 4);
}
}
}