Remove run-time allocation of XLP IRQs
Follow the same static IRQ to Interrupt Table Entry mapping as the other OS supported on XLP.
This commit is contained in:
Jayachandran C.
parent
70abc1ff8e
commit
5441635eb0
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=279306
@ -62,7 +62,7 @@
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current-speed = <115200>;
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clock-frequency = <133000000>;
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interrupt-parent = <&pic>;
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interrupts = <9>;
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interrupts = <17>;
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};
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};
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@ -43,13 +43,26 @@
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#define XLP_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \
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(irq) <= PIC_IRT_LAST_IRQ)
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#define PIC_UART_0_IRQ 9
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#define PIC_PCIE_0_IRQ 11
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#define PIC_PCIE_1_IRQ 12
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#define PIC_PCIE_2_IRQ 13
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#define PIC_PCIE_3_IRQ 14
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#define PIC_EHCI_0_IRQ 16
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#define PIC_MMC_IRQ 21
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#define PIC_UART_0_IRQ 17
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#define PIC_UART_1_IRQ 18
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#define PIC_PCIE_0_IRQ 19
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#define PIC_PCIE_1_IRQ 20
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#define PIC_PCIE_2_IRQ 21
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#define PIC_PCIE_3_IRQ 22
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#define PIC_PCIE_IRQ(l) (PIC_PCIE_0_IRQ + (l))
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#define PIC_USB_0_IRQ 23
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#define PIC_USB_1_IRQ 24
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#define PIC_USB_2_IRQ 25
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#define PIC_USB_3_IRQ 26
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#define PIC_USB_4_IRQ 27
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#define PIC_USB_IRQ(n) (PIC_USB_0_IRQ + (n))
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#define PIC_MMC_IRQ 29
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#define PIC_I2C_0_IRQ 30
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#define PIC_I2C_1_IRQ 31
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#define PIC_I2C_IRQ(n) (PIC_I2C_0_IRQ + (n))
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/*
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* XLR needs custom pre and post handlers for PCI/PCI-e interrupts
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@ -61,12 +61,46 @@ struct xlp_intrsrc {
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void (*busack)(int); /* Additional ack */
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struct intr_event *ie; /* event corresponding to intr */
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int irq;
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int irt;
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};
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static struct xlp_intrsrc xlp_interrupts[XLR_MAX_INTR];
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static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
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static int intrcnt_index;
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int
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xlp_irq_to_irt(int irq)
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{
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uint32_t offset;
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switch (irq) {
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case PIC_UART_0_IRQ:
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case PIC_UART_1_IRQ:
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offset = XLP_IO_UART_OFFSET(0, irq - PIC_UART_0_IRQ);
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return (xlp_socdev_irt(offset));
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case PIC_PCIE_0_IRQ:
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case PIC_PCIE_1_IRQ:
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case PIC_PCIE_2_IRQ:
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case PIC_PCIE_3_IRQ:
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offset = XLP_IO_PCIE_OFFSET(0, irq - PIC_PCIE_0_IRQ);
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return (xlp_socdev_irt(offset));
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case PIC_USB_0_IRQ:
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case PIC_USB_1_IRQ:
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case PIC_USB_2_IRQ:
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case PIC_USB_3_IRQ:
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case PIC_USB_4_IRQ:
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offset = XLP_IO_USB_OFFSET(0, irq - PIC_USB_0_IRQ);
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return (xlp_socdev_irt(offset));
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case PIC_I2C_0_IRQ:
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case PIC_I2C_1_IRQ:
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offset = XLP_IO_I2C0_OFFSET(0);
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return (xlp_socdev_irt(offset) + irq - PIC_I2C_0_IRQ);
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default:
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printf("ERROR: %s: unknown irq %d\n", __func__, irq);
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return (-1);
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}
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}
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void
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xlp_enable_irq(int irq)
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{
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@ -102,7 +136,7 @@ xlp_post_filter(void *source)
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if (src->busack)
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src->busack(src->irq);
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nlm_pic_ack(xlp_pic_base, xlp_irq_to_irt(src->irq));
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nlm_pic_ack(xlp_pic_base, src->irt);
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}
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static void
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@ -119,7 +153,7 @@ xlp_post_ithread(void *source)
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{
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struct xlp_intrsrc *src = source;
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nlm_pic_ack(xlp_pic_base, xlp_irq_to_irt(src->irq));
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nlm_pic_ack(xlp_pic_base, src->irt);
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}
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void
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@ -163,6 +197,13 @@ xlp_establish_intr(const char *name, driver_filter_t filt,
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src->busack = busack;
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src->ie = ie;
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}
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if (XLP_IRQ_IS_PICINTR(irq)) {
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/* Set all irqs to CPU 0 for now */
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src->irt = xlp_irq_to_irt(irq);
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nlm_pic_write_irt_direct(xlp_pic_base, src->irt, 1, 0,
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PIC_LOCAL_SCHEDULING, irq, 0);
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}
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intr_event_add_handler(ie, name, filt, handler, arg,
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intr_priority(flags), flags, cookiep);
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xlp_enable_irq(irq);
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@ -62,7 +62,6 @@ extern void xlp_enable_threads(int code);
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#endif
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uint32_t xlp_get_cpu_frequency(int node, int core);
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int nlm_set_device_frequency(int node, int devtype, int frequency);
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int xlp_irt_to_irq(int irt);
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int xlp_irq_to_irt(int irq);
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static __inline int nlm_processor_id(void)
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@ -127,5 +126,12 @@ static __inline int nlm_is_xlp8xx_b0(void)
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rev == XLP_REVISION_B0);
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}
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static __inline int xlp_socdev_irt(uint32_t offset)
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{
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uint64_t base;
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base = nlm_pcicfg_base(offset);
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return (nlm_irtstart(base));
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}
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#endif /* LOCORE */
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#endif /* __NLM_XLP_H__ */
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@ -74,31 +74,6 @@ __FBSDID("$FreeBSD$");
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#define EMUL_MEM_START 0x16000000UL
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#define EMUL_MEM_END 0x18ffffffUL
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/* SoC device qurik handling */
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static int irt_irq_map[4 * 256];
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static int irq_irt_map[64];
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static void
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xlp_add_irq(int node, int irt, int irq)
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{
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int nodeirt = node * 256 + irt;
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irt_irq_map[nodeirt] = irq;
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irq_irt_map[irq] = nodeirt;
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}
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int
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xlp_irq_to_irt(int irq)
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{
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return irq_irt_map[irq];
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}
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int
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xlp_irt_to_irq(int nodeirt)
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{
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return irt_irq_map[nodeirt];
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}
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/* Override PCI a bit for SoC devices */
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enum {
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@ -108,24 +83,6 @@ enum {
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DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */
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};
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struct soc_dev_desc {
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u_int devid; /* device ID */
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int irqbase; /* start IRQ */
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u_int flags; /* flags */
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int ndevs; /* to keep track of number of devices */
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};
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struct soc_dev_desc xlp_dev_desc[] = {
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{ PCI_DEVICE_ID_NLM_ICI, 0, INTERNAL_DEV },
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{ PCI_DEVICE_ID_NLM_PIC, 0, INTERNAL_DEV },
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{ PCI_DEVICE_ID_NLM_FMN, 0, INTERNAL_DEV },
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{ PCI_DEVICE_ID_NLM_UART, PIC_UART_0_IRQ, MEM_RES_EMUL | DEV_MMIO32},
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{ PCI_DEVICE_ID_NLM_I2C, 0, MEM_RES_EMUL | DEV_MMIO32 },
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{ PCI_DEVICE_ID_NLM_NOR, 0, MEM_RES_EMUL },
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{ PCI_DEVICE_ID_NLM_MMC, PIC_MMC_IRQ, MEM_RES_EMUL },
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{ PCI_DEVICE_ID_NLM_EHCI, PIC_EHCI_0_IRQ, 0 }
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};
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struct xlp_devinfo {
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struct pci_devinfo pcidev;
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int irq;
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@ -133,19 +90,6 @@ struct xlp_devinfo {
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u_long mem_res_start;
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};
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static __inline struct soc_dev_desc *
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xlp_find_soc_desc(int devid)
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{
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struct soc_dev_desc *p;
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int i, n;
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n = sizeof(xlp_dev_desc) / sizeof(xlp_dev_desc[0]);
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for (i = 0, p = xlp_dev_desc; i < n; i++, p++)
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if (p->devid == devid)
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return (p);
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return (NULL);
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}
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static struct resource *
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xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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@ -219,9 +163,7 @@ xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f)
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{
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struct pci_devinfo *dinfo;
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struct xlp_devinfo *xlp_dinfo;
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struct soc_dev_desc *si;
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uint64_t pcibase;
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int domain, node, irt, irq, flags, devoffset, num;
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int domain, node, irq, devoffset, flags;
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uint16_t devid;
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domain = pcib_get_domain(dev);
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@ -232,36 +174,35 @@ xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f)
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/* Find if there is a desc for the SoC device */
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devid = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVICE, 2);
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si = xlp_find_soc_desc(devid);
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/* update flags and irq from desc if available */
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irq = 0;
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flags = 0;
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if (si != NULL) {
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if (si->irqbase != 0)
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irq = si->irqbase + si->ndevs;
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flags = si->flags;
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si->ndevs++;
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}
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/* skip internal devices */
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if ((flags & INTERNAL_DEV) != 0)
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irq = 0;
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switch (devid) {
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case PCI_DEVICE_ID_NLM_UART:
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irq = PIC_UART_0_IRQ + f;
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flags = MEM_RES_EMUL | DEV_MMIO32;
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break;
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case PCI_DEVICE_ID_NLM_I2C:
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flags = MEM_RES_EMUL | DEV_MMIO32;
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break;
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case PCI_DEVICE_ID_NLM_NOR:
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flags = MEM_RES_EMUL;
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break;
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case PCI_DEVICE_ID_NLM_MMC:
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irq = PIC_MMC_IRQ;
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flags = MEM_RES_EMUL;
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break;
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case PCI_DEVICE_ID_NLM_EHCI:
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irq = PIC_USB_0_IRQ + f;
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break;
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case PCI_DEVICE_ID_NLM_PCIE:
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break;
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case PCI_DEVICE_ID_NLM_ICI:
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case PCI_DEVICE_ID_NLM_PIC:
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case PCI_DEVICE_ID_NLM_FMN:
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default:
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return;
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/* PCIe interfaces are special, bug in Ax */
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if (devid == PCI_DEVICE_ID_NLM_PCIE) {
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xlp_add_irq(node, xlp_pcie_link_irt(f), PIC_PCIE_0_IRQ + f);
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} else {
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/* Stash intline and pin in shadow reg for devices */
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pcibase = nlm_pcicfg_base(devoffset);
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irt = nlm_irtstart(pcibase);
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num = nlm_irtnum(pcibase);
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if (irq != 0 && num > 0) {
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xlp_add_irq(node, irt, irq);
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nlm_write_reg(pcibase, XLP_PCI_DEVSCRATCH_REG0,
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(1 << 8) | irq);
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}
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}
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dinfo = pci_read_device(pcib, domain, b, s, f, sizeof(*xlp_dinfo));
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if (dinfo == NULL)
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return;
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@ -269,6 +210,11 @@ xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f)
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xlp_dinfo->irq = irq;
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xlp_dinfo->flags = flags;
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/* SoC device with interrupts need fixup (except PCIe controllers) */
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if (irq != 0 && devid != PCI_DEVICE_ID_NLM_PCIE)
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PCIB_WRITE_CONFIG(pcib, b, s, f, XLP_PCI_DEVSCRATCH_REG0 << 2,
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(1 << 8) | irq, 4);
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/* memory resource from ecfg space, if MEM_RES_EMUL is set */
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if ((flags & MEM_RES_EMUL) != 0)
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xlp_dinfo->mem_res_start = XLP_DEFAULT_IO_BASE + devoffset +
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@ -601,21 +547,17 @@ static int
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xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
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uint32_t *data)
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{
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int msi, irt;
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int link;
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if (irq >= 64) {
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msi = irq - 64;
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*addr = MIPS_MSI_ADDR(0);
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irt = xlp_pcie_link_irt(msi/32);
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if (irt != -1)
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*data = MIPS_MSI_DATA(xlp_irt_to_irq(irt));
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return (0);
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} else {
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if (irq < 64) {
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device_printf(dev, "%s: map_msi for irq %d - ignored",
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device_get_nameunit(pcib), irq);
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return (ENXIO);
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}
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link = (irq - 64) / 32;
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*addr = MIPS_MSI_ADDR(0);
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*data = MIPS_MSI_DATA(PIC_PCIE_IRQ(link));
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return (0);
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}
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static void
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@ -711,18 +653,13 @@ mips_platform_pcib_setup_intr(device_t dev, device_t child,
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nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
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(val | (PCIM_MSICTRL_MSI_ENABLE << 16) |
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(PCIM_MSICTRL_MMC_32 << 16)));
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xlpirq = xlp_pcie_link_irt(xlpirq / 32);
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if (xlpirq == -1)
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return (EINVAL);
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xlpirq = xlp_irt_to_irq(xlpirq);
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xlpirq = PIC_PCIE_IRQ(link);
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}
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/* Set all irqs to CPU 0 for now */
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nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0,
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PIC_LOCAL_SCHEDULING, xlpirq, 0);
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extra_ack = NULL;
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if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ)
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extra_ack = bridge_pcie_ack;
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else
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extra_ack = NULL;
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xlp_establish_intr(device_get_name(child), filt,
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intr, arg, xlpirq, flags, cookiep, extra_ack);
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@ -816,7 +753,7 @@ xlp_pcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
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static int
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mips_pcib_route_interrupt(device_t bus, device_t dev, int pin)
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{
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int irt, link;
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int f, d;
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/*
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* Validate requested pin number.
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@ -826,38 +763,21 @@ mips_pcib_route_interrupt(device_t bus, device_t dev, int pin)
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if (pci_get_bus(dev) == 0 &&
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pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) {
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/* SoC devices */
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uint64_t pcibase;
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int f, n, d, num;
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f = pci_get_function(dev);
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n = pci_get_slot(dev) / 8;
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d = pci_get_slot(dev) % 8;
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/*
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* For PCIe links, return link IRT, for other SoC devices
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* get the IRT from its PCIe header
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*/
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if (d == 1) {
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irt = xlp_pcie_link_irt(f);
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} else {
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pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f));
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irt = nlm_irtstart(pcibase);
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num = nlm_irtnum(pcibase);
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if (num != 1)
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device_printf(bus, "[%d:%d:%d] Error %d IRQs\n",
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n, d, f, num);
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}
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if (d == 1)
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return (PIC_PCIE_IRQ(f));
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else
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return (255); /* use intline, don't reroute */
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} else {
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/* Regular PCI devices */
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link = xlp_pcie_link(bus, dev);
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irt = xlp_pcie_link_irt(link);
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return (PIC_PCIE_IRQ(xlp_pcie_link(bus, dev)));
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}
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if (irt != -1)
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return (xlp_irt_to_irq(irt));
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return (255);
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}
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static device_method_t xlp_pcib_methods[] = {
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