Make 64-bit AIM trap handlers relocatable by changing all absolute branch
instructions to call through pointers instead. In general, these are set implicitly through relocation processing. One has to be set explicitly in machdep.c, however, to fit one handler in the tiny (8 instruction) space available. Reviewed by: andreast Differential revision: D1554 Tested on: UP and SMP G5, Cell, POWER5+
This commit is contained in:
Nathan Whitehorn
parent
da010b5606
commit
554dab448e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=277498
@ -238,7 +238,7 @@ extern void *trapcode64;
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#endif
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extern void *rstcode, *rstsize;
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extern void *trapcode, *trapsize;
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extern void *trapcode, *trapsize, *trapcode2;
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extern void *slbtrap, *slbtrapsize;
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extern void *alitrap, *alisize;
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extern void *dsitrap, *dsisize;
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@ -506,6 +506,7 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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generictrap = &trapcode;
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/* Set TOC base so that the interrupt code can get at it */
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*((void **)TRAP_GENTRAP) = &trapcode2;
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*((register_t *)TRAP_TOCBASE) = toc;
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#endif
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@ -302,8 +302,13 @@ CNAME(rstcode):
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insrdi %r9,%r8,1,0
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mtmsrd %r9
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isync
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bl 1f
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.llong cpu_reset
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1: mflr %r9
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ld %r9,0(%r9)
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mtlr %r9
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ba cpu_reset
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blr
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CNAME(rstsize) = . - CNAME(rstcode)
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cpu_reset:
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@ -342,16 +347,20 @@ cpu_reset:
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/*
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* This code gets copied to all the trap vectors
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* (except ISI/DSI, ALI, and the interrupts)
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* (except ISI/DSI, ALI, and the interrupts). Has to fit in 8 instructions!
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*/
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.globl CNAME(trapcode),CNAME(trapsize)
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.p2align 3
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CNAME(trapcode):
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mtsprg1 %r1 /* save SP */
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mflr %r1 /* Save the old LR in r1 */
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mtsprg2 %r1 /* And then in SPRG2 */
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li %r1,TRAP_GENTRAP
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ld %r1,0(%r1)
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mtlr %r1
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li %r1, 0xA0 /* How to get the vector from LR */
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bla generictrap /* LR & SPRG3 is exception # */
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blrl /* Branch to generictrap */
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CNAME(trapsize) = .-CNAME(trapcode)
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/*
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@ -361,6 +370,7 @@ CNAME(trapsize) = .-CNAME(trapcode)
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* the only time this can be called.
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*/
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.globl CNAME(slbtrap),CNAME(slbtrapsize)
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.p2align 3
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CNAME(slbtrap):
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mtsprg1 %r1 /* save SP */
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GET_CPUINFO(%r1)
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@ -369,17 +379,31 @@ CNAME(slbtrap):
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std %r2,(PC_SLBSAVE+104)(%r1)
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mfsrr1 %r2 /* test kernel mode */
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mtcr %r2
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bf 17,1f /* branch if PSL_PR is false */
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bf 17,2f /* branch if PSL_PR is false */
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/* User mode */
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ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
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mtcr %r2
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ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */
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mflr %r1 /* Save the old LR in r1 */
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mtsprg2 %r1 /* And then in SPRG2 */
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/* 52 bytes so far */
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bl 1f
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.llong generictrap
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1: mflr %r1
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ld %r1,0(%r1)
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mtlr %r1
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li %r1, 0x80 /* How to get the vector from LR */
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bla generictrap /* LR & SPRG3 is exception # */
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1: mflr %r2 /* Save the old LR in r2 */
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bla kern_slbtrap
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blrl /* Branch to generictrap */
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/* 84 bytes */
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2: mflr %r2 /* Save the old LR in r2 */
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nop
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bl 3f /* Begin dance to jump to kern_slbtrap*/
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.llong kern_slbtrap
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3: mflr %r1
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ld %r1,0(%r1)
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mtlr %r1
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GET_CPUINFO(%r1)
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blrl /* 124 bytes -- 4 to spare */
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CNAME(slbtrapsize) = .-CNAME(slbtrap)
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kern_slbtrap:
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@ -518,6 +542,16 @@ CNAME(alitrap):
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mflr %r28 /* save LR */
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mfcr %r29 /* save CR */
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/* Begin dance to branch to s_trap in a bit */
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b 1f
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.p2align 3
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1: nop
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bl 1f
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.llong s_trap
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1: mflr %r31
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ld %r31,0(%r31)
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mtlr %r31
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/* Put our exception vector in SPRG3 */
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li %r31, EXC_ALI
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mtsprg3 %r31
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@ -525,13 +559,12 @@ CNAME(alitrap):
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/* Test whether we already had PR set */
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mfsrr1 %r31
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mtcr %r31
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bla s_trap
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blrl
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CNAME(alisize) = .-CNAME(alitrap)
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/*
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* Similar to the above for DSI
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* Has to handle BAT spills
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* and standard pagetable spills
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* Has to handle standard pagetable spills
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*/
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.globl CNAME(dsitrap),CNAME(dsisize)
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CNAME(dsitrap):
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@ -542,14 +575,18 @@ CNAME(dsitrap):
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std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
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std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
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std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
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mfsprg1 %r1 /* restore SP */
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mfcr %r29 /* save CR */
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mfxer %r30 /* save XER */
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mtsprg2 %r30 /* in SPRG2 */
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mfsrr1 %r31 /* test kernel mode */
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mtcr %r31
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mflr %r28 /* save LR (SP already saved) */
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bla disitrap
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bl 1f /* Begin branching to disitrap */
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.llong disitrap
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1: mflr %r1
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ld %r1,0(%r1)
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mtlr %r1
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blrl /* Branch to generictrap */
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CNAME(dsisize) = .-CNAME(dsitrap)
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/*
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@ -624,7 +661,7 @@ realtrap:
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bl restore_kernsrs /* enable kernel mapping */
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mfsprg2 %r29
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mr %r28,%r27
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ba s_trap
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b s_trap
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/*
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* generictrap does some standard setup for trap handling to minimize
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@ -636,6 +673,8 @@ realtrap:
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* SPRG2 - Original LR
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*/
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.globl CNAME(trapcode2)
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trapcode2:
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generictrap:
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/* Save R1 for computing the exception vector */
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mtsprg3 %r1
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@ -657,6 +696,7 @@ generictrap:
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mfsprg3 %r31
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ori %r31,%r31,0xff00
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mflr %r30
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addi %r30,%r30,-4 /* The branch instruction, not the next */
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and %r30,%r30,%r31
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mtsprg3 %r30
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@ -804,9 +844,16 @@ CNAME(dblow):
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mfsprg2 %r29 /* ... and r29 */
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mflr %r1 /* save LR */
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mtsprg2 %r1 /* And then in SPRG2 */
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li %r1, 0 /* How to get the vector from LR */
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bla generictrap /* and we look like a generic trap */
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nop /* Begin branching to generictrap */
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bl 9f
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.llong generictrap
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9: mflr %r1
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ld %r1,0(%r1)
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mtlr %r1
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li %r1, 0 /* How to get the vector from LR */
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blrl /* Branch to generictrap */
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1:
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GET_CPUINFO(%r1)
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std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */
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@ -816,6 +863,11 @@ CNAME(dblow):
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std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
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std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
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mflr %r28 /* save LR */
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bla dbtrap
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bl 9f /* Begin branch */
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.llong dbtrap
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9: mflr %r1
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ld %r1,0(%r1)
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mtlr %r1
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blrl /* Branch to generictrap */
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CNAME(dbsize) = .-CNAME(dblow)
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#endif /* KDB */
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@ -123,7 +123,8 @@
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/* DTrace trap opcode. */
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#define EXC_DTRACE 0x7c810808
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/* Magic pointer to store TOC base for trap handlers on ppc64 */
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/* Magic pointer to store TOC base and other info for trap handlers on ppc64 */
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#define TRAP_GENTRAP 0x1f0
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#define TRAP_TOCBASE 0x1f8
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#ifndef LOCORE
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