hwpstate_intel(4): Add fallback EPP using PERF_BIAS MSR
Per Intel SDM (Vol 3b Part 2), if HWP indicates EPP (energy-performance preference) is not supported, the hardware instead uses the ENERGY_PERF_BIAS MSR. In the epp sysctl handler, fall back to that MSR if HWP does not support EPP and CPUID indicates the ENERGY_PERF_BIAS MSR is supported.
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parent
5e3574c8cd
commit
556a1a0bc6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=357378
@ -88,6 +88,7 @@ struct hwp_softc {
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bool hwp_activity_window;
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bool hwp_pref_ctrl;
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bool hwp_pkg_ctrl;
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bool hwp_perf_bias;
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uint64_t req; /* Cached copy of last request */
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@ -215,6 +216,26 @@ raw_to_percent(int x)
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return (round10(x * 1000 / 0xff));
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}
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/* Range of MSR_IA32_ENERGY_PERF_BIAS is more limited: 0-0xf. */
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static inline int
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percent_to_raw_perf_bias(int x)
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{
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/*
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* Round up so that raw values present as nice round human numbers and
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* also round-trip to the same raw value.
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*/
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MPASS(x <= 100 && x >= 0);
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return (((0xf * x) + 50) / 100);
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}
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static inline int
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raw_to_percent_perf_bias(int x)
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{
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/* Rounding to nice human numbers despite a step interval of 6.67%. */
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MPASS(x <= 0xf && x >= 0);
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return (((x * 20) / 0xf) * 5);
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}
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static int
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sysctl_epp_select(SYSCTL_HANDLER_ARGS)
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{
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@ -227,7 +248,7 @@ sysctl_epp_select(SYSCTL_HANDLER_ARGS)
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dev = oidp->oid_arg1;
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sc = device_get_softc(dev);
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if (!sc->hwp_pref_ctrl)
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if (!sc->hwp_pref_ctrl && !sc->hwp_perf_bias)
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return (ENODEV);
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pc = cpu_get_pcpu(dev);
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@ -238,11 +259,24 @@ sysctl_epp_select(SYSCTL_HANDLER_ARGS)
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sched_bind(curthread, pc->pc_cpuid);
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thread_unlock(curthread);
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ret = rdmsr_safe(MSR_IA32_HWP_REQUEST, &requested);
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if (ret)
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goto out;
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val = (requested & IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE) >> 24;
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val = raw_to_percent(val);
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if (sc->hwp_pref_ctrl) {
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ret = rdmsr_safe(MSR_IA32_HWP_REQUEST, &requested);
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if (ret)
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goto out;
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val = (requested & IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE) >> 24;
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val = raw_to_percent(val);
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} else {
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/*
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* If cpuid indicates EPP is not supported, the HWP controller
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* uses MSR_IA32_ENERGY_PERF_BIAS instead (Intel SDM §14.4.4).
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* This register is per-core (but not HT).
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*/
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ret = rdmsr_safe(MSR_IA32_ENERGY_PERF_BIAS, &requested);
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if (ret)
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goto out;
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val = requested & IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK;
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val = raw_to_percent_perf_bias(val);
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}
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MPASS(val >= 0 && val <= 100);
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@ -255,12 +289,18 @@ sysctl_epp_select(SYSCTL_HANDLER_ARGS)
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goto out;
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}
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val = percent_to_raw(val);
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if (sc->hwp_pref_ctrl) {
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val = percent_to_raw(val);
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requested &= ~IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE;
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requested |= val << 24;
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requested &= ~IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE;
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requested |= val << 24;
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ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, requested);
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ret = wrmsr_safe(MSR_IA32_HWP_REQUEST, requested);
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} else {
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requested = percent_to_raw_perf_bias(val);
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MPASS((requested & ~IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK) == 0);
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ret = wrmsr_safe(MSR_IA32_ENERGY_PERF_BIAS, requested);
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}
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out:
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thread_lock(curthread);
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@ -405,6 +445,7 @@ intel_hwpstate_attach(device_t dev)
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sc = device_get_softc(dev);
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sc->dev = dev;
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/* eax */
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if (cpu_power_eax & CPUTPM1_HWP_NOTIFICATION)
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sc->hwp_notifications = true;
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if (cpu_power_eax & CPUTPM1_HWP_ACTIVITY_WINDOW)
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@ -414,6 +455,10 @@ intel_hwpstate_attach(device_t dev)
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if (cpu_power_eax & CPUTPM1_HWP_PKG)
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sc->hwp_pkg_ctrl = true;
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/* ecx */
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if (cpu_power_ecx & CPUID_PERF_BIAS)
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sc->hwp_perf_bias = true;
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ret = set_autonomous_hwp(sc);
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if (ret)
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return (ret);
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@ -812,6 +812,9 @@
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#define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8)
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#define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0)
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/* MSR IA32_ENERGY_PERF_BIAS */
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#define IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK (0xfULL << 0)
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/*
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* PAT modes.
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*/
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