Merge FreeBSD modifications into gcc 3.2.1-prerelease:
1.11 -mno-align-long-strings Approved by: obrien
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parent
8aa7a77c78
commit
559be21b12
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=104767
@ -296,25 +296,25 @@ struct processor_costs athlon_cost = {
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8, /* "large" insn */
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9, /* MOVE_RATIO */
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4, /* cost for loading QImode using movzbl */
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{4, 5, 4}, /* cost of loading integer registers
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{3, 4, 3}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{2, 3, 2}, /* cost of storing integer registers */
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{3, 4, 3}, /* cost of storing integer registers */
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4, /* cost of reg,reg fld/fst */
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{6, 6, 20}, /* cost of loading fp registers
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{4, 4, 12}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{4, 4, 16}, /* cost of loading integer registers */
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{6, 6, 8}, /* cost of loading integer registers */
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2, /* cost of moving MMX register */
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{2, 2}, /* cost of loading MMX registers
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{4, 4}, /* cost of loading MMX registers
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in SImode and DImode */
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{2, 2}, /* cost of storing MMX registers
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{4, 4}, /* cost of storing MMX registers
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in SImode and DImode */
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2, /* cost of moving SSE register */
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{2, 2, 8}, /* cost of loading SSE registers
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{4, 4, 6}, /* cost of loading SSE registers
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in SImode, DImode and TImode */
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{2, 2, 8}, /* cost of storing SSE registers
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{4, 4, 5}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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6, /* MMX or SSE register to integer */
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5, /* MMX or SSE register to integer */
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64, /* size of prefetch block */
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6, /* number of parallel prefetches */
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};
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@ -1661,7 +1661,11 @@ classify_argument (mode, type, classes, bit_offset)
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{
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int bytes =
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(mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
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int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
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int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
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/* Variable sized structures are always passed on the stack. */
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if (mode == BLKmode && type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
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return 0;
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if (type && AGGREGATE_TYPE_P (type))
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{
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@ -3218,7 +3222,7 @@ q_regs_operand (op, mode)
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return 0;
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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return QI_REG_P (op);
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return ANY_QI_REG_P (op);
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}
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/* Return true if op is a NON_Q_REGS class register. */
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@ -6135,7 +6139,10 @@ print_operand_address (file, addr)
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int scale;
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if (! ix86_decompose_address (addr, &parts))
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abort ();
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{
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output_operand_lossage ("Wrong address expression or operand constraint");
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return;
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}
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base = parts.base;
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index = parts.index;
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@ -8249,7 +8256,7 @@ ix86_expand_int_movcc (operands)
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clob = gen_rtx_CLOBBER (VOIDmode, clob);
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tmp = gen_rtx_SET (VOIDmode, out, tmp);
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tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
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tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, copy_rtx (tmp), clob));
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emit_insn (tmp);
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}
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else
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@ -12367,17 +12374,33 @@ ix86_register_move_cost (mode, class1, class2)
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enum reg_class class1, class2;
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{
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/* In case we require secondary memory, compute cost of the store followed
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by load. In case of copying from general_purpose_register we may emit
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multiple stores followed by single load causing memory size mismatch
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stall. Count this as arbitarily high cost of 20. */
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by load. In order to avoid bad register allocation choices, we need
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for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
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if (ix86_secondary_memory_needed (class1, class2, mode, 0))
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{
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int add_cost = 0;
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int cost = 1;
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cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
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MEMORY_MOVE_COST (mode, class1, 1));
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cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
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MEMORY_MOVE_COST (mode, class2, 1));
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/* In case of copying from general_purpose_register we may emit multiple
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stores followed by single load causing memory size mismatch stall.
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Count this as arbitarily high cost of 20. */
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if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
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add_cost = 20;
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return (MEMORY_MOVE_COST (mode, class1, 0)
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+ MEMORY_MOVE_COST (mode, class2, 1) + add_cost);
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cost += 20;
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/* In the case of FP/MMX moves, the registers actually overlap, and we
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have to switch modes in order to treat them differently. */
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if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
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|| (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
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cost += 20;
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return cost;
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}
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/* Moves between SSE/MMX and integer unit are expensive. */
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if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
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|| SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
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