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n64 support - enable UX bit in STATUS for kernel and userspace.

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- enable UX in kernel start, and kernel entry
- keep UX flag in cpu_fork and cpu_set_upcall
- enable UX for userspace
This commit is contained in:
Jayachandran C. 2010-07-30 12:45:00 +00:00
parent 32ba16b6e6
commit 55bf3928c0
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=210644
4 changed files with 18 additions and 11 deletions
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6
sys/mips/mips/exception.S
View File

@ -238,7 +238,7 @@ SlowFault:
#elif defined(TARGET_XLR_XLS)
#define CLEAR_STATUS \
mfc0 a0, MIPS_COP_0_STATUS ;\
li a2, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) ; \
li a2, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) ; \
or a0, a0, a2 ; \
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \
and a0, a0, a2 ; \
@ -484,7 +484,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
#if defined(CPU_CNMIPS)
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
#elif defined(TARGET_XLR_XLS)
or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT)
or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT)
#endif
mtc0 t0, MIPS_COP_0_STATUS
PTR_ADDU a0, k1, U_PCB_REGS
@ -708,7 +708,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
#ifdef CPU_CNMIPS
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
#elif defined(TARGET_XLR_XLS)
or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT)
or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT)
#endif
mtc0 t0, MIPS_COP_0_STATUS
ITLBNOPFIX

2
sys/mips/mips/locore.S
View File

@ -101,7 +101,7 @@ VECTOR(_locore, unknown)
li t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE)
#elif defined (TARGET_XLR_XLS)
/* Set these bits */
li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX)
li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX | MIPS_SR_UX)
/* Reset these bits */
li t0, ~(MIPS_SR_BEV | MIPS_SR_SOFT_RESET | MIPS_SR_INT_IE)

4
sys/mips/mips/pm_machdep.c
View File

@ -514,8 +514,10 @@ exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
td->td_frame->t9 = imgp->entry_addr & ~3; /* abicall req */
td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
(mips_rd_status() & MIPS_SR_INT_MASK);
#if defined(__mips_n32) || defined(__mips_n64)
#if defined(__mips_n32)
td->td_frame->sr |= MIPS_SR_PX;
#elif defined(__mips_n64)
td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX;
#endif
#ifdef CPU_CNMIPS
td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS_SR_PX | MIPS_SR_UX |

17
sys/mips/mips/vm_machdep.c
View File

@ -148,8 +148,8 @@ cpu_fork(register struct thread *td1,register struct proc *p2,
pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return;
pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td2;
pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td2->td_frame;
pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | MIPS_SR_INT_MASK) &
mips_rd_status();
pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() &
(MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK);
/*
* FREEBSD_DEVELOPERS_FIXME:
* Setup any other CPU-Specific registers (Not MIPS Standard)
@ -351,8 +351,8 @@ cpu_set_upcall(struct thread *td, struct thread *td0)
pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td;
pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame;
/* Dont set IE bit in SR. sched lock release will take care of it */
pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | MIPS_SR_INT_MASK) &
mips_rd_status();
pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() &
(MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK);
#ifdef CPU_CNMIPS
pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT |
@ -414,8 +414,13 @@ cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
/*
* Keep interrupt mask
*/
tf->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | (MIPS_SR_INT_MASK & mips_rd_status()) |
MIPS_SR_INT_IE;
td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
(mips_rd_status() & MIPS_SR_INT_MASK);
#if defined(__mips_n32)
td->td_frame->sr |= MIPS_SR_PX;
#elif defined(__mips_n64)
td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX;
#endif
#ifdef CPU_CNMIPS
tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX |
MIPS_SR_KX;