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map the optional GPS and RS485 uart's on the Gateworks Cambria board

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(may want to make these conditional)
This commit is contained in:
Sam Leffler 2009-06-22 20:41:02 +00:00
parent a8c053089c
commit 55ca456dcd
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=194654
2 changed files with 32 additions and 21 deletions
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21
sys/arm/xscale/ixp425/avila_machdep.c
View File

@ -183,14 +183,9 @@ static const struct pmap_devmap ixp435_devmap[] = {
{ IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* Expansion Bus */
{ IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* CFI Flash on the Expansion Bus */
{ IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* IXP425 PCI Configuration */
{ IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
@ -207,6 +202,10 @@ static const struct pmap_devmap ixp435_devmap[] = {
{ IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* CFI Flash on the Expansion Bus */
{ IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* USB1 Memory Space */
{ IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
@ -214,6 +213,14 @@ static const struct pmap_devmap ixp435_devmap[] = {
{ IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* GPS Memory Space */
{ CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* RS485 Memory Space */
{ CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
{ 0 }
};
@ -456,8 +463,8 @@ initarm(void *arg, void *arg2)
phys_avail[i++] = PHYSADDR;
phys_avail[i++] = PHYSADDR + PAGE_SIZE; /*
*XXX: Gross hack to get our
* pages in the vm_page_array
. */
* pages in the vm_page_array.
*/
#endif
phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR);
phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1);

32
sys/arm/xscale/ixp425/ixp425reg.h
View File

@ -88,10 +88,10 @@
* SDRAM/DDR Memory Controller
* F020 0000 --------------------------- IXP425_MCU_VBASE
*
* EHCI USB 2 (IXP435)
* F001 D000 --------------------------- IXP435_USB2_VBASE
* EHCI USB 1 (IXP435)
* F001 C000 --------------------------- IXP435_USB1_VBASE
* F001 F000 RS485 (Cambria) CAMBRIA_RS485_VBASE
* F001 E000 GPS (Cambria) CAMBRIA_GPS_VBASE
* F001 D000 EHCI USB 2 (IXP435) IXP435_USB2_VBASE
* F001 C000 EHCI USB 1 (IXP435) IXP435_USB1_VBASE
* Queue manager
* F001 8000 --------------------------- IXP425_QMGR_VBASE
* PCI Configuration and Status
@ -686,10 +686,22 @@
/*
* IXP435/Gateworks Cambria
*/
#define IXP435_USB1_HWBASE 0xCD000000UL /* USB host controller 1 */
#define IXP435_USB1_VBASE 0xF001C000UL
#define IXP435_USB1_SIZE 0x1000 /* NB: only uses 0x300 */
#define IXP435_USB2_HWBASE 0xCE000000UL /* USB host controller 2 */
#define IXP435_USB2_VBASE 0xF001D000UL
#define IXP435_USB2_SIZE 0x1000 /* NB: only uses 0x300 */
#define CAMBRIA_GPS_HWBASE 0x53FC0000UL /* optional GPS Serial Port */
#define CAMBRIA_GPS_SIZE 0x40000
#define CAMBRIA_GPS_VBASE 0xF001E000UL
#define CAMBRIA_GPS_SIZE 0x1000
#define CAMBRIA_RS485_HWBASE 0x53F80000UL /* optional RS485 Serial Port */
#define CAMBRIA_RS485_SIZE 0x40000
#define CAMBRIA_RS485_VBASE 0xF001F000UL
#define CAMBRIA_RS485_SIZE 0x1000
/* NB: these are mapped on the fly, so no fixed virtual addresses */
#define CAMBRIA_OCTAL_LED_HWBASE 0x53F40000UL /* Octal Status LED Latch */
#define CAMBRIA_OCTAL_LED_SIZE 0x1000
#define CAMBRIA_CFSEL1_HWBASE 0x53E40000UL /* Compact Flash Socket Sel 0 */
@ -697,12 +709,4 @@
#define CAMBRIA_CFSEL0_HWBASE 0x53E00000UL /* Compact Flash Socket Sel 1 */
#define CAMBRIA_CFSEL0_SIZE 0x40000
#define IXP435_USB1_HWBASE 0xcd000000UL /* USB host controller 1 */
#define IXP435_USB1_VBASE 0xf001C000UL
#define IXP435_USB1_SIZE 0x1000 /* NB: only uses 0x300 */
#define IXP435_USB2_HWBASE 0xce000000UL /* USB host controller 2 */
#define IXP435_USB2_VBASE 0xf001D000UL
#define IXP435_USB2_SIZE 0x1000 /* NB: only uses 0x300 */
#endif /* _IXP425REG_H_ */