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Add/improve mips64r2, Octeon, n32 and n64 support in the toolchain.

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o) Add TARGET_ABI to the MIPS toolchain build process.  This sets the default
   ABI to one of o32, n32 or n64.  If it is not set, o32 is assumed as that is
   the current default.
o) Set the default GCC cpu type to any specified TARGET_CPUTYPE.  This is
   necessary to have a working "cc" if e.g. mips64 is specified, as binutils
   will refuse to link objects using different ISAs in some cases.
o) Add support for n32 and n64 ABIs to binutils and GCC.
o) Add additional required libgcc2 stubs for n32 and n64.
o) Add support for the "mips64r2" architecture to GCC.  Add the "octeon"
o) When static linking, wrap default libraries in --start-group and
   --end-group.  This is required for static linking to work on n64 with the
   interdependencies between libraries there.  This is what other OSes that
   support n64 seem to do, as well.
o) Fix our GCC spec to define __mips64 for 64-bit targets, not __mips64__, the
   former being what libgcc, etc., check and the latter seemingly being a
   misspelling of a hand merge from a Linux spec.
o) When no TARGET_CPUTYPE is specified at build time, make GCC take the default
   ISA from the ABI.  Our old defaults were too liberal and assumed that 64-bit
   ABIs should default to the MIPS64 ISA and that 32-bit ABIs should default to
   the MIPS32 ISA, when we are supporting or will support some systems based on
   earlier 32-bit and 64-bit ISAs, most notably MIPS-III.
o) Merge a new opcode file (and support code) from a later version of binutils
   and add flags and code necessary to support Octeon-specific instructions.
   This should also make merging opcodes for other modern architectures easier.

Reviewed by:	imp
This commit is contained in:
Juli Mallett 2010-06-02 11:06:03 +00:00
parent e3303e900e
commit 5619a3e4bf
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=208737
30 changed files with 5407 additions and 4053 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
contrib/binutils/bfd/archures.c
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@ -1,6 +1,6 @@
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003
2000, 2001, 2002, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
@ -18,7 +18,7 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -141,10 +141,12 @@ DESCRIPTION
.#define bfd_mach_mips6000 6000
.#define bfd_mach_mips7000 7000
.#define bfd_mach_mips8000 8000
.#define bfd_mach_mips9000 9000
.#define bfd_mach_mips10000 10000
.#define bfd_mach_mips12000 12000
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_octeon 6502
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33

5
contrib/binutils/bfd/bfd-in2.h
View File

@ -8,7 +8,8 @@
/* Main header file for the bfd library -- portable access to object files.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
Contributed by Cygnus Support.
@ -26,7 +27,7 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef __BFD_H_SEEN__
#define __BFD_H_SEEN__

8
contrib/binutils/bfd/cpu-mips.c
View File

@ -1,6 +1,6 @@
/* bfd back-end for mips support
Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001,
2002, 2003 Free Software Foundation, Inc.
2002, 2003, 2004 Free Software Foundation, Inc.
Written by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
@ -17,7 +17,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -76,6 +76,7 @@ enum
I_mips6000,
I_mips7000,
I_mips8000,
I_mips9000,
I_mips10000,
I_mips12000,
I_mips16,
@ -84,6 +85,7 @@ enum
I_mipsisa32r2,
I_mipsisa64,
I_mipsisa64r2,
I_mipsocteon,
I_sb1,
};
@ -108,6 +110,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (32, 32, bfd_mach_mips6000, "mips:6000", FALSE, NN(I_mips6000)),
N (64, 64, bfd_mach_mips7000, "mips:7000", FALSE, NN(I_mips7000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", FALSE, NN(I_mips8000)),
N (64, 64, bfd_mach_mips9000, "mips:9000", FALSE, NN(I_mips9000)),
N (64, 64, bfd_mach_mips10000,"mips:10000", FALSE, NN(I_mips10000)),
N (64, 64, bfd_mach_mips12000,"mips:12000", FALSE, NN(I_mips12000)),
N (64, 64, bfd_mach_mips16, "mips:16", FALSE, NN(I_mips16)),
@ -116,6 +119,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
};

45
contrib/binutils/bfd/elfxx-mips.c
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@ -1,6 +1,6 @@
/* MIPS-specific support for ELF
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003 Free Software Foundation, Inc.
2003, 2004, 2005, 2006 Free Software Foundation, Inc.
Most of the information added by Ian Lance Taylor, Cygnus Support,
<ian@cygnus.com>.
@ -23,7 +23,7 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* This file handles functionality common to the different MIPS ABI's. */
@ -4088,6 +4088,12 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_5500:
return bfd_mach_mips5500;
case E_MIPS_MACH_9000:
return bfd_mach_mips9000;
case E_MIPS_MACH_OCTEON:
return bfd_mach_mips_octeon;
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
@ -7142,6 +7148,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_4 | E_MIPS_MACH_5500;
break;
case bfd_mach_mips9000:
val = E_MIPS_ARCH_4 | E_MIPS_MACH_9000;
break;
case bfd_mach_mips5000:
case bfd_mach_mips7000:
case bfd_mach_mips8000:
@ -7154,6 +7164,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_5;
break;
case bfd_mach_mips_octeon:
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
break;
case bfd_mach_mips_sb1:
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
@ -8856,6 +8870,9 @@ struct mips_mach_extension {
are ordered topologically with MIPS I extensions listed last. */
static const struct mips_mach_extension mips_mach_extensions[] = {
/* MIPS64r2 extensions. */
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
@ -8879,6 +8896,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = {
{ bfd_mach_mips10000, bfd_mach_mips8000 },
{ bfd_mach_mips5000, bfd_mach_mips8000 },
{ bfd_mach_mips7000, bfd_mach_mips8000 },
{ bfd_mach_mips9000, bfd_mach_mips8000 },
/* VR4100 extensions. */
{ bfd_mach_mips4120, bfd_mach_mips4100 },
@ -8913,11 +8931,26 @@ mips_mach_extends_p (unsigned long base, unsigned long extension)
{
size_t i;
for (i = 0; extension != base && i < ARRAY_SIZE (mips_mach_extensions); i++)
if (extension == mips_mach_extensions[i].extension)
extension = mips_mach_extensions[i].base;
if (extension == base)
return TRUE;
return extension == base;
if (base == bfd_mach_mipsisa32
&& mips_mach_extends_p (bfd_mach_mipsisa64, extension))
return TRUE;
if (base == bfd_mach_mipsisa32r2
&& mips_mach_extends_p (bfd_mach_mipsisa64r2, extension))
return TRUE;
for (i = 0; i < ARRAY_SIZE (mips_mach_extensions); i++)
if (extension == mips_mach_extensions[i].extension)
{
extension = mips_mach_extensions[i].base;
if (extension == base)
return TRUE;
}
return FALSE;
}

5135
contrib/binutils/gas/config/tc-mips.c
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File diff suppressed because it is too large Load Diff

22
contrib/binutils/gas/config/tc-mips.h
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@ -89,15 +89,6 @@ enum mips_pic_level
extern enum mips_pic_level mips_pic;
struct mips_cl_insn
{
unsigned long insn_opcode;
const struct mips_opcode *insn_mo;
/* The next two fields are used when generating mips16 code. */
bfd_boolean use_extend;
unsigned short extend;
};
extern int tc_get_register (int frame);
#define md_after_parse_args() mips_after_parse_args()
@ -143,15 +134,6 @@ extern int mips_force_relocation (struct fix *);
#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) \
(! SEG_NORMAL (SEG) || mips_force_relocation (FIX))
/* We use this to turn branches to global symbols into branches to
local symbols, so that they can be simplified. */
#define TC_VALIDATE_FIX(fixp, this_segment, skip_label) \
do \
if (! mips_validate_fix ((fixp), (this_segment))) \
goto skip_label; \
while (0)
extern int mips_validate_fix (struct fix *, asection *);
/* Register mask variables. These are set by the MIPS assembly code
and used by ECOFF and possibly other object file formats. */
extern unsigned long mips_gprmask;
@ -174,8 +156,8 @@ extern void md_mips_end (void);
extern void mips_pop_insert (void);
#define md_pop_insert() mips_pop_insert()
extern void mips_flush_pending_output (void);
#define md_flush_pending_output mips_flush_pending_output
extern void mips_emit_delays (void);
#define md_flush_pending_output mips_emit_delays
extern void mips_enable_auto_align (void);
#define md_elf_section_change_hook() mips_enable_auto_align()

7
contrib/binutils/include/elf/mips.h
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@ -1,5 +1,6 @@
/* MIPS ELF support for BFD.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003, 2004, 2005
Free Software Foundation, Inc.
By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from
@ -20,7 +21,7 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* This file holds definitions specific to the MIPS ELF ABI. Note
that most of this is not actually implemented by BFD. */
@ -187,8 +188,10 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_4120 0x00870000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
#define E_MIPS_MACH_OCTEON 0x008b0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these

111
contrib/binutils/include/opcode/mips.h
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@ -1,5 +1,6 @@
/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
@ -18,7 +19,7 @@ the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _MIPS_H_
#define _MIPS_H_
@ -89,6 +90,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
#define OP_MASK_BITIND OP_MASK_RT
#define OP_SH_BITIND OP_SH_RT
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
@ -147,6 +150,38 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
#define OP_SH_EXTMSBD 11
/* MIPS DSP ASE */
#define OP_SH_DSPACC 11
#define OP_MASK_DSPACC 0x3
#define OP_SH_DSPACC_S 21
#define OP_MASK_DSPACC_S 0x3
#define OP_SH_DSPSFT 20
#define OP_MASK_DSPSFT 0x3f
#define OP_SH_DSPSFT_7 19
#define OP_MASK_DSPSFT_7 0x7f
#define OP_SH_SA3 21
#define OP_MASK_SA3 0x7
#define OP_SH_SA4 21
#define OP_MASK_SA4 0xf
#define OP_SH_IMM8 16
#define OP_MASK_IMM8 0xff
#define OP_SH_IMM10 16
#define OP_MASK_IMM10 0x3ff
#define OP_SH_WRDSP 11
#define OP_MASK_WRDSP 0x3f
#define OP_SH_RDDSP 16
#define OP_MASK_RDDSP 0x3f
/* MIPS MT ASE */
#define OP_SH_MT_U 5
#define OP_MASK_MT_U 0x1
#define OP_SH_MT_H 4
#define OP_MASK_MT_H 0x1
#define OP_SH_MTACC_T 18
#define OP_MASK_MTACC_T 0x3
#define OP_SH_MTACC_D 13
#define OP_MASK_MTACC_D 0x3
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
@ -192,6 +227,8 @@ struct mips_opcode
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
/* A collection of additional bits describing the instruction. */
unsigned long pinfo2;
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
@ -207,6 +244,8 @@ struct mips_opcode
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"^" 5 bit bit index amount (OP_*_BITIND)
"~" bit index between 32 and 63, stored after subtracting 32 (OP_*_BITIND)
"a" 26 bit target address (OP_*_TARGET)
"b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE)
@ -231,6 +270,7 @@ struct mips_opcode
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
"J" 19 bit wait function code (OP_*_CODE19)
"x" accept and ignore register name
"y" 10 bit signed const (OP_*_CODE2)
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
@ -293,6 +333,28 @@ struct mips_opcode
"Y" MDMX source register (OP_*_FS)
"Z" MDMX source register (OP_*_FT)
DSP ASE usage:
"3" 3 bit unsigned immediate (OP_*_SA3)
"4" 4 bit unsigned immediate (OP_*_SA4)
"5" 8 bit unsigned immediate (OP_*_IMM8)
"6" 5 bit unsigned immediate (OP_*_RS)
"7" 2 bit dsp accumulator register (OP_*_DSPACC)
"8" 6 bit unsigned immediate (OP_*_WRDSP)
"9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
"0" 6 bit signed immediate (OP_*_DSPSFT)
":" 7 bit signed immediate (OP_*_DSPSFT_7)
"'" 6 bit unsigned immediate (OP_*_RDDSP)
"@" 10 bit signed immediate (OP_*_IMM10)
MT ASE usage:
"!" 1 bit immediate at bit 5
"$" 1 bit immediate at bit 4
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
Other:
"()" parens surrounding optional value
"," separates operands
@ -300,13 +362,15 @@ struct mips_opcode
"+" Start of extension sequence.
Characters used so far, for quick reference when adding more:
"%[]<>(),+"
"34567890"
"%[]<>(),+:'@!$*&^~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefhijklopqrstuvwxz"
"abcdefghijklopqrstuvwxyz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"ABCDEFGHI"
"ABCDEFGHIT"
"t"
*/
/* These are the bits which may be set in the pinfo field of an
@ -376,10 +440,16 @@ struct mips_opcode
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
#define INSN_READ_MDMX_ACC 0
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
#define INSN_WRITE_MDMX_ACC 0
/* These are the bits which may be set in the pinfo2 field of an
instruction. */
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
#define INSN2_ALIAS 0x00000001
/* Instruction reads MDMX accumulator. */
#define INSN2_READ_MDMX_ACC 0x00000002
/* Instruction writes MDMX accumulator. */
#define INSN2_WRITE_MDMX_ACC 0x00000004
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
@ -402,8 +472,10 @@ struct mips_opcode
#define INSN_ISA64R2 0x00000100
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x0000f000
#define INSN_ASE_MASK 0x0400f000
/* DSP ASE */
#define INSN_DSP 0x00001000
/* MIPS 16 ASE */
#define INSN_MIPS16 0x00002000
/* MIPS-3D ASE */
@ -433,6 +505,10 @@ struct mips_opcode
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
/* MT ASE */
#define INSN_MT 0x04000000
/* Cavium Networks Octeon instruction. */
#define INSN_OCTEON 0x08000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@ -470,6 +546,7 @@ struct mips_opcode
#define CPU_R6000 6000
#define CPU_RM7000 7000
#define CPU_R8000 8000
#define CPU_RM9000 9000
#define CPU_R10000 10000
#define CPU_R12000 12000
#define CPU_MIPS16 16
@ -479,6 +556,7 @@ struct mips_opcode
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_OCTEON 6502
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@ -489,12 +567,14 @@ struct mips_opcode
(((insn)->membership & isa) != 0 \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
&& ((insn)->membership & INSN_10000) != 0) \
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|| (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
@ -654,6 +734,8 @@ enum
M_S_DOB,
M_S_DAB,
M_S_S,
M_SAA_AB,
M_SAAD_AB,
M_SC_AB,
M_SCD_AB,
M_SD_A,
@ -857,7 +939,14 @@ extern int bfd_mips_num_opcodes;
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
*/
"m" 7 bit register list for save instruction (18 bit extended)
"M" 7 bit register list for restore instruction (18 bit extended)
*/
/* Save/restore encoding for the args field when all 4 registers are
either saved as arguments or saved/restored as statics. */
#define MIPS16_ALL_ARGS 0xe
#define MIPS16_ALL_STATICS 0xb
/* For the mips16, we use the same opcode table format and a few of
the same flags. However, most of the flags are different. */

1095
contrib/binutils/opcodes/mips-dis.c
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File diff suppressed because it is too large Load Diff

2327
contrib/binutils/opcodes/mips-opc.c
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File diff suppressed because it is too large Load Diff

333
contrib/binutils/opcodes/mips16-opc.c
View File

@ -1,5 +1,5 @@
/* mips16-opc.c. Mips16 opcode table.
Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc.
Contributed by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
@ -16,8 +16,8 @@ the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
@ -64,163 +64,176 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
const struct mips_opcode mips16_opcodes[] =
{
{"nop", "", 0x6500, 0xffff, RD_Z, 0 }, /* move $0,$Z */
{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0 },
{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0 },
{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 },
{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 },
{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 },
{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 },
{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0 },
{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 },
{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 },
{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 },
{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 },
{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0 },
{"b", "q", 0x1000, 0xf800, BR, 0 },
{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0 },
{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0 },
{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0 },
{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0 },
{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0 },
{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0 },
{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0 },
{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0 },
{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0 },
{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0 },
{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0 },
{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0 },
{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0 },
{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0 },
{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0 },
{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0 },
{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0 },
{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0 },
{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0 },
{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0 },
{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0 },
{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0 },
{"break", "6", 0xe805, 0xf81f, TRAP, 0 },
{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0 },
{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0 },
{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 },
{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0 },
{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 },
{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, I3 },
{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 },
{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 },
{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 },
{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 },
{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, I3 },
{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 },
{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 },
{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 },
{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 },
{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0 },
{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0 },
{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0 },
{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0 },
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, I3 },
{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0 },
{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0 },
{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 },
{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, I3 },
{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 },
{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 },
{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, I3 },
{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 },
{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 },
{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, I3 },
{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 },
{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, I3 },
{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0 },
{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0 },
{"exit", "L", 0xed09, 0xff1f, TRAP, 0 },
{"exit", "L", 0xee09, 0xff1f, TRAP, 0 },
{"exit", "L", 0xef09, 0xff1f, TRAP, 0 },
{"entry", "l", 0xe809, 0xf81f, TRAP, 0 },
{"extend", "e", 0xf000, 0xf800, 0, 0 },
{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0 },
{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0 },
{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 },
{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0 },
{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 },
{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0 },
{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0 },
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0 },
{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 },
{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, I3 },
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, I3 },
{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, I3 },
{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0 },
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0 },
{"li", "x,U", 0x6800, 0xf800, WR_x, 0 },
{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0 },
{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0 },
{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0 },
{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0 },
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, I3 },
{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0 },
{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0 },
{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0 },
{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0 },
{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0 },
{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0 },
{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0 },
{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0 },
{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0 },
{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0 },
{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0 },
{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, I3 },
{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, I3 },
{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0 },
{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0 },
{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 },
{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0 },
{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 },
{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 },
{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0 },
{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 },
{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 },
{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0 },
{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 },
{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 },
{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0 },
{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 },
{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 },
{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0 },
{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 },
{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0 },
{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0 },
{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0 },
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0 },
{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0 },
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0 },
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0 },
{"nop", "", 0x6500, 0xffff, RD_Z, 0, 0 }, /* move $0,$Z */
{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 },
{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, 0 },
{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, 0 },
{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, 0 },
{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 },
{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, 0 },
{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, 0 },
{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, 0 },
{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, 0 },
{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 },
{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, 0 },
{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, 0 },
{"b", "q", 0x1000, 0xf800, BR, 0, 0 },
{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, 0 },
{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, 0 },
{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0, 0 },
{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, 0 },
{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, 0 },
{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, 0 },
{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, 0 },
{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, 0 },
{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0, 0 },
{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, 0 },
{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, 0 },
{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, 0 },
{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0, 0 },
{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, 0 },
{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, 0 },
{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, 0 },
{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0, 0 },
{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, 0 },
{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, 0 },
{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, 0 },
{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, 0 },
{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0, 0 },
{"break", "6", 0xe805, 0xf81f, TRAP, 0, 0 },
{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0, 0 },
{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0, 0 },
{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, 0 },
{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, 0 },
{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, 0 },
{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, 0 },
{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, 0 },
{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, 0 },
{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, 0 },
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, 0 },
{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, 0 },
{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3 },
{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3 },
{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3 },
{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0, 0 },
{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, 0 },
{"exit", "L", 0xed09, 0xff1f, TRAP, 0, 0 },
{"exit", "L", 0xee09, 0xff1f, TRAP, 0, 0 },
{"exit", "L", 0xef09, 0xff1f, TRAP, 0, 0 },
{"entry", "l", 0xe809, 0xf81f, TRAP, 0, 0 },
{"extend", "e", 0xf000, 0xf800, 0, 0, 0 },
{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, 0 },
{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, 0 },
{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, 0 },
{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, 0 },
{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, 0 },
{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, 0 },
{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, 0 },
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, 0 },
{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3 },
{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, 0 },
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, 0 },
{"li", "x,U", 0x6800, 0xf800, WR_x, 0, 0 },
{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, 0 },
{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, 0 },
{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, 0 },
{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, 0 },
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3 },
{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, 0 },
{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, 0 },
{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, 0 },
{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, 0 },
{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, 0 },
{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, 0 },
{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, 0 },
{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, 0 },
{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, 0 },
{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, 0 },
{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, 0 },
{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3 },
{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3 },
{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, 0 },
{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, 0 },
{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, 0 },
{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, 0 },
{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, 0 },
{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, 0 },
{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, 0 },
{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, 0 },
{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, 0 },
{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, 0 },
{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, 0 },
{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, 0 },
{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0, 0 },
{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0, 0 },
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, 0 },
{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, 0 },
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, 0 },
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, 0 },
/* MIPS16e additions */
{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, 0 },
{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, 0 },
{"jrc", "x", 0xe880, 0xf8ff, RD_x|TRAP, 0, 0 },
{"jrc", "R", 0xe8a0, 0xffff, RD_31|TRAP, 0, 0 },
{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, 0 },
{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, 0 },
{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, 0 },
{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, 0 },
{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I3 },
{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, 0 },
{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, 0 },
{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I3 },
};
const int bfd_mips16_num_opcodes =

28
contrib/gcc/config/fixdfdi.c Normal file
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@ -0,0 +1,28 @@
/* Public domain. */
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef unsigned int UDItype __attribute__ ((mode (DI)));
typedef float DFtype __attribute__ ((mode (DF)));
DItype __fixdfdi (DFtype);
/* This version is needed to prevent recursion; fixunsdfdi in libgcc
calls fixdfdi, which in turn calls calls fixunsdfdi. */
static DItype
local_fixunsdfdi (DFtype a)
{
USItype hi, lo;
hi = a / (((UDItype) 1) << (sizeof (USItype) * 8));
lo = a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (USItype) * 8));
return ((UDItype) hi << (sizeof (USItype) * 8)) | lo;
}
DItype
__fixdfdi (DFtype a)
{
if (a < 0)
return - local_fixunsdfdi (-a);
return local_fixunsdfdi (a);
}

30
contrib/gcc/config/fixsfdi.c Normal file
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@ -0,0 +1,30 @@
/* Public domain. */
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef unsigned int UDItype __attribute__ ((mode (DI)));
typedef float SFtype __attribute__ ((mode (SF)));
typedef float DFtype __attribute__ ((mode (DF)));
DItype __fixsfdi (SFtype);
/* This version is needed to prevent recursion; fixunssfdi in libgcc
calls fixsfdi, which in turn calls calls fixunssfdi. */
static DItype
local_fixunssfdi (SFtype original_a)
{
DFtype a = original_a;
USItype hi, lo;
hi = a / (((UDItype) 1) << (sizeof (USItype) * 8));
lo = a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (USItype) * 8));
return ((UDItype) hi << (sizeof (USItype) * 8)) | lo;
}
DItype
__fixsfdi (SFtype a)
{
if (a < 0)
return - local_fixunssfdi (-a);
return local_fixunssfdi (a);
}

18
contrib/gcc/config/fixunsdfsi.c Normal file
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@ -0,0 +1,18 @@
/* Public domain. */
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int SItype __attribute__ ((mode (SI)));
typedef float SFtype __attribute__ ((mode (SF)));
typedef float DFtype __attribute__ ((mode (DF)));
USItype __fixunsdfsi (DFtype);
#define SItype_MIN \
(- ((SItype) (((USItype) 1 << ((sizeof (SItype) * 8) - 1)) - 1)) - 1)
USItype
__fixunsdfsi (DFtype a)
{
if (a >= - (DFtype) SItype_MIN)
return (SItype) (a + SItype_MIN) - SItype_MIN;
return (SItype) a;
}

17
contrib/gcc/config/fixunssfsi.c Normal file
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@ -0,0 +1,17 @@
/* Public domain. */
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int SItype __attribute__ ((mode (SI)));
typedef float SFtype __attribute__ ((mode (SF)));
USItype __fixunssfsi (SFtype);
#define SItype_MIN \
(- ((SItype) (((USItype) 1 << ((sizeof (SItype) * 8) - 1)) - 1)) - 1)
USItype
__fixunssfsi (SFtype a)
{
if (a >= - (SFtype) SItype_MIN)
return (SItype) (a + SItype_MIN) - SItype_MIN;
return (SItype) a;
}

17
contrib/gcc/config/floatdidf.c Normal file
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@ -0,0 +1,17 @@
/* Public domain. */
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef float DFtype __attribute__ ((mode (DF)));
DFtype __floatdidf (DItype);
DFtype
__floatdidf (DItype u)
{
/* When the word size is small, we never get any rounding error. */
DFtype f = (SItype) (u >> (sizeof (SItype) * 8));
f *= 0x1p32f;
f += (USItype) u;
return f;
}

38
contrib/gcc/config/floatdisf.c Normal file
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@ -0,0 +1,38 @@
/* Public domain. */
typedef int DItype __attribute__ ((mode (DI)));
typedef unsigned int UDItype __attribute__ ((mode (DI)));
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef float SFtype __attribute__ ((mode (SF)));
typedef float DFtype __attribute__ ((mode (DF)));
SFtype __floatdisf (DItype);
SFtype
__floatdisf (DItype u)
{
/* Protect against double-rounding error.
Represent any low-order bits, that might be truncated by a bit that
won't be lost. The bit can go in anywhere below the rounding position
of SFtype. A fixed mask and bit position handles all usual
configurations. */
if (53 < (sizeof (DItype) * 8)
&& 53 > ((sizeof (DItype) * 8) - 53 + 24))
{
if (!(- ((DItype) 1 << 53) < u
&& u < ((DItype) 1 << 53)))
{
if ((UDItype) u & (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1))
{
u &= ~ (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1);
u |= (UDItype) 1 << (sizeof (DItype) * 8 - 53);
}
}
}
/* Do the calculation in a wider type so that we don't lose any of
the precision of the high word while multiplying it. */
DFtype f = (SItype) (u >> (sizeof (SItype) * 8));
f *= 0x1p32f;
f += (USItype) u;
return (SFtype) f;
}

16
contrib/gcc/config/floatundidf.c Normal file
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@ -0,0 +1,16 @@
/* Public domain. */
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef unsigned int UDItype __attribute__ ((mode (DI)));
typedef float DFtype __attribute__ ((mode (DF)));
DFtype __floatundidf (UDItype);
DFtype
__floatundidf (UDItype u)
{
/* When the word size is small, we never get any rounding error. */
DFtype f = (USItype) (u >> (sizeof (USItype) * 8));
f *= 0x1p32f;
f += (USItype) u;
return f;
}

36
contrib/gcc/config/floatundisf.c Normal file
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@ -0,0 +1,36 @@
/* Public domain. */
typedef int DItype __attribute__ ((mode (DI)));
typedef unsigned int UDItype __attribute__ ((mode (DI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef float SFtype __attribute__ ((mode (SF)));
typedef float DFtype __attribute__ ((mode (DF)));
SFtype __floatundisf (UDItype);
SFtype
__floatundisf (UDItype u)
{
/* Protect against double-rounding error.
Represent any low-order bits, that might be truncated by a bit that
won't be lost. The bit can go in anywhere below the rounding position
of SFTYPE. A fixed mask and bit position handles all usual
configurations. */
if (53 < (sizeof (DItype) * 8)
&& 53 > ((sizeof (DItype) * 8) - 53 + 24))
{
if (u >= ((UDItype) 1 << 53))
{
if ((UDItype) u & (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1))
{
u &= ~ (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1);
u |= (UDItype) 1 << (sizeof (DItype) * 8 - 53);
}
}
}
/* Do the calculation in a wider type so that we don't lose any of
the precision of the high word while multiplying it. */
DFtype f = (USItype) (u >> (sizeof (USItype) * 8));
f *= 0x1p32f;
f += (USItype) u;
return (SFtype) f;
}

37
contrib/gcc/config/mips/freebsd.h
View File

@ -75,7 +75,10 @@ Boston, MA 02110-1301, USA. */
%{mabi=o64:-melf64%{EB:b}%{EL:l}tsmip_fbsd} \
%(fbsd_link_spec)"
#undef LINK_GCC_C_SEQUENCE_SPEC
#define LINK_GCC_C_SEQUENCE_SPEC \
"%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
/* Reset our STARTFILE_SPEC which was properly set in config/freebsd.h
but trashed by config/mips/elf.h. */
#undef STARTFILE_SPEC
@ -124,7 +127,7 @@ Boston, MA 02110-1301, USA. */
builtin_define ("__mips__"); \
\
if (TARGET_64BIT) \
builtin_define ("__mips64__"); \
builtin_define ("__mips64"); \
\
if (TARGET_FLOAT64) \
builtin_define ("__mips_fpr=64"); \
@ -228,13 +231,13 @@ Boston, MA 02110-1301, USA. */
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
builtin_define ("__mips_isa_rev=1"); \
} \
/* else if (ISA_MIPS64R2) \
else if (ISA_MIPS64R2) \
{ \
builtin_define ("__mips=64"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
builtin_define ("__mips_isa_rev=2"); \
} \
*/ \
\
if (TARGET_HARD_FLOAT) \
builtin_define ("__mips_hard_float"); \
else if (TARGET_SOFT_FLOAT) \
@ -255,27 +258,37 @@ Boston, MA 02110-1301, USA. */
while (0)
/* Default ABI and ISA */
/*
* XXX/juli
* Shouldn't this also be dependent on !mips*?
*/
#ifdef MIPS_CPU_STRING_DEFAULT
#define DRIVER_SELF_ISA_SPEC "%{!march=*: -march=" MIPS_CPU_STRING_DEFAULT "}"
#else
#define DRIVER_SELF_ISA_SPEC "%{!march=*: -march=from-abi}"
#endif
#undef DRIVER_SELF_SPECS
#if MIPS_ABI_DEFAULT == ABI_N32
#define DRIVER_SELF_SPECS \
"%{!EB:%{!EL:%(endian_spec)}}", \
"%{!march=*: -march=mips64}", \
"%{!mabi=*: -mabi=n32}"
"%{!mabi=*: -mabi=n32}", \
DRIVER_SELF_ISA_SPEC
#elif MIPS_ABI_DEFAULT == ABI_64
#define DRIVER_SELF_SPECS \
"%{!EB:%{!EL:%(endian_spec)}}", \
"%{!march=*: -march=mips64}", \
"%{!mabi=*: -mabi=64}"
"%{!mabi=*: -mabi=64}", \
DRIVER_SELF_ISA_SPEC
#elif MIPS_ABI_DEFAULT == ABI_O64
#define DRIVER_SELF_SPECS \
"%{!EB:%{!EL:%(endian_spec)}}", \
"%{!march=*: -march=mips64}", \
"%{!mabi=*: -mabi=o64}"
"%{!mabi=*: -mabi=o64}", \
DRIVER_SELF_ISA_SPEC
#else /* default to o32 */
#define DRIVER_SELF_SPECS \
"%{!EB:%{!EL:%(endian_spec)}}", \
"%{!march=*: -march=mips32}", \
"%{!mabi=*: -mabi=32}"
"%{!mabi=*: -mabi=32}", \
DRIVER_SELF_ISA_SPEC
#endif
#if 0

7
contrib/gcc/config/mips/mips.c
View File

@ -713,6 +713,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
{ "mips32", PROCESSOR_4KC, 32 },
{ "mips32r2", PROCESSOR_M4K, 33 },
{ "mips64", PROCESSOR_5KC, 64 },
{ "mips64r2", PROCESSOR_5KC, 65 },
/* MIPS I */
{ "r3000", PROCESSOR_R3000, 1 },
@ -762,6 +763,9 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
{ "sb1a", PROCESSOR_SB1A, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
/* MIPS64R2 */
{ "octeon", PROCESSOR_OCTEON, 65 },
/* End marker */
{ 0, 0, 0 }
};
@ -4829,7 +4833,7 @@ override_options (void)
issue those instructions unless instructed to do so by
-mbranch-likely. */
if (ISA_HAS_BRANCHLIKELY
&& !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
&& !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
&& !(TUNE_MIPS5500 || TUNE_SB1))
target_flags |= MASK_BRANCHLIKELY;
else
@ -9943,6 +9947,7 @@ mips_issue_rate (void)
case PROCESSOR_R5500:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
case PROCESSOR_OCTEON:
return 2;
case PROCESSOR_SB1:

47
contrib/gcc/config/mips/mips.h
View File

@ -41,6 +41,7 @@ enum processor_type {
PROCESSOR_24K,
PROCESSOR_24KX,
PROCESSOR_M4K,
PROCESSOR_OCTEON,
PROCESSOR_R3900,
PROCESSOR_R6000,
PROCESSOR_R4000,
@ -199,6 +200,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_MIPS32 (mips_isa == 32)
#define ISA_MIPS32R2 (mips_isa == 33)
#define ISA_MIPS64 (mips_isa == 64)
#define ISA_MIPS64R2 (mips_isa == 65)
/* Architecture target defines. */
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
@ -212,6 +214,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
|| mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
@ -227,6 +230,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)
#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
/* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example,
@ -379,6 +383,12 @@ extern const struct mips_rtx_cost_data *mips_cost;
builtin_define ("__mips=64"); \
builtin_define ("__mips_isa_rev=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
} \
else if (ISA_MIPS64R2) \
{ \
builtin_define ("__mips=64"); \
builtin_define ("__mips_isa_rev=2"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
} \
\
if (TARGET_HARD_FLOAT) \
@ -501,7 +511,11 @@ extern const struct mips_rtx_cost_data *mips_cost;
# if MIPS_ISA_DEFAULT == 64
# define MULTILIB_ISA_DEFAULT "mips64"
# else
# define MULTILIB_ISA_DEFAULT "mips1"
# if MIPS_ISA_DEFAULT == 65
# define MULTILIB_ISA_DEFAULT "mips64r2"
# else
# define MULTILIB_ISA_DEFAULT "mips1"
# endif
# endif
# endif
# endif
@ -562,7 +576,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
|| TARGET_MAD \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* Generate three-operand multiply instructions for DImode. */
@ -584,7 +599,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
|| ISA_MIPS64)
|| ISA_MIPS64 \
|| ISA_MIPS64R2)
/* ISA has branch likely instructions (e.g. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
@ -595,7 +611,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
@ -604,13 +621,15 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_HAS_8CC (ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64)
|| ISA_MIPS64 \
|| ISA_MIPS64R2)
/* This is a catch all for other mips4 instructions: indexed load, the
FP madd and msub instructions, and the FP recip and recip sqrt
instructions. */
#define ISA_HAS_FP4 ((ISA_MIPS4 \
|| ISA_MIPS64) \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* ISA has conditional trap instructions. */
@ -621,11 +640,13 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
|| ISA_MIPS64R2 \
) && !TARGET_MIPS16)
/* ISA has floating-point nmadd and nmsub instructions. */
#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
|| ISA_MIPS64) \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& (!TARGET_MIPS5400 || TARGET_MAD) \
&& ! TARGET_MIPS16)
@ -633,11 +654,13 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
|| ISA_MIPS64R2 \
) && !TARGET_MIPS16)
/* ISA has double-word count leading zeroes/ones instruction (not
implemented). */
#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
|| ISA_MIPS64R2 \
&& !TARGET_MIPS16)
/* ISA has three operand multiply instructions that put
@ -677,6 +700,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
/* ISA has 32-bit rotate right instruction. */
#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
|| ISA_MIPS64R2 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
@ -694,7 +718,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* ISA has data indexed prefetch instructions. This controls use of
@ -702,7 +727,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
(prefx is a cop1x instruction, so can only be used if FP is
enabled.) */
#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
|| ISA_MIPS64) \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* True if trunc.w.s and trunc.w.d are real (not synthetic)
@ -713,11 +739,13 @@ extern const struct mips_rtx_cost_data *mips_cost;
/* ISA includes the MIPS32r2 seb and seh instructions. */
#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
|| ISA_MIPS64R2 \
))
/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
|| ISA_MIPS64R2 \
))
/* True if the result of a load is not available to the next instruction.
@ -748,6 +776,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
|| ISA_MIPS64R2 \
|| TARGET_MIPS5500)
/* Add -G xx support. */

3
contrib/gcc/config/mips/mips.md
View File

@ -1041,7 +1041,8 @@
|| TARGET_MIPS9000
|| ISA_MIPS32
|| ISA_MIPS32R2
|| ISA_MIPS64)
|| ISA_MIPS64
|| ISA_MIPS64R2)
return "mul\t%0,%1,%2";
return "mult\t%0,%1,%2";
}

6
gnu/lib/libgcc/Makefile
View File

@ -118,6 +118,12 @@ LIB2FUNCS_EXTRA = floatunsidf.c floatunsisf.c
.if ${TARGET_ARCH} == "mips"
LIB2FUNCS_EXTRA = floatunsidf.c floatunsisf.c
.if defined(TARGET_ABI) && ${TARGET_ABI} != "o32"
LIB2FUNCS_EXTRA+= floatdidf.c fixunsdfsi.c
LIB2FUNCS_EXTRA+= floatdisf.c floatundidf.c
LIB2FUNCS_EXTRA+= fixsfdi.c floatundisf.c
LIB2FUNCS_EXTRA+= fixdfdi.c fixunssfsi.c
.endif
.endif
.if ${TARGET_ARCH} == "ia64"

3
gnu/lib/libgomp/Makefile
View File

@ -24,7 +24,8 @@ VERSION_MAP= ${SRCDIR}/libgomp.map
# Target-specific OpenMP configuration
.if ${MACHINE_ARCH} == arm || ${MACHINE_ARCH} == i386 || \
${MACHINE_ARCH} == mips || ${MACHINE_ARCH} == powerpc
${MACHINE_ARCH} == powerpc || \
(${MACHINE_ARCH} == mips && (!defined(TARGET_ABI) || ${TARGET_ABI} != "n64"))
OMP_LOCK_ALIGN = 4
OMP_LOCK_KIND= 4
OMP_LOCK_SIZE= 4

3
gnu/usr.bin/binutils/Makefile.inc0
View File

@ -23,7 +23,8 @@ RELSRC= ${RELTOP}/../../../contrib/binutils
SRCDIR= ${.CURDIR}/${RELSRC}
.if ${TARGET_ARCH} == "arm" || ${TARGET_ARCH} == "i386" || \
${TARGET_ARCH} == "powerpc" || ${TARGET_ARCH} == "mips"
${TARGET_ARCH} == "powerpc" || \
(${TARGET_ARCH} == "mips" && (!defined(TARGET_ABI) || ${TARGET_ABI} != "n64"))
CFLAGS+= -DBFD_DEFAULT_TARGET_SIZE=32
.else
CFLAGS+= -DBFD_DEFAULT_TARGET_SIZE=64

17
gnu/usr.bin/binutils/ld/Makefile.mips
View File

@ -1,15 +1,22 @@
# $FreeBSD$
#xxxIMPxxx: size?
#xxxIMPxxx: TARGET_BIG_ENDIAN is lame. We should use the netbsd convention
# of mipsel and mips.
_sz?=32
.if defined(TARGET_BIG_ENDIAN)
NATIVE_EMULATION=elf${_sz}btsmip_fbsd
.if !defined(TARGET_BIG_ENDIAN)
_EMULATION_ENDIAN=l
.else
NATIVE_EMULATION=elf${_sz}ltsmip_fbsd
_EMULATION_ENDIAN=b
.endif
.if defined(TARGET_ABI) && ${TARGET_ABI} != "o32"
.if ${TARGET_ABI} == "n32"
NATIVE_EMULATION=elf32${_EMULATION_ENDIAN}tsmipn32_fbsd
.elif ${TARGET_ABI} == "n64"
NATIVE_EMULATION=elf64${_EMULATION_ENDIAN}tsmip_fbsd
.endif
.endif
NATIVE_EMULATION?=elf32${_EMULATION_ENDIAN}tsmip_fbsd
MIPS_ABIS=elf32btsmip_fbsd elf32ltsmip_fbsd elf64btsmip_fbsd elf64ltsmip_fbsd \
elf32btsmipn32_fbsd elf32ltsmipn32_fbsd
.for abi in ${MIPS_ABIS}

18
gnu/usr.bin/binutils/libbfd/Makefile.mips
View File

@ -1,8 +1,24 @@
# $FreeBSD$
#xxxIMPxxx: endian and size
#xxxIMPxxx: TARGET_BIG_ENDIAN is lame. We should use the netbsd convention
# of mipsel and mips.
.if !defined(TARGET_BIG_ENDIAN)
_EMULATION_ENDIAN=little
.else
_EMULATION_ENDIAN=big
.endif
DEFAULT_VECTOR= bfd_elf32_tradbigmips_vec
.if defined(TARGET_ABI) && ${TARGET_ABI} != "o32"
.if ${TARGET_ABI} == "n32"
DEFAULT_VECTOR= bfd_elf32_ntrad${_EMULATION_ENDIAN}mips_vec
.elif ${TARGET_ABI} == "n64"
DEFAULT_VECTOR= bfd_elf64_trad${_EMULATION_ENDIAN}mips_vec
.endif
.endif
DEFAULT_VECTOR?=bfd_elf32_trad${_EMULATION_ENDIAN}mips_vec
SRCS+= coff-mips.c \
cpu-mips.c \
ecoff.c \

2
gnu/usr.bin/binutils/libbfd/bfd.h
View File

@ -1546,10 +1546,12 @@ enum bfd_architecture
#define bfd_mach_mips6000 6000
#define bfd_mach_mips7000 7000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips9000 9000
#define bfd_mach_mips10000 10000
#define bfd_mach_mips12000 12000
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
#define bfd_mach_mips_octeon 6502
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33

23
gnu/usr.bin/cc/Makefile.inc
View File

@ -32,10 +32,31 @@ CFLAGS+= -DLONG_TYPE_SIZE=${LONG_TYPE_SIZE}
CFLAGS+= -DCROSS_COMPILE
.endif
.if ${TARGET_ARCH} == "mips" && !defined(TARGET_BIG_ENDIAN)
.if ${TARGET_ARCH} == "mips"
# XXX This is backwards, MIPS should default to BE.
.if !defined(TARGET_BIG_ENDIAN)
CFLAGS += -DTARGET_ENDIAN_DEFAULT=0
.endif
.if defined(TARGET_ABI) && ${TARGET_ABI} != "o32"
.if ${TARGET_ABI} == "n32"
MIPS_ABI_DEFAULT=ABI_N32
.elif ${TARGET_ABI} == "n64"
MIPS_ABI_DEFAULT=ABI_64
.endif
.endif
MIPS_ABI_DEFAULT?=ABI_32
CFLAGS += -DMIPS_ABI_DEFAULT=${MIPS_ABI_DEFAULT}
# GCC by default takes the ISA from the ABI's requirements. If world is built
# with a superior ISA, since we lack multilib, we have to set the right
# default ISA to be able to link against what's in /usr/lib. Terrible stuff.
.if defined(TARGET_CPUTYPE)
CFLAGS += -DMIPS_CPU_STRING_DEFAULT=\"${TARGET_CPUTYPE}\"
.endif
.endif
.if defined(WANT_FORCE_OPTIMIZATION_DOWNGRADE)
CFLAGS+= -DFORCE_OPTIMIZATION_DOWNGRADE=${WANT_FORCE_OPTIMIZATION_DOWNGRADE}
.endif