Initial PG_NX support (no-execute page bit)
- export the rest of the cpu features (and amd's features). - turn on EFER_NXE, depending on the NX amd feature bit - reorg the identcpu stuff a bit in order to stop treating the amd features as second class features (since it is now a primary feature bit set) and make it easier to export.
This commit is contained in:
peter
parent
2eebe98baa
commit
56777bd5f3
@ -69,13 +69,10 @@ void identify_cpu(void);
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void earlysetcpuclass(void);
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void panicifcpuunsupported(void);
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static void print_AMD_features(void);
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static void print_AMD_info(void);
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static void print_AMD_assoc(int i);
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int cpu_feature2; /* XXX change cpu_feature to long? */
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int cpu_class;
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u_int cpu_exthigh; /* Highest arg to extended CPUID */
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char machine[] = "amd64";
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SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
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machine, 0, "Machine class");
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@ -109,26 +106,18 @@ printcpuinfo(void)
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strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
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/* Check for extended CPUID information and a processor name. */
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if (cpu_high > 0 &&
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(strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0)) {
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do_cpuid(0x80000000, regs);
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if (regs[0] >= 0x80000000) {
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cpu_exthigh = regs[0];
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if (cpu_exthigh >= 0x80000004) {
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brand = cpu_brand;
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for (i = 0x80000002; i < 0x80000005; i++) {
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do_cpuid(i, regs);
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memcpy(brand, regs, sizeof(regs));
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brand += sizeof(regs);
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}
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}
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if (cpu_exthigh >= 0x80000004) {
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brand = cpu_brand;
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for (i = 0x80000002; i < 0x80000005; i++) {
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do_cpuid(i, regs);
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memcpy(brand, regs, sizeof(regs));
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brand += sizeof(regs);
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}
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}
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if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
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/* Better late than never I suppose.. */
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strcat(cpu_model, "IA-32e");
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/* Please make up your mind folks! */
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strcat(cpu_model, "EM64T");
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} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
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/*
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* Values taken from AMD Processor Recognition
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@ -259,6 +248,44 @@ printcpuinfo(void)
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"\040<b31>"
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);
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}
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0x0183f3ff
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if (amd_feature != 0) {
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printf("\n AMD Features=0x%b", amd_feature,
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"\020" /* in hex */
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"\001<s0>" /* Same */
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"\002<s1>" /* Same */
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"\003<s2>" /* Same */
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"\004<s3>" /* Same */
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"\005<s4>" /* Same */
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"\006<s5>" /* Same */
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"\007<s6>" /* Same */
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"\010<s7>" /* Same */
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"\011<s8>" /* Same */
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"\012<s9>" /* Same */
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"\013<b10>" /* Undefined */
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"\014SYSCALL" /* Have SYSCALL/SYSRET */
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"\015<s12>" /* Same */
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"\016<s13>" /* Same */
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"\017<s14>" /* Same */
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"\020<s15>" /* Same */
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"\021<s16>" /* Same */
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"\022<s17>" /* Same */
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"\023<b18>" /* Reserved, unknown */
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"\024MP" /* Multiprocessor Capable */
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"\025NX" /* Has EFER.NXE, NX */
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"\026<b21>" /* Undefined */
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"\027MMX+" /* AMD MMX Extensions */
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"\030<s23>" /* Same */
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"\031<s24>" /* Same */
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"\032<b25>" /* Undefined */
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"\033<b26>" /* Undefined */
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"\034<b27>" /* Undefined */
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"\035<b28>" /* Undefined */
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"\036LM" /* 64 bit long mode */
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"\0373DNow+" /* AMD 3DNow! Extensions */
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"\0403DNow" /* AMD 3DNow! */
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);
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}
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/*
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* If this CPU supports hyperthreading then mention
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@ -269,8 +296,6 @@ printcpuinfo(void)
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printf("\n Hyperthreading: %d logical CPUs",
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(cpu_procinfo & CPUID_HTT_CORES) >> 16);
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}
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if (cpu_exthigh >= 0x80000001)
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print_AMD_features();
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}
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/* Avoid ugly blank lines: only print newline when we have to. */
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if (*cpu_vendor || cpu_id)
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@ -327,6 +352,16 @@ identify_cpu(void)
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cpu_feature = regs[3];
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cpu_feature2 = regs[2];
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0) {
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do_cpuid(0x80000000, regs);
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cpu_exthigh = regs[0];
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}
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if (cpu_exthigh >= 0x80000001) {
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do_cpuid(0x80000001, regs);
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amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
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}
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/* XXX */
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cpu = CPU_CLAWHAMMER;
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}
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@ -357,112 +392,65 @@ print_AMD_l2_assoc(int i)
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static void
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print_AMD_info(void)
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{
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if (cpu_exthigh >= 0x80000005) {
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u_int regs[4];
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do_cpuid(0x80000005, regs);
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printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
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print_AMD_assoc(regs[0] >> 24);
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printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
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print_AMD_assoc((regs[0] >> 8) & 0xff);
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printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
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print_AMD_assoc(regs[1] >> 24);
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printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
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print_AMD_assoc((regs[1] >> 8) & 0xff);
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printf("L1 data cache: %d kbytes", regs[2] >> 24);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
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print_AMD_assoc((regs[2] >> 16) & 0xff);
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printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
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printf(", %d bytes/line", regs[3] & 0xff);
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printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
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print_AMD_assoc((regs[3] >> 16) & 0xff);
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if (cpu_exthigh >= 0x80000006) {
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do_cpuid(0x80000006, regs);
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if ((regs[0] >> 16) != 0) {
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printf("L2 2MB data TLB: %d entries",
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(regs[0] >> 16) & 0xfff);
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print_AMD_l2_assoc(regs[0] >> 28);
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printf("L2 2MB instruction TLB: %d entries",
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regs[0] & 0xfff);
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print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
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} else {
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printf("L2 2MB unified TLB: %d entries",
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regs[0] & 0xfff);
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print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
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}
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if ((regs[1] >> 16) != 0) {
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printf("L2 4KB data TLB: %d entries",
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(regs[1] >> 16) & 0xfff);
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print_AMD_l2_assoc(regs[1] >> 28);
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printf("L2 4KB instruction TLB: %d entries",
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(regs[1] >> 16) & 0xfff);
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print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
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} else {
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printf("L2 4KB unified TLB: %d entries",
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(regs[1] >> 16) & 0xfff);
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print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
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}
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printf("L2 unified cache: %d kbytes", regs[2] >> 16);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
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print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
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}
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}
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}
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static void
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print_AMD_features(void)
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{
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u_int regs[4];
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/*
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* Values taken from AMD Processor Recognition
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* http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
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*/
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do_cpuid(0x80000001, regs);
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printf("\n AMD Features=0x%b", regs[3] & ~(cpu_feature & 0x0183f3ff),
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"\020" /* in hex */
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"\001FPU" /* Integral FPU */
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"\002VME" /* Extended VM86 mode support */
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"\003DE" /* Debug extensions */
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"\004PSE" /* 4MByte page tables */
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"\005TSC" /* Timestamp counter */
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"\006MSR" /* Machine specific registers */
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"\007PAE" /* Physical address extension */
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"\010MCE" /* Machine Check support */
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"\011CX8" /* CMPEXCH8 instruction */
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"\012APIC" /* SMP local APIC */
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"\013<b10>"
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"\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
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"\015MTRR" /* Memory Type Range Registers */
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"\016PGE" /* PG_G (global bit) support */
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"\017MCA" /* Machine Check Architecture */
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"\020CMOV" /* CMOV instruction */
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"\021PAT" /* Page attributes table */
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"\022PGE36" /* 36 bit address space support */
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"\023RSVD" /* Reserved, unknown */
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"\024MP" /* Multiprocessor Capable */
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"\025NX" /* Has EFER.NXE, NX (no execute pte bit) */
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"\026<b21>"
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"\027MMX+" /* AMD MMX Instruction Extensions */
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"\030MMX"
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"\031FXSAVE" /* FXSAVE/FXRSTOR */
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"\032<b25>"
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"\033<b26>"
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"\034<b27>"
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"\035<b28>"
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"\036LM" /* Long mode */
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"\0373DNow!+" /* AMD 3DNow! Instruction Extensions */
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"\0403DNow!" /* AMD 3DNow! Instructions */
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);
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if (cpu_exthigh < 0x80000005)
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return;
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do_cpuid(0x80000005, regs);
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printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
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print_AMD_assoc(regs[0] >> 24);
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printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
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print_AMD_assoc((regs[0] >> 8) & 0xff);
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printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
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print_AMD_assoc(regs[1] >> 24);
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printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
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print_AMD_assoc((regs[1] >> 8) & 0xff);
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printf("L1 data cache: %d kbytes", regs[2] >> 24);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
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print_AMD_assoc((regs[2] >> 16) & 0xff);
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printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
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printf(", %d bytes/line", regs[3] & 0xff);
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printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
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print_AMD_assoc((regs[3] >> 16) & 0xff);
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if (cpu_exthigh >= 0x80000006) {
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do_cpuid(0x80000006, regs);
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if ((regs[0] >> 16) != 0) {
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printf("L2 2MB data TLB: %d entries",
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(regs[0] >> 16) & 0xfff);
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print_AMD_l2_assoc(regs[0] >> 28);
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printf("L2 2MB instruction TLB: %d entries",
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regs[0] & 0xfff);
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print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
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} else {
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printf("L2 2MB unified TLB: %d entries",
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regs[0] & 0xfff);
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print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
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}
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if ((regs[1] >> 16) != 0) {
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printf("L2 4KB data TLB: %d entries",
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(regs[1] >> 16) & 0xfff);
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print_AMD_l2_assoc(regs[1] >> 28);
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printf("L2 4KB instruction TLB: %d entries",
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(regs[1] >> 16) & 0xfff);
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print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
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} else {
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printf("L2 4KB unified TLB: %d entries",
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(regs[1] >> 16) & 0xfff);
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print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
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}
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printf("L2 unified cache: %d kbytes", regs[2] >> 16);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
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print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
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}
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}
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@ -41,7 +41,8 @@ __FBSDID("$FreeBSD$");
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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void initializecpu(void);
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#include <vm/vm.h>
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#include <vm/pmap.h>
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static int hw_instruction_sse;
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SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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@ -49,31 +50,30 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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int cpu; /* Are we 386, 386sx, 486, etc? */
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u_int cpu_feature; /* Feature flags */
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u_int cpu_feature2; /* Feature flags */
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u_int amd_feature; /* Feature flags */
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u_int cpu_high; /* Highest arg to CPUID */
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u_int cpu_exthigh; /* Highest arg to extended CPUID */
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u_int cpu_id; /* Stepping ID */
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u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
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char cpu_vendor[20]; /* CPU Origin code */
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u_int cpu_fxsr; /* SSE enabled */
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/*
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* Initialize CR4 (Control register 4) to enable SSE instructions.
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* Initialize CPU control registers
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*/
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void
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enable_sse(void)
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initializecpu(void)
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{
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uint64_t msr;
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if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
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load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
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cpu_fxsr = hw_instruction_sse = 1;
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}
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}
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void
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initializecpu(void)
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{
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switch (cpu) {
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default:
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break;
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if ((amd_feature & AMDID_NX) != 0) {
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msr = rdmsr(MSR_EFER) | EFER_NXE;
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wrmsr(MSR_EFER, msr);
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pg_nx = PG_NX;
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}
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enable_sse();
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}
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@ -130,7 +130,6 @@ extern void dblfault_handler(void);
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extern void printcpuinfo(void); /* XXX header file */
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extern void identify_cpu(void);
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extern void panicifcpuunsupported(void);
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extern void initializecpu(void);
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#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
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#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
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@ -1108,12 +1107,6 @@ hammer_time(u_int64_t modulep, u_int64_t physfree)
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#error "have you forgotten the isa device?";
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#endif
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#if 0 /* Not till we test the features bit */
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/* Turn on PTE NX (no execute) bit */
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msr = rdmsr(MSR_EFER) | EFER_NXE;
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wrmsr(MSR_EFER, msr);
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#endif
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proc0.p_uarea = (struct user *)(physfree + KERNBASE);
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bzero(proc0.p_uarea, UAREA_PAGES * PAGE_SIZE);
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physfree += UAREA_PAGES * PAGE_SIZE;
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@ -432,8 +432,8 @@ init_secondary(void)
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/* set up FPU state on the AP */
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fpuinit();
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/* set up SSE registers */
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enable_sse();
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/* set up SSE/NX registers */
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initializecpu();
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/* A quick check from sanity claus */
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if (PCPU_GET(apic_id) != lapic_id()) {
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@ -102,11 +102,7 @@ protmode:
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*/
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movl $MSR_EFER, %ecx
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rdmsr
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#if 0 /* not till we test the NX cpuid bits */
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orl $EFER_LME | EFER_SCE | EFER_NXE, %eax
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#else
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orl $EFER_LME | EFER_SCE, %eax
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#endif
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wrmsr
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/*
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@ -174,6 +174,7 @@ static int nkpt;
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static int ndmpdp;
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static vm_paddr_t dmaplimit;
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vm_offset_t kernel_vm_end;
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pt_entry_t pg_nx;
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static u_int64_t KPTphys; /* phys addr of kernel level 1 */
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static u_int64_t KPDphys; /* phys addr of kernel level 2 */
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@ -1972,10 +1973,8 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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newpte = (pt_entry_t)(pa | PG_V);
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if ((prot & VM_PROT_WRITE) != 0)
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newpte |= PG_RW;
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#ifdef PG_NX
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if ((prot & VM_PROT_EXECUTE) == 0)
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newpte |= PG_NX;
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#endif
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newpte |= pg_nx;
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if (wired)
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newpte |= PG_W;
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if (va < VM_MAXUSER_ADDRESS)
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@ -42,6 +42,8 @@ extern u_int basemem;
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extern int busdma_swi_pending;
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extern u_int cpu_exthigh;
|
||||
extern u_int cpu_feature;
|
||||
extern u_int cpu_feature2;
|
||||
extern u_int amd_feature;
|
||||
extern u_int cpu_fxsr;
|
||||
extern u_int cpu_high;
|
||||
extern u_int cpu_id;
|
||||
@ -63,7 +65,7 @@ void busdma_swi(void);
|
||||
void cpu_setregs(void);
|
||||
void doreti_iret(void) __asm(__STRING(doreti_iret));
|
||||
void doreti_iret_fault(void) __asm(__STRING(doreti_iret_fault));
|
||||
void enable_sse(void);
|
||||
void initializecpu(void);
|
||||
void fillw(int /*u_short*/ pat, void *base, size_t cnt);
|
||||
void fpstate_drop(struct thread *td);
|
||||
int is_physical_memory(vm_paddr_t addr);
|
||||
|
||||
@ -62,6 +62,7 @@
|
||||
#define PG_AVAIL1 0x200 /* / Available for system */
|
||||
#define PG_AVAIL2 0x400 /* < programmers use */
|
||||
#define PG_AVAIL3 0x800 /* \ */
|
||||
#define PG_NX (1ul<<63) /* No-execute */
|
||||
|
||||
|
||||
/* Our various interpretations of the above */
|
||||
@ -202,6 +203,8 @@ pte_load_store(pt_entry_t *ptep, pt_entry_t pte)
|
||||
|
||||
#define pde_store(pdep, pde) pte_store((pdep), (pde))
|
||||
|
||||
extern pt_entry_t pg_nx;
|
||||
|
||||
#endif /* _KERNEL */
|
||||
|
||||
/*
|
||||
|
||||
@ -112,6 +112,22 @@
|
||||
#define CPUID_B30 0x40000000
|
||||
#define CPUID_PBE 0x80000000
|
||||
|
||||
#define CPUID2_SSE3 0x00000001
|
||||
#define CPUID2_MON 0x00000008
|
||||
#define CPUID2_DS_CPL 0x00000010
|
||||
#define CPUID2_EST 0x00000080
|
||||
#define CPUID2_TM2 0x00000100
|
||||
#define CPUID2_CNTXID 0x00000400
|
||||
#define CPUID2_CX16 0x00002000
|
||||
|
||||
/*
|
||||
* Important bits in the AMD extended cpuid flags
|
||||
*/
|
||||
#define AMDID_SYSCALL 0x00000800
|
||||
#define AMDID_MP 0x00080000
|
||||
#define AMDID_NX 0x00100000
|
||||
#define AMDID_LM 0x20000000
|
||||
|
||||
/*
|
||||
* CPUID instruction 1 ebx info
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user