arm/ralink cleanup
Remove the non-INTRNG code. Remove left over cut and paste code from the lpc code that was the start for the port. Set KERNPHYSADDR and KERNVIRTADDR Tested on Buffalo_WZR2-G300N Differential Revision: https://reviews.freebsd.org/D16622
This commit is contained in:
Warner Losh
parent
e896acd05e
commit
56b9659ee7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=337822
@ -60,32 +60,24 @@ __FBSDID("$FreeBSD$");
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#define INTC_NIRQS 32
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#ifdef INTRNG
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#include "pic_if.h"
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struct rt1310_irqsrc {
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struct intr_irqsrc ri_isrc;
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u_int ri_irq;
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};
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#endif
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struct rt1310_intc_softc {
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device_t dev;
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struct resource * ri_res;
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bus_space_tag_t ri_bst;
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bus_space_handle_t ri_bsh;
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#ifdef INTRNG
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struct rt1310_irqsrc ri_isrcs[INTC_NIRQS];
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#endif
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};
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static int rt1310_intc_probe(device_t);
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static int rt1310_intc_attach(device_t);
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#ifndef INTRNG
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static void rt1310_intc_eoi(void *);
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#else
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static int rt1310_pic_attach(struct rt1310_intc_softc *sc);
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#endif
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static struct rt1310_intc_softc *intc_softc = NULL;
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@ -143,11 +135,7 @@ rt1310_intc_probe(device_t dev)
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if (!ofw_bus_is_compatible_strict(dev, "rt,pic"))
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return (ENXIO);
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#ifdef INTRNG
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device_set_desc(dev, "RT1310 INTRNG Interrupt Controller");
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#else
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device_set_desc(dev, "RT1310 Interrupt Controller");
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#endif
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return (BUS_PROBE_DEFAULT);
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}
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@ -173,11 +161,7 @@ rt1310_intc_attach(device_t dev)
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sc->ri_bst = rman_get_bustag(sc->ri_res);
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sc->ri_bsh = rman_get_bushandle(sc->ri_res);
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intc_softc = sc;
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#ifndef INTRNG
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arm_post_filter = rt1310_intc_eoi;
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#else
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rt1310_pic_attach(sc);
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#endif
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intc_write_4(sc, RT_INTC_IECR, 0);
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intc_write_4(sc, RT_INTC_ICCR, ~0);
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@ -195,72 +179,6 @@ rt1310_intc_attach(device_t dev)
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return (0);
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}
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#ifndef INTRNG
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int
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arm_get_next_irq(int last)
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{
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struct rt1310_intc_softc *sc = intc_softc;
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uint32_t value;
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int i;
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value = intc_read_4(sc, RT_INTC_IPR);
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for (i = 0; i < 32; i++) {
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if (value & (1 << i))
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return (i);
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}
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return (-1);
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}
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void
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arm_mask_irq(uintptr_t nb)
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{
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struct rt1310_intc_softc *sc = intc_softc;
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uint32_t value;
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/* Make sure that interrupt isn't active already */
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rt1310_intc_eoi((void *)nb);
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/* Clear bit in ER register */
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value = intc_read_4(sc, RT_INTC_IECR);
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value &= ~(1 << nb);
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intc_write_4(sc, RT_INTC_IECR, value);
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intc_write_4(sc, RT_INTC_IMR, value);
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intc_write_4(sc, RT_INTC_ICCR, 1 << nb);
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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struct rt1310_intc_softc *sc = intc_softc;
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uint32_t value;
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value = intc_read_4(sc, RT_INTC_IECR);
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value |= (1 << nb);
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intc_write_4(sc, RT_INTC_IMR, value);
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intc_write_4(sc, RT_INTC_IECR, value);
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}
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static void
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rt1310_intc_eoi(void *data)
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{
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struct rt1310_intc_softc *sc = intc_softc;
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int nb = (int)data;
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intc_write_4(sc, RT_INTC_ICCR, 1 << nb);
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if (nb == 0) {
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uint32_t value;
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value = intc_read_4(sc, RT_INTC_IECR);
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value &= ~(1 << nb);
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intc_write_4(sc, RT_INTC_IECR, value);
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intc_write_4(sc, RT_INTC_IMR, value);
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}
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}
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#else
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static void
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rt1310_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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@ -390,43 +308,20 @@ rt1310_pic_attach(struct rt1310_intc_softc *sc)
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return (intr_pic_claim_root(sc->dev, xref, rt1310_intr, sc, 0));
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}
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#endif
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struct fdt_fixup_entry fdt_fixup_table[] = {
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{ NULL, NULL }
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};
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#ifndef INTRNG
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static int
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fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
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int *pol)
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{
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if (!fdt_is_compatible(node, "lpc,pic"))
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return (ENXIO);
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*interrupt = fdt32_to_cpu(intr[0]);
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*trig = INTR_TRIGGER_CONFORM;
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*pol = INTR_POLARITY_CONFORM;
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return (0);
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}
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fdt_pic_decode_t fdt_pic_table[] = {
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&fdt_pic_decode_ic,
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NULL
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};
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#endif
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static device_method_t rt1310_intc_methods[] = {
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DEVMETHOD(device_probe, rt1310_intc_probe),
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DEVMETHOD(device_attach, rt1310_intc_attach),
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#ifdef INTRNG
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DEVMETHOD(pic_disable_intr, rt1310_disable_intr),
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DEVMETHOD(pic_enable_intr, rt1310_enable_intr),
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DEVMETHOD(pic_map_intr, rt1310_map_intr),
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DEVMETHOD(pic_post_filter, rt1310_post_filter),
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DEVMETHOD(pic_post_ithread, rt1310_post_ithread),
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DEVMETHOD(pic_pre_ithread, rt1310_pre_ithread),
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#endif
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{ 0, 0 }
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};
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@ -33,39 +33,12 @@
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#include <sys/bus.h>
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#include <machine/bus.h>
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/* Clocking and power control */
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uint32_t lpc_pwr_read(device_t, int);
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void lpc_pwr_write(device_t, int, uint32_t);
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/* GPIO */
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void rt1310_gpio_init(void);
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int rt1310_gpio_set_flags(device_t, int, int);
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int rt1310_gpio_set_state(device_t, int, int);
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int rt1310_gpio_get_state(device_t, int, int *);
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/* DMA */
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struct lpc_dmac_channel_config
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{
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int ldc_fcntl;
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int ldc_src_periph;
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int ldc_src_width;
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int ldc_src_incr;
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int ldc_src_burst;
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int ldc_dst_periph;
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int ldc_dst_width;
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int ldc_dst_incr;
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int ldc_dst_burst;
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void (*ldc_success_handler)(void *);
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void (*ldc_error_handler)(void *);
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void * ldc_handler_arg;
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};
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int lpc_dmac_config_channel(device_t, int, struct lpc_dmac_channel_config *);
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int lpc_dmac_setup_transfer(device_t, int, bus_addr_t, bus_addr_t, bus_size_t, int);
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int lpc_dmac_enable_channel(device_t, int);
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int lpc_dmac_disable_channel(device_t, int);
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int lpc_dmac_start_burst(device_t, int);
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extern uint32_t rt1310_master_clock;
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#endif /* _ARM_RT_RTVAR_H */
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@ -4,3 +4,8 @@ cpu CPU_ARM9E
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machine arm
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makeoptions CONF_CFLAGS="-march=armv5te"
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options INTRNG
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makeoptions KERNPHYSADDR=0x40000000
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makeoptions KERNVIRTADDR=0xc0000000
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options KERNVIRTADDR=0xc0000000
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options PHYSADDR=0x40000000
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